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Stair56E UART project

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吴琪
2026-08-05 19:07:52 +08:00
parent 7ca1af130d
commit f5654b70cc
2500 changed files with 619007 additions and 282610 deletions
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project/example/2.4g/RF24_HOP/app/src/main.c
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/*!
* \file main.c
*
* \brief Target main implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "main.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
#define XC_HOPPING_NUM 4
#define XC_RETRY_NUM 5
/*------------------------------------------------------------------------------------
Global Variables
-------------------------------------------------------------------------------------*/
bool rf_send_timer_flag = false;
bool rf_recv_timer_flag = false;
uint16_t rf_channel_base = 2400;
uint8_t rf_channel_hop[XC_HOPPING_NUM] = {02, 24, 51, 78}; //{02,13,24,34,46,51,56,61,78};
uint8_t rf_channel_index = 0;
uint32_t recv_hop_num = 0;
uint32_t tx_cnt, rx_cnt;
uint8_t tx_len, rx_len;
uint8_t tx_buff[256] = {0};
uint8_t rx_buff[256] = {0};
/*------------------------------------------------------------------------------------
Func Prototype
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
/**
****************************************************************************************
* @brief
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void timer_init(uint8_t timer_id, uint32_t timer_cnt)
{
LOGI("timer_init\r\n");
uint32_t timerx_us = timer_cnt * 1000;
Timer_InitCfg_t timer_cfg;
timer_cfg.timer_src_clk = TIMER_CLK_SRC_32M_DIV;
timer_cfg.timer_div_clk = TIMER_DIV_CLK_1MHzOr1K;
timer_cfg.timer_mode = TIMER_MODE_CYCLE;
xc_timer_init(timer_id, &timer_cfg);
xc_timer_set_value(timer_id, timerx_us);
}
/**
* @brief timer0_Callback
* @param void * - context
*
* @retval void
*/
void timer0_callback(void *context)
{
#if !(XINCX_RF_MODE)
rf_send_timer_flag = true;
#else
rf_recv_timer_flag = true;
#endif // !(XINCX_RF_MODE)
}
/**
****************************************************************************************
* @brief Clock Initialization
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void clock_init(void)
{
CLOCK_InitCfg_t clock_cfg;
clock_cfg.hfclk_src = CLOCK_HFCLK_SRC_XTAL;
clock_cfg.hfclk_in = CLOCK_HFCLK_IN_32M;
#if (RC_32K)
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_RC;
#endif //(RC_32K)
#if (XTAL_32K)
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL;
#endif // (XTAL_32K)
#if (XTAL_32768K)
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL;
#endif // (XTAL_32768K)
#ifdef XC62XX
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_RC;
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32K;
#else
if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_XTAL) {
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32768;
} else if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_RC) {
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32K;
}
#endif
xc_clock_init_cfg(&clock_cfg);
SysTick_Config(xc_clock_hfclk_in_get() / 100);
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
}
#ifdef DEBUG_LOG
/**
* @brief RF 2.4g register information printing
* @param void
* @retval void
*/
void rf_2M_reg_info(void)
{
/* Register information printing */
LOGI("CFG_TOP: 0x%08x\r\n", XC_RF_2_4G->CFG_TOP);
LOGI("TXPROC_CFG: 0x%08x\r\n", XC_RF_2_4G->TXPROC_CFG);
LOGI("RXPROC_CFG_L: 0x%08x\r\n", XC_RF_2_4G->RXPROC_CFG_L);
LOGI("RF_CH: 0x%08x\r\n", XC_RF_2_4G->RF_CH);
LOGI("rccal_reg_l: 0x%08x\r\n", XC_BT_RF->rccal_reg_l);
LOGI("ana2_reg_l: 0x%08x\r\n", XC_BT_RF->ana2_reg_l);
LOGI("ana3_reg_l: 0x%08x\r\n", XC_BT_RF->ana3_reg_l);
LOGI("ana4_reg_l: 0x%08x\r\n", XC_BT_RF->ana4_reg_l);
LOGI("ana5_reg_l: 0x%08x\r\n", XC_BT_RF->ana5_reg_l);
LOGI("ana14_reg_l: 0x%08x\r\n", XC_BT_RF->ana14_reg_l);
LOGI("ana15_reg_l: 0x%08x\r\n", XC_BT_RF->ana15_reg_l);
LOGI("ana16_reg_l: 0x%08x\r\n", XC_BT_RF->ana16_reg_l);
LOGI("ana17_reg_l: 0x%08x\r\n", XC_BT_RF->ana17_reg_l);
LOGI("ana18_reg_l: 0x%08x\r\n", XC_BT_RF->ana18_reg_l);
LOGI("ana21_reg_l: 0x%08x\r\n", XC_BT_RF->ana21_reg_l);
LOGI("AON_RF_AONREG: 0x%08x\r\n", cprao_aon_rf_aonreg_get()); // 0x36
}
/**
* @brief Rf 2.4g dump log
* @param void
*
* @retval void
*/
void rf_dump_log(void)
{
LOGI("***************** 2.4G Param ******************\n");
LOGI("CFG_TOP: 0x%08x\r\n", XC_RF_2_4G->CFG_TOP);
LOGI("EN_AA: 0x%08x\r\n", XC_RF_2_4G->EN_AA);
LOGI("EN_RXADDR: 0x%08x\r\n", XC_RF_2_4G->EN_RXADDR);
LOGI("SETUP_AW: 0x%08x\r\n", XC_RF_2_4G->SETUP_AW);
LOGI("SETUP_RETR: 0x%08x\r\n", XC_RF_2_4G->SETUP_RETR);
LOGI("RF_CH: 0x%08x\r\n", XC_RF_2_4G->RF_CH);
LOGI("SETUP_RF: 0x%08x\r\n", XC_RF_2_4G->SETUP_RF);
LOGI("STATUS: 0x%08x\r\n", XC_RF_2_4G->STATUS);
LOGI("OBSERVE_TX: 0x%08x\r\n", XC_RF_2_4G->OBSERVE_TX);
LOGI("RSSI: 0x%08x\r\n", XC_RF_2_4G->RSSI);
LOGI("RX_ADDR_P0: 0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RX_ADDR_P0_H), XC_RF_2_4G->RX_ADDR_P0_L);
LOGI("RX_ADDR_P1: 0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RX_ADDR_P1_H), XC_RF_2_4G->RX_ADDR_P1_L);
LOGI("RX_ADDR_P2TOP5:0x%08x\r\n", XC_RF_2_4G->RX_ADDR_P2TOP5);
LOGI("BER_RESULT: 0x%08x%08x\r\n", XC_RF_2_4G->BER_ERR_CNT, XC_RF_2_4G->BER_RECV_CNT);
LOGI("AGC_SETTING: 0x%08x\r\n", XC_RF_2_4G->AGC_SETTING);
LOGI("PGA_SETTING: 0x%02x %08x\r\n", ((XC_RF_2_4G->TX_ADDR_H) & 0xFF00) >> 8, XC_RF_2_4G->PGA_SETTING);
LOGI("TX_ADDR: 0x%02x %08x\r\n", ((XC_RF_2_4G->TX_ADDR_H) & 0xFF), XC_RF_2_4G->TX_ADDR_L);
LOGI("RX_PW_PX: 0x%04x %08x\r\n", 0xFFFF & (XC_RF_2_4G->RX_PW_Px_H), XC_RF_2_4G->RX_PW_Px_L);
LOGI("STATUS_FIFO: 0x%08x\r\n", XC_RF_2_4G->STATUS_FIFO);
LOGI("RSSIREC: 0x%08x\r\n", XC_RF_2_4G->RSSIREC);
LOGI("TXPROC_CFG: 0x%08x\r\n", XC_RF_2_4G->TXPROC_CFG);
LOGI("RXPROC_CFG: 0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RXPROC_CFG_H), XC_RF_2_4G->RXPROC_CFG_L);
LOGI("DYNPD: 0x%08x\r\n", XC_RF_2_4G->DYNPD);
LOGI("FEATURE: 0x%08x\r\n", XC_RF_2_4G->FEATURE);
LOGI("PGA_SETTING_H: 0x%08x\r\n", XC_RF_2_4G->TX_ADDR_H);
LOGI("TX_POWER 0x%08x\r\n", (XC_BT_RF->ana21_reg_l >> 6) & 0x3f);
LOGI("ana11_reg_l: 0x%08x\r\n", XC_BT_RF->ana11_reg_l);
LOGI("***********************************************\n");
LOGI("\r\n");
}
#endif // DEBUG_LOG
/**
* @brief RF 2.4g data config
* @param uint8_t * - buff
* uint8 - len
* @retval uint8_t - 0
*/
uint8_t rf_data_config(uint8_t *buff, uint8_t len)
{
if (len == 0) {
return RF_FAIL;
}
for (uint8_t i = 0; i < len; i++) {
buff[i] = i;
}
return RF_SUCCESS;
}
void rf_recv_hop(void)
{
LOGI("rf_recv_hop:%d %d\r\n", recv_hop_num, XC_RF_2_4G->RF_CH & 0x3fff);
rf_channel_index += 1;
if (rf_channel_index >= sizeof(rf_channel_hop)) {
rf_channel_index = 0;
}
rf_set_channel(rf_channel_hop[rf_channel_index] + rf_channel_base);
}
/**
* @brief RF 2.4g tx manage
* @param rf_data_typedef_t * - rf_data
* @retval uint8_t - cnt
*/
void rf_tx_manage(void)
{
static uint8_t ack_check = 0;
static uint16_t ack_cnt = 0;
if ((rf_send_timer_flag)) {
rf_send_timer_flag = false;
tx_cnt += 1;
/* Filling in software frame number */
tx_buff[0] = tx_cnt;
LOGI("send_cnt:%d\r\n", tx_cnt);
/* data transmission */
int status = rf_tx_event(tx_buff, tx_len);
if (status == TX_DATA_OK) {
ack_cnt += 1;
LOGI("ack ok :%d\r\n", ack_cnt);
ack_check = 0;
} else // if(status == TX_RETRANS_MAX)
{
LOGI("failed\r\n");
ack_check++;
}
// retry XC_RETRY_NUM times transporttion
if (ack_check > XC_RETRY_NUM) {
rf_recv_hop();
ack_check = 0;
}
LOGI("channel:%d\r\n\r\n", XC_RF_2_4G->RF_CH & 0x3fff);
}
}
/**
* @brief RF 2.4g rx manage
* @param rf_data_typedef_t * - rf_data
* @retval uint32_t - 0
*/
#if !(XINCX_RF_NVIC_MODE)
void rf_rx_manage(void)
{
static uint32_t conut = 0;
/* Receive event processing */
rx_len = rf_rx_event(rx_buff);
/* Receiving end polling data processing */
if (rx_len != 0) {
xc_timer_stop(RF_RX_TIMERx);
/* Entering standby mode */
CE_CTL_LOW;
/* Receiving data processing */
if (rx_buff[RF_CONFIRMED_VALUE] == RF_CONFIRMED_VALUE) {
// LOGI("%d\r\n", conut);
}
// rf_buff_info(rf_data->buff, len);
/* Receive Count */
conut += 1;
recv_hop_num = 0;
LOGI("channel:%d\r\n", XC_RF_2_4G->RF_CH & 0x3fff);
LOGI("recv:%d\r\n", conut);
/* Receive read data buffer reset */
memset(rx_buff, 0, rx_len);
rx_len = 0;
xc_timer_start(RF_RX_TIMERx);
/* Entering the receiver */
CE_CTL_HIGH;
}
}
#else
void rf_rx_manage(void)
{
static uint32_t conut = 0;
uint8_t len = recv_len;
if (rf24g_rx_irq_flag) {
xc_timer_stop(RF_RX_TIMERx);
rf24g_rx_irq_flag = false;
/* Entering standby mode */
CE_CTL_LOW;
if ((len != 0) && (recv_buf[RF_CONFIRMED_VALUE] == RF_CONFIRMED_VALUE)) {
// LOGI("%d\r\n", recv_buf[0]);
}
// rf_buff_info(recv_buf, len);
/* Receive Count */
conut += 1;
LOGI("channel:%d\r\n", XC_RF_2_4G->RF_CH & 0x3fff);
LOGI("recv:%d\r\n\r\n", conut);
recv_hop_num = 0;
/* Receive read data buffer reset */
memset(recv_buf, 0, len);
len = 0;
// rf_recv_hop();
xc_timer_start(RF_RX_TIMERx);
/* Entering the receiver */
CE_CTL_HIGH;
}
}
#endif //!(XINCX_RF_NVIC_MODE)
/**
* @brief RF 2.4g buff info
* @param uint8_t * - buff
* uint8_t len
* @retval void
*/
void rf_buff_info(uint8_t *buff, uint8_t len)
{
for (uint8_t i = 0; i < len; i++)
LOGI("%02x ", buff[i]);
LOGI("\r\n");
}
void app_uart_init(void)
{
GPIO_InitCfg_t gpio_cfg = {0};
gpio_cfg.Mux = GPIO_Mux0;
gpio_cfg.Pull = GPIO_PULLUP;
gpio_cfg.Int = NOT_INT;
gpio_cfg.FunSel = UART0_TX;
gpio_cfg.Pin = GPIO_18;
gpio_cfg.Dir = GPIO_DIR_OUTPUT;
xc_gpio_init(&gpio_cfg);
gpio_cfg.FunSel = UART0_RX;
gpio_cfg.Pin = GPIO_19;
gpio_cfg.Dir = GPIO_DIR_INPUT;
xc_gpio_init(&gpio_cfg);
UART_InitCfg_t uart_cfg = {0};
uart_cfg.Parity = UART_PARITY_DISABLE;
uart_cfg.StopBits = UART_STOP_1_BITS;
uart_cfg.WordLength = UART_DATA_8_BITS;
uart_cfg.BaudRate = UART_BAUDRATE_115200;
uart_cfg.HardwareFlowControl = UART_HWFC_DISABLE;
xc_uart_init(UART0_IDX, &uart_cfg);
}
/**
* @brief main
* @details
* @param[in] void
* @param[out] void
* @retval int - 0
* @retval void
* @par identifier
* reserve
* @par other
* void
* @par change log
* Alex created on 2023-05-31
*/
int main(void)
{
/* Clock initialization */
clock_init();
/* Serial port initialization */
app_uart_init();
/* rf 2.4g initialization configuration */
rf24g_init();
/* Set testing frequency points */
rf_channel_hop[0] = XINCX_2_4G_CHANNEL - rf_channel_base;
rf_set_channel(rf_channel_base + rf_channel_hop[0]);
#if (XINCX_RF_TRANS_RATE == DR_2M)
/* Set 2M mode register configuration */
/* Don't move this function interface */
rf_2M_config();
#endif //(XINCX_RF_TRANS_RATE == DR_2M)
#ifdef DEBUG_LOG
/* Register information printing */
rf_dump_log();
#endif // DEBUG_LOG
#if XINCX_RF_MODE
#if (XINCX_RF_NVIC_MODE)
/* Enable RF2.4G interrupts */
NVIC_EnableIRQ(RF24G_IRQn);
/* Configure the RF2.4G interrupt priority */
NVIC_SetPriority(RF24G_IRQn, 0);
#endif // XINCX_RF_NVIC_MODE
/* Set emission interval */
timer_init(RF_RX_TIMERx, RECV_TIMERMS_OUT);
/* RX enters receiver */
CE_CTL_HIGH;
#else
tx_len = BUFF_LEN;
/* Set emission interval */
timer_init(RF_TX_TIMERx, SEND_TIMERMS_CNT);
xc_timer_start(RF_TX_TIMERx);
#endif // XINCX_RF_MODE
for (;;) {
#if XINCX_RF_MODE
/* receive */
rf_rx_manage();
if (rf_recv_timer_flag) {
rf_recv_timer_flag = false;
recv_hop_num++;
// RX retry XC_RETRY_NUM times in first hop cycle
if ((recv_hop_num % (XC_RETRY_NUM) == 0) && (recv_hop_num < XC_HOPPING_NUM * XC_RETRY_NUM)) {
rf_recv_hop();
}
// hopping XC_HOPPING_NUM
else if (recv_hop_num % (XC_HOPPING_NUM * XC_RETRY_NUM) == 0) {
rf_recv_hop();
}
}
#else
/* Launch data packaging filling */
rf_data_config(tx_buff, tx_len);
/* sending */
rf_tx_manage();
#endif // XINCX_RF_MODE
}
}