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Stair56E UART project

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This commit is contained in:
吴琪
2026-08-05 19:07:52 +08:00
parent 7ca1af130d
commit f5654b70cc
2500 changed files with 619007 additions and 282610 deletions
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project/example/2.4g/RF24_TEST_CMD/app/Startup/lora/startup_xinc.s
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;/*****************************************************************************
; * @file: startup_xinc.s
; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
; * Device xinc.
; *****************************************************************************/
Stack_Size EQU 0x00000600
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; ToDo: Add here the vectors for the device specific external interrupts handler
DCD 0 ; 0 BLE Handler
DCD DMAS_Handler ; 1
DCD CPR_Handler ; 2
DCD GPIO_Handler ; 3
DCD RTC_Handler ; 4
DCD TIMER0_Handler ; 5
DCD TIMER1_Handler
DCD TIMER2_Handler
DCD TIMER3_Handler
DCD WDT_Handler
DCD I2C_Handler
DCD UART0_Handler
DCD UART1_Handler
DCD SPI0_Handler
DCD SPI1_Handler
DCD 0
DCD 0
DCD GADC_Handler ; 17
DCD 0 ; 18
DCD 0 ; 19
DCD 0 ; 20
DCD 0 ; 21
DCD RF24G_Handler ; 22
DCD PWM_Handler ; 23
DCD BOR_Handler ; 24
DCD 0 ; 25
DCD 0 ; 26
DCD AOTIMER0_Handler ; 27
DCD AOTIMER1_Handler ; 28
DCD CMP_Handler ; 29
DCD FMC_Handler ; 30
DCD CAN_Handler ; 31
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR r0, =0x4000013C ; remap
LDR r1, =0x10000001
STR r1, [r0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
Default_Handler PROC
;EXPORT BLE_Handler [WEAK]
EXPORT DMAS_Handler [WEAK]
EXPORT CPR_Handler [WEAK]
EXPORT GPIO_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT TIMER2_Handler [WEAK]
EXPORT TIMER3_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT I2C_Handler [WEAK]
EXPORT UART0_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
EXPORT SPI0_Handler [WEAK]
EXPORT SPI1_Handler [WEAK]
;EXPORT KBS_Handler [WEAK]
;EXPORT QDEC_Handler [WEAK]
EXPORT GADC_Handler [WEAK]
EXPORT AOTIMER0_Handler [WEAK]
EXPORT AOTIMER1_Handler [WEAK]
EXPORT CMP_Handler [WEAK]
EXPORT FMC_Handler [WEAK]
EXPORT CAN_Handler [WEAK]
;EXPORT SIM_Handler [WEAK]
;EXPORT AES_Handler [WEAK]
EXPORT PendSV_Handler [WEAK]
EXPORT SysTick_Handler [WEAK]
EXPORT RF24G_Handler [WEAK]
EXPORT PWM_Handler [WEAK]
EXPORT BOR_Handler [WEAK]
PendSV_Handler
SysTick_Handler
;BLE_Handler
DMAS_Handler
CPR_Handler
GPIO_Handler
RTC_Handler
TIMER0_Handler
TIMER1_Handler
TIMER2_Handler
TIMER3_Handler
WDT_Handler
I2C_Handler
UART0_Handler
UART1_Handler
SPI0_Handler
SPI1_Handler
;KBS_Handler
;QDEC_Handler
GADC_Handler
;SIM_Handler
;AES_Handler
AOTIMER0_Handler
AOTIMER1_Handler
CMP_Handler
FMC_Handler
CAN_Handler
RF24G_Handler
PWM_Handler
BOR_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
END
project/example/2.4g/RF24_TEST_CMD/app/Startup/system_it_xinc.c
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/*!
* \file system_it_xinc.c
*
* \brief Target system interruption implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "system_it_xinc.h"
/*------------------------------------------------------------------------------------
Func Prototype
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
/**
****************************************************************************************
* @brief This function handles NMI exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void NMI_Handler(void)
{
/* USER CODE BEGIN NonMaskableInt_IRQn */
DEBUG("%s\n", __func__);
/* USER CODE END NonMaskableInt_IRQn */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles Hard Fault exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void HardFault_Handler(void)
{
/* USER CODE BEGIN HardFault_IRQn */
DEBUG("%s\n", __func__);
/* USER CODE END HardFault_IRQn */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles Memory Manage exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void MemManage_Handler(void)
{
/* USER CODE BEGIN */
DEBUG("%s\n", __func__);
/* USER CODE END */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles Bus Fault exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void BusFault_Handler(void)
{
/* USER CODE BEGIN */
DEBUG("%s\n", __func__);
/* USER CODE END */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles Usage Fault exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void UsageFault_Handler(void)
{
/* USER CODE BEGIN */
DEBUG("%s\n", __func__);
/* USER CODE END */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles SVCall exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void SVC_Handler(void)
{
/* USER CODE BEGIN SVCall_IRQn */
DEBUG("%s\n", __func__);
/* USER CODE END SVCall_IRQn */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles Debug Monitor exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void DebugMon_Handler(void)
{
/* USER CODE BEGIN */
DEBUG("%s\n", __func__);
/* USER CODE END */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles PendSVC exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void PendSV_Handler(void)
{
/* USER CODE BEGIN PendSV_IRQn */
DEBUG("%s\n", __func__);
/* USER CODE END PendSV_IRQn */
while (1)
{
}
}
/****************************** Hard Fault Handler Functions *******************************/
/*------------------------------------------------------------------------------------
Private Functions
-------------------------------------------------------------------------------------*/
void HardFault_Handler_c(unsigned int * HardFault_args)
{
/*栈帧里面内容：*/
unsigned int stack_r0; //压栈的 R0
unsigned int stack_r1; //压栈的 R1
unsigned int stack_r2; //压栈的 R2
unsigned int stack_r3; //压栈的 R3
unsigned int stack_r12; //压栈的 R12
unsigned int stack_lr; //压栈的 lr
unsigned int stack_pc; //压栈的 pc
unsigned int stack_psr; //压栈的 psr
stack_r0 = ((unsigned int)HardFault_args[0]);
stack_r1 = ((unsigned int)HardFault_args[1]);
stack_r2 = ((unsigned int)HardFault_args[2]);
stack_r3 = ((unsigned int)HardFault_args[3]);
stack_r12 = ((unsigned int)HardFault_args[4]);
stack_lr = ((unsigned int)HardFault_args[5]);
stack_pc = ((unsigned int)HardFault_args[6]);
stack_psr = ((unsigned int)HardFault_args[7]);
DEBUG("----%s----\n", __func__);
DEBUG("R0=%x\n",stack_r0);
DEBUG("R1=%x\n",stack_r1);
DEBUG("R2=%x\n",stack_r2);
DEBUG("R3=%x\n",stack_r3);
DEBUG("R12=%x\n",stack_r12);
DEBUG("LR[R14]=%x\n",stack_lr);
DEBUG("PC[R15]=%x\n",stack_pc);
DEBUG("PSR=%x\n",stack_psr);
DEBUG("SCB_SHCSR=%x\n",SCB->SHCSR);
DEBUG("---------------------------\n");
while(1);
}
/*******************************************************************************************/
project/example/2.4g/RF24_TEST_CMD/app/Startup/system_it_xinc.h
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/*!
* \file system_it_xinc.h
*
* \brief The header of system_it_xinc.c
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __SYSTEM_IT_XINC_H__
#define __SYSTEM_IT_XINC_H__
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "xc6xxx.h"
/*------------------------------------------------------------------------------------
Exported Functions
-------------------------------------------------------------------------------------*/
void NMI_Handler( void );
void HardFault_Handler( void );
void MemManage_Handler( void );
void BusFault_Handler( void );
void UsageFault_Handler( void );
void SVC_Handler( void );
void DebugMon_Handler( void );
void PendSV_Handler( void );
void HardFault_Handler_c(unsigned int * HardFault_args);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_IT_XINC_H__ */
project/example/2.4g/RF24_TEST_CMD/app/Startup/system_xinc.c
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/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system
*
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include <stdio.h>
#include "xc6xxx.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
#define __DEBUG_OUT_PORT 0
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
#define VECTOR_NUM 48
void set_vector(void)
{
#if (USE_XIP == 1)
__disable_irq();
for (uint32_t i = 0, *Pvector = (uint32_t *)(0x11001000 + 0),
*_vector_table = (uint32_t *)(0x10000000);
i < VECTOR_NUM; i++) // copy vertor table
{
_vector_table[i] = *Pvector++;
}
*((volatile unsigned int *)(0x4000013C)) =
0x10000001; // inter vertor table remap
__enable_irq();
#endif
}
static void WDT_ResetInit(void)
{
cpr_ctlapbclken_grctl__wdt_pclk_en__setf(ENABLE);
cpr_rstctl_ctlapb_sw__wdt_rstn__setf(RSTCTL_ENABLE);
cpr_rstctl_ctlapb_sw__wdt_rstn__setf(RSTCTL_DISABLE);
cpr_rstctl_wdtrst_mask_set(
(WDT_SYS_RSTN_MASK_DISABLE | WDT_M0_RSTN_MASK_ENABLE));
cpr_lp_ctl__wdt_tclk_en__setf(ENABLE);
wdt_cr__wdt_en__setf(DISABLE);
}
void SystemInit(void)
{
WDT_ResetInit();
#if (USE_XIP == 1)
set_vector();
#endif
}
__RAM_CODE int sendchar(int c)
{
unsigned int status;
#if (__DEBUG_OUT_PORT == 1)
for (;;) {
status = (*((volatile unsigned *)(0x40011000 + 0x14)));
status &= 0x20;
if (status == 0x20)
break;
}
(*((volatile unsigned *)(0x40011000 + 0x00))) = c;
return (1);
#else
for (;;) {
status = (*((volatile unsigned *)(0x40010000 + 0x14)));
status &= 0x20;
if (status == 0x20)
break;
}
(*((volatile unsigned *)(0x40010000 + 0x00))) = c;
return (1);
#endif
}
struct __FILE
{
int handle; /* Add whatever you need here */
};
FILE __stdout;
__RAM_CODE int fputc(int ch, FILE *f) { return (sendchar(ch)); }
int ferror(FILE *f)
{
/* Your implementation of ferror */
return EOF;
}
void _ttywrch(int ch) { sendchar(ch); }
void _sys_exit(int return_code)
{
label:
goto label; /* endless loop */
}
project/example/2.4g/RF24_TEST_CMD/app/Startup/xc60xx/startup_xinc.s
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;/*****************************************************************************
; * @file: startup_xinc.s
; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
; * Device xinc.
; *****************************************************************************/
Stack_Size EQU 0x00000800
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; ToDo: Add here the vectors for the device specific external interrupts handler
DCD BLE_Handler ; 0
DCD DMA_Handler ; 1
DCD CPR_Handler ; 2
DCD GPIO_Handler ; 3
DCD RTC_Handler ; 4
DCD TIMER0_Handler ; 5
DCD TIMER1_Handler ; 6
DCD TIMER2_Handler ; 7
DCD TIMER3_Handler ; 8
DCD WDT_Handler ; 9
DCD I2C_Handler ; 10
DCD UART0_Handler ; 11
DCD UART1_Handler ; 12
DCD SPI0_Handler ; 13
DCD SPI1_Handler ; 14
DCD 0 ; 15
DCD 0 ; 16
DCD GADC_Handler ; 17
DCD PWM_Handler ; 18
DCD AES_Handler ; 19
DCD USB_Handler ; 20
DCD AUDIO_Handler ; 21
DCD RF24G_Handler ; 22
DCD SPI2_Handler ; 23
DCD 0 ; 24
DCD UART2_Handler ; 25
DCD I2S_Handler ; 26
DCD AOTIMER0_Handler ; 27
DCD AOTIMER1_Handler ; 28
DCD CMP_Handler ; 29
DCD FMC_Handler ; 30
DCD CAN_Handler ; 31
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR r0, =0x4000013C ; remap
LDR r1, =0x10000001
STR r1, [r0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
IMPORT HardFault_Handler_c ;函数声明
movs r0, #4 ;判断主栈指针还是进程栈指针
mov r1, lr
tst r0, r1
beq hf_used_msp ;如果是主栈指针
mrs r0, psp ;否则是进程栈指针,把进程栈指针地址付给 R0
ldr r1, =HardFault_Handler_c ;跳转到 HardFault 中断程序
bx r1
hf_used_msp
mrs r0, msp ;把主栈指针地址赋给 R0
ldr r1, =HardFault_Handler_c
bx r1
;EXPORT HardFault_Handler [WEAK]
;B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT BLE_Handler [WEAK]
EXPORT DMA_Handler [WEAK]
EXPORT CPR_Handler [WEAK]
EXPORT GPIO_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT TIMER2_Handler [WEAK]
EXPORT TIMER3_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT I2C_Handler [WEAK]
EXPORT UART0_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
EXPORT SPI0_Handler [WEAK]
EXPORT SPI1_Handler [WEAK]
;EXPORT KBS_Handler [WEAK]
;EXPORT QDEC_Handler [WEAK]
EXPORT GADC_Handler [WEAK]
EXPORT PWM_Handler [WEAK]
EXPORT AES_Handler [WEAK]
EXPORT PendSV_Handler [WEAK]
EXPORT SysTick_Handler [WEAK]
EXPORT USB_Handler [WEAK];20
EXPORT AUDIO_Handler [WEAK];21
EXPORT RF24G_Handler [WEAK];22
EXPORT SPI2_Handler [WEAK];23
;EXPORT MPU_Handler [WEAK];24
EXPORT UART2_Handler [WEAK];25
EXPORT I2S_Handler [WEAK];26
EXPORT AOTIMER0_Handler [WEAK];27
EXPORT AOTIMER1_Handler [WEAK];28
EXPORT CMP_Handler [WEAK];29
EXPORT FMC_Handler [WEAK];30
EXPORT CAN_Handler [WEAK];31
PendSV_Handler
SysTick_Handler
BLE_Handler
RF24G_Handler
DMA_Handler
CPR_Handler
GPIO_Handler
RTC_Handler
TIMER0_Handler
TIMER1_Handler
TIMER2_Handler
TIMER3_Handler
WDT_Handler
I2C_Handler
I2S_Handler
UART0_Handler
UART1_Handler
UART2_Handler
SPI0_Handler
SPI1_Handler
SPI2_Handler
;KBS_Handler
;QDEC_Handler
GADC_Handler
PWM_Handler
AUDIO_Handler
;SIM_Handler
AES_Handler
AOTIMER0_Handler
AOTIMER1_Handler
CMP_Handler
FMC_Handler
CAN_Handler
USB_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
END
project/example/2.4g/RF24_TEST_CMD/app/Startup/xc60xx/startup_xinc_xc62xx.s
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;/*****************************************************************************
; * @file: startup_xinc_xc62xx.s
; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
; * Device xinc.
; *****************************************************************************/
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; ToDo: Add here the vectors for the device specific external interrupts handler
DCD BLE_Handler ; 0
DCD DMA_Handler ; 1
DCD CPR_Handler ; 2
DCD GPIO_Handler ; 3
DCD RTC_Handler ; 4
DCD TIMER0_Handler ; 5
DCD TIMER1_Handler ; 6
DCD TIMER2_Handler ; 7
DCD TIMER3_Handler ; 8
DCD WDT_Handler ; 9
DCD I2C_Handler ; 10
DCD UART0_Handler ; 11
DCD UART1_Handler ; 12
DCD SPI0_Handler ; 13
DCD SPI1_Handler ; 14
DCD 0 ; 15
DCD 0 ; 16
DCD GADC_Handler ; 17
DCD PWM_Handler ; 18
DCD AES_Handler ; 19
DCD USB_Handler ; 20
DCD AUDIO_Handler ; 21
DCD RF24G_Handler ; 22
DCD SPI2_Handler ; 23
DCD 0 ; 24
DCD UART2_Handler ; 25
DCD I2S_Handler ; 26
DCD AOTIMER0_Handler ; 27
DCD AOTIMER1_Handler ; 28
DCD CMP_Handler ; 29
DCD FMC_Handler ; 30
DCD CAN_Handler ; 31
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR r0, =0x4000013C ; remap
LDR r1, =0x10000001
STR r1, [r0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
IMPORT HardFault_Handler_c ;函数声明
movs r0, #4 ;判断主栈指针还是进程栈指针
mov r1, lr
tst r0, r1
beq hf_used_msp ;如果是主栈指针
mrs r0, psp ;否则是进程栈指针,把进程栈指针地址付给 R0
ldr r1, =HardFault_Handler_c ;跳转到 HardFault 中断程序
bx r1
hf_used_msp
mrs r0, msp ;把主栈指针地址赋给 R0
ldr r1, =HardFault_Handler_c
bx r1
;EXPORT HardFault_Handler [WEAK]
;B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT BLE_Handler [WEAK]
EXPORT DMA_Handler [WEAK]
EXPORT CPR_Handler [WEAK]
EXPORT GPIO_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT TIMER2_Handler [WEAK]
EXPORT TIMER3_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT I2C_Handler [WEAK]
EXPORT UART0_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
EXPORT SPI0_Handler [WEAK]
EXPORT SPI1_Handler [WEAK]
;EXPORT KBS_Handler [WEAK]
;EXPORT QDEC_Handler [WEAK]
EXPORT GADC_Handler [WEAK]
EXPORT PWM_Handler [WEAK]
EXPORT AES_Handler [WEAK]
EXPORT PendSV_Handler [WEAK]
EXPORT SysTick_Handler [WEAK]
EXPORT USB_Handler [WEAK];20
EXPORT AUDIO_Handler [WEAK];21
EXPORT RF24G_Handler [WEAK];22
EXPORT SPI2_Handler [WEAK];23
;EXPORT MPU_Handler [WEAK];24
EXPORT UART2_Handler [WEAK];25
EXPORT I2S_Handler [WEAK];26
EXPORT AOTIMER0_Handler [WEAK];27
EXPORT AOTIMER1_Handler [WEAK];28
EXPORT CMP_Handler [WEAK];29
EXPORT FMC_Handler [WEAK];30
EXPORT CAN_Handler [WEAK];31
PendSV_Handler
SysTick_Handler
BLE_Handler
RF24G_Handler
DMA_Handler
CPR_Handler
GPIO_Handler
RTC_Handler
TIMER0_Handler
TIMER1_Handler
TIMER2_Handler
TIMER3_Handler
WDT_Handler
I2C_Handler
I2S_Handler
UART0_Handler
UART1_Handler
UART2_Handler
SPI0_Handler
SPI1_Handler
SPI2_Handler
;KBS_Handler
;QDEC_Handler
GADC_Handler
PWM_Handler
AUDIO_Handler
;SIM_Handler
AES_Handler
AOTIMER0_Handler
AOTIMER1_Handler
CMP_Handler
FMC_Handler
CAN_Handler
USB_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
END
project/example/2.4g/RF24_TEST_CMD/app/api/app_rf24g.h
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/*
* @Descripttion:
* @version:
* @Author: sueRimn
* @Date: 2023-12-21 10:56:45
* @LastEditors: sueRimn
* @LastEditTime: 2023-12-29 19:42:40
*/
#ifndef __APP_RF24G_EVENT_H__
#define __APP_RF24G_EVENT_H__
#include "xc6xxx_rf_ADV.h"
#define ADV_LENGTH XINCX_ADV_PIPE0_LEN
#define XC_RF_SEND_TIMER TIMER0_IDX
#define XC_SEND_NUM 1000U
#define SEND_TIMERMS_CNT 10U
#define RF_CONFIRMED_VALUE 5U
#ifdef RF_ADV_INTER
extern uint8_t recv_adv_buf[XINCX_ADV_PIPE0_LEN];
#endif
extern uint32_t tx_cnt, rx_cnt;
#define RF_ADV_BASE 2400U
#define RF_ADV_CHANNEL_37 2
#define RF_ADV_CHANNEL_38 26
#define RF_ADV_CHANNEL_39 80
void timer_init(uint8_t timer_id, uint32_t timer_cnt);
uint8_t rf_data_config(uint8_t *buff, uint8_t len);
uint32_t rf_ack_tx_manage(uint8_t *buff);
uint32_t rf_ack_rx_manage(uint8_t *buff);
uint8_t rf_adv_packet(uint8_t *buff);
void rf_adv_tx_evevt(void);
void rf_adv_rx_evevt(void);
//extern rf_data_typedef_t rf_data;
#endif //__APP_RF24G_EVENT_H__
project/example/2.4g/RF24_TEST_CMD/app/api/main.h
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/*
* @Descripttion:
* @version:
* @Author: sueRimn
* @Date: 2023-12-12 14:23:55
* @LastEditors: sueRimn
* @LastEditTime: 2024-06-07 13:46:09
*/
/*!
* \file main.h
*
* \brief The head file of main.c
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MAIN_H__
#define __MAIN_H__
#ifdef __cplusplus
extern "C"
{
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "rf_config.h"
#include "xc6xxx.h"
#include "xc6xxx_rf_2_4g.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
#define DEBUG_LOG
#define RECV_TIMERMS_OUT 1000
//#define SEND_TIMERMS_CNT 30
#define XC_SEND_NUM 1000U
#define RF_TX_TIMERx TIMER0_IDX
#define RF_RX_TIMERx TIMER0_IDX
//#define RF_CONFIRMED_VALUE 5
/*------------------------------------------------------------------------------------
TypeDef
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Global Variables
-------------------------------------------------------------------------------------*/
extern uint16_t recv_len;
extern uint8_t recv_buf[256];
extern bool rf_send_timer_flag;
extern bool rf24g_handler_flag;
/*------------------------------------------------------------------------------------
Exported Functions
-------------------------------------------------------------------------------------*/
uint32_t rf_tx_manage(uint8_t *buff);
uint32_t rf_rx_manage(uint8_t *buff);
void rf_buff_info(uint8_t *buff, uint8_t len);
void rf_2M_reg_info(void);
void rf_dump_log(void);
uint8_t rf_data_config(uint8_t *buff, uint8_t len);
#ifdef __cplusplus
}
#endif
#endif /* __MAIN_H__ */
project/example/2.4g/RF24_TEST_CMD/app/rf_adv_config/rf_adv_config.h
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#ifndef SDK_ADV_CONFIG_H
#define SDK_ADV_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>\n
// <h> Xinc_RF
// <o> XINCX_ADV_MODE - RF Tx or Rx Mode
// <0=> TX Mode
// <1=> RX Mode
#ifndef XINCX_ADV_MODE
#define XINCX_ADV_MODE 0
#endif
// <o> XINCX_ADV_ADDR_L - rf Address Set
#ifndef XINCX_ADV_ADDR_L
#define XINCX_ADV_ADDR_L 0x71917d6b
#endif
// <o> XINCX_ADV_ADDR_H - rf Address Set
#ifndef XINCX_ADV_ADDR_H
#define XINCX_ADV_ADDR_H 0x00
#endif
// <o> XINCX_ADV_CHANNEL - ADV Channel Set
// <2402=> ADV_CHANNEL_37
// <2426=> ADV_CHANNEL_38
// <2480=> ADV_CHANNEL_39
#ifndef XINCX_ADV_CHANNEL
#define XINCX_ADV_CHANNEL 2402
#endif
// <o> XINCX_RF_POWER - rf Power Set
#ifndef XINCX_POWER
#define XINCX_POWER 0x08
#endif
// <o> XINCX_RF_NVIC_MODE - RF NVIC Mode
// <0=> Disable
// <1=> Enable
#ifndef XINCX_RF_ADV_NVIC_MODE
#define XINCX_RF_ADV_NVIC_MODE 0
#endif
// <o> XINCX_RF_TX_ADDR_WIDTH - RF Tx Addr Width
// <4=> 4 Bytes
#ifndef XINCX_RF_TX_ADDR_WIDTH
#define XINCX_RF_TX_ADDR_WIDTH 4
#endif
// <o> XINCX_RF_TRANS_RATE - RF Transmission Rate Config
// <0x02=> 1M
#ifndef XINCX_RF_TRANS_RATE
#define XINCX_RF_TRANS_RATE 0x02
#endif
// <e> XINCX_RF_CRC_ENABLE - RF CRC Enable
//==========================================================
#ifndef XINCX_RF_CRC_ENABLE
#define XINCX_RF_CRC_ENABLE 0
#endif
// </e>
// <o> XINCX_RF_CRC_BIT - RF CRC Bits Set
// <1=> 1 Bit
// <2=> 2 Bits
#ifndef XINCX_RF_CRC_BIT
#define XINCX_RF_CRC_BIT 2
#endif
// <h> XINCX_ADV_FEATURE_PARAM - ADV Feature Parameters
//==========================================================
// <q> XINCX_ADV_LONG_PLD - ADV Long Payload Feature
#ifndef XINCX_ADV_LONG_PLD
#define XINCX_ADV_LONG_PLD 1
#endif
// <q> XINCX_ADV_FEC - ADV FEC&Interleave Feature
#ifndef XINCX_ADV_FEC
#define XINCX_ADV_FEC 0
#endif
// <q> XINCX_ADV_WHITEN - ADV Whiten Feature
#ifndef XINCX_ADV_WHITEN
#define XINCX_ADV_WHITEN 0
#endif
// <q> XINCX_ADV_DPL - ADV Dynamic Payload Length Feature
#ifndef XINCX_ADV_DPL
#define XINCX_ADV_DPL 0
#endif
// <q> XINCX_ADV_ACK_PAY - 2.4g Payload on ACK
#ifndef XINCX_ADV_ACK_PAY
#define XINCX_ADV_ACK_PAY 1
#endif
// <q> XINCX_ADV_DYN_ACK - 2.4g W_TX_PAYLOAD_NOACK Command
#ifndef XINCX_ADV_DYN_ACK
#define XINCX_ADV_DYN_ACK 0
#endif
// </h>
// <h> XINCX_PIPE_PIPE_RX_PAYLEN - ADV Pipe Rx Payload Len
//==========================================================
// <o> XINCX_ADV_PIPE0_LEN - ADV Pipe0 Rx Payload Len
#ifndef XINCX_ADV_PIPE0_LEN
#define XINCX_ADV_PIPE0_LEN 42
#endif
// <o> XINCX_ADV_PIPE1_LEN - ADV Pipe1 Rx Payload Len
#ifndef XINCX_ADV_PIPE1_LEN
#define XINCX_ADV_PIPE1_LEN 0
#endif
// <o> XINCX_ADV_PIPE2_LEN - ADV Pipe2 Rx Payload Len
#ifndef XINCX_ADV_PIPE2_LEN
#define XINCX_ADV_PIPE2_LEN 0
#endif
// <o> XINCX_ADV_PIPE3_LEN - ADV Pipe3 Rx Payload Len
#ifndef XINCX_ADV_PIPE3_LEN
#define XINCX_ADV_PIPE3_LEN 0
#endif
// <o> XINCX_ADV_PIPE4_LEN - ADV Pipe4 Rx Payload Len
#ifndef XINCX_ADV_PIPE4_LEN
#define XINCX_ADV_PIPE4_LEN 0
#endif
// <o> XINCX_ADV_PIPE5_LEN - ADV Pipe5 Rx Payload Len
#ifndef XINCX_ADV_PIPE5_LEN
#define XINCX_ADV_PIPE5_LEN 0
#endif
// </h>
// <h> XINC_ADV_MAC_ADDR
// <o> XINC_ADV_MAC_ADDR_0
#ifndef XINC_ADV_MAC_ADDR_0
#define XINC_ADV_MAC_ADDR_0 0xa6
#endif
// <o> XINC_ADV_MAC_ADDR_1
#ifndef XINC_ADV_MAC_ADDR_1
#define XINC_ADV_MAC_ADDR_1 0xa5
#endif
// <o> XINC_ADV_MAC_ADDR_2
#ifndef XINC_ADV_MAC_ADDR_2
#define XINC_ADV_MAC_ADDR_2 0xa4
#endif
// <o> XINC_ADV_MAC_ADDR_3
#ifndef XINC_ADV_MAC_ADDR_3
#define XINC_ADV_MAC_ADDR_3 0xa3
#endif
// <o> XINC_ADV_MAC_ADDR_4
#ifndef XINC_ADV_MAC_ADDR_4
#define XINC_ADV_MAC_ADDR_4 0xa2
#endif
// <o> XINC_ADV_MAC_ADDR_5
#ifndef XINC_ADV_MAC_ADDR_5
#define XINC_ADV_MAC_ADDR_5 0xc1
#endif
// </h>
// </h>
// <<< end of configuration section >>>
#endif
project/example/2.4g/RF24_TEST_CMD/app/rf_adv_config/rf_config.h
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#ifndef SDK_CONFIG_H
#define SDK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>\n
// <h> Xinc_RF
// <o> XINCX_RF_MODE - RF Tx or Rx Mode
// <0=> TX Mode
// <1=> RX Mode
#ifndef XINCX_RF_MODE
#define XINCX_RF_MODE 0
#endif
// <o> XINCX_2_4G_ADDR_L - rf Address Set
#ifndef XINCX_2_4G_ADDR_L
#define XINCX_2_4G_ADDR_L 0xE7E7E7E6
#endif
// <o> XINCX_2_4G_ADDR_H - rf Address Set
#ifndef XINCX_2_4G_ADDR_H
#define XINCX_2_4G_ADDR_H 0xEA
#endif
// <h> XINCX_2_4G_AUTO_ACK - 2.4g Auto Acknowledgement
//==========================================================
// <o> XINCX_2_4G_PIPE0_ENAA - 2.4g Pipe0 Auto Ack
// <0=> Disable
// <1=> Enable
#ifndef XINCX_2_4G_PIPE0_ENAA
#define XINCX_2_4G_PIPE0_ENAA 1
#endif
// <o> XINCX_2_4G_PIPE1_ENAA - 2.4g Pipe1 Auto Ack
// <0=> Disable
// <1=> Enable
#ifndef XINCX_2_4G_PIPE1_ENAA
#define XINCX_2_4G_PIPE1_ENAA 1
#endif
// <o> XINCX_2_4G_PIPE2_ENAA - 2.4g Pipe2 Auto Ack
// <0=> Disable
// <1=> Enable
#ifndef XINCX_2_4G_PIPE2_ENAA
#define XINCX_2_4G_PIPE2_ENAA 1
#endif
// <o> XINCX_2_4G_PIPE3_ENAA - 2.4g Pipe3 Auto Ack
// <0=> Disable
// <1=> Enable
#ifndef XINCX_2_4G_PIPE3_ENAA
#define XINCX_2_4G_PIPE3_ENAA 1
#endif
// <o> XINCX_2_4G_PIPE4_ENAA - 2.4g Pipe4 Auto Ack
// <0=> Disable
// <1=> Enable
#ifndef XINCX_2_4G_PIPE4_ENAA
#define XINCX_2_4G_PIPE4_ENAA 1
#endif
// <o> XINCX_2_4G_PIPE5_ENAA - 2.4g Pipe5 Auto Ack
// <0=> Disable
// <1=> Enable
#ifndef XINCX_2_4G_PIPE5_ENAA
#define XINCX_2_4G_PIPE5_ENAA 1
#endif
// </h>
// <o> XINCX_RF_POWER - rf Power Set
#ifndef XINCX_POWER
#define XINCX_POWER 0x00008
#endif
// <o> XINCX_2_4G_CHANNEL - 2.4g Channel Set
#ifndef XINCX_2_4G_CHANNEL
#define XINCX_2_4G_CHANNEL 2350
#endif
// <o> XINCX_RF_NVIC_MODE - RF NVIC Mode
// <0=> Disable
// <1=> Enable
#ifndef XINCX_RF_NVIC_MODE
#define XINCX_RF_NVIC_MODE 0
#endif
// <o> XINCX_RF_TX_ADDR_WIDTH - RF Tx Addr Width
// <3=> 3 Bytes
// <4=> 4 Bytes
// <5=> 5 Bytes
#ifndef XINCX_RF_TX_ADDR_WIDTH
#define XINCX_RF_TX_ADDR_WIDTH 5
#endif
// <o> XINCX_RF_TRANS_RATE - RF Transmission Rate Config
// <0x02=> 1M
// <0x0A=> 2M
// <0x22=> 250k
// <0x2A=> 125k
#ifndef XINCX_RF_TRANS_RATE
#define XINCX_RF_TRANS_RATE 0x02
#endif
// <e> XINCX_RF_CRC_ENABLE - RF CRC Enable
//==========================================================
#ifndef XINCX_RF_CRC_ENABLE
#define XINCX_RF_CRC_ENABLE 1
#endif
// <o> XINCX_2_4G_CRC_BYTE - 2.4g CRC Bytes Set
// <1=> 1 Byte
// <2=> 2 Bytes
#ifndef XINCX_2_4G_CRC_BYTE
#define XINCX_2_4G_CRC_BYTE 2
#endif
// </e>
// <h> XINCX_2_4G_FEATURE_PARAM - 2.4g Feature Parameters
//==========================================================
// <q> XINCX_2_4G_GUARD_CFG - 2.4g Long Payload Feature
#ifndef XINCX_2_4G_GUARD_CFG
#define XINCX_2_4G_GUARD_CFG 0
#endif
// <q> XINCX_2_4G_LONG_PLD_TYPE - 2.4g Long Pld Type
#ifndef XINCX_2_4G_LONG_PLD_TYPE
#define XINCX_2_4G_LONG_PLD_TYPE 0
#endif
// <q> XINCX_2_4G_PREAMBLE_NUM - 2.4g Preamble
// <o> XINCX_2_4G_PREAMBLE_NUM
// <0=> 1 Byte
// <1=> 2 Bytes
// <2=> 3 Bytes
// <3=> 4 Bytes
#ifndef XINCX_2_4G_PREAMBLE_NUM
#define XINCX_2_4G_PREAMBLE_NUM 0
#endif
// <q> XINCX_2_4G_PREAMBLE_TYPE - 2.4g Preamble Type
#ifndef XINCX_2_4G_PREAMBLE_TYPE
#define XINCX_2_4G_PREAMBLE_TYPE 0
#endif
// <q> XINCX_2_4G_CRC_SCOPE_GUARD - 2.4g CRC Scope Guard
#ifndef XINCX_2_4G_CRC_SCOPE_GUARD
#define XINCX_2_4G_CRC_SCOPE_GUARD 0
#endif
// <q> XINCX_2_4G_CRC_SCOPE_HEADER - 2.4g CRC Scope Header
#ifndef XINCX_2_4G_CRC_SCOPE_HEADER
#define XINCX_2_4G_CRC_SCOPE_HEADER 1
#endif
// <q> XINCX_2_4G_CRC_SCOPE_ADDR - 2.4g CRC Scope Addr
#ifndef XINCX_2_4G_CRC_SCOPE_ADDR
#define XINCX_2_4G_CRC_SCOPE_ADDR 1
#endif
// <q> XINCX_2_4G_LONG_PLD - 2.4g Long Payload Feature
#ifndef XINCX_2_4G_LONG_PLD
#define XINCX_2_4G_LONG_PLD 0
#endif
// <q> XINCX_2_4G_FEC - 2.4g FEC&Interleave Feature
#ifndef XINCX_2_4G_FEC
#define XINCX_2_4G_FEC 1
#endif
// <q> XINCX_2_4G_WHITEN - 2.4g Whiten Feature
#ifndef XINCX_2_4G_WHITEN
#define XINCX_2_4G_WHITEN 1
#endif
// <q> XINCX_2_4G_DPL - 2.4g Dynamic Payload Length Feature
#ifndef XINCX_2_4G_DPL
#define XINCX_2_4G_DPL 1
#endif
// <q> XINCX_2_4G_ACK_PAY - 2.4g Payload on ACK
#ifndef XINCX_2_4G_ACK_PAY
#define XINCX_2_4G_ACK_PAY 0
#endif
// <q> XINCX_2_4G_DYN_ACK - 2.4g W_TX_PAYLOAD_NOACK Command
#ifndef XINCX_2_4G_DYN_ACK
#define XINCX_2_4G_DYN_ACK 0
#endif
// </h>
// </h>
// <h> XINCX_2_4G_DYNPD - 2.4g dynpd
//==========================================================
// <o> XINCX_2_4G_DYNPD - 2.4g dynpd
#ifndef XINCX_2_4G_DYNPD
#define XINCX_2_4G_DYNPD 0x3f
#endif
// </h>
// <h> XINCX_2_4G_CRY_CPT_ARRAY - 2.4g Crystal capacitor array
//==========================================================
// <o> XINCX_2_4G_CRY_CPT_ARRAY - 2.4g Crystal capacitor array
#ifndef XINCX_2_4G_CRY_CPT_ARRAY
#ifdef XC62XX
#define XINCX_2_4G_CRY_CPT_ARRAY 0x38
#else
#define XINCX_2_4G_CRY_CPT_ARRAY 0x36
#endif
#endif
// </h>
// <h> XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
//==========================================================
// <o> XINCX_2_4G_RETRANS_CNT - 2.4g Retransmit Count
#ifndef XINCX_2_4G_RETRANS_CNT
#define XINCX_2_4G_RETRANS_CNT 0
#endif
// <o> XINCX_2_4G_RETRANS_DELAY - 2.4g Retransmission Delay
#ifndef XINCX_2_4G_RETRANS_DELAY
#define XINCX_2_4G_RETRANS_DELAY 3
#endif
// <h> XINCX_2_4G_PIPE_RX_PAYLEN - 2.4g Pipe Rx Payload Len
//==========================================================
// <o> - 2.4g Pipe0 Rx Payload Len
#ifndef XINCX_2_4G_PIPE0_LEN
#define XINCX_2_4G_PIPE0_LEN 32
#endif
// <o> XINCX_2_4G_PIPE1_LEN - 2.4g Pipe1 Rx Payload Len
#ifndef XINCX_2_4G_PIPE1_LEN
#define XINCX_2_4G_PIPE1_LEN 32
#endif
// <o> XINCX_2_4G_PIPE2_LEN - 2.4g Pipe2 Rx Payload Len
#ifndef XINCX_2_4G_PIPE2_LEN
#define XINCX_2_4G_PIPE2_LEN 32
#endif
// <o> XINCX_2_4G_PIPE3_LEN - 2.4g Pipe3 Rx Payload Len
#ifndef XINCX_2_4G_PIPE3_LEN
#define XINCX_2_4G_PIPE3_LEN 32
#endif
// <o> XINCX_2_4G_PIPE4_LEN - 2.4g Pipe4 Rx Payload Len
#ifndef XINCX_2_4G_PIPE4_LEN
#define XINCX_2_4G_PIPE4_LEN 32
#endif
// <o> XINCX_2_4G_PIPE5_LEN - 2.4g Pipe5 Rx Payload Len
#ifndef XINCX_2_4G_PIPE5_LEN
#define XINCX_2_4G_PIPE5_LEN 32
#endif
// </h>
// </h>
// <<< end of configuration section >>>
#endif
project/example/2.4g/RF24_TEST_CMD/app/rf_config/rf_config.h
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#ifndef SDK_CONFIG_H
#define SDK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>\n
// <h> Xinc_RF
// <o> XINCX_RF_MODE - RF Tx or Rx Mode
// <0=> TX Mode
// <1=> RX Mode
#ifndef XINCX_RF_MODE
#define XINCX_RF_MODE 0
#endif
// <o> XINCX_2_4G_ADDR_L - rf Address Set
#ifndef XINCX_2_4G_ADDR_L
#define XINCX_2_4G_ADDR_L 0xE7E7E7E6
#endif
// <o> XINCX_2_4G_ADDR_H - rf Address Set
#ifndef XINCX_2_4G_ADDR_H
#define XINCX_2_4G_ADDR_H 0xEA
#endif
// <h> XINCX_2_4G_AUTO_ACK - 2.4g Auto Acknowledgement
//==========================================================
// <o> XINCX_2_4G_PIPE0_ENAA - 2.4g Pipe0 Auto Ack
// <0=> Disable
// <1=> Enable
#ifndef XINCX_2_4G_PIPE0_ENAA
#define XINCX_2_4G_PIPE0_ENAA 1
#endif
// <o> XINCX_2_4G_PIPE1_ENAA - 2.4g Pipe1 Auto Ack
// <0=> Disable
// <1=> Enable
#ifndef XINCX_2_4G_PIPE1_ENAA
#define XINCX_2_4G_PIPE1_ENAA 1
#endif
// <o> XINCX_2_4G_PIPE2_ENAA - 2.4g Pipe2 Auto Ack
// <0=> Disable
// <1=> Enable
#ifndef XINCX_2_4G_PIPE2_ENAA
#define XINCX_2_4G_PIPE2_ENAA 1
#endif
// <o> XINCX_2_4G_PIPE3_ENAA - 2.4g Pipe3 Auto Ack
// <0=> Disable
// <1=> Enable
#ifndef XINCX_2_4G_PIPE3_ENAA
#define XINCX_2_4G_PIPE3_ENAA 1
#endif
// <o> XINCX_2_4G_PIPE4_ENAA - 2.4g Pipe4 Auto Ack
// <0=> Disable
// <1=> Enable
#ifndef XINCX_2_4G_PIPE4_ENAA
#define XINCX_2_4G_PIPE4_ENAA 1
#endif
// <o> XINCX_2_4G_PIPE5_ENAA - 2.4g Pipe5 Auto Ack
// <0=> Disable
// <1=> Enable
#ifndef XINCX_2_4G_PIPE5_ENAA
#define XINCX_2_4G_PIPE5_ENAA 1
#endif
// </h>
// <o> XINCX_RF_POWER - rf Power Set
#ifndef XINCX_POWER
#define XINCX_POWER 0x00008
#endif
// <o> XINCX_2_4G_CHANNEL - 2.4g Channel Set
#ifndef XINCX_2_4G_CHANNEL
#define XINCX_2_4G_CHANNEL 2410
#endif
// <o> XINCX_RF_NVIC_MODE - RF NVIC Mode
// <0=> Disable
// <1=> Enable
#ifndef XINCX_RF_NVIC_MODE
#define XINCX_RF_NVIC_MODE 0
#endif
// <o> XINCX_RF_TX_ADDR_WIDTH - RF Tx Addr Width
// <3=> 3 Bytes
// <4=> 4 Bytes
// <5=> 5 Bytes
#ifndef XINCX_RF_TX_ADDR_WIDTH
#define XINCX_RF_TX_ADDR_WIDTH 5
#endif
// <o> XINCX_RF_TRANS_RATE - RF Transmission Rate Config
// <0x02=> 1M
// <0x0A=> 2M
// <0x22=> 250k
// <0x2A=> 125k
#ifndef XINCX_RF_TRANS_RATE
#define XINCX_RF_TRANS_RATE 0x02
#endif
// <e> XINCX_RF_CRC_ENABLE - RF CRC Enable
//==========================================================
#ifndef XINCX_RF_CRC_ENABLE
#define XINCX_RF_CRC_ENABLE 1
#endif
// <o> XINCX_2_4G_CRC_BYTE - 2.4g CRC Bytes Set
// <1=> 1 Byte
// <2=> 2 Bytes
#ifndef XINCX_2_4G_CRC_BYTE
#define XINCX_2_4G_CRC_BYTE 2
#endif
// </e>
// <h> XINCX_2_4G_FEATURE_PARAM - 2.4g Feature Parameters
//==========================================================
// <q> XINCX_2_4G_GUARD_CFG - 2.4g Long Payload Feature
#ifndef XINCX_2_4G_GUARD_CFG
#define XINCX_2_4G_GUARD_CFG 0
#endif
// <q> XINCX_2_4G_LONG_PLD_TYPE - 2.4g Long Pld Type
#ifndef XINCX_2_4G_LONG_PLD_TYPE
#define XINCX_2_4G_LONG_PLD_TYPE 0
#endif
// <q> XINCX_2_4G_PREAMBLE_NUM - 2.4g Preamble
// <o> XINCX_2_4G_PREAMBLE_NUM
// <0=> 1 Byte
// <1=> 2 Bytes
// <2=> 3 Bytes
// <3=> 4 Bytes
#ifndef XINCX_2_4G_PREAMBLE_NUM
#define XINCX_2_4G_PREAMBLE_NUM 0
#endif
// <q> XINCX_2_4G_PREAMBLE_TYPE - 2.4g Preamble Type
#ifndef XINCX_2_4G_PREAMBLE_TYPE
#define XINCX_2_4G_PREAMBLE_TYPE 0
#endif
// <q> XINCX_2_4G_CRC_SCOPE_GUARD - 2.4g CRC Scope Guard
#ifndef XINCX_2_4G_CRC_SCOPE_GUARD
#define XINCX_2_4G_CRC_SCOPE_GUARD 0
#endif
// <q> XINCX_2_4G_CRC_SCOPE_HEADER - 2.4g CRC Scope Header
#ifndef XINCX_2_4G_CRC_SCOPE_HEADER
#define XINCX_2_4G_CRC_SCOPE_HEADER 1
#endif
// <q> XINCX_2_4G_CRC_SCOPE_ADDR - 2.4g CRC Scope Addr
#ifndef XINCX_2_4G_CRC_SCOPE_ADDR
#define XINCX_2_4G_CRC_SCOPE_ADDR 1
#endif
// <q> XINCX_2_4G_LONG_PLD - 2.4g Long Payload Feature
#ifndef XINCX_2_4G_LONG_PLD
#define XINCX_2_4G_LONG_PLD 0
#endif
// <q> XINCX_2_4G_FEC - 2.4g FEC&Interleave Feature
#ifndef XINCX_2_4G_FEC
#define XINCX_2_4G_FEC 1
#endif
// <q> XINCX_2_4G_WHITEN - 2.4g Whiten Feature
#ifndef XINCX_2_4G_WHITEN
#define XINCX_2_4G_WHITEN 1
#endif
// <q> XINCX_2_4G_DPL - 2.4g Dynamic Payload Length Feature
#ifndef XINCX_2_4G_DPL
#define XINCX_2_4G_DPL 0
#endif
// <q> XINCX_2_4G_ACK_PAY - 2.4g Payload on ACK
#ifndef XINCX_2_4G_ACK_PAY
#define XINCX_2_4G_ACK_PAY 0
#endif
// <q> XINCX_2_4G_DYN_ACK - 2.4g W_TX_PAYLOAD_NOACK Command
#ifndef XINCX_2_4G_DYN_ACK
#define XINCX_2_4G_DYN_ACK 0
#endif
// </h>
// </h>
// <h> XINCX_2_4G_PREAMBLE - 2.4g preamble
//==========================================================
// <o> XINCX_2_4G_PREAMBLE - 2.4g preamble
#ifndef XINCX_2_4G_PREAMBLE
#define XINCX_2_4G_PREAMBLE 0x710f5555
#endif
// </h>
// <h> XINCX_2_4G_GUARD - 2.4g guard
//==========================================================
// <o> XINCX_2_4G_GUARD - 2.4g guard
#ifndef XINCX_2_4G_GUARD
#define XINCX_2_4G_GUARD 0x8fc9
#endif
// </h>
// <h> XINCX_2_4G_DYNPD - 2.4g dynpd
//==========================================================
// <o> XINCX_2_4G_DYNPD - 2.4g dynpd
#ifndef XINCX_2_4G_DYNPD
#define XINCX_2_4G_DYNPD 0x3f
#endif
// </h>
// <h> XINCX_2_4G_CRY_CPT_ARRAY - 2.4g Crystal capacitor array
//==========================================================
// <o> XINCX_2_4G_CRY_CPT_ARRAY - 2.4g Crystal capacitor array
#ifndef XINCX_2_4G_CRY_CPT_ARRAY
#ifdef XC62XX
#define XINCX_2_4G_CRY_CPT_ARRAY 0x38
#else
#define XINCX_2_4G_CRY_CPT_ARRAY 0x36
#endif
#endif
// </h>
// <h> XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
//==========================================================
// <o> XINCX_2_4G_RETRANS_CNT - 2.4g Retransmit Count
#ifndef XINCX_2_4G_RETRANS_CNT
#define XINCX_2_4G_RETRANS_CNT 0
#endif
// <o> XINCX_2_4G_RETRANS_DELAY - 2.4g Retransmission Delay
#ifndef XINCX_2_4G_RETRANS_DELAY
#define XINCX_2_4G_RETRANS_DELAY 3
#endif
// <h> XINCX_2_4G_PIPE_RX_PAYLEN - 2.4g Pipe Rx Payload Len
//==========================================================
// <o> - 2.4g Pipe0 Rx Payload Len
#ifndef XINCX_2_4G_PIPE0_LEN
#define XINCX_2_4G_PIPE0_LEN 32
#endif
// <o> XINCX_2_4G_PIPE1_LEN - 2.4g Pipe1 Rx Payload Len
#ifndef XINCX_2_4G_PIPE1_LEN
#define XINCX_2_4G_PIPE1_LEN 32
#endif
// <o> XINCX_2_4G_PIPE2_LEN - 2.4g Pipe2 Rx Payload Len
#ifndef XINCX_2_4G_PIPE2_LEN
#define XINCX_2_4G_PIPE2_LEN 32
#endif
// <o> XINCX_2_4G_PIPE3_LEN - 2.4g Pipe3 Rx Payload Len
#ifndef XINCX_2_4G_PIPE3_LEN
#define XINCX_2_4G_PIPE3_LEN 32
#endif
// <o> XINCX_2_4G_PIPE4_LEN - 2.4g Pipe4 Rx Payload Len
#ifndef XINCX_2_4G_PIPE4_LEN
#define XINCX_2_4G_PIPE4_LEN 32
#endif
// <o> XINCX_2_4G_PIPE5_LEN - 2.4g Pipe5 Rx Payload Len
#ifndef XINCX_2_4G_PIPE5_LEN
#define XINCX_2_4G_PIPE5_LEN 32
#endif
// </h>
// <o> XINCX_RF_PIPE_ENABLE
#ifndef XINCX_RF_PIPE_ENABLE
#define XINCX_RF_PIPE_ENABLE 1
#endif
// </h>
// <<< end of configuration section >>>
#endif
project/example/2.4g/RF24_TEST_CMD/app/rf_single_config/rf_single_config.h
+79
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#ifndef SDK_SINGLE_CONFIG_H
#define SDK_SINGLE_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <o> XINCX_2_4G_CHANNEL_SINGLE - 2.4g Channel Set
#ifndef XINCX_2_4G_CHANNEL_SINGLE
#define XINCX_2_4G_CHANNEL_SINGLE 2440
#endif
// <o> XINCX_POWER_SINGLE - rf Power Set
// <1=> -10dbm
// <2=> -9dbm
// <4=> -4dbm
// <6=> 0dbm
// <8=> 3dbm
// <9=> 5dbm
// <12=> 7dbm
// <14=> 8dbm
// <16=> 9dbm
// <19=> 10dbm
// <24=> 11dbm
// <30=> 12dbm
// <36=> 13dbm
#ifndef XINCX_POWER_SINGLE
#define XINCX_POWER_SINGLE 0x00006
#endif
// <o> XINCX_2_4G_FREQ_DEV - 2.4g freq dev
//<0x0=> 0 k
//<0x8=> 10 k
//<0x10=> 20 k
//<0x19=> 30 k
//<0x21=> 40 k
//<0x29=> 50 k
//<0x31=> 60 k
//<0x39=> 70 k
//<0x42=> 80 k
//<0x4a=> 90 k
//<0x52=> 100 k
//<0x5a=> 110 k
//<0x62=> 120 k
//<0x6b=> 130 k
//<0x73=> 140 k
//<0x7b=> 150 k
//<0x83=> 160 k
//<0x8b=> 170 k
//<0x94=> 180 k
//<0x9c=> 190 k
//<0xa4=> 200 k
//<0xac=> 210 k
//<0xb4=> 220 k
//<0xbd=> 230 k
//<0xc5=> 240 k
//<0xcd=> 250 k
//<0xd5=> 260 k
//<0xdd=> 270 k
//<0xe6=> 280 k
//<0xee=> 290 k
//<0xf6=> 300 k
//<0xfe=> 310 k
//<0x106=> 320 k
//<0x10f=> 330 k
#ifndef XINCX_2_4G_FREQ_DEV
#define XINCX_2_4G_FREQ_DEV 0x00
#endif
// XINCX_2_4G_CRY_CPT_ARRAY_SINGLE - 2.4g Crystal capacitor array
#ifndef XINCX_2_4G_CRY_CPT_ARRAY_SINGLE
#ifdef XC62XX
#define XINCX_2_4G_CRY_CPT_ARRAY_SINGLE 0x38
#else
#define XINCX_2_4G_CRY_CPT_ARRAY_SINGLE 0x36
#endif
#endif
// <<< end of configuration section >>>
#endif // SDK_SINGLE_CONFIG_H
project/example/2.4g/RF24_TEST_CMD/app/shell/api/shell.h
+78
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/*!
* \file shell.h
*
* \brief The head file of shell.c
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __SHELL_H__
#define __SHELL_H__
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include "xc6xxx_rf_2_4g.h"
//#include "dbg.h"
#include "shell_handler.h"
#include "shell_rf_handler.h"
#include "xc6xxx.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
#define XC_DATA_LEN 64U
/*------------------------------------------------------------------------------------
TypeDef
-------------------------------------------------------------------------------------*/
typedef enum
{
XC_SHELL_CMD_RECV = 0,
XC_SHELL_CMD_PROC
} eXC_Shell_Proc_state;
typedef struct
{
char *cmd;
eXC_Cmd_State (*fn)(eCMD_Type opt, int srgc, char *srgv[]);
} XC_Cmd_Table_t;
/*------------------------------------------------------------------------------------
Global Variables
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Exported Functions
-------------------------------------------------------------------------------------*/
void app_uart_init(void);
void xc_shell_init(void);
void xc_shell_test_case(void);
void shell_cmd_process(void);
#ifdef __cplusplus
}
#endif
#endif /* __SHELL_H__ */
project/example/2.4g/RF24_TEST_CMD/app/shell/api/shell_handler.h
+115
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@@ -0,0 +1,115 @@
/*!
* \file shell.h
*
* \brief The head file of shell_handler.c
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __SHELL_HANDLER_H__
#define __SHELL_HANDLER_H__
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
//#include "co_bt_defines.h"
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "xc6xxx.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
#define XC_CMD_SIZE 255U
#define SEND_DATA_LEN 512
// XC Command
#define XC_OK "OK"
#define XC_ERROR "+CME ERROR:"
#define XC_CMD_TEST "+TEST"
#define XC_CMD_REBOOT "+REBOOT"
#define XC_CMD_RF_ACK_INIT "+RF_ACK_INIT"
#define XC_CMD_RF_ADV_INIT "+RF_ADV_INIT"
#define XC_CMD_RF_SINGLE_INIT "+RF_SINGLE_INIT"
#define XC_CMD_RF_ACK_SEND_EVENT "+RF_ACK_SEND_EVENT"
#define XC_CMD_RF_ACK_RECV_EVENT "+RF_ACK_RECV_EVENT"
#define XC_CMD_RF_ADV_SEND_EVENT "+RF_ADV_SEND_EVENT"
#define XC_CMD_RF_ADV_RECV_EVENT "+RF_ADV_RECV_EVENT"
#define XC_CMD_RF_SET_CHANNEL "+RF_SET_CHANNEL"
#define XC_CMD_RF_SET_POWER "+RF_SET_POWER"
#define XC_CMD_RF_SET_RATE "+RF_SET_RATE"
#define XC_CMD_RF_SET_ADDR "+RF_SET_ADDR"
#define XC_CMD_RF_GET_REG_VALUE "+RF_GET_REG_VALUE"
#define XC_CMD_RF_SET_ANA_REG "+RF_SET_ANA_REG"
#define XC_CMD_RF_GET_ANA_REG "+RF_GET_ANA_REG"
/*------------------------------------------------------------------------------------
TypeDef
-------------------------------------------------------------------------------------*/
typedef enum
{
RF_IDLE = 0,
RF_BLE_MODE,
RF_24G_MODE
} eRF_MODE_Status;
typedef enum
{
XC_CMD_ERROR = -1,
XC_CMD_SUCCESS = 0
} eXC_Cmd_State;
typedef enum
{
QUERY_CMD = 0x00,
SET_CMD
} eCMD_Type;
typedef struct
{
uint8_t byte0;
uint8_t byte1;
uint8_t byte2;
uint8_t byte3;
uint8_t byte4;
uint8_t byte5;
} BLE_Mac_Addr_t;
/*------------------------------------------------------------------------------------
Global Variables
-------------------------------------------------------------------------------------*/
extern uint8_t XC_Cmd[XC_CMD_SIZE];
/*------------------------------------------------------------------------------------
Exported Functions
-------------------------------------------------------------------------------------*/
int ascii_strn2val(const char str[], char base, char n);
eXC_Cmd_State xc_reboot_handler(eCMD_Type opt, int srgc, char *srgv[]);
#ifdef __cplusplus
}
#endif
#endif /* __SHELL_HANDLER_H__ */
project/example/2.4g/RF24_TEST_CMD/app/shell/api/shell_rf_handler.h
+44
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#ifndef SHELL_RF_HANDLER_H__
#define SHELL_RF_HANDLER_H__
#include "shell_handler.h"
typedef enum
{
RF_STANY,
RF_ACK_SEND,
RF_ACK_RECV,
RF_ADV_SEND,
RF_ADV_RECV,
RF_SINGLE
} erf_status_t;
extern uint16_t temp_ch;
erf_status_t rf24g_get_status(void);
eXC_Cmd_State xc_rf_ack_init_handler(eCMD_Type opt, int srgc, char *srgv[]);
eXC_Cmd_State xc_rf_adv_init_handler(eCMD_Type opt, int srgc, char *srgv[]);
eXC_Cmd_State xc_rf_single_handler(eCMD_Type opt, int srgc, char *srgv[]);
eXC_Cmd_State xc_rf_ack_send_handler(eCMD_Type opt, int srgc, char *srgv[]);
eXC_Cmd_State xc_rf_ack_recv_handler(eCMD_Type opt, int srgc, char *srgv[]);
eXC_Cmd_State xc_rf_ack_payload_handler(eCMD_Type opt, int srgc, char *srgv[]);
eXC_Cmd_State xc_rf_adv_send_handler(eCMD_Type opt, int srgc, char *srgv[]);
eXC_Cmd_State xc_rf_adv_recv_handler(eCMD_Type opt, int srgc, char *srgv[]);
eXC_Cmd_State xc_rf_sleep_handler(eCMD_Type opt, int srgc, char *srgv[]);
eXC_Cmd_State xc_rf_wakeup_handler(eCMD_Type opt, int srgc, char *srgv[]);
eXC_Cmd_State xc_rf_set_channel_handler(eCMD_Type opt, int srgc, char *srgv[]);
eXC_Cmd_State xc_rf_set_power_handler(eCMD_Type opt, int srgc, char *srgv[]);
eXC_Cmd_State xc_rf_set_trans_rate_handler(eCMD_Type opt, int srgc, char *srgv[]);
eXC_Cmd_State xc_rf_set_addr_handler(eCMD_Type opt, int srgc, char *srgv[]);
eXC_Cmd_State xc_rf_get_reg_handler(eCMD_Type opt, int srgc, char *srgv[]);
eXC_Cmd_State xc_rf_set_ana_reg_handler(eCMD_Type opt, int srgc, char *srgv[]);
eXC_Cmd_State xc_rf_get_ana_reg_handler(eCMD_Type opt, int srgc, char *srgv[]);
int data_power(int data,uint8_t power);
int hexToDec(uint8_t hex);
#endif //SHELL_RF_HANDLER_H__
project/example/2.4g/RF24_TEST_CMD/app/shell/src/shell.c
+218
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/*!
* \file shell.c
*
* \brief Target shell implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "shell.h"
/*------------------------------------------------------------------------------------
Local Variables
-------------------------------------------------------------------------------------*/
static XC_Cmd_Table_t XC_CMD_Table[] = {
{XC_CMD_REBOOT, xc_reboot_handler},
{XC_CMD_RF_ACK_INIT, xc_rf_ack_init_handler},
{XC_CMD_RF_ADV_INIT, xc_rf_adv_init_handler},
{XC_CMD_RF_SINGLE_INIT, xc_rf_single_handler},
{XC_CMD_RF_ACK_SEND_EVENT, xc_rf_ack_send_handler},
{XC_CMD_RF_ACK_RECV_EVENT, xc_rf_ack_recv_handler},
{XC_CMD_RF_ADV_SEND_EVENT, xc_rf_adv_send_handler},
{XC_CMD_RF_ADV_RECV_EVENT, xc_rf_adv_recv_handler},
{XC_CMD_RF_SET_CHANNEL, xc_rf_set_channel_handler},
{XC_CMD_RF_SET_POWER, xc_rf_set_power_handler},
{XC_CMD_RF_SET_RATE, xc_rf_set_trans_rate_handler},
{XC_CMD_RF_SET_ADDR, xc_rf_set_addr_handler},
{XC_CMD_RF_GET_REG_VALUE, xc_rf_get_reg_handler},
{XC_CMD_RF_SET_ANA_REG, xc_rf_set_ana_reg_handler},
{XC_CMD_RF_GET_ANA_REG, xc_rf_get_ana_reg_handler},
};
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
#define XC_CMD_TABLE_SIZE (sizeof(XC_CMD_Table) / sizeof(XC_Cmd_Table_t))
/*------------------------------------------------------------------------------------
Global Variables
-------------------------------------------------------------------------------------*/
eXC_Shell_Proc_state sh_sta = XC_SHELL_CMD_RECV;
uint8_t recv_buff[XC_CMD_SIZE] = {0};
//uint16_t recv_len = 0;
/*------------------------------------------------------------------------------------
Func Prototype
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
/**
****************************************************************************************
* @brief
*
* @param[in]
* @param[in]
*
* @return[out]
*
****************************************************************************************
*/
void xc_shell_init(void)
{
UART_InitCfg_t uart_cfg = {0};
uart_cfg.Parity = UART_PARITY_DISABLE;
uart_cfg.StopBits = UART_STOP_1_BITS;
uart_cfg.WordLength = UART_DATA_8_BITS;
uart_cfg.BaudRate = UART_BAUDRATE_115200;
uart_cfg.HardwareFlowControl = UART_HWFC_DISABLE;
xc_uart_init(UART0_IDX, &uart_cfg);
xc_uart_enable_rx_it(UART0_IDX);
NVIC_EnableIRQ(UART0_IRQn);
}
/**
****************************************************************************************
* @brief
*
* @param[in]
* @param[in]
*
* @return[out]
*
****************************************************************************************
*/
eXC_Cmd_State xc_shell_proc(uint8_t *data, uint16_t data_len)
{
int srgc = 0;
int index = 0;
char *ptr = NULL;
char *srgv[XC_DATA_LEN];
eXC_Cmd_State ret = XC_CMD_ERROR;
uint8_t *rx_cmd = data + 2;
if (data_len <= 2 && data[data_len] == '\0') {
LOGI("error 1\r\n");
return ret;
}
// 注意这里 XC指令 只判定大写
if (data[0] != 'X' || data[1] != 'C') {
LOGI("error 2 \r\n");
goto xc_end;
}
for (index = 0; index < XC_CMD_TABLE_SIZE; index++) {
int cmd_len = strlen(XC_CMD_Table[index].cmd);
if (!strncmp((const char *)rx_cmd, XC_CMD_Table[index].cmd, cmd_len)) {
ptr = (char *)rx_cmd + cmd_len;
break;
}
}
if (index >= XC_CMD_TABLE_SIZE || !XC_CMD_Table[index].fn) {
LOGI("error 3 \r\n");
goto xc_end;
}
if (ptr[0] == '?') {
ret = XC_CMD_Table[index].fn(QUERY_CMD, srgc, srgv);
} else if (ptr[0] == '=') {
ptr += 1;
char *str = strtok((char *)ptr, " ");
while (str) {
srgv[srgc++] = str;
str = strtok((char *)NULL, " ");
}
ret = XC_CMD_Table[index].fn(SET_CMD, srgc, srgv);
} else {
LOGI("error 4 \r\n");
ret = XC_CMD_ERROR;
}
xc_end:
if (ret == XC_CMD_ERROR) {
snprintf((char *)XC_Cmd, XC_CMD_SIZE, "\r\n%s %x\r\n", XC_ERROR, 1);
xc_uart_send_data(UART0_IDX, XC_Cmd, strlen((const char *)XC_Cmd));
} else {
xc_uart_send_data(UART0_IDX, XC_Cmd, strlen((const char *)XC_Cmd));
}
memset(XC_Cmd, 0, XC_CMD_SIZE);
return ret;
}
/**
****************************************************************************************
* @brief
*
* @param[in]
* @param[in]
*
* @return[out]
*
****************************************************************************************
*/
void shell_cmd_process(void)
{
/* main loop */
static uint16_t recv_len = 0;
switch (sh_sta) {
case XC_SHELL_CMD_RECV: {
// DEBUG(".");
recv_len += xc_uart_receive_data(UART0_IDX, recv_buff + recv_len);
if (recv_len) {
if ((recv_buff[recv_len - 2] == '\r') &&
(recv_buff[recv_len - 1] == '\n')) {
sh_sta = XC_SHELL_CMD_PROC;
//DEBUG("k");
} else {
//DEBUG("e");
}
}
} break;
case XC_SHELL_CMD_PROC: {
(void)xc_shell_proc(recv_buff, recv_len);
recv_len = 0;
sh_sta = XC_SHELL_CMD_RECV;
} break;
default:
break;
}
}
void xc_shell_test_case(void)
{
xc_shell_init();
while (1) {
shell_cmd_process();
}
}
project/example/2.4g/RF24_TEST_CMD/app/shell/src/shell_handler.c
+121
View File
@@ -0,0 +1,121 @@
/*!
* \file shell_handler.c
*
* \brief Target shell handler implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "shell_handler.h"
/*------------------------------------------------------------------------------------
Global Variables
-------------------------------------------------------------------------------------*/
uint8_t XC_Cmd[XC_CMD_SIZE] = {0};
static eRF_MODE_Status rf_mode_status = RF_IDLE;
static char ascii_char2val(const char c)
{
if (c >= '0' && c <= '9')
return c - '0';
if ((c >= 'a' && c <= 'f') || (c >= 'A' && c <= 'F'))
return (c & 0x7) + 9;
return (char)(-1);
}
/*-------------------------------------------------------------------------
Function : ascii_strn2val ----add by chsheng,
chsheng@accelsemi.com Return: -1=error Description: str = "123" bas = 10 return
123 str = "123" bas = 16 return 0x123
-------------------------------------------------------------------------*/
int ascii_strn2val(const char str[], char base, char n)
{
int val = 0;
char v;
while (n != 0) {
v = ascii_char2val(*str);
#if 0
if (v == -1 || v >= base)
return -1;
#else
if (v == (char)(-1) || v >= base) {
if (val == 0) // to filter abormal beginning and ending
{
str++;
n--;
continue;
} else {
break;
}
}
#endif
val = val * base + v;
str++;
n--;
}
return val;
}
/**
****************************************************************************************
* @brief
*
* @param[in]
* @param[in]
*
* @return[out]
*
****************************************************************************************
*/
eXC_Cmd_State xc_test_handler(eCMD_Type opt, int srgc, char *srgv[])
{
eXC_Cmd_State ret = XC_CMD_ERROR;
switch (opt) {
case QUERY_CMD: {
ret = XC_CMD_SUCCESS;
snprintf((char *)XC_Cmd, XC_CMD_SIZE, "\r\n%s\r\n", XC_OK);
} break;
default:
break;
}
return ret;
}
eRF_MODE_Status get_ble_init_flag(void) { return rf_mode_status; }
eXC_Cmd_State xc_reboot_handler(eCMD_Type opt, int srgc, char *srgv[])
{
eXC_Cmd_State ret = XC_CMD_SUCCESS;
WDT_InitCfg_t wdt_cfg ;
wdt_cfg.WorkMode = WDT_WORK_MODE0;
wdt_cfg.ReloadValue = WDT_CLK_32M_RESET_MODE0_4096US;
xc_wdt_init( &wdt_cfg);
xc_wdt_start();
snprintf((char *)XC_Cmd, XC_CMD_SIZE, "\r\n%s\r\nOK\r\n", XC_CMD_REBOOT);
return ret;
}
project/example/2.4g/RF24_TEST_CMD/app/shell/src/shell_rf_handler.c
+544
View File
@@ -0,0 +1,544 @@
#include "shell_rf_handler.h"
#include "app_rf24g.h"
#include "xc6xxx_rf_single.h"
erf_status_t rf_status = RF_STANY;
static uint8_t rf_ack_addr[5] = {0};
uint32_t rf_ack_addr_l = 0;
uint32_t rf_ack_addr_h = 0;
uint8_t rf_ack_addr_width = 0;
uint16_t temp_ch = 0;
#define setbit(x,y) ((x) |= (1<<(y)))
#define clrbit(x,y) ((x) &= ~(1<<(y)))
void wbit(uint16_t reg_addr,int end,int start,uint32_t bit_str)
{
uint16_t reg_val = 0;
reg_val = *((volatile uint32_t *)(0x53021000UL + reg_addr * 4));
//LOGI("1-reg_val:0x%04x,bit_str:0x%04x\n",reg_val,bit_str);
uint16_t temp = 0;
for(int i=start;i<=end;i++)
{
if((bit_str>>(temp++))&0x1)
{
setbit(reg_val,i);
}
else
{
clrbit(reg_val,i);
}
}
//LOGI("2-reg_val:0x%04x\n",reg_val);
*((volatile uint32_t *)(0x53021000UL + reg_addr * 4)) = reg_val;
}
uint16_t rbit(uint16_t reg_addr)
{
return *((volatile uint32_t *)(0x53021000UL + reg_addr * 4));
}
/**
* @brief Rf 2.4g dump log
* @param void
*
* @retval void
*/
void rf_dump_log(void)
{
LOGI("***************** 2.4G Param ******************\n");
LOGI("CFG_TOP: 0x%08x\r\n", XC_RF_2_4G->CFG_TOP);
LOGI("EN_AA: 0x%08x\r\n", XC_RF_2_4G->EN_AA);
LOGI("EN_RXADDR: 0x%08x\r\n", XC_RF_2_4G->EN_RXADDR);
LOGI("SETUP_AW: 0x%08x\r\n", XC_RF_2_4G->SETUP_AW);
LOGI("SETUP_RETR: 0x%08x\r\n", XC_RF_2_4G->SETUP_RETR);
LOGI("RF_CH: 0x%08x\r\n", XC_RF_2_4G->RF_CH);
LOGI("SETUP_RF: 0x%08x\r\n", XC_RF_2_4G->SETUP_RF);
LOGI("STATUS: 0x%08x\r\n", XC_RF_2_4G->STATUS);
LOGI("OBSERVE_TX: 0x%08x\r\n", XC_RF_2_4G->OBSERVE_TX);
LOGI("RSSI: 0x%08x\r\n", XC_RF_2_4G->RSSI);
LOGI("RX_ADDR_P0: 0x%02x%08x\r\n", 0xFF & (XC_RF_2_4G->RX_ADDR_P0_H), XC_RF_2_4G->RX_ADDR_P0_L);
LOGI("RX_ADDR_P1: 0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RX_ADDR_P1_H), XC_RF_2_4G->RX_ADDR_P1_L);
LOGI("RX_ADDR_P2TOP5:0x%08x\r\n", XC_RF_2_4G->RX_ADDR_P2TOP5);
LOGI("BER_RESULT: 0x%08x%08x\r\n", XC_RF_2_4G->BER_ERR_CNT, XC_RF_2_4G->BER_RECV_CNT);
LOGI("AGC_SETTING: 0x%08x\r\n", XC_RF_2_4G->AGC_SETTING);
LOGI("PGA_SETTING: 0x%02x%08x\r\n", ((XC_RF_2_4G->TX_ADDR_H) & 0xFF00) >> 8, XC_RF_2_4G->PGA_SETTING);
LOGI("TX_ADDR: 0x%02x%08x\r\n", ((XC_RF_2_4G->TX_ADDR_H) & 0xFF), XC_RF_2_4G->TX_ADDR_L);
LOGI("RX_PW_PX: 0x%04x %08x\r\n", 0xFFFF & (XC_RF_2_4G->RX_PW_Px_H), XC_RF_2_4G->RX_PW_Px_L);
LOGI("STATUS_FIFO: 0x%08x\r\n", XC_RF_2_4G->STATUS_FIFO);
LOGI("RSSIREC: 0x%08x\r\n", XC_RF_2_4G->RSSIREC);
LOGI("TXPROC_CFG: 0x%08x\r\n", XC_RF_2_4G->TXPROC_CFG);
LOGI("RXPROC_CFG: 0x%02x%08x\r\n", 0xFF & (XC_RF_2_4G->RXPROC_CFG_H), XC_RF_2_4G->RXPROC_CFG_L);
LOGI("DYNPD: 0x%08x\r\n", XC_RF_2_4G->DYNPD);
LOGI("FEATURE: 0x%08x\r\n", XC_RF_2_4G->FEATURE);
LOGI("PGA_SETTING_H: 0x%08x\r\n", XC_RF_2_4G->TX_ADDR_H);
LOGI("TX_POWER 0x%08x\r\n", (XC_BT_RF->ana21_reg_l >> 6) & 0x3f);
LOGI("ana2_reg_l: 0x%08x\r\n", XC_BT_RF->ana2_reg_l);
LOGI("ana3_reg_l: 0x%08x\r\n", XC_BT_RF->ana3_reg_l);
LOGI("ana11_reg_l: 0x%08x\r\n", XC_BT_RF->ana11_reg_l);
LOGI("***********************************************\n");
LOGI("\r\n");
}
/**
* @brief Rf 2.4g get status
* @param void
*
* @retval erf_status_t - rf_status
*/
erf_status_t rf24g_get_status(void) { return rf_status; }
/**
* @brief Rf ack init handler
* @param eCMD_Type - opt
* @param int - srgc
* @param char * - srgv[]
* @retval erf_status_t - ret
*/
eXC_Cmd_State xc_rf_ack_init_handler(eCMD_Type opt, int srgc, char *srgv[])
{
eXC_Cmd_State ret = XC_CMD_SUCCESS;
uint8_t rf_mode = ascii_strn2val((const char *)srgv[0], 16, 2);
uint16_t rf_channel = ascii_strn2val((const char *)srgv[1], 10, 4);
LOGI("mode:%d---- channel:%04x", rf_mode, rf_channel);
rf24g_init();
set_rf_mode(rf_mode);
rf_set_channel(rf_channel);
rf_dump_log();
snprintf((char *)XC_Cmd, XC_CMD_SIZE, "\r\n%s\r\nOK\r\n", XC_CMD_RF_ACK_INIT);
rf_status = RF_STANY;
return ret;
}
/**
* @brief Rf adv init handler
* @param eCMD_Type - opt
* @param int - srgc
* @param char * - srgv[]
* @retval erf_status_t - ret
*/
eXC_Cmd_State xc_rf_adv_init_handler(eCMD_Type opt, int srgc, char *srgv[])
{
eXC_Cmd_State ret = XC_CMD_SUCCESS;
uint8_t rf_mode = ascii_strn2val((const char *)srgv[0], 16, 2);
uint16_t rf_channel = ascii_strn2val((const char *)srgv[1], 10, 4);
rf24g_adv_init();
set_rf_mode(rf_mode);
rf_set_channel(rf_channel);
rf_dump_log();
snprintf((char *)XC_Cmd, XC_CMD_SIZE, "\r\n%s\r\nOK\r\n", XC_CMD_RF_ADV_INIT);
rf_status = RF_STANY;
return ret;
}
/**
* @brief Rf single init handler
* @param eCMD_Type - opt
* @param int - srgc
* @param char * - srgv[]
* @retval erf_status_t - ret
*/
eXC_Cmd_State xc_rf_single_handler(eCMD_Type opt, int srgc, char *srgv[])
{
eXC_Cmd_State ret = XC_CMD_SUCCESS;
rf_single_init();
uint16_t rf_channel = ascii_strn2val((const char *)srgv[0], 10, 4);
/* */
uint16_t tx_proc_cfg = ascii_strn2val((const char *)srgv[1], 16, 2);
if (tx_proc_cfg == NULL) {
tx_proc_cfg = 0;
}
XC_RF_2_4G->TXPROC_CFG = tx_proc_cfg;
rf_set_channel(rf_channel);
rf_dump_log();
uint32_t channel = XC_RF_2_4G->RF_CH;
temp_ch = 0;
if (channel == rf_channel) {
temp_ch = rf_channel;
LOGI("OK:%d\r\n", channel);
} else {
LOGI("error:%d\r\n", channel);
}
rf_status = RF_SINGLE;
snprintf((char *)XC_Cmd, XC_CMD_SIZE, "\r\n%s\r\nOK\r\n", XC_CMD_RF_SINGLE_INIT);
return ret;
}
/**
* @brief Rf ack send handler
* @param eCMD_Type - opt
* @param int - srgc
* @param char * - srgv[]
* @retval erf_status_t - ret
*/
eXC_Cmd_State xc_rf_ack_send_handler(eCMD_Type opt, int srgc, char *srgv[])
{
eXC_Cmd_State ret = XC_CMD_SUCCESS;
static uint16_t rf_channel = 0;
rf_ack_addr_l = XC_RF_2_4G->TX_ADDR_L;
rf_ack_addr_h = XC_RF_2_4G->TX_ADDR_H;
rf_channel = ascii_strn2val((const char *)srgv[0], 10, 4);
rf_ack_addr_width = ascii_strn2val((const char *)srgv[1], 16, 2);
if (rf_ack_addr_width != 0) {
/* Address buffer */
for (uint8_t i = 0; i < rf_ack_addr_width; i++) {
rf_ack_addr[i] = ascii_strn2val((const char *)srgv[2 + i], 16, 2);
rf_ack_addr_l &= ~(0xff << (8 * i));
if (i == 5)
rf_ack_addr_h &= ~0xff;
}
for (uint8_t i = 0; i < rf_ack_addr_width; i++) {
rf_ack_addr_l |= rf_ack_addr[rf_ack_addr_width - i - 1] << (i * 8);
}
if (rf_ack_addr_width == 5)
rf_ack_addr_h = rf_ack_addr[0];
else
rf_ack_addr_h = XC_RF_2_4G->RX_ADDR_P0_H;
/* Set PTX address */
set_rf_txaddr(rf_ack_addr_l, rf_ack_addr_h);
/* Set PRX address */
set_rf_pipe0_rxaddr(rf_ack_addr_l, rf_ack_addr_h);
/* Set address width */
set_rf_tx_addr_width(rf_ack_addr_width);
memset(rf_ack_addr, 0, 5);
}
set_rf_mode(TX_MODE);
rf_set_channel(rf_channel);
uint32_t channel = XC_RF_2_4G->RF_CH;
if (channel == rf_channel) {
LOGI("OK:%02x\r\n", channel);
} else {
LOGI("error:%02x\r\n", channel);
}
tx_cnt = 0;
// rf_data.cnt = 0;
rf_dump_log();
rf_status = RF_ACK_SEND;
// timer_init(XC_RF_SEND_TIMER, SEND_TIMERMS_CNT);
snprintf((char *)XC_Cmd, XC_CMD_SIZE, "\r\n%s\r\nOK\r\n", XC_CMD_RF_ACK_SEND_EVENT);
return ret;
}
/**
* @brief Rf ack recv handler
* @param eCMD_Type - opt
* @param int - srgc
* @param char * - srgv[]
* @retval erf_status_t - ret
*/
eXC_Cmd_State xc_rf_ack_recv_handler(eCMD_Type opt, int srgc, char *srgv[])
{
eXC_Cmd_State ret = XC_CMD_SUCCESS;
rf_ack_addr_l = XC_RF_2_4G->TX_ADDR_L;
rf_ack_addr_h = XC_RF_2_4G->TX_ADDR_H;
static uint16_t rf_channel = 0;
rf_channel = ascii_strn2val((const char *)srgv[0], 10, 4);
rf_ack_addr_width = ascii_strn2val((const char *)srgv[1], 16, 2);
if (rf_ack_addr_width != 0) {
for (uint8_t i = 0; i < rf_ack_addr_width; i++) {
rf_ack_addr[i] = ascii_strn2val((const char *)srgv[2 + i], 16, 2);
rf_ack_addr_l &= ~(0xff << (8 * i));
if (i == 5)
rf_ack_addr_h &= ~0xff;
}
for (uint8_t i = 0; i < rf_ack_addr_width; i++) {
rf_ack_addr_l |= rf_ack_addr[rf_ack_addr_width - i - 1] << (i * 8);
}
if (rf_ack_addr_width == 5)
rf_ack_addr_h = rf_ack_addr[0];
else
rf_ack_addr_h = XC_RF_2_4G->RX_ADDR_P0_H;
/* Set PTX address */
set_rf_txaddr(rf_ack_addr_l, rf_ack_addr_h);
/* Set PRX address */
set_rf_pipe0_rxaddr(rf_ack_addr_l, rf_ack_addr_h);
/* Set address width */
set_rf_tx_addr_width(rf_ack_addr_width);
}
set_rf_mode(RX_MODE);
rf_set_channel(rf_channel);
rf_status = RF_ACK_RECV;
rx_cnt = 0;
CE_CTL_HIGH;
rf_dump_log();
snprintf((char *)XC_Cmd, XC_CMD_SIZE, "\r\n%s\r\nOK\r\n", XC_CMD_RF_ACK_RECV_EVENT);
return ret;
}
/**
* @brief Rf adv send handler
* @param eCMD_Type - opt
* @param int - srgc
* @param char * - srgv[]
* @retval erf_status_t - ret
*/
eXC_Cmd_State xc_rf_adv_send_handler(eCMD_Type opt, int srgc, char *srgv[])
{
eXC_Cmd_State ret = XC_CMD_SUCCESS;
uint16_t rf_channel = ascii_strn2val((const char *)srgv[0], 10, 4);
set_rf_mode(TX_MODE);
/* Set testing frequency points */
rf_set_channel(rf_channel);
rf_status = RF_ADV_SEND;
rf_dump_log();
snprintf((char *)XC_Cmd, XC_CMD_SIZE, "\r\n%s\r\nOK\r\n", XC_CMD_RF_ADV_SEND_EVENT);
return ret;
}
/**
* @brief Rf adv recv handler
* @param eCMD_Type - opt
* @param int - srgc
* @param char * - srgv[]
* @retval erf_status_t - ret
*/
eXC_Cmd_State xc_rf_adv_recv_handler(eCMD_Type opt, int srgc, char *srgv[])
{
eXC_Cmd_State ret = XC_CMD_SUCCESS;
uint16_t rf_channel = ascii_strn2val((const char *)srgv[0], 10, 4);
/* Set mode */
set_rf_mode(RX_MODE);
LOGI("************ADV Recv Start**************\r\n");
/* Set testing frequency points */
rf_set_channel(rf_channel);
rf_dump_log();
#if (XINCX_RF_ADV_NVIC_MODE == true)
/* Enable RF24G interrupt */
NVIC_EnableIRQ(RF24G_IRQn);
#endif
rf_status = RF_ADV_RECV;
XC_RF_2_4G->CMD_CFG = CMD_DONE | FLUSH_RX;
XC_RF_2_4G->CMD_CFG = CMD_DONE | FLUSH_TX;
XC_RF_2_4G->STATUS = MASK_ALL_INTER;
/* Entering the receiver */
CE_CTL_HIGH;
snprintf((char *)XC_Cmd, XC_CMD_SIZE, "\r\n%s\r\nOK\r\n", XC_CMD_RF_ADV_RECV_EVENT);
return ret;
}
/**
* @brief Rf set channel handler
* @param eCMD_Type - opt
* @param int - srgc
* @param char * - srgv[]
* @retval erf_status_t - ret
*/
eXC_Cmd_State xc_rf_set_channel_handler(eCMD_Type opt, int srgc, char *srgv[])
{
eXC_Cmd_State ret = XC_CMD_SUCCESS;
static uint16_t rf_channel = 0;
rf_channel = ascii_strn2val((const char *)srgv[0], 10, 4);
rf_set_channel(rf_channel);
uint32_t channel = XC_RF_2_4G->RF_CH;
if (channel == rf_channel) {
LOGI("OK:%02x\r\n", channel);
} else {
LOGI("error:%02x\r\n", channel);
}
LOGI("CHANNEL:%d\r\n", XC_RF_2_4G->RF_CH & 0x3ff);
snprintf((char *)XC_Cmd, XC_CMD_SIZE, "\r\n%s\r\nOK\r\n", XC_CMD_RF_SET_CHANNEL);
return ret;
}
/**
* @brief Rf set power handler
* @param eCMD_Type - opt
* @param int - srgc
* @param char * - srgv[]
* @retval erf_status_t - ret
*/
eXC_Cmd_State xc_rf_set_power_handler(eCMD_Type opt, int srgc, char *srgv[])
{
eXC_Cmd_State ret = XC_CMD_SUCCESS;
static uint8_t rf_power = 0;
rf_power = ascii_strn2val((const char *)srgv[0], 16, 2);
set_rf_power(rf_power);
uint8_t power = (XC_BT_RF->ana21_reg_l >> 6) & 0x3f;
if (power == rf_power) {
LOGI("OK:%02x\r\n", power);
ret = XC_CMD_SUCCESS;
} else {
LOGI("error:%02x\r\n", power);
ret = XC_CMD_ERROR;
}
snprintf((char *)XC_Cmd, XC_CMD_SIZE, "\r\n%s\r\nOK\r\n", XC_CMD_RF_SET_POWER);
return ret;
}
/**
* @brief Rf set trans rate handler
* @param eCMD_Type - opt
* @param int - srgc
* @param char * - srgv[]
* @retval erf_status_t - ret
*/
eXC_Cmd_State xc_rf_set_trans_rate_handler(eCMD_Type opt, int srgc, char *srgv[])
{
eXC_Cmd_State ret = XC_CMD_SUCCESS;
static uint8_t rf_trans_rate = 0;
rf_trans_rate = ascii_strn2val((const char *)srgv[0], 16, 2);
set_rf_DR(rf_trans_rate);
uint8_t rf_rate = XC_RF_2_4G->SETUP_RF;
if (rf_rate == rf_trans_rate) {
// if(rf_rate == DR_2M){
// rf_2M_config();
// }
LOGI("OK:%02x\r\n", rf_rate);
ret = XC_CMD_SUCCESS;
} else {
LOGI("error:%02x\r\n", rf_rate);
ret = XC_CMD_ERROR;
}
LOGI("SETUP:%04x\r\n", XC_RF_2_4G->SETUP_RF);
snprintf((char *)XC_Cmd, XC_CMD_SIZE, "\r\n%s\r\nOK\r\n", XC_CMD_RF_SET_RATE);
return ret;
}
/**
* @brief Rf set addr handler
* @param eCMD_Type - opt
* @param int - srgc
* @param char * - srgv[]
* @retval erf_status_t - ret
*/
eXC_Cmd_State xc_rf_set_addr_handler(eCMD_Type opt, int srgc, char *srgv[])
{
eXC_Cmd_State ret = XC_CMD_SUCCESS;
rf_ack_addr_width = ascii_strn2val((const char *)srgv[0], 16, 2);
rf_ack_addr_l = XC_RF_2_4G->TX_ADDR_L;
rf_ack_addr_h = XC_RF_2_4G->TX_ADDR_H;
for (uint8_t i = 0; i < rf_ack_addr_width; i++) {
rf_ack_addr[i] = ascii_strn2val((const char *)srgv[1 + i], 16, 2);
rf_ack_addr_l &= ~(0xff << (8 * i));
if (i == 5)
rf_ack_addr_h &= ~0xff;
}
if (rf_ack_addr_width == 0x5) {
for (uint8_t i = 0; i < 4; i++) {
rf_ack_addr_l |= rf_ack_addr[4 - i] << (i * 8);
}
rf_ack_addr_h = rf_ack_addr[0];
} else {
for (uint8_t i = 0; i < rf_ack_addr_width; i++) {
for (uint8_t i = 0; i < rf_ack_addr_width; i++) {
rf_ack_addr_l |= rf_ack_addr[rf_ack_addr_width - 1 - i] << (i * 8);
}
}
}
/* Set PTX address */
set_rf_txaddr(rf_ack_addr_l, rf_ack_addr_h);
/* Set PRX address */
set_rf_pipe0_rxaddr(rf_ack_addr_l, rf_ack_addr_h);
/* Set address width */
set_rf_tx_addr_width(rf_ack_addr_width);
LOGI("TX_ADDR: 0x%02x%08x\r\n", ((XC_RF_2_4G->TX_ADDR_H) & 0xFF), XC_RF_2_4G->TX_ADDR_L);
rf_ack_addr_l = 0;
rf_ack_addr_h = 0;
memset(rf_ack_addr, 0, sizeof(rf_ack_addr));
snprintf((char *)XC_Cmd, XC_CMD_SIZE, "\r\n%s\r\nOK\r\n", XC_CMD_RF_SET_ADDR);
return ret;
}
/**
* @brief Rf get reg handler
* @param eCMD_Type - opt
* @param int - srgc
* @param char * - srgv[]
* @retval erf_status_t - ret
*/
eXC_Cmd_State xc_rf_get_reg_handler(eCMD_Type opt, int srgc, char *srgv[])
{
eXC_Cmd_State ret = XC_CMD_SUCCESS;
uint8_t rf24g_reg_addr = 0;
rf24g_reg_addr = ascii_strn2val((const char *)srgv[0], 16, 2);
uint32_t reg_temp = XC_RF_2_4G_BASE + rf24g_reg_addr * 4;
LOGI("REG(%02x):%08x\r\n", reg_temp, *(uint32_t *)reg_temp);
snprintf((char *)XC_Cmd, XC_CMD_SIZE, "\r\n%s\r\nOK\r\n", XC_CMD_RF_GET_REG_VALUE);
return ret;
}
eXC_Cmd_State xc_rf_set_ana_reg_handler(eCMD_Type opt, int srgc, char *srgv[])
{
eXC_Cmd_State ret = XC_CMD_SUCCESS;
uint8_t rf_reg_value = ascii_strn2val((const char *)srgv[0], 10, 2);
uint8_t start_bit = ascii_strn2val((const char *)srgv[1], 10, 2);
uint8_t end_bit = ascii_strn2val((const char *)srgv[2], 10, 2);
uint8_t set_value_b = ascii_strn2val((const char *)srgv[3], 16, 2);
LOGI("W_REG(%02x)[%d:%d]:%d\r\n", ((volatile uint32_t *)(0x53021000UL + rf_reg_value * 4)), start_bit,end_bit, ascii_strn2val((const char *)srgv[3], 16, 2));
//printf("addr:%04x\n",*((volatile uint32_t *)(0x53021000UL + rf_reg_value * 4)));
wbit(rf_reg_value,start_bit,end_bit,set_value_b);
snprintf((char *)XC_Cmd, XC_CMD_SIZE, "\r\n%s\r\nOK\r\n", XC_CMD_RF_SET_ANA_REG);
//printf("addr:%04x\n",*((volatile uint32_t *)(0x53021000UL + rf_reg_value * 4)));
return ret;
}
eXC_Cmd_State xc_rf_get_ana_reg_handler(eCMD_Type opt, int srgc, char *srgv[])
{
eXC_Cmd_State ret = XC_CMD_SUCCESS;
uint8_t rf_reg_value = ascii_strn2val((const char *)srgv[0], 10, 2);
LOGI("addr:0x53021000UL+%x;value:0x%04x",rf_reg_value*4, rbit(rf_reg_value));
snprintf((char *)XC_Cmd, XC_CMD_SIZE, "\r\n%s\r\nOK\r\n", XC_CMD_RF_GET_ANA_REG);
return ret;
}
project/example/2.4g/RF24_TEST_CMD/app/src/app_rf24g.c
+323
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#include "app_rf24g.h"
extern uint8_t recv_buf[256];
uint8_t recv_adv_buf[ADV_LENGTH];
bool rf_send_timer_flag = false;
extern bool rf24g_handler_flag;
uint8_t rf_adv_channel[] = {RF_ADV_CHANNEL_37, RF_ADV_CHANNEL_38, RF_ADV_CHANNEL_39};
uint8_t adv_index = 0;
uint32_t tx_cnt = 0, rx_cnt = 0;
/**
****************************************************************************************
* @brief
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void timer_init(uint8_t timer_id, uint32_t timer_cnt)
{
LOGI("timer_init\r\n");
uint32_t timerx_us = timer_cnt * 1000;
Timer_InitCfg_t timer_cfg;
timer_cfg.timer_src_clk = TIMER_CLK_SRC_32M_DIV;
timer_cfg.timer_div_clk = TIMER_DIV_CLK_1MHzOr1K;
timer_cfg.timer_mode = TIMER_MODE_CYCLE;
xc_timer_init(timer_id, &timer_cfg);
xc_timer_set_value(timer_id, timerx_us);
xc_timer_start(timer_id);
}
/**
* @brief Timer0_Callback
* @param void * - context
*
* @retval void
*/
void timer0_callback(void *context)
{
LOGI("Timer0_Callback\r\n");
#if !(XINCX_RF_MODE)
rf_send_timer_flag = true;
#endif // !(XINCX_RF_MODE)
}
/**
* @brief RF 2.4g data config
* @param uint8_t * - buff
* uint8 - len
* @retval uint8_t - 0
*/
uint8_t rf_data_config(uint8_t *buff, uint8_t len)
{
if (len == 0) {
return RF_FAIL;
}
for (uint8_t i = 0; i < len; i++) {
buff[i] = i;
}
return RF_SUCCESS;
}
/**
* @brief RF 2.4g tx manage
* @param rf_data_typedef_t * - rf_data
* @retval uint8_t - cnt
*/
uint32_t rf_ack_tx_manage(uint8_t *buff)
{
if ((tx_cnt < XC_SEND_NUM)) { //&& (rf_send_timer_flag)) {
rf_send_timer_flag = false;
tx_cnt += 1;
/* Filling in software frame number */
buff[0] = tx_cnt;
LOGI("send_cnt:%d\r\n", tx_cnt);
/* data transmission */
rf_tx_event(buff, BUFF_LEN);
/* TX data packaging filling */
rf_data_config(buff, BUFF_LEN);
}
if (tx_cnt == XC_SEND_NUM) {
tx_cnt += 1;
LOGI("SEND END\r\n");
/* Turn off the send timer */
// xc_timer_stop(XC_RF_SEND_TIMER);
}
return tx_cnt;
}
/**
* @brief RF 2.4g rx manage
* @param rf_data_typedef_t * - rf_data
* @retval uint32_t - 0
*/
#if !(XINCX_RF_NVIC_MODE)
uint32_t rf_ack_rx_manage(uint8_t *buff)
{
static uint32_t conut = 0;
/* Receive event processing */
uint8_t len = rf_rx_event(buff);
/* Receiving end polling data processing */
if (len != 0) {
/* Entering standby mode */
CE_CTL_LOW;
/* Receiving data processing */
if (buff[RF_CONFIRMED_VALUE] == RF_CONFIRMED_VALUE) {
LOGI("%d\r\n", rx_cnt);
}
/* Receive Count */
rx_cnt += 1;
/* Receive read data buffer reset */
memset(buff, 0, len);
len = 0;
/* Entering the receiver */
CE_CTL_HIGH;
}
return 0;
}
#else
uint32_t rf_ack_rx_manage(rf_data_typedef_t *rf_data)
{
uint8_t len = recv_len;
if (rf24g_handler_flag) {
rf24g_handler_flag = false;
/* Entering standby mode */
CE_CTL_LOW;
if ((len != 0) && (recv_buf[RF_CONFIRMED_VALUE] == RF_CONFIRMED_VALUE)) {
LOGI("%d\r\n", recv_buf[0]);
}
/* Receive Count */
rx_cnt += 1;
LOGI("recv:%d\r\n", rx_cnt);
/* Receive read data buffer reset */
memset(recv_buf, 0, len);
len = 0;
/* Entering the receiver */
CE_CTL_HIGH;
}
return 0;
}
#endif
/**
* @brief RF ADV data package filling
* @param uint8_t * - buff
* uint8_t - len
* @return uint8_t - data len
*/
uint8_t rf_adv_packet(uint8_t *buff)
{
if (sizeof(buff) > ADV_LENGTH) {
buff = NULL;
return RF_FAIL;
}
uint8_t l = 0;
buff[l++] = 0x42;
buff[l++] = ADV_LENGTH - 5;
/* Simulate Bluetooth MAC address */
uint8_t rf_adv_mac_addr[6] = {MAC_ADDR_0, MAC_ADDR_1, MAC_ADDR_2, MAC_ADDR_3, MAC_ADDR_4, MAC_ADDR_5};
memcpy(&buff[l], rf_adv_mac_addr, sizeof(rf_adv_mac_addr));
l += sizeof(rf_adv_mac_addr);
buff[l++] = 0x02;
buff[l++] = 0x01;
buff[l++] = 0x06;
buff[l++] = ADV_LENGTH - 15;
// Complete Local Name
buff[l++] = 0x09;
/* Simulate Bluetooth broadcast data */
uint8_t rf_adv_data_buff[26] = {"RF-ADV-TEST-123456789BLE52"};
memcpy(&buff[l], rf_adv_data_buff, sizeof(rf_adv_data_buff));
l += sizeof(rf_adv_data_buff);
/* CRC */
buff[l++] = 0x55;
buff[l++] = 0x55;
buff[l++] = 0x55;
return l;
}
/**
* @brief Rf adv tx event
* @param void
*
* @retval void
*/
void rf_adv_tx_evevt(void)
{
uint8_t len = 0;
uint8_t buff[ADV_LENGTH];
/* Set testing frequency points */
rf_set_channel(RF_ADV_BASE + rf_adv_channel[adv_index]);
/* Simulate Bluetooth broadcast data filling */
len = rf_adv_packet(buff);
/* Simulate Bluetooth broadcast package software CRC */
ble_crc(buff, len - 3, buff + len - 3);
/* Simulate Bluetooth broadcast package software whitening */
ble_whiten(buff, len, bleWhitenStart(RF_ADV_BASE + rf_adv_channel[adv_index]));
/* Send data processing */
rf_tx_packet(buff, len);
adv_index += 1;
if (adv_index == sizeof(rf_adv_channel)) {
adv_index = 0;
delay_ms(10);
}
delay_ms(1);
}
/**
* @brief RF rx adv event
* @param void
*
* @retval void
*/
#if (XINCX_RF_ADV_NVIC_MODE == true)
void rf_adv_rx_evevt(void)
{
uint8_t data_len = 0;
uint32_t blecrc = 0;
// printf("rf_adv_rx_evevt\r\n");
if ((recv_len != 0) && (rf24g_handler_flag)) {
/* Entering standby mode */
CE_CTL_LOW;
rf24g_handler_flag = false;
/* Whitening of packet software */
blecrc = rf_adv_packet_whiten(&data_len);
/* Packet software CRC judgment */
if (rf_adv_crc(recv_adv_buf, &data_len, blecrc) == 1) {
/* Only after 5 bytes is valid data */
for (uint8_t i = 0; i < data_len + 5; i++)
LOGI("%02x ", recv_adv_buf[i]);
LOGI("\r\n");
}
memset(recv_adv_buf, 0, sizeof(recv_adv_buf));
recv_len = 0;
/* Entering the receiver */
CE_CTL_HIGH;
}
}
#else
void rf_adv_rx_evevt(void)
{
uint8_t data_len = 0;
uint32_t blecrc = 0;
if ((XC_RF_2_4G->STATUS) & MASK_RX_DR) {
/* Entering standby mode */
CE_CTL_LOW;
recv_len = rf_rx_packet(recv_adv_buf);
if (recv_len != 0) {
/* Whitening of packet software */
blecrc = rf_adv_packet_whiten(&data_len);
/* Packet software CRC judgment */
//if (rf_adv_crc(recv_adv_buf, &data_len, blecrc) == 1)
{
for (uint8_t i = 0; i < data_len + 5; i++)
LOGI("%02x ", recv_adv_buf[i]);
LOGI("\r\n");
}
memset(recv_adv_buf, 0, sizeof(recv_adv_buf));
recv_len = 0;
}
/* Entering the receiver */
CE_CTL_HIGH;
}
}
#endif
extern uint16_t temp_ch;
void rf_single_event(void)
{
rf_set_channel(temp_ch);
}
project/example/2.4g/RF24_TEST_CMD/app/src/main.c
+289
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/*!
* \file main.c
*
* \brief Target main implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "main.h"
#include "shell.h"
#include "app_rf24g.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Global Variables
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Func Prototype
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
/**
****************************************************************************************
* @brief Clock Initialization
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void clock_init(void)
{
CLOCK_InitCfg_t clock_cfg;
clock_cfg.hfclk_src = CLOCK_HFCLK_SRC_XTAL;
clock_cfg.hfclk_in = CLOCK_HFCLK_IN_32M;
#if (RC_32K)
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_RC;
#endif //(RC_32K)
#if (XTAL_32K)
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL;
#endif // (XTAL_32K)
#if (XTAL_32768K)
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL;
#endif // (XTAL_32768K)
if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_XTAL) {
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32768;
} else if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_RC) {
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32K;
}
xc_clock_init_cfg(&clock_cfg);
SysTick_Config(xc_clock_hfclk_in_get() / 100);
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
}
void rf_2M_reg_info(void)
{
/* Register information printing */
LOGI("CFG_TOP: 0x%08x\r\n", XC_RF_2_4G->CFG_TOP);
LOGI("TXPROC_CFG: 0x%08x\r\n", XC_RF_2_4G->TXPROC_CFG);
LOGI("RXPROC_CFG_L: 0x%08x\r\n", XC_RF_2_4G->RXPROC_CFG_L);
LOGI("RF_CH: 0x%08x\r\n", XC_RF_2_4G->RF_CH);
LOGI("rccal_reg_l: 0x%08x\r\n", XC_BT_RF->rccal_reg_l);
LOGI("ana2_reg_l: 0x%08x\r\n", XC_BT_RF->ana2_reg_l);
LOGI("ana3_reg_l: 0x%08x\r\n", XC_BT_RF->ana3_reg_l);
LOGI("ana4_reg_l: 0x%08x\r\n", XC_BT_RF->ana4_reg_l);
LOGI("ana5_reg_l: 0x%08x\r\n", XC_BT_RF->ana5_reg_l);
LOGI("ana14_reg_l: 0x%08x\r\n", XC_BT_RF->ana14_reg_l);
LOGI("ana15_reg_l: 0x%08x\r\n", XC_BT_RF->ana15_reg_l);
LOGI("ana16_reg_l: 0x%08x\r\n", XC_BT_RF->ana16_reg_l);
LOGI("ana17_reg_l: 0x%08x\r\n", XC_BT_RF->ana17_reg_l);
LOGI("ana18_reg_l: 0x%08x\r\n", XC_BT_RF->ana18_reg_l);
LOGI("ana21_reg_l: 0x%08x\r\n", XC_BT_RF->ana21_reg_l);
LOGI("AON_RF_AONREG: 0x%08x\r\n", cprao_aon_rf_aonreg_get()); // 0x36
}
/**
* @brief RF 2.4g buff info
* @param uint8_t * - buff
* uint8_t len
* @retval void
*/
void rf_buff_info(uint8_t *buff, uint8_t len)
{
for (uint8_t i = 0; i < len; i++)
LOGI("%02x ", buff[i]);
LOGI("\r\n");
}
#define UART0_BUFFER_LEN 128
typedef struct
{
uint8_t r_buff[26];
uint8_t w_buff[26];
uint8_t r_len;
bool rx_done;
} uart_user_t;
uint8_t uart0_buff[UART0_BUFFER_LEN];
uart_user_t uart_user_ctl;
ring_buffer_t uart0_ring_buff;
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
void uart_receive_cb(uint8_t *buff, uint16_t len)
{
static uint8_t cnt = 0;
for (int i = 0; i < len; i++) {
uart_user_ctl.r_buff[cnt++] = buff[i];
uart_user_ctl.r_len++;
ring_buffer_queue(&uart0_ring_buff, buff[i]);
}
// if (cnt == sizeof(uart_user_ctl.r_buff))
{
uart_user_ctl.rx_done = true;
cnt = 0;
}
}
void app_uart_init(void)
{
GPIO_InitCfg_t gpio_cfg = {0};
gpio_cfg.Mux = GPIO_Mux0;
gpio_cfg.Pull = GPIO_PULLUP;
gpio_cfg.Int = NOT_INT;
gpio_cfg.FunSel = UART0_TX;
gpio_cfg.Pin = GPIO_18;
gpio_cfg.Dir = GPIO_DIR_OUTPUT;
xc_gpio_init(&gpio_cfg);
gpio_cfg.FunSel = UART0_RX;
gpio_cfg.Pin = GPIO_19;
gpio_cfg.Dir = GPIO_DIR_INPUT;
xc_gpio_init(&gpio_cfg);
UART_InitCfg_t uart_cfg = {0};
uart_cfg.Parity = UART_PARITY_DISABLE;
uart_cfg.StopBits = UART_STOP_1_BITS;
uart_cfg.WordLength = UART_DATA_8_BITS;
uart_cfg.BaudRate = UART_BAUDRATE_115200;
uart_cfg.HardwareFlowControl = UART_HWFC_DISABLE;
xc_uart_init(UART0_IDX, &uart_cfg);
ring_buffer_create(&uart0_ring_buff, uart0_buff, UART0_BUFFER_LEN);
xc_uart_register_receive_cb(uart_receive_cb);
xc_uart_enable_rx_it(UART0_IDX);
NVIC_EnableIRQ(UART0_IRQn);
}
uint16_t xc_uart_receive_data(uint8_t reg_idx, uint8_t *data)
{
if(!ring_buffer_is_empty(&uart0_ring_buff)){
uint16_t recv_len = ring_buffer_num_items(&uart0_ring_buff);
ring_buffer_dequeue_arr(&uart0_ring_buff, data, recv_len);
return recv_len;
}
return 0;
}
void wdt_init(void)
{
WDT_InitCfg_t wdt_cfg ;
wdt_cfg.WorkMode = WDT_WORK_MODE0;
wdt_cfg.ReloadValue = WDT_CLK_32K_RESET_MODE0_1048576MS;
wdt_cfg.PclkSel = WDT_WORK_32K;
xc_wdt_init(&wdt_cfg);
}
/**
* @brief main
* @details
* @param[in] void
* @param[out] void
* @retval int - 0
* @retval void
* @par identifier
* reserve
* @par other
* void
* @par change log
* Alex created on 2023-05-31
*/
//rf_data_typedef_t rf_data;
int main(void)
{
bool rf_send_timer_flag = false;
erf_status_t rf24g_stat = RF_STANY;
uint8_t tx_buff[255] = {0};
uint8_t rx_buff[255] = {0};
uint32_t tx_cnt = 0,rx_cnt = 0;
uint8_t tx_len = 0,rx_len = 0;
xc_shell_init();
/* TX data packaging filling */
// rf_data_config(rf_data.buff, sizeof(rf_data.buff));
// rf_data.cnt = 0;
// rf_data.temp = SEND_TIMERMS_CNT;
/* Clock initialization */
clock_init();
wdt_init();
/* Serial port initialization */
app_uart_init();
/* rf 2.4g initialization configuration */
rf24g_init();
rf_dump_log();
xc_wdt_start();
rf_data_config(tx_buff,BUFF_LEN);
while (1) {
xc_wdt_refresh();
shell_cmd_process();
rf24g_stat = rf24g_get_status();
switch (rf24g_stat) {
case RF_ACK_SEND:
rf_send_timer_flag = true;
tx_cnt = rf_ack_tx_manage(tx_buff);
break;
case RF_ACK_RECV:
rf_send_timer_flag = false;
rf_ack_rx_manage(rx_buff);
break;
case RF_ADV_SEND:
rf_send_timer_flag = false;
rf_adv_tx_evevt();
break;
case RF_ADV_RECV:
rf_send_timer_flag = false;
rf_adv_rx_evevt();
break;
case RF_SINGLE:
rf_send_timer_flag = false;
rf_single_event();
default:
rf_send_timer_flag = false;
break;
};
if(rf_send_timer_flag == false)
{
/* Turn off the send timer */
//xc_timer_stop(XC_RF_SEND_TIMER);
}
}
}
project/example/2.4g/RF24_TEST_CMD/mdk/Linker/Initialization.ini
+12
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@@ -0,0 +1,12 @@
FUNC void Initialization(void)
{
SP = _RDWORD(0x10000000);
PC = _RDWORD(0x10000004);
}
LOAD %L INCREMENTAL
Initialization();
project/example/2.4g/RF24_TEST_CMD/mdk/Linker/XIPInitialization.ini
+84
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@@ -0,0 +1,84 @@
FUNC void InitGpio(void)
{
// Config IOMUX
/*
gpio_mux_ctl_u(33,1);//d2
gpio_mux_ctl_u(34,1);//d3
gpio_mux_ctl_u(35,2);//clk
gpio_mux_ctl_u(36,2);//cs
gpio_mux_ctl_u(37,2);//d0 rx
gpio_mux_ctl_u(38,2);//d1 tx
*/
_WDWORD(0x4000019c, 0x00002A94);
}
FUNC void InitFlash(void)
{
}
FUNC void InitXIP(void)
{
_WDWORD(0x40000104,0x040000);//reset ssi0
_WDWORD(0x40000104,0x040004);//reset ssi0
_WDWORD(0x40000050,0x110000);//close spi0 mclk
_WDWORD(0x40000070,0x1000000);//close spi0 pclk
//config fmc
_WDWORD(0x40000270, 0x0503);
_Sleep_(1);// delay about 400us
_WDWORD(0x40000270, 0x3503);
//config cache
_Sleep_(1);// delay about 400us
_WDWORD(0x52000000, 0x0);
_Sleep_(1);// delay about 400us
_WDWORD(0x52000000, 0x21);
_Sleep_(1);// delay about 400us
_Sleep_(1);// delay about 400us
_Sleep_(1);// delay about 400us
_Sleep_(1);// delay about 400us
//config xip spi
_WDWORD(0x51000008, 0); //disable spi
_WDWORD(0x5100002c,0); //close IE
_WDWORD(0x51000000,0x1F); //32bit SPI data
_WDWORD(0x51000010,0x01); //enable select slave -- SE
_WDWORD(0x51000018,0x0); //TXFTL be set 0
_WDWORD(0x5100001c,0x0); //RXFTL be set 0
_WDWORD(0x5100010c, 0x01);//enable select slave
_WDWORD(0x51000114, 0xFF);//XIP time out
_WDWORD(0x51000014, 0x2);//div 2
//quad
// _WDWORD(0x51000108, (2)|(6<<4)|(2<<9)|(1<<22)|(1<<29)|(1<<23)|(0<<24)|(8<<13));
// _WDWORD(0x51000100, 0x6b);//quad read cmd
// _WDWORD(0x51000104, 0x6b);//quad read cmd
//dual
_WDWORD(0x51000108, (1)|(6<<4)|(2<<9)|(1<<22)|(1<<29)|(1<<23)|(0)|(8<<13));
_WDWORD(0x51000100, 0x3b);//dual read cmd
_WDWORD(0x51000104, 0x3b);//dual read cmd
_WDWORD(0x51000008, 1); //enable spi
}
FUNC void Initialization(void)
{
InitGpio();
InitFlash();
InitXIP();
SP = _RDWORD(0x11001000);
PC = _RDWORD(0x11001004);
_WDWORD(0x4000013C, 0x11001001);
}
LOAD %L INCREMENTAL
Initialization();
project/example/2.4g/RF24_TEST_CMD/mdk/Linker/cpu.scat
+18
View File
@@ -0,0 +1,18 @@
LOAD 0x10000000
{
EXE 0x10000000
{
startup_xinc.o (RESET, +FIRST)
* (+RO)
}
RW +0000
{
* (+RW,+ZI)
}
;ScatterAssert(ImageLength(RW) < 1024 * 28)
}
project/example/2.4g/RF24_TEST_CMD/mdk/Linker/cpu_xip.scat
+20
View File
@@ -0,0 +1,20 @@
LOAD 0x11001000
{
EXE 0x11001000
{
startup_xinc.o (RESET, +FIRST)
* (+RO)
}
RW 0x10002000
{
* (+RW,+ZI)
*(ram_code)
aeabi_sdiv.o(.text)
uread4.o(.text)
rt_memclr.o(.text)
}
}
project/example/2.4g/RF24_TEST_CMD/mdk/Linker/cpu_xip_xc62xx.scat
+21
View File
@@ -0,0 +1,21 @@
LOAD 0x11001000
{
EXE 0x11001000
{
startup_xinc.o (RESET, +FIRST)
* (+RO)
}
RW 0x100000C8 0x1F38
{
* (+RW,+ZI)
*(ram_code)
aeabi_sdiv.o(.text)
}
ScatterAssert((0x10000100 )+ImageLength(RW) < 0x10000100 + 1024 * 8)
}
project/example/2.4g/RF24_TEST_CMD/mdk/Output/ram_program.bat
+1
View File
@@ -0,0 +1 @@
Xincboot_tool.exe 0_ram.bin 1_ram_download.bin 0 0 0 0 1
project/example/2.4g/RF24_TEST_CMD/mdk/Output/xip_dual
BIN
View File
Binary file not shown.
project/example/2.4g/RF24_TEST_CMD/mdk/Output/xip_program.bat
+1
View File
@@ -0,0 +1 @@
.\Tools\xinchip_xip_tool.exe .\Output\0_ram.bin .\Output\xip_dual .\Output\rf24_ack_xip.bin
project/example/2.4g/RF24_TEST_CMD/mdk/RF24_ACK.uvoptx
+669
View File
@@ -0,0 +1,669 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>rf_2_4g_cmd_demo</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>0</IsCurrentTarget>
</OPTFL>
<CpuCode>7</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>4</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile>.\JLinkSettings.ini</tIfile>
<pMon>Segger\JL2CM3.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGUARM</Key>
<Name>??H</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMRTXEVENTFLAGS</Key>
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMDBGFLAGS</Key>
<Name></Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>JL2CM3</Key>
<Name>-U4294967295 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC1000 -FN1 -FF0xc66xx -FS010000000 -FL020000</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>0</periodic>
<aLwin>1</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>1</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
<Target>
<TargetName>rf_2_4g_cmd_xip_demo</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>7</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>0</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>BIN\UL2CM3.DLL</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>0</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
<Group>
<GroupName>Startup</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>5</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\..\component\xc6xx_drivers\Drivers\CMSIS\core_cm0.h</PathWithFileName>
<FilenameWithoutPath>core_cm0.h</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>2</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\app\Startup\xc60xx\startup_xinc.s</PathWithFileName>
<FilenameWithoutPath>startup_xinc.s</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>3</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\app\Startup\system_xinc.c</PathWithFileName>
<FilenameWithoutPath>system_xinc.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
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<FileNumber>4</FileNumber>
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<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\app\Startup\system_it_xinc.c</PathWithFileName>
<FilenameWithoutPath>system_it_xinc.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>Application</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
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<File>
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<FileNumber>5</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\app\src\main.c</PathWithFileName>
<FilenameWithoutPath>main.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>6</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\app\src\app_rf24g.c</PathWithFileName>
<FilenameWithoutPath>app_rf24g.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>RF_Config</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>7</FileNumber>
<FileType>5</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\app\rf_config\rf_config.h</PathWithFileName>
<FilenameWithoutPath>rf_config.h</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>8</FileNumber>
<FileType>5</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\app\rf_adv_config\rf_adv_config.h</PathWithFileName>
<FilenameWithoutPath>rf_adv_config.h</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>RF_Drivers</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>9</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\..\component\rf24\Drivers\xc6xxx_rf_2_4g\xc6xxx_rf_2_4g.c</PathWithFileName>
<FilenameWithoutPath>xc6xxx_rf_2_4g.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>10</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
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<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\..\component\rf24\Drivers\xc6xxx_rf_single\xc6xxx_rf_single.c</PathWithFileName>
<FilenameWithoutPath>xc6xxx_rf_single.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>11</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\..\component\rf24\Drivers\xc6xxx_rf_ADV\xc6xxx_rf_ADV.c</PathWithFileName>
<FilenameWithoutPath>xc6xxx_rf_ADV.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>Drivers</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>12</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\ringbuffer.c</PathWithFileName>
<FilenameWithoutPath>ringbuffer.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>13</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_clock.c</PathWithFileName>
<FilenameWithoutPath>xc_drv_clock.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>14</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_gpio.c</PathWithFileName>
<FilenameWithoutPath>xc_drv_gpio.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>15</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_pwr.c</PathWithFileName>
<FilenameWithoutPath>xc_drv_pwr.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
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project/example/2.4g/RF24_TEST_CMD/mdk/RF24_ACK.uvprojx
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project/example/2.4g/RF24_TEST_CMD/mdk/Tools/dump.py
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#!/usr/bin/env python
#-*- coding:UTF-8 -*-
import socket
from select import select
import time
import os
import sys
import threading
import json
import struct
import binascii
import time
import re
import fileinput
def dump_addr(addr):
file_asm = "./Xinc_ble_sdk_asm"
cur_func = ""
with open(file_asm, 'r') as fd:
for line in fd:
if re.match(r" \w+", line) != None:
cur_func = line.strip()
#
if re.search("^ 0x", line) != None and re.search(addr, line) != None:
print(addr, cur_func)
break
fd.close()
if __name__ == "__main__":
file_in = "./dump.txt"
for line in fileinput.input(file_in):
# 处理 PC 指针信息
if re.search("PC = ", line) != None:
pc_addr = line.split("PC = ")[1].split(",")[0]
#print(hex(int(pc_addr, 16)))
dump_addr(hex(int(pc_addr, 16)))
# 处理 栈信息
if re.search("^[0-9]",line) != None:
#print(line)
stack = line.split('=')[1].replace('\n', '').split(' ')
for addr in stack:
if addr == ' ' or re.search("^1", addr) == None:
continue
#print(addr, hex(int(addr,16)-1))
dump_addr(hex(int(addr,16)-1))
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project/example/2.4g/RF24_TEST_CMD/readme.docx
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