#ifndef _BSP_2_4_G_H_
#define _BSP_2_4_G_H_
#include    "Includes.h"






#define    _2_4G_BASE           0x50003000 
#define    CFG_TOP			    ((volatile unsigned *)(_2_4G_BASE	+ 0x00))
#define	   EN_AA				((volatile unsigned *)(_2_4G_BASE	+ 0x04))
#define	   EN_RXADDR			((volatile unsigned *)(_2_4G_BASE	+ 0x08)) 
#define	   SETUP_AW			    ((volatile unsigned *)(_2_4G_BASE	+ 0x0C)) 
#define	   SETUP_RETR			((volatile unsigned *)(_2_4G_BASE	+ 0x10)) 
#define	   RF_CH				((volatile unsigned *)(_2_4G_BASE	+ 0x14)) 
#define	   SETUP_RF			    ((volatile unsigned *)(_2_4G_BASE	+ 0x18)) 
#define	   STATUS				((volatile unsigned *)(_2_4G_BASE	+ 0x1C)) 
#define	   OBSERVE_TX		 	((volatile unsigned *)(_2_4G_BASE	+ 0x20)) 
#define	   RSSI				    ((volatile unsigned *)(_2_4G_BASE	+ 0x24)) 
#define	   RX_ADDR_P0_L			((volatile unsigned *)(_2_4G_BASE	+ 0x28)) 
#define	   RX_ADDR_P0_H			((volatile unsigned *)(_2_4G_BASE	+ 0x2C))    
#define	   RX_ADDR_P1_L			((volatile unsigned *)(_2_4G_BASE	+ 0x30)) 
#define	   RX_ADDR_P1_H			((volatile unsigned *)(_2_4G_BASE	+ 0x34)) 
#define	   RX_ADDR_P2TOP5		((volatile unsigned *)(_2_4G_BASE	+ 0x38)) 
  
#define	   BER_RESULT_L			((volatile unsigned *)(_2_4G_BASE	+ 0x3C))
#define	   BER_RESULT_H			((volatile unsigned *)(_2_4G_BASE	+ 0x40)) 
    
#define	   AGC_SETTING			((volatile unsigned *)(_2_4G_BASE	+ 0x44)) 
#define	   PGA_SETTING_L		((volatile unsigned *)(_2_4G_BASE	+ 0x48))   
#define	   PGA_SETTING_H		((volatile unsigned *)(_2_4G_BASE	+ 0x50)) 
    
#define	   TX_ADDR_L			((volatile unsigned *)(_2_4G_BASE	+ 0x4C)) 
#define	   TX_ADDR_H			((volatile unsigned *)(_2_4G_BASE	+ 0x50))     

#define	   RX_PW_PX_L			((volatile unsigned *)(_2_4G_BASE	+ 0x54)) 
#define	   RX_PW_PX_H			((volatile unsigned *)(_2_4G_BASE	+ 0x58))    
    
#define	   STATUS_FIFO			((volatile unsigned *)(_2_4G_BASE	+ 0x80)) 
#define	   RSSIREC				((volatile unsigned *)(_2_4G_BASE	+ 0x84)) 
#define	   TXPROC_CFG			((volatile unsigned *)(_2_4G_BASE	+ 0x88)) 
#define	   RXPROC_CFG_L			((volatile unsigned *)(_2_4G_BASE	+ 0x8C)) 
#define	   RXPROC_CFG_H			((volatile unsigned *)(_2_4G_BASE	+ 0xA8)) 
#define	   DYNPD				((volatile unsigned *)(_2_4G_BASE	+ 0x94)) 
#define	   FEATURE				((volatile unsigned *)(_2_4G_BASE	+ 0x98))  
    
#define	   CMD_BYTE				((volatile unsigned *)(_2_4G_BASE	+ 0xC0))  
#define	   TXFIFO_WDATA			((volatile unsigned *)(_2_4G_BASE	+ 0xC4))  
#define	   RXFIFO_RDTA			((volatile unsigned *)(_2_4G_BASE	+ 0xC8))  
#define    RXFIFO_LEN           ((volatile unsigned *)(_2_4G_BASE	+ 0xCC)) 
    
#define    R_REG				0x00 
#define    W_REG 				0x20 
#define    R_RX_PLOAD 			0x61 
#define    W_TX_PLOAD			0xA0 
#define    FLUSH_TX			    0xE1 
#define    FLUSH_RX			    0xE2 
#define    REUSE_TX_PL			0xE3 
#define    R_RX_PL_WID			0x60 
#define    W_ACK_PLOAD			0xA8 
#define    W_TX_PLOAD_NOACK	    0xB0 
#define    CMD_NOP				0xFF 
#define    CMD_DONE				0x100 

#define TX_REUSE        		(0x1 << 6) 
#define TX_FULL            		(0x1 << 5) 
#define TX_EMPTY        		(0x1 << 4) 
#define RX_FULL            		(0x2) 
#define RX_EMPTY        		(0x1) 

/* STATUS Interrupt status */
#define XC_RX_DR    		(0x1 << 6)//@
#define XC_TX_DS    		(0x1 << 5)//@
#define XC_MAX_RT   		(0x1 << 4)//@
#define ALL_IRQ_STATUS          (0x70)//@

// 
#define EN_LONG_PLD        1
#define EN_FEC             1
#define EN_WHITEN          1
#define EN_DPL             1
#define EN_ACK_PAY         1

#define DIS_LONG_PLD        0
#define DIS_FEC             0
#define DIS_WHITEN          0
#define DIS_DPL             0
#define DIS_ACK_PAY         0

#define EN_CRC              1
#define DIS_CRC             0

#define CRC_1BIT            1
#define CRC_2BIT            2

#define setbit_array(x,y) (setbit((x)[(y)/8],(y)%8))
#define clrbit_array(x,y) (clrbit((x)[(y)/8],(y)%8))

#define    CE_High    *CFG_TOP |=0x4000 
#define    CE_Low     *CFG_TOP &=(~0x4000)
 
 
#define 	TX_MODE    0x0
#define     RX_MODE    0x1


#define nop()   __NOP();\
                __NOP();\
				__NOP();\
				__NOP()






extern void send_cmd(uint8_t cmd);
extern void     BLEcrc(const uint8_t* data, uint8_t dataLen, uint8_t* outputCRC);  
extern void     bleWhiten(uint8_t* data, uint8_t len, uint8_t whitenCoeff);        
extern uint8_t  bleWhitenStart(uint16_t Fre);
extern uint8_t  reverseBits(uint8_t input);
extern uint8_t XC_RxPacket(uint8_t en_ack_pay,uint8_t *ack_buf,uint8_t ack_len,uint8_t *rxbuf);
extern void     XC_TxPacket(uint8_t *txbuf, uint8_t len);
extern void     init_24G(uint8_t mode);
extern void     init_adv(uint8_t mode);
extern void     set_channel(uint16_t channel);
extern void     config_2_4g_rf(void);
extern void     set_power(uint8_t gc);
void  set_txaddr(uint32_t txaddr_l,uint32_t txaddr_h);
void  set_pipe0_rxaddr(uint32_t rxaddr_l,uint32_t rxaddr_h);
void  set_trx_addr_len(uint8_t len);
void  set_rate(uint8_t rate);
void  set_feature(uint8_t long_pld,uint8_t fec,uint8_t whiten,uint8_t dpl,uint8_t ack_pay);
void  set_mode(uint8_t mode);
void  set_crc(uint8_t enable,uint8_t crc_bit);
void  set_p012345_revlen(uint32_t p0123len,uint32_t p45len);
void  set_pipe0_revlen(uint8_t p0len);
void  rf_rccalib(void);
void  go_tx(uint16_t ch);
void  go_rx(uint16_t ch);
void  rx_24g_ota(void);

uint8_t wait_ack(uint8_t *ack_pay_buf,uint8_t *len,uint32_t timeout);

void  set_retry_cnt(uint8_t ch);

/////////////////////////////////////////////////////////
#define CLK_BBPLL64M        0
#define CLK_BBPLL96M        1
#define  _24G_CLK_SOURCE    CLK_BBPLL96M
///////////////////////////////////////////////////////// 
 
#define BUFF_ADV_LENGTH 15
#define BUFF_24G_LENGTH 32
#define BUFF_24G_ACK_PAY_LENGTH 7

/////////////////////////////////////////////////////////
#define RF_ADV_CHANNELS_37    2402
#define RF_ADV_CHANNELS_38    2426
#define RF_ADV_CHANNELS_39    2480
#define RF_ADV_CHANNELS       RF_ADV_CHANNELS_38

#define CHANNEL_24G        2402

/////////////////////////////////////////////////////////
#define RATE_2M            0x0A
#define RATE_1M            0x02
#define RATE_250K          0x22   
#define RATE_125K          0x2A 

//#define TRANS_RATE         RATE_250K 
//#define TRANS_RATE         RATE_1M 
#define TRANS_RATE         RATE_1M  //RATE_250K RATE_125K RATE_1M 
/////////////////////////////////////////////////////////
#define POWER_LEVEL        0x10 /////tip:1M Max Power 0x2c(6.8dbm)  
/////////////////////////////////////////////////////////
//#define  USE_24G_IRQ
/////////////////////////////////////////////////////////
#define  ACK_TOMEOUT       0x10000    //4550
/////////////////////////////////////////////////////////
#define TEST_SINGLE       0
#define TEST_24G          1
#define TEST_ADV          0
#define TEST_SWITCH_24G   0
/////////////////////////////////////////////////////////



#define DEBUG1
//#define DEBUG2




#define FLASH_BIN_ADDR_OFFSET    (0x3000)
#define PACKET_LENGTH            (29) 
enum{
 
    STATUS_OK=0,
	STATUS_FAIL=1,
    STATUS_BUSY=2,
    STATUS_READY=3,
};
enum{
    rFALSE=0,//false
	rTRUE=1, //true
};
typedef struct{
    
	uint32_t SoftVer;/**/
	uint32_t RomVer;
	uint32_t Len;/*file len*/
	uint32_t CRC32;/*crc32*/
	
	uint32_t PacketNum;
	uint32_t cPacketNo;
	
	uint32_t Channel;
	
	uint32_t AddrH;
	uint32_t AddrL;
	
	uint32_t FrameNum;
	uint32_t cFrameNo;
	
	uint32_t WriteAddr;
	
	uint32_t DataStatus:8;
    uint32_t CheckStatus:8; 
    uint32_t RevComplete:8;
    uint32_t ResStatus1:8;	
}INFO_24G;
extern volatile INFO_24G info_24g;


#endif