#ifndef _BSP_GP_ADC_H_
#define _BSP_GP_ADC_H_

#define FIFO_DEEP 16

#define GADC_FREQ_500K 16
#define GADC_FREQ_1M 8
#define GADC_FREQ_2M 4
#define GADC_FREQ_4M 2
#define GADC_FREQ_8M 1

#define GADC_REF_2_47V 1
#define GADC_REF_AVDD 2

typedef struct gadc_cache_struct
{
    unsigned int value_2 : 10;
    unsigned int chanel_2 : 4;
    unsigned int : 2;
    unsigned int value_1 : 10;
    unsigned int chanel_1 : 4;
    unsigned int : 2;
} gadc_cache_t;

void init_adc(uint8_t freq, uint8_t gadc_ref);
void adc_gpio_config(uint8_t cio);
int gadc_calibration_get(uint32_t *value);

#define IO_GPADC_CHANNEL0 21   /*gpio21*/
#define IO_GPADC_CHANNEL1 20   /*gpio20*/
#define IO_GPADC_CHANNEL2 19   /*gpio19*/
#define IO_GPADC_CHANNEL3 18   /*gpio18*/
#define IO_GPADC_CHANNEL4 0    /*gpio0 */
#define IO_GPADC_CHANNEL5 1    /*gpio1 */
#define IO_GPADC_CHANNEL6 4    /*gpio4 */
#define IO_GPADC_CHANNEL7 5    /*gpio5 */
#define IO_GPADC_CHANNEL8 0xff /*???????2/3 ???????3.3V????8?????2.2V*/
#define IO_GPADC_CHANNEL9 0xff
#define IO_GPADC_CHANNEL10 2 /*gpio2 */
#define IO_GPADC_CHANNEL11 3 /*gpio3 */

#define GPADC_MAIN_CTL_EX_SAMPLE_NUM_Pos 12
#define GPADC_MAIN_CTL_EX_SAMPLE_NUM_Msk (0xFul << GPADC_MAIN_CTL_EX_SAMPLE_NUM_Pos)

#define GPADC_MAIN_CTL_EX_TRIGGER_SEL_Pos 8
#define GPADC_MAIN_CTL_EX_TRIGGER_SEL_Msk (0x7ul << GPADC_MAIN_CTL_EX_TRIGGER_SEL_Pos)

#define GPADC_MAIN_CTL_EX_EDGE_SEL_Pos 4
#define GPADC_MAIN_CTL_EX_EDGE_SEL_Msk (0x3ul << GPADC_MAIN_CTL_EX_EDGE_SEL_Pos)

#define GPADC_MAIN_CTL_EDGE_SEL_Pos 3
#define GPADC_MAIN_CTL_EDGE_SEL_Msk (1ul << GPADC_MAIN_CTL_EDGE_SEL_Pos)

#define GPADC_MAIN_CTL_AUTO_SW_Pos 2
#define GPADC_MAIN_CTL_AUTO_SW_Msk (1ul << GPADC_MAIN_CTL_AUTO_SW_Pos)

#define GPADC_MAIN_CTL_DMAS_ON_Pos 1
#define GPADC_MAIN_CTL_DMAS_ON_Msk (1ul << GPADC_MAIN_CTL_DMAS_ON_Pos)

#define GPADC_MAIN_CTL_EN_Pos 0
#define GPADC_MAIN_CTL_EN_Msk (1ul << GPADC_MAIN_CTL_EN_Pos)
#endif