#include "Includes.h"


// #define     printf(...)             (0)

#ifdef XIP_JUMP

#endif
typedef void (*iapfun)(void); // 定义一个函数类型的参数.
iapfun jump2app;
__asm void MSR_MSP(uint32_t addr) // 设置栈顶地址  addr:栈顶地址
{
    MSR MSP, r0 // set Main Stack value
                 BX r14
}
void delay_wait(uint8_t cn)
{
    for (int i = 0; i < cn; i++)
        for (int j = 0; j < 0x200; j++)
            ;
}
void jump_app()
{
    uint32_t pes=0x11001000;
    typedef void (*iapfun)(void); // 定义一个函数类型的参数static iapfun jump2app;
    jump2app = (iapfun) * (uint32_t *)(pes + 4);
     MSR_MSP(*(uint32_t *) (pes));
    jump2app ();

    while(1);
}

#define __write_hw_reg32(reg,val)  ((*reg) = (val))
#define __read_hw_reg32(reg, val)  ((val) = (*reg))  
#define setbit(x,y) ((x) |= (1<<(y)))
#define clrbit(x,y) ((x) &= ~(1<<(y)))

#define CPR_BASE						0x40000000
#define CPR_SPIx_MCLK_CTL(a)            ((volatile unsigned *)(CPR_BASE + 0x050 + (a*0x04)))
#define CPR_CTLAPBCLKEN_GRCTL        ((volatile unsigned *)(CPR_BASE + 0x070))
#define CPR_RSTCTL_SUBRST_SW         ((volatile unsigned *)(CPR_BASE + 0x104))
#define CPR_CTL_MUXCTL3              ((volatile unsigned *)(CPR_BASE + 0x19c))
void close_ssi0(void)
{
   	__write_hw_reg32(CPR_SPIx_MCLK_CTL(0), 0x110000);//close ssi0 mclk
    __write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL , (0x1000000)); //close ssi0 pclk
    __write_hw_reg32(CPR_RSTCTL_SUBRST_SW , 0x040000); //复位ssi0
    __write_hw_reg32(CPR_RSTCTL_SUBRST_SW , 0x040004); //复位ssi0
}

extern void gpio_mux_ctl_u(uint8_t num, uint8_t mux) //(num:32-34)
{
    if (mux > 3)
        return;
    uint32_t tv = 0;
    __read_hw_reg32(CPR_CTL_MUXCTL3, tv);
    tv = (tv & (~(0x3 << ((num % 16) * 2)))) | (mux << ((num % 16) * 2));
    __write_hw_reg32(CPR_CTL_MUXCTL3, tv);
}

extern void init_xip(uint8_t mode)
{

#ifdef QUAD_ENABLE
    if (mode == QUAD_MODE)
    {

        if ((spi_flash_read_stat() & 0x02) == 0)
        {

            spi_flash_write_enable();
            spi_flash_quad_en();
            while (spi_flash_wait_till_ready())
                ;
        }
        else
        {
#ifdef DEBUG_PRINT
            printf("quad has been enabled !!!\n");
#endif
        }
    }
#endif
    close_ssi0(); // close ssi0

    // config fmc pin
    gpio_mux_ctl_u(33, 1); // d2
    gpio_mux_ctl_u(34, 1); // d3

    gpio_mux_ctl_u(35, 2); // clk
    gpio_mux_ctl_u(36, 2); // cs
    gpio_mux_ctl_u(37, 2); // d0 rx
    gpio_mux_ctl_u(38, 2); // d1 tx

    // open fmc clk
    __write_hw_reg32(FMC_CTL, 0x0503 | (0 << 11)); //
    delay_wait(1);
    __write_hw_reg32(FMC_CTL, 0x3503 | (0 << 11)); //
    delay_wait(1);
    // config cache
    __write_hw_reg32(CACHE_CCR, 0x00);
    delay_wait(6);
    __write_hw_reg32(CACHE_CCR, 0x21);
    delay_wait(6);

    // config fmc contrl
    __write_hw_reg32(FMC_EN, 0x00); // Disables DWC_ssi

    __write_hw_reg32(FMC_IE, 0x00);
    __write_hw_reg32(FMC_CTRL0, 0x1F); /* 32bit SPI data */
    __write_hw_reg32(FMC_SE, 0x01);
    __write_hw_reg32(FMC_RXFTL, 0x00);
    __write_hw_reg32(FMC_TXFTL, 0x00);

    __write_hw_reg32(FMC_XIP_SER, 0x01);
    __write_hw_reg32(FMC_XIP_CNT_TIME_OUT, 0xFF); // XIP time out
    __write_hw_reg32(FMC_BAUD, 0x2);              // SSI Clock Divider= 2 --mclk/2
    if (mode == QUAD_MODE)                        // #ifdef  QUAD_ENABLE //1   //quad
    {
#ifdef DEBUG_PRINT
        uart_printf("xip quad cmd\n");
#endif
        __write_hw_reg32(FMC_XIP_CTRL, (2) | (6 << 4) | (2 << 9) | (1 << 22) | (1 << 29) | (1 << 23) | (0 << 24) | (8 << 13));
        __write_hw_reg32(FMC_XIP_INCR_INST, 0x6b); // quad read cmd
        __write_hw_reg32(FMC_XIP_WRAP_INST, 0x6b); // quad read cmd
    }
    else // #else   //dual
    {
#ifdef DEBUG_PRINT
//        printf("xip dual cmd\n");
#endif
        __write_hw_reg32(FMC_XIP_CTRL, (1) | (6 << 4) | (2 << 9) | (1 << 22) | (1 << 29) | (1 << 23) | (0) | (8 << 13));
        __write_hw_reg32(FMC_XIP_INCR_INST, 0x3b); // dual read cmd
        __write_hw_reg32(FMC_XIP_WRAP_INST, 0x3b); // dual read cmd
    }                                              // #endif

    __write_hw_reg32(FMC_EN, 0x01); // Enables  DWC_ssi
    __write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL, 0x100000);
    __write_hw_reg32(CPR_RSTCTL_SUBRST_SW, 0x10000);
}