/*! * \file xc6axx.h * * \brief The header of xc6axx chip * * \copyright Revised BSD License, see section \ref LICENSE. * * \code * * _ __ _ ________ _ * | |/ /(_)___ / ____/ /_ (_)___ * | // / __ \/ / / __ \/ / __ \ * / |/ / / / / /___/ / / / / /_/ / * /_/|_/_/_/ /_/\____/_/ /_/_/ .___/ * /_/ * (C) 2022-2025 XinChip * * \endcode * * \author ( XinChip ) Alex-J * * \author ( XinChip ) */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __XC6AXX_H__ #define __XC6AXX_H__ #ifdef __cplusplus extern "C" { #endif /*----------------------------------------------------------------------------------- INCLUDE HEADE FILES ------------------------------------------------------------------------------------*/ #include #include #include #include /*------------------------------------------------------------------------------------ Macros -------------------------------------------------------------------------------------*/ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ #define __RAM_CODE __attribute__((section("ram_code"))) #define __WEAK __attribute__((weak)) #ifndef __PACKED #define __PACKED __attribute__((packed)) #endif #ifndef __UNALIGNED_UINT32_WRITE #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) #endif #define __STATIC_INLINE static __inline #define QDEC_USE_P20_P21 #define HFCLK_SRC_XTAL_IS_24M #define XC6AXX_TEST_CODE #define NEW_BLE_COMMON_BASE #define XC6AXX_ROM_DRIVER_ADDR #define NO_SUPPORT_ROM_FMC_SPI /* * ========================================================================== * ---------- Interrupt Number Definition ----------------------------------- * ========================================================================== */ typedef enum IRQn { /* ------------------- Processor Exceptions Numbers ----------------------------- */ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /* 3 HardFault Interrupt */ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ SVCall_IRQn = -5, /* 11 SV Call Interrupt */ DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ SysTick_IRQn = -1, /* 15 System Tick Interrupt */ /* ------------------- Processor Interrupt Numbers ------------------------------ */ BLE_IRQn = 0, /*!< Device Interrupt */ DMA_IRQn = 1, CPR_IRQn = 2, GPIO_IRQn = 3, RTC_IRQn = 4, TIMER0_IRQn = 5, TIMER1_IRQn = 6, TIMER2_IRQn = 7, TIMER3_IRQn = 8, WDT_IRQn = 9, I2C_IRQn = 10, UART0_IRQn = 11, UART1_IRQn = 12, SPI0_IRQn = 13, SPI1_IRQn = 14, KBS_IRQn = 15, QDEC_IRQn = 16, GADC_IRQn = 17, PWM_IRQn = 18, AES_IRQn = 19, USB_IRQn = 20, CDC_IRQn = 21, RF24G_IRQn = 22, SPI2_IRQn = 23, FPU_IRQn = 24, UART2_IRQn = 25, I2S_IRQn = 26, TIMER_AO0_IRQn = 27, TIMER_AO1_IRQn = 28, CMP_IRQn = 29, FMC_IRQn = 30, CAN_IRQn = 31, BT_IRQn = 32, BT_DM_IRQn = 33, BT_DBM_IRQn = 34, UNUSED_IRQn /* Interrupts 46 .. 63 are left out */ } IRQn_Type; /* * ========================================================================== * ----------- Processor and Core Peripheral Section ------------------------ * ========================================================================== */ /* Configuration of the Cortex-M# Processor and Core Peripherals */ /* ToDo: set the defines according your Device */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ #if defined ( __CC_ARM ) #if defined (__TARGET_FPU_VFP) #define __FPU_PRESENT 1 /*!< FPU present or not */ #else #define __FPU_PRESENT 0 /*!< FPU present or not */ #endif #else #define __FPU_PRESENT 0 /*!< FPU present or not */ #endif /*@}*/ /* end of group _CMSIS */ #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ #include "compiler.h" /* =========================================================================================================================== */ /* ================ QDEC ================ */ /* =========================================================================================================================== */ /** * @brief Quadrature Decoder (QDEC) */ typedef struct { /*!< (@ 0x40016000UL) QDEC Structure */ __IOM uint32_t QDEC_CTL; /*!< (@ 0x00000000) QDEC Control Register */ __IOM uint32_t SAMP_CTL; /*!< (@ 0x00000004) QDEC Sample Control Register */ __IM uint32_t SAMPLE; /*!< (@ 0x00000008) QDEC Sample State Register */ __IM uint32_t ACC; /*!< (@ 0x0000000C) QDEC Acc Counter Now Register */ __IM uint32_t ACC_R; /*!< (@ 0x00000010) QDEC Acc Counter Record Register */ __IM uint32_t DB; /*!< (@ 0x00000014) QDEC Double Bounce Counter Now Register */ __IM uint32_t DB_R; /*!< (@ 0x00000018) QDEC Double Bounce Counter Record Register */ __IOM uint32_t INT; /*!< (@ 0x0000001C) QDEC Interrupt Register */ __IOM uint32_t INT_MSK; /*!< (@ 0x00000020) QDEC Interrupt Mask Register */ __IM uint32_t QDEC_STAT; /*!< (@ 0x00000024) QDEC Counter Busy State Register */ } QDEC_TypeDef; /* =========================================================================================================================== */ /* ================ 2.4G ================ */ /* =========================================================================================================================== */ /* RF 2.4G Module Register Typedef */ typedef struct { __IOM uint32_t CFG_TOP; /*!< Top-level configuration (0x000) */ __IOM uint32_t EN_AA; /*!< Auto-acknowledgement settings (0x004) */ __IOM uint32_t EN_RXADDR; /*!< Enable RX addresses (0x008) */ __IOM uint32_t SETUP_AW; /*!< Address width & timing stup (0x00C) */ __IOM uint32_t SETUP_RETR; /*!< Automatic retransmission setup (0x010) */ __IOM uint32_t RF_CH; /*!< RF channel (0x014) */ __IOM uint32_t SETUP_RF; /*!< RF settings (0x018) */ __IOM uint32_t STATUS; /*!< Status, SDO output may be adjusted (0x01C) */ __IOM uint32_t OBSERVE_TX; /*!< Transmission observation (0x020) */ __IOM uint32_t RSSI; /*!< TSSI and RSSI indicator/control (0x024) */ __IOM uint32_t RX_ADDR_P0_L; /*!< RX address low 32bit for data pipe 0 (0x028) */ __IOM uint32_t RX_ADDR_P0_H; /*!< RX address high 8bit for data pipe 0 (0x02C) */ __IOM uint32_t RX_ADDR_P1_L; /*!< RX address low 32bit for data pipe 1 (0x030) */ __IOM uint32_t RX_ADDR_P1_H; /*!< RX address high 8bit for data pipe 1 (0x034) */ __IOM uint32_t RX_ADDR_P2TOP5; /*!< Only LSB are set, MSB use RX_ADDR_P1 (0x038) */ __IOM uint32_t BER_RECV_CNT; /*!< Receive total Bit Counter for BER Test (0x03C) */ __IOM uint32_t BER_ERR_CNT; /*!< Receive error Bit Counter for BER Test (0x040) */ __IOM uint32_t AGC_SETTING; /*!< AGC setting (0x044) */ __IOM uint32_t PGA_SETTING; /*!< PGA setting (0x048) */ __IOM uint32_t TX_ADDR_L; /*!< TX address low 32bit (0x04C) */ __IOM uint32_t TX_ADDR_H; /*!< TX address high 8bit (0x050) */ __IOM uint32_t RX_PW_Px_L; /*!< Number of bytes in data pipe0~3 (0x054) */ __IOM uint32_t RX_PW_Px_H; /*!< Number of bytes in data pipe4~5 (0x058) */ __IOM uint32_t ANALOG_CFG0_L; /*!< Analog register 0 low 32bit (0x05C) */ __IOM uint32_t ANALOG_CFG0_H; /*!< Analog register 0 high 32bit (0x060) */ __IOM uint32_t ANALOG_CFG1_L; /*!< Analog register 1 low 32bit (0x064) */ __IOM uint32_t ANALOG_CFG1_H; /*!< Analog register 1 high 32bit (0x068) */ __IOM uint32_t ANALOG_CFG2_L; /*!< Analog register 2 low 32bit (0x06C) */ __IOM uint32_t ANALOG_CFG2_H; /*!< Analog register 2 high 32bit (0x070) */ __IOM uint32_t ANALOG_CFG3_L; /*!< Analog register 3 low 32bit (0x074) */ __IOM uint32_t ANALOG_CFG3_H; /*!< Analog register 3 high 32bit (0x078) */ __IM uint32_t Reserved1; /*!< Reserved1 (0x07C) */ __IOM uint32_t STATUS_FIFO; /*!< FIFO status (0x080) */ __IOM uint32_t RSSIREC; /*!< RSSI recorder feature (0x084) */ __IOM uint32_t TXPROC_CFG; /*!< TX Process configuration (0x088) */ __IOM uint32_t RXPROC_CFG_L; /*!< RX Process configuration (0x08C) */ __IM uint32_t Reserved2; /*!< Reserved2 (0x090) */ __IOM uint32_t DYNPD; /*!< Dynamic payload length (0x094) */ __IOM uint32_t FEATURE; /*!< Features (0x098) */ __IM uint32_t Reserved3[3]; /*!< Reserved3 (0x09C - 0x0A4) */ __IOM uint32_t RXPROC_CFG_H; /*!< PA Ramp Configuration (0x0A8) */ __IM uint32_t Reserved4[5]; /*!< Reserved4 (0x0AC - 0x0BC) */ __IOM uint32_t CMD_CFG; /*!< Command Configuration (0x0C0) */ __IOM uint32_t TX_FIFO_DATA; /*!< Tx Fifo Data (0x0C4) */ __IOM uint32_t RX_FIFO_DATA; /*!< Rx Fifo Data (0x0C8) */ __IOM uint32_t RX_FIFO_LEN; /*!< Tx Fifo Data Len (0x0CC) */ } RF_2_4G_TypeDef; #ifdef __cplusplus } #endif #endif /* __XC6AXX_H__ */