333 lines
9.4 KiB
C
333 lines
9.4 KiB
C
#include "Includes.h"
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#if 1
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#define RCV_LEN 1024
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#define SND_LEN 1024
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#define CH_TX 3
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#define CH_RX 11
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#define CH11_BLK (1 << 11) //通道 11 块传输结束
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#define CH3_BLK_EN (1 << 3) //通道3 块传输结束使能
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static uint8_t __attribute__((aligned(4))) spi1_rcv_data[RCV_LEN];
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volatile uint16_t spi1_rcv_len = 0;
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static uint8_t __attribute__((aligned(4))) spi1_send_data[SND_LEN];
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volatile uint16_t spi1_send_len = 0;
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/* ---------------------------------------------------------------------------------------------------
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- 函数名称: dma_ssi1_send
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- 函数功能: spi slave 发送接口函数
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- 输入参数:
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- 创建日期:
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----------------------------------------------------------------------------------------------------*/
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void dma_ssi1_send(uint32_t snd_len)
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{
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__write_hw_reg32(DMAS_CHx_CTL0((CH_TX)) ,snd_len); //set trans byte len
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__write_hw_reg32(DMAS_CLR ,CH_TX); //disable DMA TX channel
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__write_hw_reg32(DMAS_EN ,CH_TX); //enable DMA TX channel
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}
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/* ---------------------------------------------------------------------------------------------------
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- 函数名称: Init_spi_selve
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- 函数功能: spi slave 初始化函数接口
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- 输入参数:
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- 创建日期:
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----------------------------------------------------------------------------------------------------*/
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void Init_spi_selve(uint32_t ch)
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{
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uint32_t val;
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__write_hw_reg32(CPR_SPIx_MCLK_CTL(ch), 0x110010);//1分频 //- spi(x)_mclk = 32Mhz(When TXCO=32Mhz).
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__write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL , (0x1000100<<ch)); //- 打开spi(x) pclk.
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__read_hw_reg32(CPR_SSI_CTRL, val);
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val |= (ch==0)? 0x01: 0x10;
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__write_hw_reg32(CPR_SSI_CTRL, val); //spi1 set slave
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__write_hw_reg32(SSIx_EN(ch), 0x00);
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__write_hw_reg32(SSIx_IE(ch), 0x10); /*接收满中断使能 接收FIFO上溢出 下溢出中断使能 */
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__write_hw_reg32(SSIx_CTRL0(ch) , 0x07); /* 8bit SPI data */
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__write_hw_reg32(SSIx_BAUD(ch), 2); /*- spix_mclk 分频 selve 在32M时钟下只能忍受4M (内部八分频)*/
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//Init_dma_ssi1();
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__write_hw_reg32(SSI1_DMAS , 0x02);
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__write_hw_reg32(SSI1_DMATDL, 0x04);
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//- TX Channel CH_TX
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__write_hw_reg32(DMAS_CHx_SAR(CH_TX) , (uint32_t)spi1_send_data);
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__write_hw_reg32(DMAS_CHx_DAR(CH_TX) , (uint32_t)SSI1_DATA);
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__write_hw_reg32(DMAS_CHx_CTL1(CH_TX) ,((2 << 8)));
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//__write_hw_reg32(DMAS_CHx_CTL0(CH_TX) ,0);//set trans byte len
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//__write_hw_reg32(DMAS_EN , CH_TX); //enable DMA TX channel
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//__write_hw_reg32(DMAS_INT_EN0,(CH3_BLK_EN));
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//NVIC_EnableIRQ(DMAS_IRQn);
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__write_hw_reg32(SSIx_EN(ch) , 0x01); //开启SPI传输
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NVIC_EnableIRQ(SPI0_IRQn+ch);
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}
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//uint8_t rev_num=0;
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extern void SPI1_Handler(void)
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{
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uint32_t spi1_data=0;
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__read_hw_reg32(SSI1_RXFL,spi1_data);
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while(spi1_data>0)
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{
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spi1_rcv_data[spi1_rcv_len++]=*SSIx_DATA(1);
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if(spi1_rcv_len==1024)spi1_rcv_len=0;
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//*SSIx_DATA(1)=rev_num++;
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__read_hw_reg32(SSI1_RXFL,spi1_data);
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}
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__read_hw_reg32(SSI1_IC,spi1_data);
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}
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extern void test_spi1_selve(void)
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{
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gpio_mux_ctl(0,0);gpio_fun_inter(0,0);gpio_fun_sel(0,SSI1_SSN);
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gpio_mux_ctl(1,0);gpio_fun_inter(1,0);gpio_fun_sel(1,SSI1_CLK);
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gpio_mux_ctl(2,0);gpio_fun_inter(2,0);gpio_fun_sel(2,SSI1_TX);
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gpio_mux_ctl(3,0);gpio_fun_inter(3,0);gpio_fun_sel(3,SSI1_RX);
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Init_spi_selve(1);
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while(1)
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{
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switch(spi1_rcv_data[0])
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{
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case 'A':
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spi1_rcv_data[0]=0;spi1_rcv_len=0;
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for(int i=0;i<SND_LEN;i++) spi1_send_data[i]=i;
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spi1_send_data[0]=0x11;
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dma_ssi1_send(SND_LEN);
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break;
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case 'B':
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spi1_rcv_data[0]=0;spi1_rcv_len=0;
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for(int i=0;i<SND_LEN;i++) spi1_send_data[i]=i;
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spi1_send_data[0]=0x22;
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dma_ssi1_send(SND_LEN);
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break;
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case 'C':
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spi1_rcv_data[0]=0;spi1_rcv_len=0;
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for(int i=0;i<SND_LEN;i++) spi1_send_data[i]=i;
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spi1_send_data[0]=0x33;
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dma_ssi1_send(SND_LEN);
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break;
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case 'D':
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spi1_rcv_data[0]=0;spi1_rcv_len=0;
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for(int i=0;i<SND_LEN;i++) spi1_send_data[i]=i;
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spi1_send_data[0]=0x44;
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dma_ssi1_send(SND_LEN);
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break;
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default:spi1_rcv_len=0; break;
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}
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}
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}
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static uint8_t __attribute__((aligned(4))) rxbuff[256];
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static uint8_t __attribute__((aligned(4))) txbuff[256];
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void Init_spi1_master(uint32_t ch, uint32_t freq)
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{
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uint32_t val;
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__write_hw_reg32(CPR_SPIx_MCLK_CTL(ch), 0x110010);//1分频 //- spi(x)_mclk = 32Mhz(When TXCO=32Mhz).
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__write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL , (0x1000100<<ch)); //- 打开spi(x) pclk.
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__read_hw_reg32(CPR_SSI_CTRL, val);
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val |= (ch==0)? 0x01: 0x30;
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__write_hw_reg32(CPR_SSI_CTRL, val);
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__write_hw_reg32(SSIx_EN(ch), 0x00);
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__write_hw_reg32(SSIx_IE(ch), 0x00);
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__write_hw_reg32(SSIx_CTRL0(ch) , 0x07); /* 8bit SPI data */
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__write_hw_reg32(SSIx_SE(ch), 0x01);
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__write_hw_reg32(SSIx_BAUD(ch), freq); //- spix_mclk 分频.
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__write_hw_reg32(SSIx_RXFTL(ch), 0x00);
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__write_hw_reg32(SSIx_TXFTL(ch), 0x00);
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//__write_hw_reg32(SSIx_EN(ch) , 0x01);
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}
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void spi1_read_write(uint16_t len)
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{
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uint32_t iWK = 0;
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__write_hw_reg32(SSI1_EN , 0x00);
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__write_hw_reg32(SSI1_DMAS , 0x03);
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__write_hw_reg32(SSI1_DMATDL, 0x4); //-
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__write_hw_reg32(SSI1_DMARDL, 0x4); //- 1/4 FIFO
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__write_hw_reg32(SSI1_EN , 0x01);
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//- RX Channel
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__write_hw_reg32(DMAS_CHx_SAR(11) , 0x40014060);
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__write_hw_reg32(DMAS_CHx_DAR(11) , (uint32_t)rxbuff);
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__write_hw_reg32(DMAS_CHx_CTL1(11) ,((2 << 8)));//8bits
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__write_hw_reg32(DMAS_CHx_CTL0(11) ,(len));
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__write_hw_reg32(DMAS_EN , 11);
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//- TX Channel
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__write_hw_reg32(DMAS_CHx_SAR(3) , (uint32_t)txbuff);
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__write_hw_reg32(DMAS_CHx_DAR(3) , 0x40014060);
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__write_hw_reg32(DMAS_CHx_CTL1(3) ,((2 << 8)));//8bits
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__write_hw_reg32(DMAS_CHx_CTL0(3) ,(len));
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__write_hw_reg32(DMAS_EN , 3);
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do {
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__read_hw_reg32(DMAS_INT_RAW , iWK);
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}while((iWK&0x808) != 0x808);
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__write_hw_reg32(DMAS_INT_RAW, 0x808);
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__write_hw_reg32(DMAS_CLR , 11);
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__write_hw_reg32(DMAS_CLR , 3);
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__write_hw_reg32(SSI1_EN , 0x00);
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}
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void test_spi1_master(void)
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{
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gpio_mux_ctl(0,0);gpio_fun_inter(0,0);gpio_fun_sel(0,SSI1_SSN);
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gpio_mux_ctl(1,0);gpio_fun_inter(1,0);gpio_fun_sel(1,SSI1_CLK);
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gpio_mux_ctl(2,0);gpio_fun_inter(2,0);gpio_fun_sel(2,SSI1_RX);
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gpio_mux_ctl(3,0);gpio_fun_inter(3,0);gpio_fun_sel(3,SSI1_TX);
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for(int i=0;i<256;i++)
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{
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rxbuff[i]=i;
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txbuff[i]=i;
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}
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Init_spi1_master(1,SPIM_CLK_4MHZ);
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while(1){
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spi1_read_write(256);//此函数执行时间1.12ms
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for(int i=0;i<0x455000;i++);
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}
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}
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#endif
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#if 0
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static void wbit16(uint16_t reg_addr,int end,int start,char* bit_str)
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{
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uint16_t reg_val = 0;
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char ch = 0;
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int i = 0;
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if(strlen(bit_str) != (end-start+1))
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{
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while(1); //error
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}
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reg_val = *(uint16_t *)(0X4002F000+reg_addr);
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for(i=start;i<=end;i++)
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{
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int bit_idx = i-start; //index of bit string
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ch = bit_str[(end-start)-bit_idx] - '0';
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if(ch==1)
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{
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setbit(reg_val,i);
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}
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else if(ch==0)
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{
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clrbit(reg_val,i);
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}
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}
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*(uint16_t *)(0X4002F000+reg_addr)=reg_val;
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}
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void osc32M_to_pll64M(void)
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{
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//???????
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//for(uint32_t i=0;i<0x1200000;i++);
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uint32_t val;
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//??APB??
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__read_hw_reg32(((volatile unsigned *)(0x40000000+ 0x130)), val);
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__write_hw_reg32(((volatile unsigned *)(0x40000000+ 0x130)), (val&0xFFFFFFFE));
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//??PLLM 48M??
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wbit16(0x03D8,15,15,"1"); // bbpll ldo en
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//wbit16(0x03D8,4,3,"11"); // bbpll fref div4
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wbit16(0x001C,15,15,"1"); //debug BBPLL reset ,low reset
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wbit16(0x001C,14,14,"1"); //Enable for BBPLL1,high enable,also control ref clock
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wbit16(0x001C,13,13,"1"); // debug_DA_BBPLL1_EN
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wbit16(0x001C,8,8,"1"); // Enable for 104M clk output to digital module
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wbit16(0x0020,15,15,"1"); // reg BBPLL reset ,low reset
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wbit16(0x0020,14,14,"1"); // Enable for BBPLL1,high enable,also control ref clock
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wbit16(0x0020,13,13,"1"); // debug_DA_BBPLL1_EN
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wbit16(0x0020,8,8,"1"); // Enable for 104M clk output to digital module
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///wbit16(0x0024,9,4,"000110");// default 001100, div12,32m 000110,div
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wbit16(0x0024,9,4,"001000"); //64M
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wbit16(0x03D4,13,11,"011"); // vdd64m res
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//xc_delay(1);//Delay 10ms
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//??????PLL48M ??bbpll??????
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*((volatile unsigned *)(CPR_AO_BASE + 0x20)) =0x2E;
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__read_hw_reg32(((volatile unsigned *)(0x40000000+ 0x134)), val);
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__write_hw_reg32(((volatile unsigned *)(0x40000000+ 0x134)), (val&0xFFFFFFE0)|0x11);//bbpll_clk_en ?? bbpll_clk_div ???
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__read_hw_reg32(((volatile unsigned *)(0x40000000+ 0x130)), val);
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__write_hw_reg32(((volatile unsigned *)(0x40000000+ 0x130)), (val&0xFFFFFFF9)|0x04);//0x2??RC16M???,0x00??32M osc,0x04 PLL96M 48M?????
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}
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void Set_PLL64M(void)
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{
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CPR_CTL();SYS_Main_Initialise();
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osc32M_to_pll64M();
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uart_64M_source_115200(0);
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printf("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++");
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// for(int i=0;i<800;i++);
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// pll48M_to_osc32M();
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// Init_uart(0,BAUD_115200);
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// printf("\nTEST PLL48M\n");
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}
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#endif
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