311 lines
11 KiB
C
311 lines
11 KiB
C
/*----------------------------------------------------------------------------------------------------
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INCLUDE HEADE FILES
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----------------------------------------------------------------------------------------------------*/
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#include "Includes.h"
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#include "bsp_spi_master.h"
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#include "BootSecond.h"
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#include "bsp_2_4G.h"
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volatile uint8_t rf_intrrupt_flag = 0;
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volatile INFO_24G info_24g = {
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.DataStatus = STATUS_OK,
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.CheckStatus = STATUS_BUSY,
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.WriteAddr = FLASH_BIN_ADDR_OFFSET,
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.cPacketNo = 1,
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.cFrameNo = 1,
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.RevComplete = rFALSE,
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};
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uint8_t __attribute__((aligned(4))) data_buffer[1200];
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uint8_t __attribute__((aligned(4))) xc_buffer[32];
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uint8_t __attribute__((aligned(4))) ack_pay_buf[32] = {0x01, 0x00, 0x03, 0x00, 0x02, 0x00, 0x00};
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// #define printf(...) (0)
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extern void makeCRC32table(unsigned int table[]);
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extern unsigned int crc32table[];
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extern unsigned int get_crc32(unsigned int hash, unsigned char *data, unsigned int length);
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/**
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* Copyright (c) 2022 - 2025, XinChip
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*
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* All rights reserved.
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*
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* Author :
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*
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*/
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void dump_log(void)
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{
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printf("CFG_TOP: 0x%08x\r\n", *CFG_TOP);
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printf("EN_AA: 0x%08x\r\n", *EN_AA);
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printf("EN_RXADDR: 0x%08x\r\n", *EN_RXADDR);
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printf("SETUP_AW: 0x%08x\r\n", *SETUP_AW);
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printf("SETUP_RETR: 0x%08x\r\n", *SETUP_RETR);
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printf("RF_CH: 0x%08x\r\n", *RF_CH);
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printf("SETUP_RF: 0x%08x\r\n", *SETUP_RF);
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printf("STATUS: 0x%08x\r\n", *STATUS);
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printf("OBSERVE_TX: 0x%08x\r\n", *OBSERVE_TX);
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printf("RSSI: 0x%08x\r\n", *RSSI);
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printf("RX_ADDR_P0: 0x%02x%08x\r\n", 0xFF & (*RX_ADDR_P0_H), *RX_ADDR_P0_L);
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printf("RX_ADDR_P1: 0x%02x%08x\r\n", 0xFF & (*RX_ADDR_P1_H), *RX_ADDR_P1_L);
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printf("RX_ADDR_P2TOP5:0x%08x\r\n", *RX_ADDR_P2TOP5);
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printf("BER_RESULT: 0x%08x%08x\r\n", *BER_RESULT_H, *BER_RESULT_L);
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printf("AGC_SETTING: 0x%08x\r\n", *AGC_SETTING);
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printf("PGA_SETTING: 0x%02x%08x\r\n", ((*PGA_SETTING_H) & 0xFF00) >> 8, *PGA_SETTING_L);
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printf("TX_ADDR: 0x%02x%08x\r\n", ((*TX_ADDR_H) & 0xFF), *TX_ADDR_L);
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printf("RX_PW_PX: 0x%04x%08x\r\n", 0xFFFF & (*RX_PW_PX_H), *RX_PW_PX_L);
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printf("STATUS_FIFO: 0x%08x\r\n", *STATUS_FIFO);
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printf("RSSIREC: 0x%08x\r\n", *RSSIREC);
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printf("TXPROC_CFG: 0x%08x\r\n", *TXPROC_CFG);
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printf("RXPROC_CFG: 0x%02x%08x\r\n", 0xFF & (*RXPROC_CFG_H), *RXPROC_CFG_L);
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printf("DYNPD: 0x%08x\r\n", *DYNPD);
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printf("FEATURE: 0x%08x\r\n", *FEATURE);
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printf("PGA_SETTING_H: 0x%08x\r\n", *PGA_SETTING_H);
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printf("TX_ADDR_H: 0x%08x\r\n", *TX_ADDR_H);
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}
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/**
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* Copyright (c) 2022 - 2025, XinChip
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*
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* All rights reserved.
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*
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* Author :
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*
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*/
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void my_memcpy(uint8_t *des, uint8_t *src, uint16_t len)
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{
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for (int i = 0; i < len; i++)
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des[i] = src[i];
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}
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void my_memset(uint8_t *s, uint8_t val, uint16_t len)
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{
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for (int i = 0; i < len; i++)
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s[i] = val;
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}
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/**
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* Copyright (c) 2022 - 2025, XinChip
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*
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* All rights reserved.
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*
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* Author :
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*
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*/
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__RAM_CODE void packet_24g(void)
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{
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static uint8_t xCount = 0;
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static uint16_t xPacketNo = 0;
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uint8_t packet_len = 0;
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// for (uint8_t idx=0; idx<BUFF_24G_ACK_PAY_LENGTH; idx++) ack_pay_buf[idx] = idx;//���������
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// packet_len = XC_RxPacket(DIS_ACK_PAY,ack_pay_buf,BUFF_24G_ACK_PAY_LENGTH,xc_buffer);//������������
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packet_len = XC_RxPacket(EN_ACK_PAY, ack_pay_buf, BUFF_24G_ACK_PAY_LENGTH, xc_buffer); // ������������
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if (packet_len == BUFF_24G_LENGTH)
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{
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switch (xc_buffer[2])
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{
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case 1: // match packet
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xCount++;
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if (xCount >= 3)
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{
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xCount = 0;
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static uint8_t once_flag = 0;
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if (once_flag == 0)
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{
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once_flag = 1;
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info_24g.SoftVer = xc_buffer[5] + (xc_buffer[6] << 8);
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info_24g.RomVer = xc_buffer[7] + (xc_buffer[8] << 8);
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info_24g.Len = xc_buffer[9] + (xc_buffer[10] << 8) +
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(xc_buffer[11] << 16) + (xc_buffer[12] << 24);
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info_24g.CRC32 = xc_buffer[13] + (xc_buffer[14] << 8) +
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(xc_buffer[15] << 16) + (xc_buffer[16] << 24);
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info_24g.PacketNum = xc_buffer[17] + (xc_buffer[18] << 8);
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info_24g.AddrH = xc_buffer[24];
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info_24g.AddrL = xc_buffer[20] + (xc_buffer[21] << 8) +
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(xc_buffer[22] << 16) + (xc_buffer[23] << 24);
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info_24g.Channel = 2400 + xc_buffer[19];
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set_txaddr(info_24g.AddrL, info_24g.AddrH);
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set_pipe0_rxaddr(info_24g.AddrL, info_24g.AddrH);
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nop();
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nop();
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nop();
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set_channel(info_24g.Channel);
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#ifdef DEBUG1
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printf("[SoftVer:0x%08X]\n[RomVer:0x%08X]\n[Len:0x%08X]\n[CRC32:0x%08X]\n",
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info_24g.SoftVer, info_24g.RomVer, info_24g.Len, info_24g.CRC32);
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printf("[PacketNum:0x%08X]\n", info_24g.PacketNum);
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printf("[addr_H:0x%08X]\n[addr_L:0x%08X]\n[channel:%d]\n@@mathch ok@@\n",
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info_24g.AddrH, info_24g.AddrL, info_24g.Channel);
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#endif
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}
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}
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break;
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case 3: // bin info packet
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// printf("P %02x ",xc_buffer[5]);
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// info_24g.cPacketNo == (xc_buffer[5]+(xc_buffer[6]<<8))
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xPacketNo = (xc_buffer[5] + (xc_buffer[6] << 8)); // packet No
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info_24g.FrameNum = xc_buffer[15] + (xc_buffer[16] << 8);
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info_24g.cFrameNo = 1;
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// printf("info_24g.FrameNum:%X\n",info_24g.FrameNum);
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break;
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case 5: // bin packet
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if (info_24g.cFrameNo == xc_buffer[0])
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{
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my_memcpy(data_buffer + PACKET_LENGTH * (info_24g.cFrameNo - 1), xc_buffer + 3, PACKET_LENGTH);
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info_24g.cFrameNo++;
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}
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else
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{
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break;
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}
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if (xc_buffer[0] == info_24g.FrameNum)
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{
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if (info_24g.cPacketNo != xPacketNo)
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{
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info_24g.DataStatus = STATUS_FAIL;
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break;
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}
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#ifdef DEBUG2
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for (int i = 0; i < 1024; i++)
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{
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printf("%02x ", data_buffer[i]);
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if ((i + 1) % 16 == 0)
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printf("\n");
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}
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#endif
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#if 1 // exchange byte position
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for (int i = 0; i < 512; i++)
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{
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uint8_t t = data_buffer[2 * i];
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data_buffer[2 * i] = data_buffer[2 * i + 1];
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data_buffer[2 * i + 1] = t;
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}
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#endif
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// printf("F:%02x no:%x\n",info_24g.WriteAddr,info_24g.cPacketNo);
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info_24g.DataStatus = STATUS_BUSY;
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// spi_flash_write_sPages(info_24g.WriteAddr, data_buffer);
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my_memset(data_buffer, 0xff, PAGES_SIZE);
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if (info_24g.PacketNum == info_24g.cPacketNo)
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{
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info_24g.RevComplete = rTRUE;
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info_24g.DataStatus = STATUS_OK;
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#ifdef DEBUG1
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printf("Receivev Complete Write Complete !\n");
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#endif
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break;
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}
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info_24g.cPacketNo++;
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info_24g.WriteAddr = ((info_24g.cPacketNo - 1) * PAGES_SIZE) + FLASH_BIN_ADDR_OFFSET; // info_24g.WriteAddr+=PAGES_SIZE;
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info_24g.DataStatus = STATUS_OK;
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}
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// printf("F %02x ",xc_buffer[0]);
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break;
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case 6: // packet check result
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#ifdef DEBUG1
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printf("request check result...\n");
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#endif
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if (info_24g.RevComplete == rTRUE)
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{
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info_24g.RevComplete = rFALSE;
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uint32_t crc = 0;
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uint32_t PageCNT = (info_24g.Len) / FLASH_PAGE_SIZE;
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PageCNT = (((info_24g.Len) % FLASH_PAGE_SIZE) == 0) ? PageCNT : (PageCNT + 1);
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for (uint32_t i = 0; i < PageCNT; i++)
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{
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/*read a page*/
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spi_flash_Read_Page(FLASH_BIN_ADDR_OFFSET + (i * FLASH_PAGE_SIZE), data_buffer);
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for (int j = 0; j < 128; j++)
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{
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uint8_t t = data_buffer[2 * j];
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data_buffer[2 * j] = data_buffer[2 * j + 1];
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data_buffer[2 * j + 1] = t;
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}
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crc = ((PageCNT - 1) == i) ? (get_crc32(crc, data_buffer, ((info_24g.Len) % FLASH_PAGE_SIZE))) : (get_crc32(crc, data_buffer, FLASH_PAGE_SIZE));
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}
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#ifdef DEBUG1
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printf("Check crc32:0x%08X\n", crc);
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#endif
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if (crc == info_24g.CRC32)
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{
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info_24g.CheckStatus = STATUS_OK;
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}
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else
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{
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info_24g.CheckStatus = STATUS_FAIL;
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}
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}
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else
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{
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info_24g.CheckStatus = STATUS_BUSY;
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}
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break;
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default:
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break;
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}
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#ifdef DEBUG2
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for (int i = 0; i < 32; i++)
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{
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printf("%02x ", xc_buffer[i]);
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}
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printf("\r\n");
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#endif
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}
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}
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/**
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* Copyright (c) 2022 - 2025, XinChip
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*
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* All rights reserved.
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*
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* Author :
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*
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*/
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__RAM_CODE void RF24G_Handler(void)
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{
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rf_intrrupt_flag |= (*STATUS & 0x70);
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__write_hw_reg32(STATUS, ALL_IRQ_STATUS); // clear all status inter
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// printf("RF24G_Handler stu=%x\n",rf_intrrupt_flag);
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}
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void erase_flash_chip(void)
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{
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spi_flash_write_enable();
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// spi_flash_chip_erase();
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while (spi_flash_wait_till_ready())
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;
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}
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static uint8_t __attribute__((aligned(4))) ParamBuff1[FLASH_PAGE_SIZE];
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void rx_24g_ota(void)
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{
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sboot_message *ptrA = (sboot_message *)(&ParamBuff1[0]);
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spi_flash_Read_Page(2 * 4096, ParamBuff1);
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int num_1 = 0;
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init_24G(RX_MODE);
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set_channel(CHANNEL_24G);
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my_memset(data_buffer, 0xff, PAGES_SIZE);
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#ifdef DEBUG2
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dump_log();
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#endif
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CE_High; // ����RF����
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while (1)
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{
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if (*STATUS & XC_RX_DR)
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{
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CE_Low; // ��ȡ����������ʱ��ֹRF���ա�
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packet_24g();
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CE_High;
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}
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if (num_1 == 0x45500)
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{
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param_analy(&(ptrA->ParamUnit[0]));
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}
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num_1++;
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}
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}
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/**
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* Copyright (c) 2022 - 2025, XinChip
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*
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* All rights reserved.
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*
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* Author :
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*
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*/
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