V1.0

component/ble/plf/refip/src/arch/arch.h

@@ -0,0 +1,420 @@
+/**
+ ****************************************************************************************
+ *
+ * @file arch.h
+ *
+ * @brief This file contains the definitions of the macros and functions that are
+ * architecture dependent.  The implementation of those is implemented in the
+ * appropriate architecture directory.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+
+#ifndef _ARCH_H_
+#define _ARCH_H_
+
+/**
+ ****************************************************************************************
+ * @defgroup REFIP
+ * @brief Reference IP Platform
+ *
+ * This module contains reference platform components - REFIP.
+ *
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @defgroup DRIVERS
+ * @ingroup REFIP
+ * @brief Reference IP Platform Drivers
+ *
+ * This module contains the necessary drivers to run the platform with the
+ * RW BT SW protocol stack.
+ *
+ * This has the declaration of the platform architecture API.
+ *
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "rwip_config.h"       // SW configuration
+
+#include <stdint.h>        // standard integer definition
+#include <stdbool.h>       // standard boolean definition
+#include "compiler.h"      // inline functions
+
+/*
+ * CPU WORD SIZE
+ ****************************************************************************************
+ */
+/// ARM is a 32-bit CPU
+#define CPU_WORD_SIZE   4
+
+/*
+ * CPU Endianness
+ ****************************************************************************************
+ */
+/// ARM is little endian
+#define CPU_LE          1
+
+/*
+ * DEBUG configuration
+ ****************************************************************************************
+ */
+#if defined(CFG_DBG)
+#define PLF_DEBUG          1
+#else //CFG_DBG
+#define PLF_DEBUG          0
+#endif //CFG_DBG
+
+
+#if defined(CFG_PROFILING)
+#define PLF_PROFILING      1
+#else //CFG_DBG
+#define PLF_PROFILING      0
+#endif //CFG_PROFILING
+
+#if defined(CFG_MEM_PROTECTION)
+#define PLF_MEM_PROTECTION 1
+#else //CFG_DBG
+#define PLF_MEM_PROTECTION 0
+#endif //CFG_PROFILING
+
+
+/*
+ * NVDS
+ ****************************************************************************************
+ */
+
+/// NVDS
+#ifdef CFG_NVDS
+#define PLF_NVDS             1
+#else // CFG_NVDS
+#define PLF_NVDS             0
+#endif // CFG_NVDS
+
+/*
+ * DMA
+ ****************************************************************************************
+ */
+
+/// UART
+#define PLF_DMA            (BLE_EMB_PRESENT && BLE_ISO_PRESENT)
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/// Possible errors detected by FW
+#define    RESET_NO_ERROR         0x00000000
+#define    RESET_MEM_ALLOC_FAIL   0xF2F2F2F2
+
+/// Reset platform and stay in ROM
+#define    RESET_TO_ROM           0xA5A5A5A5
+/// Reset platform and reload FW
+#define    RESET_AND_LOAD_FW      0xC3C3C3C3
+
+/// Exchange memory size limit
+#if (BT_DUAL_MODE)
+#define    EM_SIZE_LIMIT          0x10000
+#else
+#define    EM_SIZE_LIMIT          0x4000
+#endif 
+
+/*
+ * EXPORTED FUNCTION DECLARATION
+ ****************************************************************************************
+ */
+
+#if (RW_DEBUG_STACK_PROF)
+/**
+****************************************************************************************
+* @brief Initialise stack memory area.
+*
+* This function initialises the stack memory with pattern for use in stack profiling.
+****************************************************************************************
+*/
+void stack_init(void);
+
+/**
+ ****************************************************************************************
+ * @brief Compute size of SW stack used.
+ *
+ * This function is compute the maximum size stack used by SW.
+ *
+ * @return Size of stack used (in bytes)
+ ****************************************************************************************
+ */
+uint16_t get_stack_usage(void);
+#endif //(RW_DEBUG_STACK_PROF)
+
+/**
+ ****************************************************************************************
+ * @brief Re-boot FW.
+ *
+ * This function is used to re-boot the FW when error has been detected, it is the end of
+ * the current FW execution.
+ * After waiting transfers on UART to be finished, and storing the information that
+ * FW has re-booted by itself in a non-loaded area, the FW restart by branching at FW
+ * entry point.
+ *
+ * Note: when calling this function, the code after it will not be executed.
+ *
+ * @param[in] error      Error detected by FW
+ ****************************************************************************************
+ */
+void platform_reset(uint32_t error);
+
+#if PLF_DEBUG
+/**
+ ****************************************************************************************
+ * @brief Print the assertion error reason and loop forever.
+ *
+ * @param condition C string containing the condition.
+ * @param file C string containing file where the assertion is located.
+ * @param line Line number in the file where the assertion is located.
+ ****************************************************************************************
+ */
+void assert_err(const char *condition, const char * file, int line);
+
+/**
+ ****************************************************************************************
+ * @brief Print the assertion error reason and loop forever.
+ * The parameter value that is causing the assertion will also be disclosed.
+ *
+ * @param param0 parameter value 0.
+ * @param param1 parameter value 1.
+ * @param file C string containing file where the assertion is located.
+ * @param line Line number in the file where the assertion is located.
+ ****************************************************************************************
+ */
+void assert_param(int param0, int param1, const char * file, int line);
+
+/**
+ ****************************************************************************************
+ * @brief Print the assertion warning reason.
+ *
+ * @param param0 parameter value 0.
+ * @param param1 parameter value 1.
+ * @param file C string containing file where the assertion is located.
+ * @param line Line number in the file where the assertion is located.
+ ****************************************************************************************
+ */
+void assert_warn(int param0, int param1, const char * file, int line);
+
+
+/**
+ ****************************************************************************************
+ * @brief Dump data value into FW.
+ *
+ * @param data start pointer of the data.
+ * @param length data size to dump
+ ****************************************************************************************
+ */
+void dump_data(uint8_t* data, uint16_t length);
+#endif //PLF_DEBUG
+
+#if (PLF_PROFILING)
+/**
+ ****************************************************************************************
+ * @brief Trace enter into a function
+ *
+ * @param[in] p_func_ptr Pointer of the function
+ * @param[in] p_func_name_ptr Pointer of the function name
+ ****************************************************************************************
+ */
+void func_enter(const void* p_func_ptr, const void* p_func_name_ptr);
+
+/**
+ ****************************************************************************************
+ * @brief Trace exit of a function
+ *
+ * @param[in] p_func_ptr      Pointer of the function
+ * @param[in] p_func_name_ptr Pointer of the function name
+ ****************************************************************************************
+ */
+void func_exit(const void* p_func_ptr, const void* p_func_name_ptr);
+
+/**
+ ****************************************************************************************
+ * @brief Trace data pointer allocation
+ *
+ * @param[in] p_ptr Data pointer address
+ ****************************************************************************************
+ */
+void data_trace_alloc(const void* p_ptr);
+
+/**
+ ****************************************************************************************
+ * @brief Trace data pointer free
+ *
+ * @param[in] p_ptr Data pointer address
+ ****************************************************************************************
+ */
+void data_trace_free(const void* p_ptr);
+
+/**
+ ****************************************************************************************
+ * @brief Trace data into a VCD
+ *
+ * @param[in] p_ptr      Data pointer address
+ * @param[in] p_name_ptr Data variable name pointer address
+ * @param[in] data_size  Size of data to trace in bytes (8, 16 or 32 only)
+ ****************************************************************************************
+ */
+void data_trace(const void* p_ptr, const void* p_name_ptr, uint8_t data_size);
+
+#endif // (PLF_PROFILING)
+
+
+#if (PLF_MEM_PROTECTION)
+/**
+ ****************************************************************************************
+ * @brief Control memory access
+ *
+ * @param[in] p_mem_ptr Pointer to memory block
+ * @param[in] enable    True to grant complete access on memory block, False to flow memory permissions
+ ****************************************************************************************
+ */
+void mem_grant_access_ctrl(const void* p_mem_ptr, bool enable);
+
+
+/**
+ ****************************************************************************************
+ * @brief Set permission onto a specific memory block
+ *
+ * @param[in] p_mem_ptr Pointer to memory block
+ * @param[in] size      Size of the memory block
+ * @param[in] write_en  True to enable write permission, False to disable write
+ * @param[in] read_en   True to enable read permission, False to disable read
+ * @param[in] init_clr  True to mark memory block not initialized, False: no action
+ ****************************************************************************************
+ */
+void mem_perm_set(const void* p_mem_ptr, uint16_t size, bool write_en, bool read_en, bool init_clr);
+
+/**
+ ****************************************************************************************
+ * @brief Mark memory block initialized - without modifying memory data
+ *
+ * @param[in] p_mem_ptr Pointer to memory block
+ * @param[in] size      Size of the memory block
+ ****************************************************************************************
+ */
+void mem_init(const void* p_mem_ptr, uint16_t size);
+#endif // (PLF_MEM_PROTECTION)
+
+/*
+ * ASSERTION CHECK
+ ****************************************************************************************
+ */
+#if PLF_DEBUG
+/// Assertions showing a critical error that could require a full system reset
+#define ASSERT_ERR(cond)                              \
+    do {                                              \
+        if (!(cond)) {                                \
+            assert_err(#cond, __MODULE__, __LINE__);  \
+        }                                             \
+    } while(0)
+
+/// Assertions showing a critical error that could require a full system reset
+#define ASSERT_INFO(cond, param0, param1)             \
+    do {                                              \
+        if (!(cond)) {                                \
+            assert_param((int)param0, (int)param1, __MODULE__, __LINE__);  \
+        }                                             \
+    } while(0)
+
+/// Assertions showing a non-critical problem that has to be fixed by the SW
+#define ASSERT_WARN(cond, param0, param1)             \
+    do {                                              \
+        if (!(cond)) {                                \
+            assert_warn((int)param0, (int)param1, __MODULE__, __LINE__); \
+        }                                             \
+    } while(0)
+
+/// DUMP data array present in the SW.
+#define DUMP_DATA(data, length) \
+    dump_data((uint8_t*)data, length)
+
+#else
+#ifndef ASSERT_ERR
+/// Assertions showing a critical error that could require a full system reset
+#define ASSERT_ERR(cond)
+#endif
+/// Assertions showing a critical error that could require a full system reset
+#define ASSERT_INFO(cond, param0, param1)
+
+/// Assertions showing a non-critical problem that has to be fixed by the SW
+#define ASSERT_WARN(cond, param0, param1)
+
+/// DUMP data array present in the SW.
+#define DUMP_DATA(data, length)
+#endif //PLF_DEBUG
+
+#if (PLF_PROFILING)
+/// Trace data into a VCD
+#define DBG_DATA_TRACE(data, size) data_trace(&data, #data, size)
+
+/// Trace data allocation
+#define DBG_DATA_ALLOC(data) data_trace_alloc(&data)
+
+/// Trace data free
+#define DBG_DATA_FREE(data) data_trace_free(&data)
+
+/// Trace Function Enter
+#define DBG_FUNC_ENTER(func) func_enter(func, #func)
+
+/// Trace Function Exit
+#define DBG_FUNC_EXIT(func) func_exit(func, #func)
+#else
+/// Trace data into a VCD
+#define DBG_DATA_TRACE(data, size)
+/// Trace data allocation
+#define DBG_DATA_ALLOC(data)
+/// Trace data free
+#define DBG_DATA_FREE(data)
+/// Trace Function Enter
+#define DBG_FUNC_ENTER(func)
+/// Trace Function Exit
+#define DBG_FUNC_EXIT(func)
+#endif //PLF_PROFILING
+
+
+#if (PLF_MEM_PROTECTION)
+/// Control memory access
+#define DBG_MEM_GRANT_CTRL(mem_ptr, enable) mem_grant_access_ctrl(mem_ptr, enable)
+/// Set permission onto a specific memory block
+#define DBG_MEM_PERM_SET(mem_ptr, size, write_en, read_en, init_clr) mem_perm_set(mem_ptr, size, write_en, read_en, init_clr)
+/// Mark memory initialized
+#define DBG_MEM_INIT(mem_ptr, size) mem_init(mem_ptr, size)
+#else // !(PLF_MEM_PROTECTION)
+/// Control memory access
+#define DBG_MEM_GRANT_CTRL(mem_ptr, enable)
+/// Set permission onto a specific memory block
+#define DBG_MEM_PERM_SET(mem_ptr, size, write_en, read_en, init_clr)
+/// Mark memory initialized
+#define DBG_MEM_INIT(mem_ptr, size)
+#endif // (PLF_MEM_PROTECTION)
+
+
+/// Object allocated in shared memory - check linker script
+#define __SHARED __attribute__ ((section("shram")))
+
+// required to define GLOBAL_INT_** macros as inline assembly. This file is included after
+// definition of ASSERT macros as they are used inside ll.h
+#include "ll.h"     // ll definitions
+/// @} DRIVERS
+#endif // _ARCH_H_

component/ble/plf/refip/src/arch/boot/armgcc/boot.h

@@ -0,0 +1,72 @@
+/**
+ ****************************************************************************************
+ *
+ * @file boot.h
+ *
+ * @brief This file contains the declarations of the boot related variables.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef _BOOT_H_
+#define _BOOT_H_
+
+/// Address of beginning of the CODE
+extern char code_base;
+#define CODE_BASE (&(code_base))
+
+/// Address of the end of the CODE
+extern char code_end;
+#define CODE_END (&(code_end))
+
+/// Length of the code
+#define CODE_LENGTH ((CODE_END) - (CODE_BASE))
+
+/// Address of beginning of the DATA
+extern char data_base;
+#define DATA_BASE (&(data_base))
+
+/// Address of the end of the DATA
+extern char data_end;
+#define DATA_END (&(data_end))
+
+/// Length of the DATA
+#define DATA_LENGTH ((DATA_END) - (DATA_BASE))
+
+/// Unloaded RAM area base address
+extern char unloaded_area_start;
+#define RAM_UNLOADED_BASE   (&(unloaded_area_start))
+
+/// Stack base address
+
+extern char stack_base_unused;
+#define STACK_BASE_UNUSED   (&(stack_base_unused))
+extern char stack_len_unused;
+#define STACK_LEN_UNUSED   (&(stack_len_unused))
+
+extern char stack_base_svc ;
+#define STACK_BASE_SVC   (&(stack_base_svc))
+
+extern char stack_len_svc;
+#define STACK_LEN_SVC  (&(stack_len_svc))
+
+extern char stack_base_irq;
+#define STACK_BASE_IRQ  (&(stack_base_irq))
+extern char stack_len_irq;
+#define STACK_LEN_IRQ   (&(stack_len_irq))
+
+extern char stack_base_fiq;
+#define STACK_BASE_FIQ   (&(stack_base_fiq))
+extern char stack_len_fiq;
+#define STACK_LEN_FIQ   (&(stack_len_fiq))
+
+#define BOOT_PATTERN_UNUSED   0xAA      // Pattern to fill UNUSED stack
+#define BOOT_PATTERN_SVC      0xBB      // Pattern to fill SVC stack
+#define BOOT_PATTERN_IRQ      0xCC      // Pattern to fill IRQ stack
+#define BOOT_PATTERN_FIQ      0xDD      // Pattern to fill FIQ stack
+
+
+#endif // _BOOT_H_

component/ble/plf/refip/src/arch/boot/armgcc/boot_handlers.s

@@ -0,0 +1,242 @@
+#/**
+# ****************************************************************************************
+# *
+# * @file boot_handlers.s
+# *
+# * @brief ARM Exception Vector handler functions.
+# *
+# * Copyright (C) RivieraWaves 2009-2015
+# *
+# * $Rev:  $
+# *
+# ****************************************************************************************
+# */
+
+
+.text
+    .align  4
+    .global boot_reset
+    .type   boot_reset, function
+    .global boot_undefined
+    .type   boot_undefined, function
+    .global boot_swi
+    .type   boot_swi, function
+    .global boot_pabort
+    .type   boot_pabort, function
+    .global boot_dabort
+    .type   boot_dabort, function
+    .global boot_reserved
+    .type   boot_reserved, function
+
+#/* ========================================================================
+# *                                Constants
+# * ======================================================================== */
+
+.set BOOT_MODE_MASK, 0x1F
+
+.set BOOT_MODE_USR, 0x10
+.set BOOT_MODE_FIQ, 0x11
+.set BOOT_MODE_IRQ, 0x12
+.set BOOT_MODE_SVC, 0x13
+.set BOOT_MODE_ABT, 0x17
+.set BOOT_MODE_UND, 0x1B
+.set BOOT_MODE_SYS, 0x1F
+
+.set BOOT_FIQ_IRQ_MASK, 0xC0
+.set BOOT_IRQ_MASK,     0x80
+
+
+#/* ========================================================================
+# *                                Macros
+# * ======================================================================== */
+
+#/* ========================================================================
+#/**
+# * Macro for switching ARM mode
+# */
+    .macro BOOT_CHANGE_MODE newmode
+        MRS   R0, CPSR
+        BIC   R0, R0, #BOOT_MODE_MASK
+        ORR   R0, R0, #BOOT_MODE_\newmode
+        MSR   CPSR_c, R0
+    .endm
+
+#/* ========================================================================
+#/**
+# * Macro for setting the stack
+# */
+    .macro BOOT_SET_STACK stackname
+        LDR   R0, boot_stack_base_\stackname
+        LDR   R1, boot_stack_len_\stackname
+        ADD   R0, R0, R1
+        MOV   SP, R0
+    .endm
+
+#/* ========================================================================
+# *                                Globals
+# * ======================================================================== */
+
+#/* ========================================================================
+#/**
+# * CP15 DTCM Control Reg settings
+# */
+boot_Cp15DtcmReg:
+    .word 0x01010001
+
+
+#/* ========================================================================
+#/**
+# * CP15 ITCM Control Reg settings
+# */
+boot_Cp15ItcmReg:
+    .word 0x01000001
+
+#/* ========================================================================
+#/**
+# * RAM_BSS
+# */
+ram_bss_base:
+    .word bss_base
+
+ram_bss_length:
+    .word bss_length
+
+#/* ========================================================================
+#/**
+# * Unused (ABT, UNDEFINED, SYSUSR) Mode
+# */
+boot_stack_base_UNUSED:
+    .word stack_base_unused
+
+boot_stack_len_UNUSED:
+    .word stack_len_unused
+
+#/* ========================================================================
+#/**
+# * IRQ Mode
+# */
+boot_stack_base_IRQ:
+    .word stack_base_irq
+
+boot_stack_len_IRQ:
+    .word stack_len_irq
+
+
+#/* ========================================================================
+#/**
+# * Supervisor Mode
+# */
+boot_stack_base_SVC:
+    .word stack_base_svc
+
+boot_stack_len_SVC:
+    .word stack_len_svc
+
+
+#/* ========================================================================
+#/**
+# * FIQ Mode
+# */
+boot_stack_base_FIQ:
+    .word stack_base_fiq
+
+boot_stack_len_FIQ:
+    .word stack_len_fiq
+
+
+#/* ========================================================================
+# *                                Functions
+# * ========================================================================
+
+#/* ========================================================================
+#/**
+# * Function to handle reset vector
+# */
+boot_reset:
+    # Disable IRQ and FIQ before starting anything
+    MRS   R0, CPSR
+    ORR   R0, R0, #0xC0
+    MSR   CPSR_c, R0
+
+    # ==================
+    # Setup all stacks
+
+    # Note: Sys and Usr mode are not used
+    BOOT_CHANGE_MODE SYS
+    BOOT_SET_STACK   UNUSED
+    BOOT_CHANGE_MODE ABT
+    BOOT_SET_STACK   UNUSED
+    BOOT_CHANGE_MODE UND
+    BOOT_SET_STACK   UNUSED
+    BOOT_CHANGE_MODE IRQ
+    BOOT_SET_STACK   IRQ
+    BOOT_CHANGE_MODE FIQ
+    BOOT_SET_STACK   FIQ
+
+    # Clear FIQ banked registers while in FIQ mode
+    MOV     R8, #0
+    MOV     R9, #0
+    MOV     R10, #0
+    MOV     R11, #0
+    MOV     R12, #0
+
+    BOOT_CHANGE_MODE SVC
+    BOOT_SET_STACK   SVC
+
+    # Stay in Supervisor Mode
+
+    # Init the BSS section
+    LDR     R0, ram_bss_base
+    LDR     R1, ram_bss_length
+    MOV     R2, #0
+    MOV     R3, #0
+    MOV     R4, #0
+    MOV     R5, #0
+init_bss_loop:
+    SUBS    R1, R1, #16
+    STMCSIA R0!, {R2, R3, R4, R5}
+    BHI     init_bss_loop
+    MOVS    R1, R1, LSL #29
+    STMCSIA R0!, {R4, R5}
+    STRMI   R3, [R0]
+
+    # ==================
+    # Clear Registers
+    MOV R0, #0
+    MOV R1, #0
+    MOV R2, #0
+    MOV R3, #0
+    MOV R4, #0
+    MOV R5, #0
+    MOV R6, #0
+    MOV R7, #0
+    MOV R8, #0
+    MOV R9, #0
+    MOV R10, #0
+    MOV R11, #0
+    MOV R12, #0
+
+    B rw_main
+
+# undefined handler
+boot_undefined:
+    B boot_undefined
+
+# SWI handler
+boot_swi:
+    B boot_swi
+
+# Prefetch error handler
+boot_pabort:
+    B boot_pabort
+
+# abort handler
+boot_dabort:
+    B boot_dabort
+
+# reserved vector
+boot_reserved:
+    B boot_reserved
+    SUBS PC, LR, #4
+
+

component/ble/plf/refip/src/arch/boot/armgcc/boot_vectors.s

@@ -0,0 +1,41 @@
+/**
+ ****************************************************************************************
+ *
+ * @file boot_vectors.s
+ *
+ * @brief ARM Exception Vectors table.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ * $Rev:  $
+ *
+ ****************************************************************************************
+ */
+
+.text
+    .align  4
+    .global vectors, boot_breakpoint
+    .type   vectors, function
+
+vectors:
+    # reset handler
+    B       boot_reset
+    # undefined handler
+    B       boot_undefined
+    # SWI handler
+    B       boot_swi
+    # Prefetch error handler
+    B       boot_pabort
+    # abort handler
+    B       boot_dabort
+    # reserved vector
+    B       boot_reserved
+    # irq
+    B       intc_irq
+    # fiq
+    B       intc_fiq
+
+boot_breakpoint:
+    # If set to 0 by host before getting out of reset, the cpu
+    # will loop and light the leds indefinitely
+    .word   1

component/ble/plf/refip/src/arch/boot/armgcc_4_8/boot.h

@@ -0,0 +1,72 @@
+/**
+ ****************************************************************************************
+ *
+ * @file boot.h
+ *
+ * @brief This file contains the declarations of the boot related variables.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef _BOOT_H_
+#define _BOOT_H_
+
+/// Address of beginning of the CODE
+extern char code_base;
+#define CODE_BASE (&(code_base))
+
+/// Address of the end of the CODE
+extern char code_end;
+#define CODE_END (&(code_end))
+
+/// Length of the code
+#define CODE_LENGTH ((CODE_END) - (CODE_BASE))
+
+/// Address of beginning of the DATA
+extern char data_base;
+#define DATA_BASE (&(data_base))
+
+/// Address of the end of the DATA
+extern char data_end;
+#define DATA_END (&(data_end))
+
+/// Length of the DATA
+#define DATA_LENGTH ((DATA_END) - (DATA_BASE))
+
+/// Unloaded RAM area base address
+extern char unloaded_area_start;
+#define RAM_UNLOADED_BASE   (&(unloaded_area_start))
+
+/// Stack base address
+
+extern char stack_base_unused;
+#define STACK_BASE_UNUSED   (&(stack_base_unused))
+extern char stack_len_unused;
+#define STACK_LEN_UNUSED   (&(stack_len_unused))
+
+extern char stack_base_svc ;
+#define STACK_BASE_SVC   (&(stack_base_svc))
+
+extern char stack_len_svc;
+#define STACK_LEN_SVC  (&(stack_len_svc))
+
+extern char stack_base_irq;
+#define STACK_BASE_IRQ  (&(stack_base_irq))
+extern char stack_len_irq;
+#define STACK_LEN_IRQ   (&(stack_len_irq))
+
+extern char stack_base_fiq;
+#define STACK_BASE_FIQ   (&(stack_base_fiq))
+extern char stack_len_fiq;
+#define STACK_LEN_FIQ   (&(stack_len_fiq))
+
+#define BOOT_PATTERN_UNUSED   0xAA      // Pattern to fill UNUSED stack
+#define BOOT_PATTERN_SVC      0xBB      // Pattern to fill SVC stack
+#define BOOT_PATTERN_IRQ      0xCC      // Pattern to fill IRQ stack
+#define BOOT_PATTERN_FIQ      0xDD      // Pattern to fill FIQ stack
+
+
+#endif // _BOOT_H_

component/ble/plf/refip/src/arch/boot/armgcc_4_8/boot_handlers.s

@@ -0,0 +1,242 @@
+#/**
+# ****************************************************************************************
+# *
+# * @file boot_handlers.s
+# *
+# * @brief ARM Exception Vector handler functions.
+# *
+# * Copyright (C) RivieraWaves 2009-2015
+# *
+# * $Rev:  $
+# *
+# ****************************************************************************************
+# */
+
+
+.text
+    .align  4
+    .global boot_reset
+    .type   boot_reset, function
+    .global boot_undefined
+    .type   boot_undefined, function
+    .global boot_swi
+    .type   boot_swi, function
+    .global boot_pabort
+    .type   boot_pabort, function
+    .global boot_dabort
+    .type   boot_dabort, function
+    .global boot_reserved
+    .type   boot_reserved, function
+
+#/* ========================================================================
+# *                                Constants
+# * ======================================================================== */
+
+.set BOOT_MODE_MASK, 0x1F
+
+.set BOOT_MODE_USR, 0x10
+.set BOOT_MODE_FIQ, 0x11
+.set BOOT_MODE_IRQ, 0x12
+.set BOOT_MODE_SVC, 0x13
+.set BOOT_MODE_ABT, 0x17
+.set BOOT_MODE_UND, 0x1B
+.set BOOT_MODE_SYS, 0x1F
+
+.set BOOT_FIQ_IRQ_MASK, 0xC0
+.set BOOT_IRQ_MASK,     0x80
+
+
+#/* ========================================================================
+# *                                Macros
+# * ======================================================================== */
+
+#/* ========================================================================
+#/**
+# * Macro for switching ARM mode
+# */
+    .macro BOOT_CHANGE_MODE newmode
+        MRS   R0, CPSR
+        BIC   R0, R0, #BOOT_MODE_MASK
+        ORR   R0, R0, #BOOT_MODE_\newmode
+        MSR   CPSR_c, R0
+    .endm
+
+#/* ========================================================================
+#/**
+# * Macro for setting the stack
+# */
+    .macro BOOT_SET_STACK stackname
+        LDR   R0, boot_stack_base_\stackname
+        LDR   R1, boot_stack_len_\stackname
+        ADD   R0, R0, R1
+        MOV   SP, R0
+    .endm
+
+#/* ========================================================================
+# *                                Globals
+# * ======================================================================== */
+
+#/* ========================================================================
+#/**
+# * CP15 DTCM Control Reg settings
+# */
+boot_Cp15DtcmReg:
+    .word 0x01010001
+
+
+#/* ========================================================================
+#/**
+# * CP15 ITCM Control Reg settings
+# */
+boot_Cp15ItcmReg:
+    .word 0x01000001
+
+#/* ========================================================================
+#/**
+# * RAM_BSS
+# */
+ram_bss_base:
+    .word bss_base
+
+ram_bss_length:
+    .word bss_length
+
+#/* ========================================================================
+#/**
+# * Unused (ABT, UNDEFINED, SYSUSR) Mode
+# */
+boot_stack_base_UNUSED:
+    .word stack_base_unused
+
+boot_stack_len_UNUSED:
+    .word stack_len_unused
+
+#/* ========================================================================
+#/**
+# * IRQ Mode
+# */
+boot_stack_base_IRQ:
+    .word stack_base_irq
+
+boot_stack_len_IRQ:
+    .word stack_len_irq
+
+
+#/* ========================================================================
+#/**
+# * Supervisor Mode
+# */
+boot_stack_base_SVC:
+    .word stack_base_svc
+
+boot_stack_len_SVC:
+    .word stack_len_svc
+
+
+#/* ========================================================================
+#/**
+# * FIQ Mode
+# */
+boot_stack_base_FIQ:
+    .word stack_base_fiq
+
+boot_stack_len_FIQ:
+    .word stack_len_fiq
+
+
+#/* ========================================================================
+# *                                Functions
+# * ========================================================================
+
+#/* ========================================================================
+#/**
+# * Function to handle reset vector
+# */
+boot_reset:
+    # Disable IRQ and FIQ before starting anything
+    MRS   R0, CPSR
+    ORR   R0, R0, #0xC0
+    MSR   CPSR_c, R0
+
+    # ==================
+    # Setup all stacks
+
+    # Note: Sys and Usr mode are not used
+    BOOT_CHANGE_MODE SYS
+    BOOT_SET_STACK   UNUSED
+    BOOT_CHANGE_MODE ABT
+    BOOT_SET_STACK   UNUSED
+    BOOT_CHANGE_MODE UND
+    BOOT_SET_STACK   UNUSED
+    BOOT_CHANGE_MODE IRQ
+    BOOT_SET_STACK   IRQ
+    BOOT_CHANGE_MODE FIQ
+    BOOT_SET_STACK   FIQ
+
+    # Clear FIQ banked registers while in FIQ mode
+    MOV     R8, #0
+    MOV     R9, #0
+    MOV     R10, #0
+    MOV     R11, #0
+    MOV     R12, #0
+
+    BOOT_CHANGE_MODE SVC
+    BOOT_SET_STACK   SVC
+
+    # Stay in Supervisor Mode
+
+    # Init the BSS section
+    LDR     R0, ram_bss_base
+    LDR     R1, ram_bss_length
+    MOV     R2, #0
+    MOV     R3, #0
+    MOV     R4, #0
+    MOV     R5, #0
+init_bss_loop:
+    SUBS    R1, R1, #16
+    STMCSIA R0!, {R2, R3, R4, R5}
+    BHI     init_bss_loop
+    MOVS    R1, R1, LSL #29
+    STMCSIA R0!, {R4, R5}
+    STRMI   R3, [R0]
+
+    # ==================
+    # Clear Registers
+    MOV R0, #0
+    MOV R1, #0
+    MOV R2, #0
+    MOV R3, #0
+    MOV R4, #0
+    MOV R5, #0
+    MOV R6, #0
+    MOV R7, #0
+    MOV R8, #0
+    MOV R9, #0
+    MOV R10, #0
+    MOV R11, #0
+    MOV R12, #0
+
+    B rw_main
+
+# undefined handler
+boot_undefined:
+    B boot_undefined
+
+# SWI handler
+boot_swi:
+    B boot_swi
+
+# Prefetch error handler
+boot_pabort:
+    B boot_pabort
+
+# abort handler
+boot_dabort:
+    B boot_dabort
+
+# reserved vector
+boot_reserved:
+    B boot_reserved
+    SUBS PC, LR, #4
+
+

component/ble/plf/refip/src/arch/boot/armgcc_4_8/boot_vectors.s

@@ -0,0 +1,41 @@
+/**
+ ****************************************************************************************
+ *
+ * @file boot_vectors.s
+ *
+ * @brief ARM Exception Vectors table.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ * $Rev:  $
+ *
+ ****************************************************************************************
+ */
+
+.text
+    .align  4
+    .global vectors, boot_breakpoint
+    .type   vectors, function
+
+vectors:
+    # reset handler
+    B       boot_reset
+    # undefined handler
+    B       boot_undefined
+    # SWI handler
+    B       boot_swi
+    # Prefetch error handler
+    B       boot_pabort
+    # abort handler
+    B       boot_dabort
+    # reserved vector
+    B       boot_reserved
+    # irq
+    B       intc_irq
+    # fiq
+    B       intc_fiq
+
+boot_breakpoint:
+    # If set to 0 by host before getting out of reset, the cpu
+    # will loop and light the leds indefinitely
+    .word   1

component/ble/plf/refip/src/arch/boot/gnuarm/boot.h

@@ -0,0 +1,72 @@
+/**
+ ****************************************************************************************
+ *
+ * @file boot.h
+ *
+ * @brief This file contains the declarations of the boot related variables.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef _BOOT_H_
+#define _BOOT_H_
+
+/// Address of beginning of the CODE
+extern char code_base;
+#define CODE_BASE (&(code_base))
+
+/// Address of the end of the CODE
+extern char code_end;
+#define CODE_END (&(code_end))
+
+/// Length of the code
+#define CODE_LENGTH ((CODE_END) - (CODE_BASE))
+
+/// Address of beginning of the DATA
+extern char data_base;
+#define DATA_BASE (&(data_base))
+
+/// Address of the end of the DATA
+extern char data_end;
+#define DATA_END (&(data_end))
+
+/// Length of the DATA
+#define DATA_LENGTH ((DATA_END) - (DATA_BASE))
+
+/// Unloaded RAM area base address
+extern char unloaded_area_start;
+#define RAM_UNLOADED_BASE   (&(unloaded_area_start))
+
+/// Stack base address
+
+extern char stack_base_unused;
+#define STACK_BASE_UNUSED   (&(stack_base_unused))
+extern char stack_len_unused;
+#define STACK_LEN_UNUSED   (&(stack_len_unused))
+
+extern char stack_base_svc ;
+#define STACK_BASE_SVC   (&(stack_base_svc))
+
+extern char stack_len_svc;
+#define STACK_LEN_SVC  (&(stack_len_svc))
+
+extern char stack_base_irq;
+#define STACK_BASE_IRQ  (&(stack_base_irq))
+extern char stack_len_irq;
+#define STACK_LEN_IRQ   (&(stack_len_irq))
+
+extern char stack_base_fiq;
+#define STACK_BASE_FIQ   (&(stack_base_fiq))
+extern char stack_len_fiq;
+#define STACK_LEN_FIQ   (&(stack_len_fiq))
+
+#define BOOT_PATTERN_UNUSED   0xAA      // Pattern to fill UNUSED stack
+#define BOOT_PATTERN_SVC      0xBB      // Pattern to fill SVC stack
+#define BOOT_PATTERN_IRQ      0xCC      // Pattern to fill IRQ stack
+#define BOOT_PATTERN_FIQ      0xDD      // Pattern to fill FIQ stack
+
+
+#endif // _BOOT_H_

component/ble/plf/refip/src/arch/boot/gnuarm/boot_handlers.s

@@ -0,0 +1,242 @@
+#/**
+# ****************************************************************************************
+# *
+# * @file boot_handlers.s
+# *
+# * @brief ARM Exception Vector handler functions.
+# *
+# * Copyright (C) RivieraWaves 2009-2015
+# *
+# * $Rev:  $
+# *
+# ****************************************************************************************
+# */
+
+
+.text
+    .align  4
+    .global boot_reset
+    .type   boot_reset, function
+    .global boot_undefined
+    .type   boot_undefined, function
+    .global boot_swi
+    .type   boot_swi, function
+    .global boot_pabort
+    .type   boot_pabort, function
+    .global boot_dabort
+    .type   boot_dabort, function
+    .global boot_reserved
+    .type   boot_reserved, function
+
+#/* ========================================================================
+# *                                Constants
+# * ======================================================================== */
+
+.set BOOT_MODE_MASK, 0x1F
+
+.set BOOT_MODE_USR, 0x10
+.set BOOT_MODE_FIQ, 0x11
+.set BOOT_MODE_IRQ, 0x12
+.set BOOT_MODE_SVC, 0x13
+.set BOOT_MODE_ABT, 0x17
+.set BOOT_MODE_UND, 0x1B
+.set BOOT_MODE_SYS, 0x1F
+
+.set BOOT_FIQ_IRQ_MASK, 0xC0
+.set BOOT_IRQ_MASK,     0x80
+
+
+#/* ========================================================================
+# *                                Macros
+# * ======================================================================== */
+
+#/* ========================================================================
+#/**
+# * Macro for switching ARM mode
+# */
+    .macro BOOT_CHANGE_MODE newmode
+        MRS   R0, CPSR
+        BIC   R0, R0, #BOOT_MODE_MASK
+        ORR   R0, R0, #BOOT_MODE_\newmode
+        MSR   CPSR_c, R0
+    .endm
+
+#/* ========================================================================
+#/**
+# * Macro for setting the stack
+# */
+    .macro BOOT_SET_STACK stackname
+        LDR   R0, boot_stack_base_\stackname
+        LDR   R1, boot_stack_len_\stackname
+        ADD   R0, R0, R1
+        MOV   SP, R0
+    .endm
+
+#/* ========================================================================
+# *                                Globals
+# * ======================================================================== */
+
+#/* ========================================================================
+#/**
+# * CP15 DTCM Control Reg settings
+# */
+boot_Cp15DtcmReg:
+    .word 0x01010001
+
+
+#/* ========================================================================
+#/**
+# * CP15 ITCM Control Reg settings
+# */
+boot_Cp15ItcmReg:
+    .word 0x01000001
+
+#/* ========================================================================
+#/**
+# * RAM_BSS
+# */
+ram_bss_base:
+    .word bss_base
+
+ram_bss_length:
+    .word bss_length
+
+#/* ========================================================================
+#/**
+# * Unused (ABT, UNDEFINED, SYSUSR) Mode
+# */
+boot_stack_base_UNUSED:
+    .word stack_base_unused
+
+boot_stack_len_UNUSED:
+    .word stack_len_unused
+
+#/* ========================================================================
+#/**
+# * IRQ Mode
+# */
+boot_stack_base_IRQ:
+    .word stack_base_irq
+
+boot_stack_len_IRQ:
+    .word stack_len_irq
+
+
+#/* ========================================================================
+#/**
+# * Supervisor Mode
+# */
+boot_stack_base_SVC:
+    .word stack_base_svc
+
+boot_stack_len_SVC:
+    .word stack_len_svc
+
+
+#/* ========================================================================
+#/**
+# * FIQ Mode
+# */
+boot_stack_base_FIQ:
+    .word stack_base_fiq
+
+boot_stack_len_FIQ:
+    .word stack_len_fiq
+
+
+#/* ========================================================================
+# *                                Functions
+# * ========================================================================
+
+#/* ========================================================================
+#/**
+# * Function to handle reset vector
+# */
+boot_reset:
+    # Disable IRQ and FIQ before starting anything
+    MRS   R0, CPSR
+    ORR   R0, R0, #0xC0
+    MSR   CPSR_c, R0
+
+    # ==================
+    # Setup all stacks
+
+    # Note: Sys and Usr mode are not used
+    BOOT_CHANGE_MODE SYS
+    BOOT_SET_STACK   UNUSED
+    BOOT_CHANGE_MODE ABT
+    BOOT_SET_STACK   UNUSED
+    BOOT_CHANGE_MODE UND
+    BOOT_SET_STACK   UNUSED
+    BOOT_CHANGE_MODE IRQ
+    BOOT_SET_STACK   IRQ
+    BOOT_CHANGE_MODE FIQ
+    BOOT_SET_STACK   FIQ
+
+    # Clear FIQ banked registers while in FIQ mode
+    MOV     R8, #0
+    MOV     R9, #0
+    MOV     R10, #0
+    MOV     R11, #0
+    MOV     R12, #0
+
+    BOOT_CHANGE_MODE SVC
+    BOOT_SET_STACK   SVC
+
+    # Stay in Supervisor Mode
+
+    # Init the BSS section
+    LDR     R0, ram_bss_base
+    LDR     R1, ram_bss_length
+    MOV     R2, #0
+    MOV     R3, #0
+    MOV     R4, #0
+    MOV     R5, #0
+init_bss_loop:
+    SUBS    R1, R1, #16
+    STMCSIA R0!, {R2, R3, R4, R5}
+    BHI     init_bss_loop
+    MOVS    R1, R1, LSL #29
+    STMCSIA R0!, {R4, R5}
+    STRMI   R3, [R0]
+
+    # ==================
+    # Clear Registers
+    MOV R0, #0
+    MOV R1, #0
+    MOV R2, #0
+    MOV R3, #0
+    MOV R4, #0
+    MOV R5, #0
+    MOV R6, #0
+    MOV R7, #0
+    MOV R8, #0
+    MOV R9, #0
+    MOV R10, #0
+    MOV R11, #0
+    MOV R12, #0
+
+    B rw_main
+
+# undefined handler
+boot_undefined:
+    B boot_undefined
+
+# SWI handler
+boot_swi:
+    B boot_swi
+
+# Prefetch error handler
+boot_pabort:
+    B boot_pabort
+
+# abort handler
+boot_dabort:
+    B boot_dabort
+
+# reserved vector
+boot_reserved:
+    B boot_reserved
+    SUBS PC, LR, #4
+
+

component/ble/plf/refip/src/arch/boot/gnuarm/boot_vectors.s

@@ -0,0 +1,41 @@
+/**
+ ****************************************************************************************
+ *
+ * @file boot_vectors.s
+ *
+ * @brief ARM Exception Vectors table.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ * $Rev:  $
+ *
+ ****************************************************************************************
+ */
+
+.text
+    .align  4
+    .global vectors, boot_breakpoint
+    .type   vectors, function
+
+vectors:
+    # reset handler
+    B       boot_reset
+    # undefined handler
+    B       boot_undefined
+    # SWI handler
+    B       boot_swi
+    # Prefetch error handler
+    B       boot_pabort
+    # abort handler
+    B       boot_dabort
+    # reserved vector
+    B       boot_reserved
+    # irq
+    B       intc_irq
+    # fiq
+    B       intc_fiq
+
+boot_breakpoint:
+    # If set to 0 by host before getting out of reset, the cpu
+    # will loop and light the leds indefinitely
+    .word   1

component/ble/plf/refip/src/arch/boot/rvds/boot.h

@@ -0,0 +1,58 @@
+/**
+ ****************************************************************************************
+ *
+ * @file boot.h
+ *
+ * @brief This file contains the declarations of the boot related variables.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef _BOOT_H_
+#define _BOOT_H_
+
+#if 0
+/// Length of the code
+extern const uint32_t Image$$EXEC_RAM_TEXT$$Length[];
+#define CODE_LENGTH        ((uint32_t)Image$$EXEC_RAM_TEXT$$Length)
+
+/// Length of the RW data
+extern const uint32_t Image$$RAM_DATA$$Length[];
+#define DATA_LENGTH        ((uint32_t)Image$$RAM_DATA$$Length)
+
+/// Unloaded RAM area base address
+extern const uint32_t Image$$RAM_UNLOADED$$Base[];
+#define RAM_UNLOADED_BASE   ((uint32_t)Image$$RAM_UNLOADED$$Base)
+
+/// Stack base address
+extern const uint32_t Image$$RAM_STACK_UNUSED$$Base[];
+#define STACK_BASE_UNUSED   ((uint32_t)Image$$RAM_STACK_UNUSED$$Base)
+extern const uint32_t Image$$RAM_STACK_UNUSED$$ZI$$Length[];
+#define STACK_LEN_UNUSED   ((uint32_t)Image$$RAM_STACK_UNUSED$$ZI$$Length)
+
+extern const uint32_t Image$$RAM_STACK_SVC$$Base[] ;
+#define STACK_BASE_SVC   ((uint32_t)Image$$RAM_STACK_SVC$$Base)
+extern const uint32_t Image$$RAM_STACK_SVC$$ZI$$Length[];
+#define STACK_LEN_SVC  ((uint32_t)Image$$RAM_STACK_SVC$$ZI$$Length)
+
+extern const uint32_t Image$$RAM_STACK_IRQ$$Base[];
+#define STACK_BASE_IRQ  ((uint32_t)Image$$RAM_STACK_IRQ$$Base)
+extern const uint32_t Image$$RAM_STACK_IRQ$$ZI$$Length[];
+#define STACK_LEN_IRQ   ((uint32_t)Image$$RAM_STACK_IRQ$$ZI$$Length)
+
+extern const uint32_t Image$$RAM_STACK_FIQ$$Base[];
+#define STACK_BASE_FIQ   ((uint32_t)Image$$RAM_STACK_FIQ$$Base)
+extern const uint32_t Image$$RAM_STACK_FIQ$$ZI$$Length[];
+#define STACK_LEN_FIQ   ((uint32_t)Image$$RAM_STACK_FIQ$$ZI$$Length)
+
+#endif
+
+#define BOOT_PATTERN_UNUSED   0xAA      // Pattern to fill UNUSED stack
+#define BOOT_PATTERN_SVC      0xBB      // Pattern to fill SVC stack
+#define BOOT_PATTERN_IRQ      0xCC      // Pattern to fill IRQ stack
+#define BOOT_PATTERN_FIQ      0xDD      // Pattern to fill FIQ stack
+
+#endif // _BOOT_H_

component/ble/plf/refip/src/arch/boot/rvds/boot_handlers.s

@@ -0,0 +1,325 @@
+;/**
+; ****************************************************************************************
+; *
+; * @file boot_handlers.s
+; *
+; * @brief ARM Exception Vector handler functions.
+; *
+; * Copyright (C) RivieraWaves 2009-2015
+; *
+; * $Rev: 7583 $
+; *
+; ****************************************************************************************
+; */
+
+    IF {CPU} /= "Cortex-M3"
+    IF {CPU} /= "Cortex-M1"
+    IF {CPU} /= "Cortex-M0"
+
+    ;Export pointers to the vector handlers.
+    EXPORT   boot_reset
+    EXPORT   boot_undefined
+    EXPORT   boot_swi
+    EXPORT   boot_pabort
+    EXPORT   boot_dabort
+    EXPORT   boot_reserved
+
+    IMPORT   rw_main
+
+;/* ========================================================================
+; *                                Constants
+; * ======================================================================== */
+
+BOOT_MODE_MASK EQU 0x1F
+
+BOOT_MODE_USR  EQU 0x10
+BOOT_MODE_FIQ  EQU 0x11
+BOOT_MODE_IRQ  EQU 0x12
+BOOT_MODE_SVC  EQU 0x13
+BOOT_MODE_ABT  EQU 0x17
+BOOT_MODE_UND  EQU 0x1B
+BOOT_MODE_SYS  EQU 0x1F
+
+I_BIT          EQU 0x80
+F_BIT          EQU 0x40
+
+BOOT_COLOR_UNUSED  EQU 0xAAAAAAAA      ; Pattern to fill UNUSED stack
+BOOT_COLOR_SVC     EQU 0xBBBBBBBB      ; Pattern to fill SVC stack
+BOOT_COLOR_IRQ     EQU 0xCCCCCCCC      ; Pattern to fill IRQ stack
+BOOT_COLOR_FIQ     EQU 0xDDDDDDDD      ; Pattern to fill FIQ stack
+
+;/* ========================================================================
+; *                                Macros
+; * ======================================================================== */
+
+;/* ========================================================================
+;/**
+; * Macro for switching ARM mode
+; */
+    MACRO
+$x  BOOT_CHANGE_MODE $newMode
+        MRS   R0, CPSR
+        BIC   R0, R0, #BOOT_MODE_MASK
+        ORR   R0, R0, #BOOT_MODE_$newMode
+        MSR   CPSR_c, R0
+    MEND
+
+
+;/* ========================================================================
+;/**
+; * Macro for setting the stack
+; */
+    MACRO
+$x  BOOT_SET_STACK $stackName
+        LDR   R0, boot_stack_base_$stackName
+        LDR   R2, boot_stack_len_$stackName
+        ADD   R1, R0, R2
+        MOV   SP, R1        ; Set stack pointer
+
+        LDR   R2, =BOOT_COLOR_$stackName
+
+90      CMP   R0, R1        ; End of stack?
+        STRLT R2, [r0]      ; Colorize stack word
+        ADDLT R0, R0, #4
+        BLT   %B90          ; branch to previous local label
+
+    MEND
+
+
+   PRESERVE8
+   AREA  ||.text||, CODE, READONLY
+;/* ========================================================================
+; *                                Globals
+; * ======================================================================== */
+
+;/* ========================================================================
+;/**
+; * CP15 DTCM Control Reg settings
+; */
+boot_Cp15DtcmReg
+    DCD 0x01010001
+
+
+;/* ========================================================================
+;/**
+; * CP15 ITCM Control Reg settings
+; */
+boot_Cp15ItcmReg
+    DCD 0x01000001
+
+;/* ========================================================================
+;/**
+; * ROM
+; */
+   IMPORT    |Load$$RAM_DATA$$Base|           ; Base of ROM data
+rom_base
+    DCD |Load$$RAM_DATA$$Base|
+   ;/* ========================================================================
+;/**
+; * RAM to initialize with rom data
+; */
+    IMPORT    |Image$$RAM_DATA$$Base|
+ram_base
+    DCD |Image$$RAM_DATA$$Base|
+    IMPORT    |Image$$RAM_DATA$$Length|
+ram_length
+    DCD |Image$$RAM_DATA$$Length|
+
+;/* ========================================================================
+;/**
+; * RAM_BSS
+; */
+    IMPORT   |Image$$RAM_BSS$$ZI$$Base|
+ram_bss_base
+    DCD |Image$$RAM_BSS$$ZI$$Base|
+
+    IMPORT   |Image$$RAM_BSS$$ZI$$Length|
+ram_bss_length
+    DCD |Image$$RAM_BSS$$ZI$$Length|
+
+;/* ========================================================================
+;/**
+; * Unused (ABT, UNDEFINED, SYSUSR) Mode
+; */
+    IMPORT   |Image$$RAM_STACK_UNUSED$$Base|
+boot_stack_base_UNUSED
+    DCD |Image$$RAM_STACK_UNUSED$$Base|
+
+    IMPORT   |Image$$RAM_STACK_UNUSED$$ZI$$Length|
+boot_stack_len_UNUSED
+    DCD |Image$$RAM_STACK_UNUSED$$ZI$$Length|
+
+
+;/* ========================================================================
+;/**
+; * IRQ Mode
+; */
+    IMPORT   |Image$$RAM_STACK_IRQ$$Base|
+boot_stack_base_IRQ
+    DCD |Image$$RAM_STACK_IRQ$$Base|
+
+    IMPORT   |Image$$RAM_STACK_IRQ$$ZI$$Length|
+boot_stack_len_IRQ
+    DCD |Image$$RAM_STACK_IRQ$$ZI$$Length|
+
+
+;/* ========================================================================
+;/**
+; * Supervisor Mode
+; */
+    IMPORT   |Image$$RAM_STACK_SVC$$Base|
+boot_stack_base_SVC
+    DCD |Image$$RAM_STACK_SVC$$Base|
+
+    IMPORT   |Image$$RAM_STACK_SVC$$ZI$$Length|
+boot_stack_len_SVC
+    DCD |Image$$RAM_STACK_SVC$$ZI$$Length|
+
+
+;/* ========================================================================
+;/**
+; * FIQ Mode
+; */
+    IMPORT   |Image$$RAM_STACK_FIQ$$Base|
+boot_stack_base_FIQ
+    DCD |Image$$RAM_STACK_FIQ$$Base|
+
+    IMPORT   |Image$$RAM_STACK_FIQ$$ZI$$Length|
+boot_stack_len_FIQ
+    DCD |Image$$RAM_STACK_FIQ$$ZI$$Length|
+
+
+;/* ========================================================================
+; *                                Functions
+; * ======================================================================== */
+
+;/* ========================================================================
+;/**
+; * Function to handle reset vector
+; */
+boot_reset
+    ; * ==================
+    ; Setup all stacks
+    ; Note: Sys and Usr mode are not used
+    BOOT_CHANGE_MODE SYS
+    BOOT_SET_STACK   UNUSED
+    BOOT_CHANGE_MODE ABT
+    BOOT_SET_STACK   UNUSED
+    BOOT_CHANGE_MODE UND
+    BOOT_SET_STACK   UNUSED
+    BOOT_CHANGE_MODE IRQ
+    BOOT_SET_STACK   IRQ
+    BOOT_CHANGE_MODE FIQ
+    BOOT_SET_STACK   FIQ
+    BOOT_CHANGE_MODE SVC
+    BOOT_SET_STACK   SVC
+
+
+    ; Stay in Supervisor Mode
+
+
+
+    ; Recopy rom to ram
+    LDR     R0, rom_base                 ; Get base of ROM data
+    LDR     R1, ram_base                 ; Get base of RAM to initialise
+    LDR     R3, ram_length               ; Get length of RAM to initialise
+
+copy_rom_ram
+    CMP     R3, #0                     ; Copy init data, init of RW area
+    LDRGT   R2, [R0], #4               ; Load data
+    STRGT   R2, [R1], #4               ; Store data
+    SUBGT   R3, R3, #4                 ; Decrement RW length
+    BGT     copy_rom_ram               ; For each word
+
+    ; Init the BSS section
+    LDR     R0, ram_bss_base
+    LDR     R1, ram_bss_length
+    MOV     R2, #0
+    MOV     R3, #0
+    MOV     R4, #0
+    MOV     R5, #0
+init_bss_loop
+    SUBS    R1, R1, #16
+    STMCSIA R0!, {R2, R3, R4, R5}
+    BHI     init_bss_loop
+    LSLS    R1, R1, #29
+    STMCSIA R0!, {R4, R5}
+    STRMI   R3, [R0]
+
+    ; * ==================
+    ; Clear Registers
+    MOV R0, #0
+    MOV R1, #0
+    MOV R2, #0
+    MOV R3, #0
+    MOV R4, #0
+    MOV R5, #0
+    MOV R6, #0
+    MOV R7, #0
+    MOV R8, #0
+    MOV R9, #0
+    MOV R10, #0
+    MOV R11, #0
+    MOV R12, #0
+
+; Now safe to enable interrupts, so do this and remain in SVC mode
+    MOV        r0, #BOOT_MODE_SVC:OR:I_BIT:OR:F_BIT ; IRQ and FIQ still disabled
+    MSR        CPSR_c, r0
+
+
+    BL rw_main
+
+
+    ; If For some reason main returns (which it shouldn't)
+    ; Just loop here and wait for the watchdog to reset
+_boot_reset_loop
+    B _boot_reset_loop
+
+
+;/* ========================================================================
+;/**
+; * Function to handle undefined vector
+; */
+boot_undefined
+
+    B boot_undefined
+
+;/* ========================================================================
+;/**
+; * Function to handle software interrupt vector
+; */
+boot_swi
+
+    B boot_swi
+
+
+;/* ========================================================================
+;/**
+; * Function to handle Prefetch Abort vector
+; */
+boot_pabort
+
+    B boot_pabort
+
+;/* ========================================================================
+;/**
+; * Function to handle Data Abort vector
+; */
+boot_dabort
+
+    B boot_dabort
+
+;/* ========================================================================
+;/**
+; * Function to handle Reserved vector
+; */
+boot_reserved
+
+    B boot_reserved
+    SUBS PC, LR, #4
+
+    ENDIF
+    ENDIF
+    ENDIF
+
+    END

component/ble/plf/refip/src/arch/boot/rvds/boot_vectors.s

@@ -0,0 +1,59 @@
+;/**
+; ****************************************************************************************
+; *
+; * @file boot_vectors.s
+; *
+; * @brief ARM Exception Vectors table.
+; *
+; * Copyright (C) RivieraWaves 2009-2015
+; *
+; * $Rev:  $
+; *
+; ****************************************************************************************
+; */
+
+    IF {CPU} /= "Cortex-M3"
+    IF {CPU} /= "Cortex-M1"
+    IF {CPU} /= "Cortex-M0"
+
+    ;Import pointers to the actual vector handlers.
+    IMPORT   boot_reset
+    IMPORT   boot_undefined
+    IMPORT   boot_swi
+    IMPORT   boot_pabort
+    IMPORT   boot_dabort
+    IMPORT   boot_reserved
+    IMPORT   intc_irq
+    IMPORT   intc_fiq
+
+    AREA |C$$zinit|,NOINIT          ; Data in ZI area
+
+    AREA  ||.boot_vectors||, CODE, READONLY
+    CODE32
+    ;
+    ; This is the entry point for the system and this vector table must be
+    ; physically located or mapped to address 0.
+    ;
+    ENTRY
+    EXPORT  boot_vectors
+boot_vectors
+    B boot_reset
+    B boot_undefined
+    B boot_swi
+    B boot_pabort
+    B boot_dabort
+    B boot_reserved
+    B intc_irq
+    B intc_fiq
+
+    EXPORT boot_breakpoint
+boot_breakpoint
+    ; If set to 0 by host before getting out of reset, the cpu
+    ; will loop and light the leds indefinitely
+    DCD 1
+
+    ENDIF
+    ENDIF
+    ENDIF
+
+    END

component/ble/plf/refip/src/arch/compiler/gnuarm/compiler.h

@@ -0,0 +1,118 @@
+/**
+ ****************************************************************************************
+ *
+ * @file gnuarm/compiler.h
+ *
+ * @brief Definitions of compiler specific directives.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+#if 0
+#ifndef _COMPILER_H_
+#define _COMPILER_H_
+
+/// define the static keyword for this compiler
+#ifdef CFG_STATIC
+#define __STATIC static
+#else // CFG_STATIC
+#define __STATIC
+#endif // CFG_STATIC
+
+/// define the force inlining attribute for this compiler
+#define __INLINE static __attribute__((__always_inline__)) inline
+
+/// define the IRQ handler attribute for this compiler
+#define __IRQ __attribute__((__interrupt__("IRQ")))
+
+/// define the BLE IRQ handler attribute for this compiler
+#define __BTIRQ
+
+/// define the BLE IRQ handler attribute for this compiler
+#define __BLEIRQ
+
+/// define the FIQ handler attribute for this compiler
+#define __FIQ __attribute__((__interrupt__("FIQ")))
+
+/// define size of an empty array (used to declare structure with an array size not defined)
+#define __ARRAY_EMPTY
+
+/// Function returns struct in registers (4 in rvds, var with gnuarm).
+/// With Gnuarm, feature depends on command line options and
+/// impacts ALL functions returning 2-words max structs
+/// (check -freg-struct-return and -mabi=xxx)
+#define __VIR
+
+/// function has no side effect and return depends only on arguments
+#define __PURE __attribute__((const))
+
+/// Align instantiated lvalue or struct member on 4 bytes
+#define __ALIGN4 __attribute__((aligned(4)))
+
+/// __MODULE__ comes from the RVDS compiler that supports it
+//#define __MODULE__ __BASE_FILE__
+
+/// Pack a structure field
+#define __PACKED __attribute__ ((__packed__))
+
+/// Put a variable in a memory maintained during deep sleep
+#define __LOWPOWER_SAVED
+
+#endif // _COMPILER_H_
+
+#endif
+
+/**
+ ****************************************************************************************
+ *
+ * @file rvds/compiler.h
+ *
+ * @brief Definitions of compiler specific directives.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef _COMPILER_H_
+#define _COMPILER_H_
+
+#include "xc6xxx.h"
+
+#ifndef __ARMCC_VERSION
+#error "File only included with RVDS!"
+#endif // __ARMCC_VERSION
+
+/// define the static keyword for this compiler
+#ifdef CFG_STATIC
+#define __STATIC static
+#else // CFG_STATIC
+#define __STATIC
+#endif // CFG_STATIC
+
+/// define the force inlining attribute for this compiler
+//#define __INLINE __forceinline static
+
+/// define the IRQ handler attribute for this compiler
+#define __IRQ __irq
+
+/// define the BLE IRQ handler attribute for this compiler
+#define __BTIRQ
+
+/// define the BLE IRQ handler attribute for this compiler
+#define __BLEIRQ
+
+/// define the FIQ handler attribute for this compiler
+#define __FIQ __irq
+
+/// define size of an empty array (used to declare structure with an array size not defined)
+#define __ARRAY_EMPTY
+
+/// Put a variable in a memory maintained during deep sleep
+#define __LOWPOWER_SAVED
+
+#endif // _COMPILER_H_
+

component/ble/plf/refip/src/arch/ll/armgcc/ll.h

@@ -0,0 +1,91 @@
+/**
+ ****************************************************************************************
+ *
+ * @file ll.h
+ *
+ * @brief Declaration of low level functions.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef LL_H_
+#define LL_H_
+
+#ifndef __GNUC__
+#error "File only included with ARM GCC"
+#endif // __GNUC__
+
+#include <stdint.h>
+
+/** @brief Enable interrupts globally in the system.
+ * This macro must be used when the initialization phase is over and the interrupts
+ * can start being handled by the system.
+ */
+#define GLOBAL_INT_START()                                                  \
+do {                                                                        \
+    uint32_t __l_cpsr_tmp;                                                  \
+    __asm volatile("MRS %0, CPSR" : "=r"(__l_cpsr_tmp));                    \
+    __asm volatile("BIC %0, %1, #0x80" : "=r"(__l_cpsr_tmp) :               \
+                 "r"(__l_cpsr_tmp));                                        \
+    __asm volatile("MSR CPSR_cxsf, %0" : : "r"(__l_cpsr_tmp));              \
+} while(0)
+
+/** @brief Disable interrupts globally in the system.
+ * This macro must be used when the system wants to disable all the interrupt
+ * it could handle.
+ */
+#define GLOBAL_INT_STOP()                                                   \
+do {                                                                        \
+    uint32_t __l_cpsr_tmp;                                                  \
+    __asm volatile("MRS %0, CPSR" : "=r"(__l_cpsr_tmp));                    \
+    __asm volatile("ORR %0, %1, #0x80" : "=r"(__l_cpsr_tmp) :               \
+                 "r"(__l_cpsr_tmp));                                        \
+    __asm volatile("MSR CPSR_cxsf, %0" : : "r"(__l_cpsr_tmp));              \
+} while(0)
+
+/** @brief Disable interrupts globally in the system.
+ * This macro must be used in conjunction with the @ref GLOBAL_INT_RESTORE macro since this
+ * last one will close the brace that the current macro opens.  This means that both
+ * macros must be located at the same scope level.
+ */
+#define GLOBAL_INT_DISABLE();                                               \
+do {                                                                        \
+    uint32_t __l_cpsr_tmp;                                                  \
+    uint32_t __l_irq_rest;                                                  \
+    __asm volatile("MRS %0, CPSR" : "=r"(__l_cpsr_tmp));                    \
+    __asm volatile("AND %0, %1, #0x80" : "=r"(__l_irq_rest) :               \
+                 "r"(__l_cpsr_tmp));                                        \
+    __asm volatile("ORR %0, %1, #0x80" : "=r"(__l_cpsr_tmp) :               \
+                 "r"(__l_cpsr_tmp));                                        \
+    __asm volatile("MSR CPSR_cxsf, %0" : : "r"(__l_cpsr_tmp));              \
+
+/** @brief Restore interrupts from the previous global disable.
+ * @sa GLOBAL_INT_DISABLE
+ */
+#define GLOBAL_INT_RESTORE();                                               \
+    __asm volatile("MRS %0, CPSR" : "=r"(__l_cpsr_tmp));                    \
+    __asm volatile("BIC %0, %1, #0x80" : "=r"(__l_cpsr_tmp) :               \
+                 "r"(__l_cpsr_tmp));                                        \
+    __asm volatile("ORR %0, %1, %2" : "=r"(__l_cpsr_tmp) :                  \
+                 "r"(__l_cpsr_tmp), "r"(__l_irq_rest));                     \
+    __asm volatile("MSR CPSR_cxsf, %0" : : "r"(__l_cpsr_tmp));              \
+} while(0)
+
+/** @brief Invoke the wait for interrupt procedure of the processor.
+ *
+ * @warning It is suggested that this macro is called while the interrupts are disabled
+ * to have performed the checks necessary to decide to move to sleep mode.
+ *
+ */
+#define WFI()                                                               \
+do {                                                                        \
+    uint32_t __l_rd;                                                        \
+    __asm volatile("MOV %0, #0" : "=r"(__l_rd));                            \
+    __asm volatile("MCR p15, 0, %0, c7, c0, 4" : "=r"(__l_rd));             \
+} while(0)
+
+
+#endif // LL_H_

component/ble/plf/refip/src/arch/ll/armgcc/ll.s

@@ -0,0 +1,15 @@
+/**
+ ****************************************************************************************
+ *
+ * @file ll.s
+ *
+ * @brief ARM low level functions.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ * $Rev:  $
+ *
+ ****************************************************************************************
+ */
+.text
+    .align  4

component/ble/plf/refip/src/arch/ll/armgcc_4_8/ll.h

@@ -0,0 +1,97 @@
+/**
+ ****************************************************************************************
+ *
+ * @file ll.h
+ *
+ * @brief Declaration of low level functions.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef LL_H_
+#define LL_H_
+
+#ifndef __GNUC__
+#error "File only included with ARM GCC"
+#endif // __GNUC__
+
+#include <stdint.h>
+
+extern uint32_t critical_sec_cnt;
+
+/** @brief Enable interrupts globally in the system.
+ * This macro must be used when the initialization phase is over and the interrupts
+ * can start being handled by the system.
+ */
+#define GLOBAL_INT_START()                                                  \
+do {                                                                        \
+    uint32_t __l_cpsr_tmp;                                                  \
+    __asm volatile("MRS %0, CPSR" : "=r"(__l_cpsr_tmp));                    \
+    __asm volatile("BIC %0, %1, #0x80" : "=r"(__l_cpsr_tmp) :               \
+                 "r"(__l_cpsr_tmp));                                        \
+    __asm volatile("MSR CPSR_cxsf, %0" : : "r"(__l_cpsr_tmp));              \
+} while(0)
+
+/** @brief Disable interrupts globally in the system.
+ * This macro must be used when the system wants to disable all the interrupt
+ * it could handle.
+ */
+#define GLOBAL_INT_STOP()                                                   \
+do {                                                                        \
+    uint32_t __l_cpsr_tmp;                                                  \
+    __asm volatile("MRS %0, CPSR" : "=r"(__l_cpsr_tmp));                    \
+    __asm volatile("ORR %0, %1, #0x80" : "=r"(__l_cpsr_tmp) :               \
+                 "r"(__l_cpsr_tmp));                                        \
+    __asm volatile("MSR CPSR_cxsf, %0" : : "r"(__l_cpsr_tmp));              \
+} while(0)
+
+/** @brief Disable interrupts globally in the system.
+ * This macro must be used in conjunction with the @ref GLOBAL_INT_RESTORE macro since this
+ * last one will close the brace that the current macro opens.  This means that both
+ * macros must be located at the same scope level.
+ */
+#define GLOBAL_INT_DISABLE()                                                \
+do {                                                                        \
+    uint32_t __l_cpsr_tmp;                                                  \
+    uint32_t __l_irq_rest;                                                  \
+    __asm volatile("MRS %0, CPSR" : "=r"(__l_cpsr_tmp));                    \
+    __asm volatile("AND %0, %1, #0x80" : "=r"(__l_irq_rest) :               \
+                 "r"(__l_cpsr_tmp));                                        \
+    __asm volatile("ORR %0, %1, #0x80" : "=r"(__l_cpsr_tmp) :               \
+                 "r"(__l_cpsr_tmp));                                        \
+    __asm volatile("MSR CPSR_cxsf, %0" : : "r"(__l_cpsr_tmp));              \
+    critical_sec_cnt++;                                                     \
+
+/** @brief Restore interrupts from the previous global disable.
+ * @sa GLOBAL_INT_DISABLE
+ */
+#define GLOBAL_INT_RESTORE()                                                \
+    critical_sec_cnt--;                                                     \
+    __asm volatile("MRS %0, CPSR" : "=r"(__l_cpsr_tmp));                    \
+    __asm volatile("BIC %0, %1, #0x80" : "=r"(__l_cpsr_tmp) :               \
+                 "r"(__l_cpsr_tmp));                                        \
+    __asm volatile("ORR %0, %1, %2" : "=r"(__l_cpsr_tmp) :                  \
+                 "r"(__l_cpsr_tmp), "r"(__l_irq_rest));                     \
+    __asm volatile("MSR CPSR_cxsf, %0" : : "r"(__l_cpsr_tmp));              \
+} while(0)
+
+/** @brief Invoke the wait for interrupt procedure of the processor.
+ *
+ * @warning It is suggested that this macro is called while the interrupts are disabled
+ * to have performed the checks necessary to decide to move to sleep mode.
+ *
+ */
+#define WFI()                                                               \
+do {                                                                        \
+    uint32_t __l_rd;                                                        \
+    if(critical_sec_cnt != 1)                                               \
+        *((uint32_t*) 0x00000) = 0xDEAD;                                    \
+    __asm volatile("MOV %0, #0" : "=r"(__l_rd));                            \
+    __asm volatile("MCR p15, 0, %0, c7, c0, 4" : "=r"(__l_rd));             \
+} while(0)
+
+
+#endif // LL_H_

component/ble/plf/refip/src/arch/ll/armgcc_4_8/ll.s

@@ -0,0 +1,15 @@
+/**
+ ****************************************************************************************
+ *
+ * @file ll.s
+ *
+ * @brief ARM low level functions.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ * $Rev:  $
+ *
+ ****************************************************************************************
+ */
+.text
+    .align  4

component/ble/plf/refip/src/arch/ll/gnuarm/ll.h

@@ -0,0 +1,58 @@
+/**
+ ****************************************************************************************
+ *
+ * @file ll.h
+ *
+ * @brief Declaration of low level functions.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef LL_H_
+#define LL_H_
+
+#ifndef __arm__
+#error "File only included with RVDS!"
+#endif // __arm__
+
+#include <stdint.h>
+#include "arch.h"
+#include "reg_intc.h"
+
+/** @brief Enable interrupts globally in the system.
+ * This macro must be used when the initialization phase is over and the interrupts
+ * can start being handled by the system.
+ */
+#define GLOBAL_INT_START() ; \
+do { \
+    __enable_irq(); \
+} while(0); 
+
+#define GLOBAL_INT_STOP()  ; \
+do { \
+    __disable_irq(); \
+} while(0);
+
+#define GLOBAL_INT_DISABLE() ; \
+do { \
+    uint32_t irq_temp; \
+    irq_temp = __disable_irq(); 
+#define GLOBAL_INT_RESTORE() ;  \
+    if(!irq_temp)               \
+    {                           \
+        __enable_irq();         \
+    }                           \
+} while(0);
+
+#define WFI() ; \
+do { \
+    __wfi(); \
+}while(0);
+
+
+#endif // LL_H_
+
+

component/ble/plf/refip/src/arch/ll/gnuarm/ll.s

@@ -0,0 +1,15 @@
+/**
+ ****************************************************************************************
+ *
+ * @file ll.s
+ *
+ * @brief ARM low level functions.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ * $Rev:  $
+ *
+ ****************************************************************************************
+ */
+.text
+    .align  4

component/ble/plf/refip/src/arch/ll/rvds/ll.h

@@ -0,0 +1,58 @@
+/**
+ ****************************************************************************************
+ *
+ * @file ll.h
+ *
+ * @brief Declaration of low level functions.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef LL_H_
+#define LL_H_
+
+#ifndef __arm__
+#error "File only included with RVDS!"
+#endif // __arm__
+
+#include <stdint.h>
+#include "arch.h"
+#include "reg_intc.h"
+
+/** @brief Enable interrupts globally in the system.
+ * This macro must be used when the initialization phase is over and the interrupts
+ * can start being handled by the system.
+ */
+#define GLOBAL_INT_START() ; \
+do { \
+    __enable_irq(); \
+} while(0); 
+
+#define GLOBAL_INT_STOP()  ; \
+do { \
+    __disable_irq(); \
+} while(0);
+
+#define GLOBAL_INT_DISABLE() ; \
+do { \
+    uint32_t irq_temp; \
+    irq_temp = __disable_irq(); 
+#define GLOBAL_INT_RESTORE() ;  \
+    if(!irq_temp)               \
+    {                           \
+        __enable_irq();         \
+    }                           \
+} while(0);
+
+#define WFI() ; \
+do { \
+    __wfi(); \
+}while(0);
+
+
+#endif // LL_H_
+
+

component/ble/plf/refip/src/arch/ll/rvds/ll.s

@@ -0,0 +1,28 @@
+;/**
+; ****************************************************************************************
+; *
+; * @file ll.s
+; *
+; * @brief ARM low level functions.
+; *
+; * Copyright (C) RivieraWaves 2009-2015
+; *
+; * $Rev:  $
+; *
+; ****************************************************************************************
+; */
+
+
+    AREA ||.text||, CODE, READONLY
+
+    IF {CPU} /= "Cortex-M3"
+    IF {CPU} /= "Cortex-M1"
+    IF {CPU} /= "Cortex-M0"
+    CODE32
+    ENDIF
+    ENDIF
+    ENDIF
+
+
+   END
+

component/ble/plf/refip/src/arch/plf.h

@@ -0,0 +1,40 @@
+/**
+ ****************************************************************************************
+ *
+ * @file plf.h
+ *
+ * @brief This file contains the definitions of the macros and functions that are
+ * platform dependent.  The implementation of those is implemented in the
+ * appropriate platform directory.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+#ifndef _PLF_H_
+#define _PLF_H_
+
+/**
+ ****************************************************************************************
+ * @defgroup PLF
+ * @ingroup DRIVERS
+ *
+ * @brief Platform register driver
+ *
+ * @{
+ *
+ ****************************************************************************************
+ */
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+#define plf_read_rf_board_id()      0
+#define plf_rf_switch()             1
+
+/// @} PLF
+
+#endif // _PLF_H_

component/ble/plf/refip/src/build/ble-full/reg/fw/_reg_assert_mgr.h

@@ -0,0 +1,10 @@
+#ifndef __REG_ASSERT_MGR_H_
+#define __REG_ASSERT_MGR_H_
+
+#define REG_ASSERT_MGR_SIZE 16
+
+#define REG_ASSERT_MGR_BASE_ADDR 0x1000D000
+
+
+#endif // __REG_ASSERT_MGR_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/_reg_blecore.h

@@ -0,0 +1,10 @@
+#ifndef __REG_BLECORE_H_
+#define __REG_BLECORE_H_
+
+#define REG_BLECORE_SIZE 532
+
+#define REG_BLECORE_BASE_ADDR 0x53000000
+
+
+#endif // __REG_BLECORE_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/_reg_dma.h

@@ -0,0 +1,10 @@
+#ifndef __REG_DMA_H_
+#define __REG_DMA_H_
+
+#define REG_DMA_SIZE 48
+
+#define REG_DMA_BASE_ADDR 0x1000B000
+
+
+#endif // __REG_DMA_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/_reg_dma_channel.h

@@ -0,0 +1,10 @@
+#ifndef __REG_DMA_CHANNEL_H_
+#define __REG_DMA_CHANNEL_H_
+
+#define REG_DMA_CHANNEL_SIZE 16
+
+#define REG_DMA_CHANNEL_BASE_ADDR 0x1000B000
+
+
+#endif // __REG_DMA_CHANNEL_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/_reg_ecc_accel.h

@@ -0,0 +1,10 @@
+#ifndef __REG_ECC_ACCEL_H_
+#define __REG_ECC_ACCEL_H_
+
+#define REG_ECC_ACCEL_SIZE 20
+
+#define REG_ECC_ACCEL_BASE_ADDR 0x1000F000
+
+
+#endif // __REG_ECC_ACCEL_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/_reg_em_ble_cs.h

@@ -0,0 +1,10 @@
+#ifndef __REG_EM_BLE_CS_H_
+#define __REG_EM_BLE_CS_H_
+
+#define REG_EM_BLE_CS_SIZE 148
+
+#define REG_EM_BLE_CS_BASE_ADDR 0x53004000
+
+
+#endif // __REG_EM_BLE_CS_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/_reg_em_ble_ral.h

@@ -0,0 +1,10 @@
+#ifndef __REG_EM_BLE_RAL_H_
+#define __REG_EM_BLE_RAL_H_
+
+#define REG_EM_BLE_RAL_SIZE 56
+
+#define REG_EM_BLE_RAL_BASE_ADDR 0x53004000
+
+
+#endif // __REG_EM_BLE_RAL_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/_reg_em_ble_rx_cte_desc.h

@@ -0,0 +1,10 @@
+#ifndef __REG_EM_BLE_RX_CTE_DESC_H_
+#define __REG_EM_BLE_RX_CTE_DESC_H_
+
+#define REG_EM_BLE_RX_CTE_DESC_SIZE 168
+
+#define REG_EM_BLE_RX_CTE_DESC_BASE_ADDR 0x53004000
+
+
+#endif // __REG_EM_BLE_RX_CTE_DESC_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/_reg_em_ble_rx_desc.h

@@ -0,0 +1,10 @@
+#ifndef __REG_EM_BLE_RX_DESC_H_
+#define __REG_EM_BLE_RX_DESC_H_
+
+#define REG_EM_BLE_RX_DESC_SIZE 28
+
+#define REG_EM_BLE_RX_DESC_BASE_ADDR 0x53004000
+
+
+#endif // __REG_EM_BLE_RX_DESC_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/_reg_em_ble_rx_iso_buf.h

@@ -0,0 +1,10 @@
+#ifndef __REG_EM_BLE_RX_ISO_BUF_H_
+#define __REG_EM_BLE_RX_ISO_BUF_H_
+
+#define REG_EM_BLE_RX_ISO_BUF_SIZE 260
+
+#define REG_EM_BLE_RX_ISO_BUF_BASE_ADDR 0x53004000
+
+
+#endif // __REG_EM_BLE_RX_ISO_BUF_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/_reg_em_ble_rx_iso_desc.h

@@ -0,0 +1,10 @@
+#ifndef __REG_EM_BLE_RX_ISO_DESC_H_
+#define __REG_EM_BLE_RX_ISO_DESC_H_
+
+#define REG_EM_BLE_RX_ISO_DESC_SIZE 12
+
+#define REG_EM_BLE_RX_ISO_DESC_BASE_ADDR 0x53004000
+
+
+#endif // __REG_EM_BLE_RX_ISO_DESC_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/_reg_em_ble_tx_desc.h

@@ -0,0 +1,10 @@
+#ifndef __REG_EM_BLE_TX_DESC_H_
+#define __REG_EM_BLE_TX_DESC_H_
+
+#define REG_EM_BLE_TX_DESC_SIZE 16
+
+#define REG_EM_BLE_TX_DESC_BASE_ADDR 0x53004000
+
+
+#endif // __REG_EM_BLE_TX_DESC_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/_reg_em_ble_tx_iso_buf.h

@@ -0,0 +1,10 @@
+#ifndef __REG_EM_BLE_TX_ISO_BUF_H_
+#define __REG_EM_BLE_TX_ISO_BUF_H_
+
+#define REG_EM_BLE_TX_ISO_BUF_SIZE 260
+
+#define REG_EM_BLE_TX_ISO_BUF_BASE_ADDR 0x53004000
+
+
+#endif // __REG_EM_BLE_TX_ISO_BUF_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/_reg_em_ble_tx_iso_desc.h

@@ -0,0 +1,10 @@
+#ifndef __REG_EM_BLE_TX_ISO_DESC_H_
+#define __REG_EM_BLE_TX_ISO_DESC_H_
+
+#define REG_EM_BLE_TX_ISO_DESC_SIZE 12
+
+#define REG_EM_BLE_TX_ISO_DESC_BASE_ADDR 0x53004000
+
+
+#endif // __REG_EM_BLE_TX_ISO_DESC_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/_reg_em_ble_wpal.h

@@ -0,0 +1,10 @@
+#ifndef __REG_EM_BLE_WPAL_H_
+#define __REG_EM_BLE_WPAL_H_
+
+#define REG_EM_BLE_WPAL_SIZE 12
+
+#define REG_EM_BLE_WPAL_BASE_ADDR 0x53004000
+
+
+#endif // __REG_EM_BLE_WPAL_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/_reg_em_et.h

@@ -0,0 +1,10 @@
+#ifndef __REG_EM_ET_H_
+#define __REG_EM_ET_H_
+
+#define REG_EM_ET_SIZE 16
+
+#define REG_EM_ET_BASE_ADDR 0x53004000
+
+
+#endif // __REG_EM_ET_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/_reg_intc.h

@@ -0,0 +1,10 @@
+#ifndef __REG_INTC_H_
+#define __REG_INTC_H_
+
+#define REG_INTC_SIZE 280
+
+#define REG_INTC_BASE_ADDR 0x10001000
+
+
+#endif // __REG_INTC_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/_reg_ipcore.h

@@ -0,0 +1,10 @@
+#ifndef __REG_IPCORE_H_
+#define __REG_IPCORE_H_
+
+#define REG_IPCORE_SIZE 408
+
+#define REG_IPCORE_BASE_ADDR 0x53000000
+
+
+#endif // __REG_IPCORE_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/_reg_ipcore_bts.h

@@ -0,0 +1,10 @@
+#ifndef __REG_IPCORE_BTS_H_
+#define __REG_IPCORE_BTS_H_
+
+#define REG_IPCORE_BTS_SIZE 80
+
+#define REG_IPCORE_BTS_BASE_ADDR 0x53000000
+
+
+#endif // __REG_IPCORE_BTS_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/_reg_iqgen.h

@@ -0,0 +1,10 @@
+#ifndef __REG_IQGEN_H_
+#define __REG_IQGEN_H_
+
+#define REG_IQGEN_SIZE 24
+
+#define REG_IQGEN_BASE_ADDR 0x1000A000
+
+
+#endif // __REG_IQGEN_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/_reg_mwsgen.h

@@ -0,0 +1,10 @@
+#ifndef __REG_MWSGEN_H_
+#define __REG_MWSGEN_H_
+
+#define REG_MWSGEN_SIZE 60
+
+#define REG_MWSGEN_BASE_ADDR 0x10009000
+
+
+#endif // __REG_MWSGEN_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/_reg_sw_profiling.h

@@ -0,0 +1,10 @@
+#ifndef __REG_SW_PROFILING_H_
+#define __REG_SW_PROFILING_H_
+
+#define REG_SW_PROFILING_SIZE 40
+
+#define REG_SW_PROFILING_BASE_ADDR 0x1000D100
+
+
+#endif // __REG_SW_PROFILING_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/_reg_timer.h

@@ -0,0 +1,10 @@
+#ifndef __REG_TIMER_H_
+#define __REG_TIMER_H_
+
+#define REG_TIMER_SIZE 28
+
+#define REG_TIMER_BASE_ADDR 0x1000E000
+
+
+#endif // __REG_TIMER_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/_reg_uart.h

@@ -0,0 +1,10 @@
+#ifndef __REG_UART_H_
+#define __REG_UART_H_
+
+#define REG_UART_SIZE 36
+
+#define REG_UART_BASE_ADDR 0x10007000
+
+
+#endif // __REG_UART_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/_reg_uart2.h

@@ -0,0 +1,10 @@
+#ifndef __REG_UART2_H_
+#define __REG_UART2_H_
+
+#define REG_UART2_SIZE 36
+
+#define REG_UART2_BASE_ADDR 0x10008000
+
+
+#endif // __REG_UART2_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/reg_assert_mgr.h

@@ -0,0 +1,273 @@
+#ifndef _REG_ASSERT_MGR_H_
+#define _REG_ASSERT_MGR_H_
+
+#include <stdint.h>
+#include "_reg_assert_mgr.h"
+#include "compiler.h"
+#include "arch.h"
+#include "reg_access.h"
+
+#define REG_ASSERT_MGR_COUNT 4
+
+#define REG_ASSERT_MGR_DECODING_MASK 0x0000000F
+
+/**
+ * @brief ASSERT register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  15:08             txt_size   0x0
+ *     02               params   0
+ *     01                 warn   0
+ *     00                trigg   0
+ * </pre>
+ */
+#define ASRT_ASSERT_ADDR   0x1000D000
+#define ASRT_ASSERT_OFFSET 0x00000000
+#define ASRT_ASSERT_INDEX  0x00000000
+#define ASRT_ASSERT_RESET  0x00000000
+
+__INLINE uint32_t asrt_assert_get(void)
+{
+    return REG_PL_RD(ASRT_ASSERT_ADDR);
+}
+
+__INLINE void asrt_assert_set(uint32_t value)
+{
+    REG_PL_WR(ASRT_ASSERT_ADDR, value);
+}
+
+// field definitions
+#define ASRT_TXT_SIZE_MASK   ((uint32_t)0x0000FF00)
+#define ASRT_TXT_SIZE_LSB    8
+#define ASRT_TXT_SIZE_WIDTH  ((uint32_t)0x00000008)
+#define ASRT_PARAMS_BIT      ((uint32_t)0x00000004)
+#define ASRT_PARAMS_POS      2
+#define ASRT_WARN_BIT        ((uint32_t)0x00000002)
+#define ASRT_WARN_POS        1
+#define ASRT_TRIGG_BIT       ((uint32_t)0x00000001)
+#define ASRT_TRIGG_POS       0
+
+#define ASRT_TXT_SIZE_RST    0x0
+#define ASRT_PARAMS_RST      0x0
+#define ASRT_WARN_RST        0x0
+#define ASRT_TRIGG_RST       0x0
+
+__INLINE void asrt_assert_pack(uint8_t txtsize, uint8_t params, uint8_t warn, uint8_t trigg)
+{
+    ASSERT_ERR((((uint32_t)txtsize << 8) & ~((uint32_t)0x0000FF00)) == 0);
+    ASSERT_ERR((((uint32_t)params << 2) & ~((uint32_t)0x00000004)) == 0);
+    ASSERT_ERR((((uint32_t)warn << 1) & ~((uint32_t)0x00000002)) == 0);
+    ASSERT_ERR((((uint32_t)trigg << 0) & ~((uint32_t)0x00000001)) == 0);
+    REG_PL_WR(ASRT_ASSERT_ADDR,  ((uint32_t)txtsize << 8) | ((uint32_t)params << 2) | ((uint32_t)warn << 1) | ((uint32_t)trigg << 0));
+}
+
+__INLINE void asrt_assert_unpack(uint8_t* txtsize, uint8_t* params, uint8_t* warn, uint8_t* trigg)
+{
+    uint32_t localVal = REG_PL_RD(ASRT_ASSERT_ADDR);
+
+    *txtsize = (localVal & ((uint32_t)0x0000FF00)) >> 8;
+    *params = (localVal & ((uint32_t)0x00000004)) >> 2;
+    *warn = (localVal & ((uint32_t)0x00000002)) >> 1;
+    *trigg = (localVal & ((uint32_t)0x00000001)) >> 0;
+}
+
+__INLINE uint8_t asrt_txt_size_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(ASRT_ASSERT_ADDR);
+    return ((localVal & ((uint32_t)0x0000FF00)) >> 8);
+}
+
+__INLINE void asrt_txt_size_setf(uint8_t txtsize)
+{
+    ASSERT_ERR((((uint32_t)txtsize << 8) & ~((uint32_t)0x0000FF00)) == 0);
+    REG_PL_WR(ASRT_ASSERT_ADDR, (REG_PL_RD(ASRT_ASSERT_ADDR) & ~((uint32_t)0x0000FF00)) | ((uint32_t)txtsize << 8));
+}
+
+__INLINE uint8_t asrt_params_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(ASRT_ASSERT_ADDR);
+    return ((localVal & ((uint32_t)0x00000004)) >> 2);
+}
+
+__INLINE void asrt_params_setf(uint8_t params)
+{
+    ASSERT_ERR((((uint32_t)params << 2) & ~((uint32_t)0x00000004)) == 0);
+    REG_PL_WR(ASRT_ASSERT_ADDR, (REG_PL_RD(ASRT_ASSERT_ADDR) & ~((uint32_t)0x00000004)) | ((uint32_t)params << 2));
+}
+
+__INLINE void asrt_warn_setf(uint8_t warn)
+{
+    ASSERT_ERR((((uint32_t)warn << 1) & ~((uint32_t)0x00000002)) == 0);
+    REG_PL_WR(ASRT_ASSERT_ADDR, (REG_PL_RD(ASRT_ASSERT_ADDR) & ~((uint32_t)0x00000002)) | ((uint32_t)warn << 1));
+}
+
+__INLINE void asrt_trigg_setf(uint8_t trigg)
+{
+    ASSERT_ERR((((uint32_t)trigg << 0) & ~((uint32_t)0x00000001)) == 0);
+    REG_PL_WR(ASRT_ASSERT_ADDR, (REG_PL_RD(ASRT_ASSERT_ADDR) & ~((uint32_t)0x00000001)) | ((uint32_t)trigg << 0));
+}
+
+/**
+ * @brief PARAM register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:16               param2   0x0
+ *  15:00               param1   0x0
+ * </pre>
+ */
+#define ASRT_PARAM_ADDR   0x1000D004
+#define ASRT_PARAM_OFFSET 0x00000004
+#define ASRT_PARAM_INDEX  0x00000001
+#define ASRT_PARAM_RESET  0x00000000
+
+__INLINE uint32_t asrt_param_get(void)
+{
+    return REG_PL_RD(ASRT_PARAM_ADDR);
+}
+
+__INLINE void asrt_param_set(uint32_t value)
+{
+    REG_PL_WR(ASRT_PARAM_ADDR, value);
+}
+
+// field definitions
+#define ASRT_PARAM_2_MASK   ((uint32_t)0xFFFF0000)
+#define ASRT_PARAM_2_LSB    16
+#define ASRT_PARAM_2_WIDTH  ((uint32_t)0x00000010)
+#define ASRT_PARAM_1_MASK   ((uint32_t)0x0000FFFF)
+#define ASRT_PARAM_1_LSB    0
+#define ASRT_PARAM_1_WIDTH  ((uint32_t)0x00000010)
+
+#define ASRT_PARAM_2_RST    0x0
+#define ASRT_PARAM_1_RST    0x0
+
+__INLINE void asrt_param_pack(uint16_t param2, uint16_t param1)
+{
+    ASSERT_ERR((((uint32_t)param2 << 16) & ~((uint32_t)0xFFFF0000)) == 0);
+    ASSERT_ERR((((uint32_t)param1 << 0) & ~((uint32_t)0x0000FFFF)) == 0);
+    REG_PL_WR(ASRT_PARAM_ADDR,  ((uint32_t)param2 << 16) | ((uint32_t)param1 << 0));
+}
+
+__INLINE void asrt_param_unpack(uint16_t* param2, uint16_t* param1)
+{
+    uint32_t localVal = REG_PL_RD(ASRT_PARAM_ADDR);
+
+    *param2 = (localVal & ((uint32_t)0xFFFF0000)) >> 16;
+    *param1 = (localVal & ((uint32_t)0x0000FFFF)) >> 0;
+}
+
+__INLINE uint16_t asrt_param_2_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(ASRT_PARAM_ADDR);
+    return ((localVal & ((uint32_t)0xFFFF0000)) >> 16);
+}
+
+__INLINE void asrt_param_2_setf(uint16_t param2)
+{
+    ASSERT_ERR((((uint32_t)param2 << 16) & ~((uint32_t)0xFFFF0000)) == 0);
+    REG_PL_WR(ASRT_PARAM_ADDR, (REG_PL_RD(ASRT_PARAM_ADDR) & ~((uint32_t)0xFFFF0000)) | ((uint32_t)param2 << 16));
+}
+
+__INLINE uint16_t asrt_param_1_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(ASRT_PARAM_ADDR);
+    return ((localVal & ((uint32_t)0x0000FFFF)) >> 0);
+}
+
+__INLINE void asrt_param_1_setf(uint16_t param1)
+{
+    ASSERT_ERR((((uint32_t)param1 << 0) & ~((uint32_t)0x0000FFFF)) == 0);
+    REG_PL_WR(ASRT_PARAM_ADDR, (REG_PL_RD(ASRT_PARAM_ADDR) & ~((uint32_t)0x0000FFFF)) | ((uint32_t)param1 << 0));
+}
+
+/**
+ * @brief LINE register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00                 line   0x0
+ * </pre>
+ */
+#define ASRT_LINE_ADDR   0x1000D008
+#define ASRT_LINE_OFFSET 0x00000008
+#define ASRT_LINE_INDEX  0x00000002
+#define ASRT_LINE_RESET  0x00000000
+
+__INLINE uint32_t asrt_line_get(void)
+{
+    return REG_PL_RD(ASRT_LINE_ADDR);
+}
+
+__INLINE void asrt_line_set(uint32_t value)
+{
+    REG_PL_WR(ASRT_LINE_ADDR, value);
+}
+
+// field definitions
+#define ASRT_LINE_MASK   ((uint32_t)0xFFFFFFFF)
+#define ASRT_LINE_LSB    0
+#define ASRT_LINE_WIDTH  ((uint32_t)0x00000020)
+
+#define ASRT_LINE_RST    0x0
+
+__INLINE uint32_t asrt_line_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(ASRT_LINE_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void asrt_line_setf(uint32_t line)
+{
+    ASSERT_ERR((((uint32_t)line << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
+    REG_PL_WR(ASRT_LINE_ADDR, (uint32_t)line << 0);
+}
+
+/**
+ * @brief TEXT register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00                 addr   0x0
+ * </pre>
+ */
+#define ASRT_TEXT_ADDR   0x1000D00C
+#define ASRT_TEXT_OFFSET 0x0000000C
+#define ASRT_TEXT_INDEX  0x00000003
+#define ASRT_TEXT_RESET  0x00000000
+
+__INLINE uint32_t asrt_text_get(void)
+{
+    return REG_PL_RD(ASRT_TEXT_ADDR);
+}
+
+__INLINE void asrt_text_set(uint32_t value)
+{
+    REG_PL_WR(ASRT_TEXT_ADDR, value);
+}
+
+// field definitions
+#define ASRT_ADDR_MASK   ((uint32_t)0xFFFFFFFF)
+#define ASRT_ADDR_LSB    0
+#define ASRT_ADDR_WIDTH  ((uint32_t)0x00000020)
+
+#define ASRT_ADDR_RST    0x0
+
+__INLINE uint32_t asrt_addr_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(ASRT_TEXT_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void asrt_addr_setf(uint32_t addr)
+{
+    ASSERT_ERR((((uint32_t)addr << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
+    REG_PL_WR(ASRT_TEXT_ADDR, (uint32_t)addr << 0);
+}
+
+
+#endif // _REG_ASSERT_MGR_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/reg_dma.h

@@ -0,0 +1,519 @@
+#ifndef _REG_DMA_H_
+#define _REG_DMA_H_
+
+#include <stdint.h>
+#include "_reg_dma.h"
+#include "compiler.h"
+#include "arch.h"
+#include "reg_access.h"
+
+#define REG_DMA_COUNT 12
+
+#define REG_DMA_DECODING_MASK 0x0000003F
+
+/**
+ * @brief CFG register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     01               ENABLE   0
+ *     00                RESET   0
+ * </pre>
+ */
+#define DMA_CFG_ADDR   0x1000B000
+#define DMA_CFG_OFFSET 0x00000000
+#define DMA_CFG_INDEX  0x00000000
+#define DMA_CFG_RESET  0x00000000
+
+__INLINE uint32_t dma_cfg_get(void)
+{
+    return REG_PL_RD(DMA_CFG_ADDR);
+}
+
+__INLINE void dma_cfg_set(uint32_t value)
+{
+    REG_PL_WR(DMA_CFG_ADDR, value);
+}
+
+// field definitions
+#define DMA_ENABLE_BIT    ((uint32_t)0x00000002)
+#define DMA_ENABLE_POS    1
+#define DMA_RESET_BIT     ((uint32_t)0x00000001)
+#define DMA_RESET_POS     0
+
+#define DMA_ENABLE_RST    0x0
+#define DMA_RESET_RST     0x0
+
+__INLINE void dma_cfg_pack(uint8_t enable, uint8_t reset)
+{
+    ASSERT_ERR((((uint32_t)enable << 1) & ~((uint32_t)0x00000002)) == 0);
+    ASSERT_ERR((((uint32_t)reset << 0) & ~((uint32_t)0x00000001)) == 0);
+    REG_PL_WR(DMA_CFG_ADDR,  ((uint32_t)enable << 1) | ((uint32_t)reset << 0));
+}
+
+__INLINE void dma_cfg_unpack(uint8_t* enable, uint8_t* reset)
+{
+    uint32_t localVal = REG_PL_RD(DMA_CFG_ADDR);
+
+    *enable = (localVal & ((uint32_t)0x00000002)) >> 1;
+    *reset = (localVal & ((uint32_t)0x00000001)) >> 0;
+}
+
+__INLINE uint8_t dma_cfg_enable_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(DMA_CFG_ADDR);
+    return ((localVal & ((uint32_t)0x00000002)) >> 1);
+}
+
+__INLINE void dma_cfg_enable_setf(uint8_t enable)
+{
+    ASSERT_ERR((((uint32_t)enable << 1) & ~((uint32_t)0x00000002)) == 0);
+    REG_PL_WR(DMA_CFG_ADDR, (REG_PL_RD(DMA_CFG_ADDR) & ~((uint32_t)0x00000002)) | ((uint32_t)enable << 1));
+}
+
+__INLINE void dma_cfg_reset_setf(uint8_t reset)
+{
+    ASSERT_ERR((((uint32_t)reset << 0) & ~((uint32_t)0x00000001)) == 0);
+    REG_PL_WR(DMA_CFG_ADDR, (REG_PL_RD(DMA_CFG_ADDR) & ~((uint32_t)0x00000001)) | ((uint32_t)reset << 0));
+}
+
+/**
+ * @brief ISR_STAT register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     01       CHANNEL_1_STAT   0
+ *     00       CHANNEL_0_STAT   0
+ * </pre>
+ */
+#define DMA_ISR_STAT_ADDR   0x1000B004
+#define DMA_ISR_STAT_OFFSET 0x00000004
+#define DMA_ISR_STAT_INDEX  0x00000001
+#define DMA_ISR_STAT_RESET  0x00000000
+
+__INLINE uint32_t dma_isr_stat_get(void)
+{
+    return REG_PL_RD(DMA_ISR_STAT_ADDR);
+}
+
+// field definitions
+#define DMA_CHANNEL_1_STAT_BIT    ((uint32_t)0x00000002)
+#define DMA_CHANNEL_1_STAT_POS    1
+#define DMA_CHANNEL_0_STAT_BIT    ((uint32_t)0x00000001)
+#define DMA_CHANNEL_0_STAT_POS    0
+
+#define DMA_CHANNEL_1_STAT_RST    0x0
+#define DMA_CHANNEL_0_STAT_RST    0x0
+
+__INLINE void dma_isr_stat_unpack(uint8_t* channel1stat, uint8_t* channel0stat)
+{
+    uint32_t localVal = REG_PL_RD(DMA_ISR_STAT_ADDR);
+
+    *channel1stat = (localVal & ((uint32_t)0x00000002)) >> 1;
+    *channel0stat = (localVal & ((uint32_t)0x00000001)) >> 0;
+}
+
+__INLINE uint8_t dma_isr_stat_channel_1_stat_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(DMA_ISR_STAT_ADDR);
+    return ((localVal & ((uint32_t)0x00000002)) >> 1);
+}
+
+__INLINE uint8_t dma_isr_stat_channel_0_stat_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(DMA_ISR_STAT_ADDR);
+    return ((localVal & ((uint32_t)0x00000001)) >> 0);
+}
+
+/**
+ * @brief ISR_EN register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     01         CHANNEL_1_EN   0
+ *     00         CHANNEL_0_EN   0
+ * </pre>
+ */
+#define DMA_ISR_EN_ADDR   0x1000B008
+#define DMA_ISR_EN_OFFSET 0x00000008
+#define DMA_ISR_EN_INDEX  0x00000002
+#define DMA_ISR_EN_RESET  0x00000000
+
+__INLINE uint32_t dma_isr_en_get(void)
+{
+    return REG_PL_RD(DMA_ISR_EN_ADDR);
+}
+
+__INLINE void dma_isr_en_set(uint32_t value)
+{
+    REG_PL_WR(DMA_ISR_EN_ADDR, value);
+}
+
+// field definitions
+#define DMA_CHANNEL_1_EN_BIT    ((uint32_t)0x00000002)
+#define DMA_CHANNEL_1_EN_POS    1
+#define DMA_CHANNEL_0_EN_BIT    ((uint32_t)0x00000001)
+#define DMA_CHANNEL_0_EN_POS    0
+
+#define DMA_CHANNEL_1_EN_RST    0x0
+#define DMA_CHANNEL_0_EN_RST    0x0
+
+__INLINE void dma_isr_en_pack(uint8_t channel1en, uint8_t channel0en)
+{
+    ASSERT_ERR((((uint32_t)channel1en << 1) & ~((uint32_t)0x00000002)) == 0);
+    ASSERT_ERR((((uint32_t)channel0en << 0) & ~((uint32_t)0x00000001)) == 0);
+    REG_PL_WR(DMA_ISR_EN_ADDR,  ((uint32_t)channel1en << 1) | ((uint32_t)channel0en << 0));
+}
+
+__INLINE void dma_isr_en_unpack(uint8_t* channel1en, uint8_t* channel0en)
+{
+    uint32_t localVal = REG_PL_RD(DMA_ISR_EN_ADDR);
+
+    *channel1en = (localVal & ((uint32_t)0x00000002)) >> 1;
+    *channel0en = (localVal & ((uint32_t)0x00000001)) >> 0;
+}
+
+__INLINE uint8_t dma_isr_en_channel_1_en_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(DMA_ISR_EN_ADDR);
+    return ((localVal & ((uint32_t)0x00000002)) >> 1);
+}
+
+__INLINE void dma_isr_en_channel_1_en_setf(uint8_t channel1en)
+{
+    ASSERT_ERR((((uint32_t)channel1en << 1) & ~((uint32_t)0x00000002)) == 0);
+    REG_PL_WR(DMA_ISR_EN_ADDR, (REG_PL_RD(DMA_ISR_EN_ADDR) & ~((uint32_t)0x00000002)) | ((uint32_t)channel1en << 1));
+}
+
+__INLINE uint8_t dma_isr_en_channel_0_en_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(DMA_ISR_EN_ADDR);
+    return ((localVal & ((uint32_t)0x00000001)) >> 0);
+}
+
+__INLINE void dma_isr_en_channel_0_en_setf(uint8_t channel0en)
+{
+    ASSERT_ERR((((uint32_t)channel0en << 0) & ~((uint32_t)0x00000001)) == 0);
+    REG_PL_WR(DMA_ISR_EN_ADDR, (REG_PL_RD(DMA_ISR_EN_ADDR) & ~((uint32_t)0x00000001)) | ((uint32_t)channel0en << 0));
+}
+
+/**
+ * @brief ISR_CLR register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     01        CHANNEL_1_CLR   0
+ *     00        CHANNEL_0_CLR   0
+ * </pre>
+ */
+#define DMA_ISR_CLR_ADDR   0x1000B00C
+#define DMA_ISR_CLR_OFFSET 0x0000000C
+#define DMA_ISR_CLR_INDEX  0x00000003
+#define DMA_ISR_CLR_RESET  0x00000000
+
+__INLINE void dma_isr_clr_set(uint32_t value)
+{
+    REG_PL_WR(DMA_ISR_CLR_ADDR, value);
+}
+
+// field definitions
+#define DMA_CHANNEL_1_CLR_BIT    ((uint32_t)0x00000002)
+#define DMA_CHANNEL_1_CLR_POS    1
+#define DMA_CHANNEL_0_CLR_BIT    ((uint32_t)0x00000001)
+#define DMA_CHANNEL_0_CLR_POS    0
+
+#define DMA_CHANNEL_1_CLR_RST    0x0
+#define DMA_CHANNEL_0_CLR_RST    0x0
+
+__INLINE void dma_isr_clr_pack(uint8_t channel1clr, uint8_t channel0clr)
+{
+    ASSERT_ERR((((uint32_t)channel1clr << 1) & ~((uint32_t)0x00000002)) == 0);
+    ASSERT_ERR((((uint32_t)channel0clr << 0) & ~((uint32_t)0x00000001)) == 0);
+    REG_PL_WR(DMA_ISR_CLR_ADDR,  ((uint32_t)channel1clr << 1) | ((uint32_t)channel0clr << 0));
+}
+
+__INLINE void dma_isr_clr_channel_1_clr_setf(uint8_t channel1clr)
+{
+    ASSERT_ERR((((uint32_t)channel1clr << 1) & ~((uint32_t)0x00000002)) == 0);
+    REG_PL_WR(DMA_ISR_CLR_ADDR, (REG_PL_RD(DMA_ISR_CLR_ADDR) & ~((uint32_t)0x00000002)) | ((uint32_t)channel1clr << 1));
+}
+
+__INLINE void dma_isr_clr_channel_0_clr_setf(uint8_t channel0clr)
+{
+    ASSERT_ERR((((uint32_t)channel0clr << 0) & ~((uint32_t)0x00000001)) == 0);
+    REG_PL_WR(DMA_ISR_CLR_ADDR, (REG_PL_RD(DMA_ISR_CLR_ADDR) & ~((uint32_t)0x00000001)) | ((uint32_t)channel0clr << 0));
+}
+
+/**
+ * @brief SAR_0 register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00                SAR_0   0x0
+ * </pre>
+ */
+#define DMA_SAR_0_ADDR   0x1000B010
+#define DMA_SAR_0_OFFSET 0x00000010
+#define DMA_SAR_0_INDEX  0x00000004
+#define DMA_SAR_0_RESET  0x00000000
+
+__INLINE uint32_t dma_sar_0_get(void)
+{
+    return REG_PL_RD(DMA_SAR_0_ADDR);
+}
+
+__INLINE void dma_sar_0_set(uint32_t value)
+{
+    REG_PL_WR(DMA_SAR_0_ADDR, value);
+}
+
+// field definitions
+#define DMA_SAR_0_MASK   ((uint32_t)0xFFFFFFFF)
+#define DMA_SAR_0_LSB    0
+#define DMA_SAR_0_WIDTH  ((uint32_t)0x00000020)
+
+#define DMA_SAR_0_RST    0x0
+
+__INLINE uint32_t dma_sar_0_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(DMA_SAR_0_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+/**
+ * @brief DAR_0 register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00                DAR_0   0x0
+ * </pre>
+ */
+#define DMA_DAR_0_ADDR   0x1000B014
+#define DMA_DAR_0_OFFSET 0x00000014
+#define DMA_DAR_0_INDEX  0x00000005
+#define DMA_DAR_0_RESET  0x00000000
+
+__INLINE void dma_dar_0_set(uint32_t value)
+{
+    REG_PL_WR(DMA_DAR_0_ADDR, value);
+}
+
+// field definitions
+#define DMA_DAR_0_MASK   ((uint32_t)0xFFFFFFFF)
+#define DMA_DAR_0_LSB    0
+#define DMA_DAR_0_WIDTH  ((uint32_t)0x00000020)
+
+#define DMA_DAR_0_RST    0x0
+
+__INLINE void dma_dar_0_setf(uint32_t dar0)
+{
+    ASSERT_ERR((((uint32_t)dar0 << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
+    REG_PL_WR(DMA_DAR_0_ADDR, (uint32_t)dar0 << 0);
+}
+
+/**
+ * @brief CCFG_0 register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     31              START_0   0
+ *  12:00               SIZE_0   0x0
+ * </pre>
+ */
+#define DMA_CCFG_0_ADDR   0x1000B018
+#define DMA_CCFG_0_OFFSET 0x00000018
+#define DMA_CCFG_0_INDEX  0x00000006
+#define DMA_CCFG_0_RESET  0x00000000
+
+__INLINE uint32_t dma_ccfg_0_get(void)
+{
+    return REG_PL_RD(DMA_CCFG_0_ADDR);
+}
+
+__INLINE void dma_ccfg_0_set(uint32_t value)
+{
+    REG_PL_WR(DMA_CCFG_0_ADDR, value);
+}
+
+// field definitions
+#define DMA_START_0_BIT    ((uint32_t)0x80000000)
+#define DMA_START_0_POS    31
+#define DMA_SIZE_0_MASK    ((uint32_t)0x00001FFF)
+#define DMA_SIZE_0_LSB     0
+#define DMA_SIZE_0_WIDTH   ((uint32_t)0x0000000D)
+
+#define DMA_START_0_RST    0x0
+#define DMA_SIZE_0_RST     0x0
+
+__INLINE void dma_ccfg_0_pack(uint8_t start0, uint16_t size0)
+{
+    ASSERT_ERR((((uint32_t)start0 << 31) & ~((uint32_t)0x80000000)) == 0);
+    ASSERT_ERR((((uint32_t)size0 << 0) & ~((uint32_t)0x00001FFF)) == 0);
+    REG_PL_WR(DMA_CCFG_0_ADDR,  ((uint32_t)start0 << 31) | ((uint32_t)size0 << 0));
+}
+
+__INLINE void dma_ccfg_0_unpack(uint8_t* start0, uint16_t* size0)
+{
+    uint32_t localVal = REG_PL_RD(DMA_CCFG_0_ADDR);
+
+    *start0 = (localVal & ((uint32_t)0x80000000)) >> 31;
+    *size0 = (localVal & ((uint32_t)0x00001FFF)) >> 0;
+}
+
+__INLINE void dma_ccfg_0_start_0_setf(uint8_t start0)
+{
+    ASSERT_ERR((((uint32_t)start0 << 31) & ~((uint32_t)0x80000000)) == 0);
+    REG_PL_WR(DMA_CCFG_0_ADDR, (REG_PL_RD(DMA_CCFG_0_ADDR) & ~((uint32_t)0x80000000)) | ((uint32_t)start0 << 31));
+}
+
+__INLINE uint16_t dma_ccfg_0_size_0_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(DMA_CCFG_0_ADDR);
+    return ((localVal & ((uint32_t)0x00001FFF)) >> 0);
+}
+
+__INLINE void dma_ccfg_0_size_0_setf(uint16_t size0)
+{
+    ASSERT_ERR((((uint32_t)size0 << 0) & ~((uint32_t)0x00001FFF)) == 0);
+    REG_PL_WR(DMA_CCFG_0_ADDR, (REG_PL_RD(DMA_CCFG_0_ADDR) & ~((uint32_t)0x00001FFF)) | ((uint32_t)size0 << 0));
+}
+
+/**
+ * @brief SAR_1 register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00                SAR_1   0x0
+ * </pre>
+ */
+#define DMA_SAR_1_ADDR   0x1000B020
+#define DMA_SAR_1_OFFSET 0x00000020
+#define DMA_SAR_1_INDEX  0x00000008
+#define DMA_SAR_1_RESET  0x00000000
+
+__INLINE uint32_t dma_sar_1_get(void)
+{
+    return REG_PL_RD(DMA_SAR_1_ADDR);
+}
+
+__INLINE void dma_sar_1_set(uint32_t value)
+{
+    REG_PL_WR(DMA_SAR_1_ADDR, value);
+}
+
+// field definitions
+#define DMA_SAR_1_MASK   ((uint32_t)0xFFFFFFFF)
+#define DMA_SAR_1_LSB    0
+#define DMA_SAR_1_WIDTH  ((uint32_t)0x00000020)
+
+#define DMA_SAR_1_RST    0x0
+
+__INLINE uint32_t dma_sar_1_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(DMA_SAR_1_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+/**
+ * @brief DAR_1 register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00                DAR_1   0x0
+ * </pre>
+ */
+#define DMA_DAR_1_ADDR   0x1000B024
+#define DMA_DAR_1_OFFSET 0x00000024
+#define DMA_DAR_1_INDEX  0x00000009
+#define DMA_DAR_1_RESET  0x00000000
+
+__INLINE void dma_dar_1_set(uint32_t value)
+{
+    REG_PL_WR(DMA_DAR_1_ADDR, value);
+}
+
+// field definitions
+#define DMA_DAR_1_MASK   ((uint32_t)0xFFFFFFFF)
+#define DMA_DAR_1_LSB    0
+#define DMA_DAR_1_WIDTH  ((uint32_t)0x00000020)
+
+#define DMA_DAR_1_RST    0x0
+
+__INLINE void dma_dar_1_setf(uint32_t dar1)
+{
+    ASSERT_ERR((((uint32_t)dar1 << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
+    REG_PL_WR(DMA_DAR_1_ADDR, (uint32_t)dar1 << 0);
+}
+
+/**
+ * @brief CCFG_1 register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     31              START_1   0
+ *  12:00               SIZE_1   0x0
+ * </pre>
+ */
+#define DMA_CCFG_1_ADDR   0x1000B028
+#define DMA_CCFG_1_OFFSET 0x00000028
+#define DMA_CCFG_1_INDEX  0x0000000A
+#define DMA_CCFG_1_RESET  0x00000000
+
+__INLINE uint32_t dma_ccfg_1_get(void)
+{
+    return REG_PL_RD(DMA_CCFG_1_ADDR);
+}
+
+__INLINE void dma_ccfg_1_set(uint32_t value)
+{
+    REG_PL_WR(DMA_CCFG_1_ADDR, value);
+}
+
+// field definitions
+#define DMA_START_1_BIT    ((uint32_t)0x80000000)
+#define DMA_START_1_POS    31
+#define DMA_SIZE_1_MASK    ((uint32_t)0x00001FFF)
+#define DMA_SIZE_1_LSB     0
+#define DMA_SIZE_1_WIDTH   ((uint32_t)0x0000000D)
+
+#define DMA_START_1_RST    0x0
+#define DMA_SIZE_1_RST     0x0
+
+__INLINE void dma_ccfg_1_pack(uint8_t start1, uint16_t size1)
+{
+    ASSERT_ERR((((uint32_t)start1 << 31) & ~((uint32_t)0x80000000)) == 0);
+    ASSERT_ERR((((uint32_t)size1 << 0) & ~((uint32_t)0x00001FFF)) == 0);
+    REG_PL_WR(DMA_CCFG_1_ADDR,  ((uint32_t)start1 << 31) | ((uint32_t)size1 << 0));
+}
+
+__INLINE void dma_ccfg_1_unpack(uint8_t* start1, uint16_t* size1)
+{
+    uint32_t localVal = REG_PL_RD(DMA_CCFG_1_ADDR);
+
+    *start1 = (localVal & ((uint32_t)0x80000000)) >> 31;
+    *size1 = (localVal & ((uint32_t)0x00001FFF)) >> 0;
+}
+
+__INLINE void dma_ccfg_1_start_1_setf(uint8_t start1)
+{
+    ASSERT_ERR((((uint32_t)start1 << 31) & ~((uint32_t)0x80000000)) == 0);
+    REG_PL_WR(DMA_CCFG_1_ADDR, (REG_PL_RD(DMA_CCFG_1_ADDR) & ~((uint32_t)0x80000000)) | ((uint32_t)start1 << 31));
+}
+
+__INLINE uint16_t dma_ccfg_1_size_1_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(DMA_CCFG_1_ADDR);
+    return ((localVal & ((uint32_t)0x00001FFF)) >> 0);
+}
+
+__INLINE void dma_ccfg_1_size_1_setf(uint16_t size1)
+{
+    ASSERT_ERR((((uint32_t)size1 << 0) & ~((uint32_t)0x00001FFF)) == 0);
+    REG_PL_WR(DMA_CCFG_1_ADDR, (REG_PL_RD(DMA_CCFG_1_ADDR) & ~((uint32_t)0x00001FFF)) | ((uint32_t)size1 << 0));
+}
+
+
+#endif // _REG_DMA_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/reg_dma_channel.h

@@ -0,0 +1,151 @@
+#ifndef _REG_DMA_CHANNEL_H_
+#define _REG_DMA_CHANNEL_H_
+
+#include <stdint.h>
+#include "_reg_dma_channel.h"
+#include "compiler.h"
+#include "arch.h"
+#include "reg_access.h"
+
+#define REG_DMA_CHANNEL_COUNT 8
+
+#define REG_DMA_CHANNEL_DECODING_MASK 0x0000001F
+
+/**
+ * @brief SAR register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00                  SAR   0x0
+ * </pre>
+ */
+#define DMA_SAR_ADDR   0x1000B010
+#define DMA_SAR_OFFSET 0x00000010
+#define DMA_SAR_INDEX  0x00000004
+#define DMA_SAR_RESET  0x00000000
+
+__INLINE uint32_t dma_sar_get(int elt_idx)
+{
+    return REG_PL_RD(DMA_SAR_ADDR + elt_idx * REG_DMA_CHANNEL_SIZE);
+}
+
+__INLINE void dma_sar_set(int elt_idx, uint32_t value)
+{
+    REG_PL_WR(DMA_SAR_ADDR + elt_idx * REG_DMA_CHANNEL_SIZE, value);
+}
+
+// field definitions
+#define DMA_SAR_MASK   ((uint32_t)0xFFFFFFFF)
+#define DMA_SAR_LSB    0
+#define DMA_SAR_WIDTH  ((uint32_t)0x00000020)
+
+#define DMA_SAR_RST    0x0
+
+__INLINE uint32_t dma_sar_getf(int elt_idx)
+{
+    uint32_t localVal = REG_PL_RD(DMA_SAR_ADDR + elt_idx * REG_DMA_CHANNEL_SIZE);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+/**
+ * @brief DAR register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00                  DAR   0x0
+ * </pre>
+ */
+#define DMA_DAR_ADDR   0x1000B014
+#define DMA_DAR_OFFSET 0x00000014
+#define DMA_DAR_INDEX  0x00000005
+#define DMA_DAR_RESET  0x00000000
+
+__INLINE void dma_dar_set(int elt_idx, uint32_t value)
+{
+    REG_PL_WR(DMA_DAR_ADDR + elt_idx * REG_DMA_CHANNEL_SIZE, value);
+}
+
+// field definitions
+#define DMA_DAR_MASK   ((uint32_t)0xFFFFFFFF)
+#define DMA_DAR_LSB    0
+#define DMA_DAR_WIDTH  ((uint32_t)0x00000020)
+
+#define DMA_DAR_RST    0x0
+
+__INLINE void dma_dar_setf(int elt_idx, uint32_t dar)
+{
+    ASSERT_ERR((((uint32_t)dar << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
+    REG_PL_WR(DMA_DAR_ADDR + elt_idx * REG_DMA_CHANNEL_SIZE, (uint32_t)dar << 0);
+}
+
+/**
+ * @brief CCFG register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     31                START   0
+ *  12:00                 SIZE   0x0
+ * </pre>
+ */
+#define DMA_CCFG_ADDR   0x1000B018
+#define DMA_CCFG_OFFSET 0x00000018
+#define DMA_CCFG_INDEX  0x00000006
+#define DMA_CCFG_RESET  0x00000000
+
+__INLINE uint32_t dma_ccfg_get(int elt_idx)
+{
+    return REG_PL_RD(DMA_CCFG_ADDR + elt_idx * REG_DMA_CHANNEL_SIZE);
+}
+
+__INLINE void dma_ccfg_set(int elt_idx, uint32_t value)
+{
+    REG_PL_WR(DMA_CCFG_ADDR + elt_idx * REG_DMA_CHANNEL_SIZE, value);
+}
+
+// field definitions
+#define DMA_START_BIT    ((uint32_t)0x80000000)
+#define DMA_START_POS    31
+#define DMA_SIZE_MASK    ((uint32_t)0x00001FFF)
+#define DMA_SIZE_LSB     0
+#define DMA_SIZE_WIDTH   ((uint32_t)0x0000000D)
+
+#define DMA_START_RST    0x0
+#define DMA_SIZE_RST     0x0
+
+__INLINE void dma_ccfg_pack(int elt_idx, uint8_t start, uint16_t size)
+{
+    ASSERT_ERR((((uint32_t)start << 31) & ~((uint32_t)0x80000000)) == 0);
+    ASSERT_ERR((((uint32_t)size << 0) & ~((uint32_t)0x00001FFF)) == 0);
+    REG_PL_WR(DMA_CCFG_ADDR + elt_idx * REG_DMA_CHANNEL_SIZE,  ((uint32_t)start << 31) | ((uint32_t)size << 0));
+}
+
+__INLINE void dma_ccfg_unpack(int elt_idx, uint8_t* start, uint16_t* size)
+{
+    uint32_t localVal = REG_PL_RD(DMA_CCFG_ADDR + elt_idx * REG_DMA_CHANNEL_SIZE);
+
+    *start = (localVal & ((uint32_t)0x80000000)) >> 31;
+    *size = (localVal & ((uint32_t)0x00001FFF)) >> 0;
+}
+
+__INLINE void dma_ccfg_start_setf(int elt_idx, uint8_t start)
+{
+    ASSERT_ERR((((uint32_t)start << 31) & ~((uint32_t)0x80000000)) == 0);
+    REG_PL_WR(DMA_CCFG_ADDR + elt_idx * REG_DMA_CHANNEL_SIZE, (REG_PL_RD(DMA_CCFG_ADDR + elt_idx * REG_DMA_CHANNEL_SIZE) & ~((uint32_t)0x80000000)) | ((uint32_t)start << 31));
+}
+
+__INLINE uint16_t dma_ccfg_size_getf(int elt_idx)
+{
+    uint32_t localVal = REG_PL_RD(DMA_CCFG_ADDR + elt_idx * REG_DMA_CHANNEL_SIZE);
+    return ((localVal & ((uint32_t)0x00001FFF)) >> 0);
+}
+
+__INLINE void dma_ccfg_size_setf(int elt_idx, uint16_t size)
+{
+    ASSERT_ERR((((uint32_t)size << 0) & ~((uint32_t)0x00001FFF)) == 0);
+    REG_PL_WR(DMA_CCFG_ADDR + elt_idx * REG_DMA_CHANNEL_SIZE, (REG_PL_RD(DMA_CCFG_ADDR + elt_idx * REG_DMA_CHANNEL_SIZE) & ~((uint32_t)0x00001FFF)) | ((uint32_t)size << 0));
+}
+
+
+#endif // _REG_DMA_CHANNEL_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/reg_ecc_accel.h

@@ -0,0 +1,223 @@
+#ifndef _REG_ECC_ACCEL_H_
+#define _REG_ECC_ACCEL_H_
+
+#include <stdint.h>
+#include "_reg_ecc_accel.h"
+#include "compiler.h"
+#include "arch.h"
+#include "reg_access.h"
+
+#define REG_ECC_ACCEL_COUNT 5
+
+#define REG_ECC_ACCEL_DECODING_MASK 0x0000001F
+
+/**
+ * @brief CTRL register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     00                Start   0
+ * </pre>
+ */
+#define ECC_CTRL_ADDR   0x1000F000
+#define ECC_CTRL_OFFSET 0x00000000
+#define ECC_CTRL_INDEX  0x00000000
+#define ECC_CTRL_RESET  0x00000000
+
+__INLINE uint32_t ecc_ctrl_get(void)
+{
+    return REG_PL_RD(ECC_CTRL_ADDR);
+}
+
+__INLINE void ecc_ctrl_set(uint32_t value)
+{
+    REG_PL_WR(ECC_CTRL_ADDR, value);
+}
+
+// field definitions
+#define ECC_START_BIT    ((uint32_t)0x00000001)
+#define ECC_START_POS    0
+
+#define ECC_START_RST    0x0
+
+__INLINE void ecc_start_setf(uint8_t start)
+{
+    ASSERT_ERR((((uint32_t)start << 0) & ~((uint32_t)0x00000001)) == 0);
+    REG_PL_WR(ECC_CTRL_ADDR, (uint32_t)start << 0);
+}
+
+/**
+ * @brief PRIV_PTR register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00             priv_ptr   0x0
+ * </pre>
+ */
+#define ECC_PRIV_PTR_ADDR   0x1000F004
+#define ECC_PRIV_PTR_OFFSET 0x00000004
+#define ECC_PRIV_PTR_INDEX  0x00000001
+#define ECC_PRIV_PTR_RESET  0x00000000
+
+__INLINE uint32_t ecc_priv_ptr_get(void)
+{
+    return REG_PL_RD(ECC_PRIV_PTR_ADDR);
+}
+
+__INLINE void ecc_priv_ptr_set(uint32_t value)
+{
+    REG_PL_WR(ECC_PRIV_PTR_ADDR, value);
+}
+
+// field definitions
+#define ECC_PRIV_PTR_MASK   ((uint32_t)0xFFFFFFFF)
+#define ECC_PRIV_PTR_LSB    0
+#define ECC_PRIV_PTR_WIDTH  ((uint32_t)0x00000020)
+
+#define ECC_PRIV_PTR_RST    0x0
+
+__INLINE uint32_t ecc_priv_ptr_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(ECC_PRIV_PTR_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void ecc_priv_ptr_setf(uint32_t privptr)
+{
+    ASSERT_ERR((((uint32_t)privptr << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
+    REG_PL_WR(ECC_PRIV_PTR_ADDR, (uint32_t)privptr << 0);
+}
+
+/**
+ * @brief PUB_X_PTR register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00            pub_x_ptr   0x0
+ * </pre>
+ */
+#define ECC_PUB_X_PTR_ADDR   0x1000F008
+#define ECC_PUB_X_PTR_OFFSET 0x00000008
+#define ECC_PUB_X_PTR_INDEX  0x00000002
+#define ECC_PUB_X_PTR_RESET  0x00000000
+
+__INLINE uint32_t ecc_pub_x_ptr_get(void)
+{
+    return REG_PL_RD(ECC_PUB_X_PTR_ADDR);
+}
+
+__INLINE void ecc_pub_x_ptr_set(uint32_t value)
+{
+    REG_PL_WR(ECC_PUB_X_PTR_ADDR, value);
+}
+
+// field definitions
+#define ECC_PUB_X_PTR_MASK   ((uint32_t)0xFFFFFFFF)
+#define ECC_PUB_X_PTR_LSB    0
+#define ECC_PUB_X_PTR_WIDTH  ((uint32_t)0x00000020)
+
+#define ECC_PUB_X_PTR_RST    0x0
+
+__INLINE uint32_t ecc_pub_x_ptr_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(ECC_PUB_X_PTR_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void ecc_pub_x_ptr_setf(uint32_t pubxptr)
+{
+    ASSERT_ERR((((uint32_t)pubxptr << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
+    REG_PL_WR(ECC_PUB_X_PTR_ADDR, (uint32_t)pubxptr << 0);
+}
+
+/**
+ * @brief PUB_Y_PTR register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00            pub_y_ptr   0x0
+ * </pre>
+ */
+#define ECC_PUB_Y_PTR_ADDR   0x1000F00C
+#define ECC_PUB_Y_PTR_OFFSET 0x0000000C
+#define ECC_PUB_Y_PTR_INDEX  0x00000003
+#define ECC_PUB_Y_PTR_RESET  0x00000000
+
+__INLINE uint32_t ecc_pub_y_ptr_get(void)
+{
+    return REG_PL_RD(ECC_PUB_Y_PTR_ADDR);
+}
+
+__INLINE void ecc_pub_y_ptr_set(uint32_t value)
+{
+    REG_PL_WR(ECC_PUB_Y_PTR_ADDR, value);
+}
+
+// field definitions
+#define ECC_PUB_Y_PTR_MASK   ((uint32_t)0xFFFFFFFF)
+#define ECC_PUB_Y_PTR_LSB    0
+#define ECC_PUB_Y_PTR_WIDTH  ((uint32_t)0x00000020)
+
+#define ECC_PUB_Y_PTR_RST    0x0
+
+__INLINE uint32_t ecc_pub_y_ptr_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(ECC_PUB_Y_PTR_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void ecc_pub_y_ptr_setf(uint32_t pubyptr)
+{
+    ASSERT_ERR((((uint32_t)pubyptr << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
+    REG_PL_WR(ECC_PUB_Y_PTR_ADDR, (uint32_t)pubyptr << 0);
+}
+
+/**
+ * @brief RESULT register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00               RESULT   0x0
+ * </pre>
+ */
+#define ECC_RESULT_ADDR   0x1000F010
+#define ECC_RESULT_OFFSET 0x00000010
+#define ECC_RESULT_INDEX  0x00000004
+#define ECC_RESULT_RESET  0x00000000
+
+__INLINE uint32_t ecc_result_get(void)
+{
+    return REG_PL_RD(ECC_RESULT_ADDR);
+}
+
+__INLINE void ecc_result_set(uint32_t value)
+{
+    REG_PL_WR(ECC_RESULT_ADDR, value);
+}
+
+// field definitions
+#define ECC_RESULT_MASK   ((uint32_t)0xFFFFFFFF)
+#define ECC_RESULT_LSB    0
+#define ECC_RESULT_WIDTH  ((uint32_t)0x00000020)
+
+#define ECC_RESULT_RST    0x0
+
+__INLINE uint32_t ecc_result_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(ECC_RESULT_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void ecc_result_setf(uint32_t result)
+{
+    ASSERT_ERR((((uint32_t)result << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
+    REG_PL_WR(ECC_RESULT_ADDR, (uint32_t)result << 0);
+}
+
+
+#endif // _REG_ECC_ACCEL_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/reg_em_ble_ral.h

@@ -0,0 +1,547 @@
+#ifndef _REG_EM_BLE_RAL_H_
+#define _REG_EM_BLE_RAL_H_
+
+#include <stdint.h>
+#include "_reg_em_ble_ral.h"
+#include "compiler.h"
+#include "arch.h"
+#include "em_map.h"
+#include "reg_access.h"
+
+#define REG_EM_BLE_RAL_COUNT 28
+
+#define REG_EM_BLE_RAL_DECODING_MASK 0x0000003F
+
+#define REG_EM_BLE_RAL_ADDR_GET(idx) (EM_BLE_RAL_OFFSET + (idx) * REG_EM_BLE_RAL_SIZE)
+
+/**
+ * @brief RAL_INFO register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     15          ENTRY_VALID   0
+ *     14            CONNECTED   0
+ *     13            IN_WHLIST   0
+ *     12       IN_PERADV_LIST   0
+ *     11                  PEF   0
+ *     07      LOCAL_RPA_VALID   0
+ *     06      LOCAL_RPA_RENEW   0
+ *     05      LOCAL_IRK_VALID   0
+ *     03       PEER_RPA_VALID   0
+ *     02       PEER_RPA_RENEW   0
+ *     01       PEER_IRK_VALID   0
+ *     00         PEER_ID_TYPE   0
+ * </pre>
+ */
+#define EM_BLE_RAL_INFO_ADDR   (0x53004000 + EM_BLE_RAL_OFFSET)
+#define EM_BLE_RAL_INFO_INDEX  0x00000000
+#define EM_BLE_RAL_INFO_RESET  0x00000000
+
+__INLINE uint16_t em_ble_ral_info_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE);
+}
+
+__INLINE void em_ble_ral_info_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_ENTRY_VALID_BIT        ((uint16_t)0x00008000)
+#define EM_BLE_ENTRY_VALID_POS        15
+#define EM_BLE_CONNECTED_BIT          ((uint16_t)0x00004000)
+#define EM_BLE_CONNECTED_POS          14
+#define EM_BLE_IN_WHLIST_BIT          ((uint16_t)0x00002000)
+#define EM_BLE_IN_WHLIST_POS          13
+#define EM_BLE_IN_PERADV_LIST_BIT     ((uint16_t)0x00001000)
+#define EM_BLE_IN_PERADV_LIST_POS     12
+#define EM_BLE_PEF_BIT                ((uint16_t)0x00000800)
+#define EM_BLE_PEF_POS                11
+#define EM_BLE_LOCAL_RPA_VALID_BIT    ((uint16_t)0x00000080)
+#define EM_BLE_LOCAL_RPA_VALID_POS    7
+#define EM_BLE_LOCAL_RPA_RENEW_BIT    ((uint16_t)0x00000040)
+#define EM_BLE_LOCAL_RPA_RENEW_POS    6
+#define EM_BLE_LOCAL_IRK_VALID_BIT    ((uint16_t)0x00000020)
+#define EM_BLE_LOCAL_IRK_VALID_POS    5
+#define EM_BLE_PEER_RPA_VALID_BIT     ((uint16_t)0x00000008)
+#define EM_BLE_PEER_RPA_VALID_POS     3
+#define EM_BLE_PEER_RPA_RENEW_BIT     ((uint16_t)0x00000004)
+#define EM_BLE_PEER_RPA_RENEW_POS     2
+#define EM_BLE_PEER_IRK_VALID_BIT     ((uint16_t)0x00000002)
+#define EM_BLE_PEER_IRK_VALID_POS     1
+#define EM_BLE_PEER_ID_TYPE_BIT       ((uint16_t)0x00000001)
+#define EM_BLE_PEER_ID_TYPE_POS       0
+
+#define EM_BLE_ENTRY_VALID_RST        0x0
+#define EM_BLE_CONNECTED_RST          0x0
+#define EM_BLE_IN_WHLIST_RST          0x0
+#define EM_BLE_IN_PERADV_LIST_RST     0x0
+#define EM_BLE_PEF_RST                0x0
+#define EM_BLE_LOCAL_RPA_VALID_RST    0x0
+#define EM_BLE_LOCAL_RPA_RENEW_RST    0x0
+#define EM_BLE_LOCAL_IRK_VALID_RST    0x0
+#define EM_BLE_PEER_RPA_VALID_RST     0x0
+#define EM_BLE_PEER_RPA_RENEW_RST     0x0
+#define EM_BLE_PEER_IRK_VALID_RST     0x0
+#define EM_BLE_PEER_ID_TYPE_RST       0x0
+
+__INLINE void em_ble_ral_info_pack(int elt_idx, uint8_t entryvalid, uint8_t connected, uint8_t inwhlist, uint8_t inperadvlist, uint8_t pef, uint8_t localrpavalid, uint8_t localrparenew, uint8_t localirkvalid, uint8_t peerrpavalid, uint8_t peerrparenew, uint8_t peerirkvalid, uint8_t peeridtype)
+{
+    ASSERT_ERR((((uint16_t)entryvalid << 15) & ~((uint16_t)0x00008000)) == 0);
+    ASSERT_ERR((((uint16_t)connected << 14) & ~((uint16_t)0x00004000)) == 0);
+    ASSERT_ERR((((uint16_t)inwhlist << 13) & ~((uint16_t)0x00002000)) == 0);
+    ASSERT_ERR((((uint16_t)inperadvlist << 12) & ~((uint16_t)0x00001000)) == 0);
+    ASSERT_ERR((((uint16_t)pef << 11) & ~((uint16_t)0x00000800)) == 0);
+    ASSERT_ERR((((uint16_t)localrpavalid << 7) & ~((uint16_t)0x00000080)) == 0);
+    ASSERT_ERR((((uint16_t)localrparenew << 6) & ~((uint16_t)0x00000040)) == 0);
+    ASSERT_ERR((((uint16_t)localirkvalid << 5) & ~((uint16_t)0x00000020)) == 0);
+    ASSERT_ERR((((uint16_t)peerrpavalid << 3) & ~((uint16_t)0x00000008)) == 0);
+    ASSERT_ERR((((uint16_t)peerrparenew << 2) & ~((uint16_t)0x00000004)) == 0);
+    ASSERT_ERR((((uint16_t)peerirkvalid << 1) & ~((uint16_t)0x00000002)) == 0);
+    ASSERT_ERR((((uint16_t)peeridtype << 0) & ~((uint16_t)0x00000001)) == 0);
+    EM_BLE_WR(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE,  ((uint16_t)entryvalid << 15) | ((uint16_t)connected << 14) | ((uint16_t)inwhlist << 13) | ((uint16_t)inperadvlist << 12) | ((uint16_t)pef << 11) | ((uint16_t)localrpavalid << 7) | ((uint16_t)localrparenew << 6) | ((uint16_t)localirkvalid << 5) | ((uint16_t)peerrpavalid << 3) | ((uint16_t)peerrparenew << 2) | ((uint16_t)peerirkvalid << 1) | ((uint16_t)peeridtype << 0));
+}
+
+__INLINE void em_ble_ral_info_unpack(int elt_idx, uint8_t* entryvalid, uint8_t* connected, uint8_t* inwhlist, uint8_t* inperadvlist, uint8_t* pef, uint8_t* localrpavalid, uint8_t* localrparenew, uint8_t* localirkvalid, uint8_t* peerrpavalid, uint8_t* peerrparenew, uint8_t* peerirkvalid, uint8_t* peeridtype)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE);
+
+    *entryvalid = (localVal & ((uint16_t)0x00008000)) >> 15;
+    *connected = (localVal & ((uint16_t)0x00004000)) >> 14;
+    *inwhlist = (localVal & ((uint16_t)0x00002000)) >> 13;
+    *inperadvlist = (localVal & ((uint16_t)0x00001000)) >> 12;
+    *pef = (localVal & ((uint16_t)0x00000800)) >> 11;
+    *localrpavalid = (localVal & ((uint16_t)0x00000080)) >> 7;
+    *localrparenew = (localVal & ((uint16_t)0x00000040)) >> 6;
+    *localirkvalid = (localVal & ((uint16_t)0x00000020)) >> 5;
+    *peerrpavalid = (localVal & ((uint16_t)0x00000008)) >> 3;
+    *peerrparenew = (localVal & ((uint16_t)0x00000004)) >> 2;
+    *peerirkvalid = (localVal & ((uint16_t)0x00000002)) >> 1;
+    *peeridtype = (localVal & ((uint16_t)0x00000001)) >> 0;
+}
+
+__INLINE uint8_t em_ble_ral_info_entry_valid_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE);
+    return ((localVal & ((uint16_t)0x00008000)) >> 15);
+}
+
+__INLINE void em_ble_ral_info_entry_valid_setf(int elt_idx, uint8_t entryvalid)
+{
+    ASSERT_ERR((((uint16_t)entryvalid << 15) & ~((uint16_t)0x00008000)) == 0);
+    EM_BLE_WR(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE, (EM_BLE_RD(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE) & ~((uint16_t)0x00008000)) | ((uint16_t)entryvalid << 15));
+}
+
+__INLINE uint8_t em_ble_ral_info_connected_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE);
+    return ((localVal & ((uint16_t)0x00004000)) >> 14);
+}
+
+__INLINE void em_ble_ral_info_connected_setf(int elt_idx, uint8_t connected)
+{
+    ASSERT_ERR((((uint16_t)connected << 14) & ~((uint16_t)0x00004000)) == 0);
+    EM_BLE_WR(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE, (EM_BLE_RD(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE) & ~((uint16_t)0x00004000)) | ((uint16_t)connected << 14));
+}
+
+__INLINE uint8_t em_ble_ral_info_in_whlist_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE);
+    return ((localVal & ((uint16_t)0x00002000)) >> 13);
+}
+
+__INLINE void em_ble_ral_info_in_whlist_setf(int elt_idx, uint8_t inwhlist)
+{
+    ASSERT_ERR((((uint16_t)inwhlist << 13) & ~((uint16_t)0x00002000)) == 0);
+    EM_BLE_WR(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE, (EM_BLE_RD(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE) & ~((uint16_t)0x00002000)) | ((uint16_t)inwhlist << 13));
+}
+
+__INLINE uint8_t em_ble_ral_info_in_peradv_list_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE);
+    return ((localVal & ((uint16_t)0x00001000)) >> 12);
+}
+
+__INLINE void em_ble_ral_info_in_peradv_list_setf(int elt_idx, uint8_t inperadvlist)
+{
+    ASSERT_ERR((((uint16_t)inperadvlist << 12) & ~((uint16_t)0x00001000)) == 0);
+    EM_BLE_WR(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE, (EM_BLE_RD(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE) & ~((uint16_t)0x00001000)) | ((uint16_t)inperadvlist << 12));
+}
+
+__INLINE uint8_t em_ble_ral_info_pef_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE);
+    return ((localVal & ((uint16_t)0x00000800)) >> 11);
+}
+
+__INLINE void em_ble_ral_info_pef_setf(int elt_idx, uint8_t pef)
+{
+    ASSERT_ERR((((uint16_t)pef << 11) & ~((uint16_t)0x00000800)) == 0);
+    EM_BLE_WR(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE, (EM_BLE_RD(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE) & ~((uint16_t)0x00000800)) | ((uint16_t)pef << 11));
+}
+
+__INLINE uint8_t em_ble_ral_info_local_rpa_valid_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE);
+    return ((localVal & ((uint16_t)0x00000080)) >> 7);
+}
+
+__INLINE void em_ble_ral_info_local_rpa_valid_setf(int elt_idx, uint8_t localrpavalid)
+{
+    ASSERT_ERR((((uint16_t)localrpavalid << 7) & ~((uint16_t)0x00000080)) == 0);
+    EM_BLE_WR(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE, (EM_BLE_RD(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE) & ~((uint16_t)0x00000080)) | ((uint16_t)localrpavalid << 7));
+}
+
+__INLINE uint8_t em_ble_ral_info_local_rpa_renew_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE);
+    return ((localVal & ((uint16_t)0x00000040)) >> 6);
+}
+
+__INLINE void em_ble_ral_info_local_rpa_renew_setf(int elt_idx, uint8_t localrparenew)
+{
+    ASSERT_ERR((((uint16_t)localrparenew << 6) & ~((uint16_t)0x00000040)) == 0);
+    EM_BLE_WR(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE, (EM_BLE_RD(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE) & ~((uint16_t)0x00000040)) | ((uint16_t)localrparenew << 6));
+}
+
+__INLINE uint8_t em_ble_ral_info_local_irk_valid_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE);
+    return ((localVal & ((uint16_t)0x00000020)) >> 5);
+}
+
+__INLINE void em_ble_ral_info_local_irk_valid_setf(int elt_idx, uint8_t localirkvalid)
+{
+    ASSERT_ERR((((uint16_t)localirkvalid << 5) & ~((uint16_t)0x00000020)) == 0);
+    EM_BLE_WR(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE, (EM_BLE_RD(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE) & ~((uint16_t)0x00000020)) | ((uint16_t)localirkvalid << 5));
+}
+
+__INLINE uint8_t em_ble_ral_info_peer_rpa_valid_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE);
+    return ((localVal & ((uint16_t)0x00000008)) >> 3);
+}
+
+__INLINE void em_ble_ral_info_peer_rpa_valid_setf(int elt_idx, uint8_t peerrpavalid)
+{
+    ASSERT_ERR((((uint16_t)peerrpavalid << 3) & ~((uint16_t)0x00000008)) == 0);
+    EM_BLE_WR(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE, (EM_BLE_RD(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE) & ~((uint16_t)0x00000008)) | ((uint16_t)peerrpavalid << 3));
+}
+
+__INLINE uint8_t em_ble_ral_info_peer_rpa_renew_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE);
+    return ((localVal & ((uint16_t)0x00000004)) >> 2);
+}
+
+__INLINE void em_ble_ral_info_peer_rpa_renew_setf(int elt_idx, uint8_t peerrparenew)
+{
+    ASSERT_ERR((((uint16_t)peerrparenew << 2) & ~((uint16_t)0x00000004)) == 0);
+    EM_BLE_WR(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE, (EM_BLE_RD(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE) & ~((uint16_t)0x00000004)) | ((uint16_t)peerrparenew << 2));
+}
+
+__INLINE uint8_t em_ble_ral_info_peer_irk_valid_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE);
+    return ((localVal & ((uint16_t)0x00000002)) >> 1);
+}
+
+__INLINE void em_ble_ral_info_peer_irk_valid_setf(int elt_idx, uint8_t peerirkvalid)
+{
+    ASSERT_ERR((((uint16_t)peerirkvalid << 1) & ~((uint16_t)0x00000002)) == 0);
+    EM_BLE_WR(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE, (EM_BLE_RD(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE) & ~((uint16_t)0x00000002)) | ((uint16_t)peerirkvalid << 1));
+}
+
+__INLINE uint8_t em_ble_ral_info_peer_id_type_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE);
+    return ((localVal & ((uint16_t)0x00000001)) >> 0);
+}
+
+__INLINE void em_ble_ral_info_peer_id_type_setf(int elt_idx, uint8_t peeridtype)
+{
+    ASSERT_ERR((((uint16_t)peeridtype << 0) & ~((uint16_t)0x00000001)) == 0);
+    EM_BLE_WR(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE, (EM_BLE_RD(EM_BLE_RAL_INFO_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE) & ~((uint16_t)0x00000001)) | ((uint16_t)peeridtype << 0));
+}
+
+/**
+ * @brief RAL_PEER_SID register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  15:00         RAL_PEER_SID   0x0
+ * </pre>
+ */
+#define EM_BLE_RAL_PEER_SID_ADDR   (0x53004002 + EM_BLE_RAL_OFFSET)
+#define EM_BLE_RAL_PEER_SID_INDEX  0x00000001
+#define EM_BLE_RAL_PEER_SID_RESET  0x00000000
+
+__INLINE uint16_t em_ble_ral_peer_sid_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_RAL_PEER_SID_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE);
+}
+
+__INLINE void em_ble_ral_peer_sid_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_RAL_PEER_SID_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_RAL_PEER_SID_MASK   ((uint16_t)0x0000FFFF)
+#define EM_BLE_RAL_PEER_SID_LSB    0
+#define EM_BLE_RAL_PEER_SID_WIDTH  ((uint16_t)0x00000010)
+
+#define EM_BLE_RAL_PEER_SID_RST    0x0
+
+__INLINE uint16_t em_ble_ral_peer_sid_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RAL_PEER_SID_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE);
+    ASSERT_ERR((localVal & ~((uint16_t)0x0000FFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void em_ble_ral_peer_sid_setf(int elt_idx, uint16_t ralpeersid)
+{
+    ASSERT_ERR((((uint16_t)ralpeersid << 0) & ~((uint16_t)0x0000FFFF)) == 0);
+    EM_BLE_WR(EM_BLE_RAL_PEER_SID_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE, (uint16_t)ralpeersid << 0);
+}
+
+/**
+ * @brief RAL_PEER_IRK register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  15:00             PEER_IRK   0x0
+ * </pre>
+ */
+#define EM_BLE_RAL_PEER_IRK_ADDR   (0x53004004 + EM_BLE_RAL_OFFSET)
+#define EM_BLE_RAL_PEER_IRK_INDEX  0x00000002
+#define EM_BLE_RAL_PEER_IRK_RESET  0x00000000
+#define EM_BLE_RAL_PEER_IRK_COUNT  8
+
+__INLINE uint16_t em_ble_ral_peer_irk_get(int elt_idx, int reg_idx)
+{
+    ASSERT_ERR(reg_idx <= 7);
+    return EM_BLE_RD(EM_BLE_RAL_PEER_IRK_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE + reg_idx * 2);
+}
+
+__INLINE void em_ble_ral_peer_irk_set(int elt_idx, int reg_idx, uint16_t value)
+{
+    ASSERT_ERR(reg_idx <= 7);
+    EM_BLE_WR(EM_BLE_RAL_PEER_IRK_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE + reg_idx * 2, value);
+}
+
+// field definitions
+#define EM_BLE_PEER_IRK_MASK   ((uint16_t)0x0000FFFF)
+#define EM_BLE_PEER_IRK_LSB    0
+#define EM_BLE_PEER_IRK_WIDTH  ((uint16_t)0x00000010)
+
+#define EM_BLE_PEER_IRK_RST    0x0
+
+__INLINE uint16_t em_ble_ral_peer_irk_peer_irk_getf(int elt_idx, int reg_idx)
+{
+    ASSERT_ERR(reg_idx <= 7);
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RAL_PEER_IRK_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE + reg_idx * 2);
+    ASSERT_ERR((localVal & ~((uint16_t)0x0000FFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void em_ble_ral_peer_irk_peer_irk_setf(int elt_idx, int reg_idx, uint16_t peerirk)
+{
+    ASSERT_ERR(reg_idx <= 7);
+    ASSERT_ERR((((uint16_t)peerirk << 0) & ~((uint16_t)0x0000FFFF)) == 0);
+    EM_BLE_WR(EM_BLE_RAL_PEER_IRK_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE + reg_idx * 2, (uint16_t)peerirk << 0);
+}
+
+/**
+ * @brief RAL_PEER_RPA register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  15:00             PEER_RPA   0x0
+ * </pre>
+ */
+#define EM_BLE_RAL_PEER_RPA_ADDR   (0x53004014 + EM_BLE_RAL_OFFSET)
+#define EM_BLE_RAL_PEER_RPA_INDEX  0x0000000A
+#define EM_BLE_RAL_PEER_RPA_RESET  0x00000000
+#define EM_BLE_RAL_PEER_RPA_COUNT  3
+
+__INLINE uint16_t em_ble_ral_peer_rpa_get(int elt_idx, int reg_idx)
+{
+    ASSERT_ERR(reg_idx <= 2);
+    return EM_BLE_RD(EM_BLE_RAL_PEER_RPA_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE + reg_idx * 2);
+}
+
+__INLINE void em_ble_ral_peer_rpa_set(int elt_idx, int reg_idx, uint16_t value)
+{
+    ASSERT_ERR(reg_idx <= 2);
+    EM_BLE_WR(EM_BLE_RAL_PEER_RPA_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE + reg_idx * 2, value);
+}
+
+// field definitions
+#define EM_BLE_PEER_RPA_MASK   ((uint16_t)0x0000FFFF)
+#define EM_BLE_PEER_RPA_LSB    0
+#define EM_BLE_PEER_RPA_WIDTH  ((uint16_t)0x00000010)
+
+#define EM_BLE_PEER_RPA_RST    0x0
+
+__INLINE uint16_t em_ble_ral_peer_rpa_peer_rpa_getf(int elt_idx, int reg_idx)
+{
+    ASSERT_ERR(reg_idx <= 2);
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RAL_PEER_RPA_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE + reg_idx * 2);
+    ASSERT_ERR((localVal & ~((uint16_t)0x0000FFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void em_ble_ral_peer_rpa_peer_rpa_setf(int elt_idx, int reg_idx, uint16_t peerrpa)
+{
+    ASSERT_ERR(reg_idx <= 2);
+    ASSERT_ERR((((uint16_t)peerrpa << 0) & ~((uint16_t)0x0000FFFF)) == 0);
+    EM_BLE_WR(EM_BLE_RAL_PEER_RPA_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE + reg_idx * 2, (uint16_t)peerrpa << 0);
+}
+
+/**
+ * @brief RAL_PEER_ID register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  15:00              PEER_ID   0x0
+ * </pre>
+ */
+#define EM_BLE_RAL_PEER_ID_ADDR   (0x5300401A + EM_BLE_RAL_OFFSET)
+#define EM_BLE_RAL_PEER_ID_INDEX  0x0000000D
+#define EM_BLE_RAL_PEER_ID_RESET  0x00000000
+#define EM_BLE_RAL_PEER_ID_COUNT  3
+
+__INLINE uint16_t em_ble_ral_peer_id_get(int elt_idx, int reg_idx)
+{
+    ASSERT_ERR(reg_idx <= 2);
+    return EM_BLE_RD(EM_BLE_RAL_PEER_ID_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE + reg_idx * 2);
+}
+
+__INLINE void em_ble_ral_peer_id_set(int elt_idx, int reg_idx, uint16_t value)
+{
+    ASSERT_ERR(reg_idx <= 2);
+    EM_BLE_WR(EM_BLE_RAL_PEER_ID_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE + reg_idx * 2, value);
+}
+
+// field definitions
+#define EM_BLE_PEER_ID_MASK   ((uint16_t)0x0000FFFF)
+#define EM_BLE_PEER_ID_LSB    0
+#define EM_BLE_PEER_ID_WIDTH  ((uint16_t)0x00000010)
+
+#define EM_BLE_PEER_ID_RST    0x0
+
+__INLINE uint16_t em_ble_ral_peer_id_peer_id_getf(int elt_idx, int reg_idx)
+{
+    ASSERT_ERR(reg_idx <= 2);
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RAL_PEER_ID_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE + reg_idx * 2);
+    ASSERT_ERR((localVal & ~((uint16_t)0x0000FFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void em_ble_ral_peer_id_peer_id_setf(int elt_idx, int reg_idx, uint16_t peerid)
+{
+    ASSERT_ERR(reg_idx <= 2);
+    ASSERT_ERR((((uint16_t)peerid << 0) & ~((uint16_t)0x0000FFFF)) == 0);
+    EM_BLE_WR(EM_BLE_RAL_PEER_ID_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE + reg_idx * 2, (uint16_t)peerid << 0);
+}
+
+/**
+ * @brief RAL_LOCAL_IRK register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  15:00            LOCAL_IRK   0x0
+ * </pre>
+ */
+#define EM_BLE_RAL_LOCAL_IRK_ADDR   (0x53004020 + EM_BLE_RAL_OFFSET)
+#define EM_BLE_RAL_LOCAL_IRK_INDEX  0x00000010
+#define EM_BLE_RAL_LOCAL_IRK_RESET  0x00000000
+#define EM_BLE_RAL_LOCAL_IRK_COUNT  8
+
+__INLINE uint16_t em_ble_ral_local_irk_get(int elt_idx, int reg_idx)
+{
+    ASSERT_ERR(reg_idx <= 7);
+    return EM_BLE_RD(EM_BLE_RAL_LOCAL_IRK_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE + reg_idx * 2);
+}
+
+__INLINE void em_ble_ral_local_irk_set(int elt_idx, int reg_idx, uint16_t value)
+{
+    ASSERT_ERR(reg_idx <= 7);
+    EM_BLE_WR(EM_BLE_RAL_LOCAL_IRK_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE + reg_idx * 2, value);
+}
+
+// field definitions
+#define EM_BLE_LOCAL_IRK_MASK   ((uint16_t)0x0000FFFF)
+#define EM_BLE_LOCAL_IRK_LSB    0
+#define EM_BLE_LOCAL_IRK_WIDTH  ((uint16_t)0x00000010)
+
+#define EM_BLE_LOCAL_IRK_RST    0x0
+
+__INLINE uint16_t em_ble_ral_local_irk_local_irk_getf(int elt_idx, int reg_idx)
+{
+    ASSERT_ERR(reg_idx <= 7);
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RAL_LOCAL_IRK_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE + reg_idx * 2);
+    ASSERT_ERR((localVal & ~((uint16_t)0x0000FFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void em_ble_ral_local_irk_local_irk_setf(int elt_idx, int reg_idx, uint16_t localirk)
+{
+    ASSERT_ERR(reg_idx <= 7);
+    ASSERT_ERR((((uint16_t)localirk << 0) & ~((uint16_t)0x0000FFFF)) == 0);
+    EM_BLE_WR(EM_BLE_RAL_LOCAL_IRK_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE + reg_idx * 2, (uint16_t)localirk << 0);
+}
+
+/**
+ * @brief RAL_LOCAL_RPA register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  15:00            LOCAL_RPA   0x0
+ * </pre>
+ */
+#define EM_BLE_RAL_LOCAL_RPA_ADDR   (0x53004030 + EM_BLE_RAL_OFFSET)
+#define EM_BLE_RAL_LOCAL_RPA_INDEX  0x00000018
+#define EM_BLE_RAL_LOCAL_RPA_RESET  0x00000000
+#define EM_BLE_RAL_LOCAL_RPA_COUNT  3
+
+__INLINE uint16_t em_ble_ral_local_rpa_get(int elt_idx, int reg_idx)
+{
+    ASSERT_ERR(reg_idx <= 2);
+    return EM_BLE_RD(EM_BLE_RAL_LOCAL_RPA_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE + reg_idx * 2);
+}
+
+__INLINE void em_ble_ral_local_rpa_set(int elt_idx, int reg_idx, uint16_t value)
+{
+    ASSERT_ERR(reg_idx <= 2);
+    EM_BLE_WR(EM_BLE_RAL_LOCAL_RPA_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE + reg_idx * 2, value);
+}
+
+// field definitions
+#define EM_BLE_LOCAL_RPA_MASK   ((uint16_t)0x0000FFFF)
+#define EM_BLE_LOCAL_RPA_LSB    0
+#define EM_BLE_LOCAL_RPA_WIDTH  ((uint16_t)0x00000010)
+
+#define EM_BLE_LOCAL_RPA_RST    0x0
+
+__INLINE uint16_t em_ble_ral_local_rpa_local_rpa_getf(int elt_idx, int reg_idx)
+{
+    ASSERT_ERR(reg_idx <= 2);
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RAL_LOCAL_RPA_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE + reg_idx * 2);
+    ASSERT_ERR((localVal & ~((uint16_t)0x0000FFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void em_ble_ral_local_rpa_local_rpa_setf(int elt_idx, int reg_idx, uint16_t localrpa)
+{
+    ASSERT_ERR(reg_idx <= 2);
+    ASSERT_ERR((((uint16_t)localrpa << 0) & ~((uint16_t)0x0000FFFF)) == 0);
+    EM_BLE_WR(EM_BLE_RAL_LOCAL_RPA_ADDR + elt_idx * REG_EM_BLE_RAL_SIZE + reg_idx * 2, (uint16_t)localrpa << 0);
+}
+
+
+#endif // _REG_EM_BLE_RAL_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/reg_em_ble_rx_cte_desc.h

@@ -0,0 +1,173 @@
+#ifndef _REG_EM_BLE_RX_CTE_DESC_H_
+#define _REG_EM_BLE_RX_CTE_DESC_H_
+
+#include <stdint.h>
+#include "_reg_em_ble_rx_cte_desc.h"
+#include "compiler.h"
+#include "arch.h"
+#include "em_map.h"
+#include "reg_access.h"
+
+#define REG_EM_BLE_RX_CTE_DESC_COUNT 3
+
+#define REG_EM_BLE_RX_CTE_DESC_DECODING_MASK 0x00000007
+
+#define REG_EM_BLE_RX_CTE_DESC_ADDR_GET(idx) (EM_BLE_RX_CTE_DESC_OFFSET + (idx) * REG_EM_BLE_RX_CTE_DESC_SIZE)
+
+/**
+ * @brief RXCTECNTL register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     15               RXDONE   0
+ *  13:00            RXNEXTPTR   0x0
+ * </pre>
+ */
+#define EM_BLE_RXCTECNTL_ADDR   (0x53004000 + EM_BLE_RX_CTE_DESC_OFFSET)
+#define EM_BLE_RXCTECNTL_INDEX  0x00000000
+#define EM_BLE_RXCTECNTL_RESET  0x00000000
+
+__INLINE uint16_t em_ble_rxctecntl_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_RXCTECNTL_ADDR + elt_idx * REG_EM_BLE_RX_CTE_DESC_SIZE);
+}
+
+__INLINE void em_ble_rxctecntl_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_RXCTECNTL_ADDR + elt_idx * REG_EM_BLE_RX_CTE_DESC_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_RXDONE_BIT       ((uint16_t)0x00008000)
+#define EM_BLE_RXDONE_POS       15
+#define EM_BLE_RXNEXTPTR_MASK   ((uint16_t)0x00003FFF)
+#define EM_BLE_RXNEXTPTR_LSB    0
+#define EM_BLE_RXNEXTPTR_WIDTH  ((uint16_t)0x0000000E)
+
+#define EM_BLE_RXDONE_RST       0x0
+#define EM_BLE_RXNEXTPTR_RST    0x0
+
+__INLINE void em_ble_rxctecntl_pack(int elt_idx, uint8_t rxdone, uint16_t rxnextptr)
+{
+    ASSERT_ERR((((uint16_t)rxdone << 15) & ~((uint16_t)0x00008000)) == 0);
+    ASSERT_ERR((((uint16_t)rxnextptr << 0) & ~((uint16_t)0x00003FFF)) == 0);
+    EM_BLE_WR(EM_BLE_RXCTECNTL_ADDR + elt_idx * REG_EM_BLE_RX_CTE_DESC_SIZE,  ((uint16_t)rxdone << 15) | ((uint16_t)rxnextptr << 0));
+}
+
+__INLINE void em_ble_rxctecntl_unpack(int elt_idx, uint8_t* rxdone, uint16_t* rxnextptr)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RXCTECNTL_ADDR + elt_idx * REG_EM_BLE_RX_CTE_DESC_SIZE);
+
+    *rxdone = (localVal & ((uint16_t)0x00008000)) >> 15;
+    *rxnextptr = (localVal & ((uint16_t)0x00003FFF)) >> 0;
+}
+
+__INLINE uint8_t em_ble_rxctecntl_rxdone_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RXCTECNTL_ADDR + elt_idx * REG_EM_BLE_RX_CTE_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00008000)) >> 15);
+}
+
+__INLINE void em_ble_rxctecntl_rxdone_setf(int elt_idx, uint8_t rxdone)
+{
+    ASSERT_ERR((((uint16_t)rxdone << 15) & ~((uint16_t)0x00008000)) == 0);
+    EM_BLE_WR(EM_BLE_RXCTECNTL_ADDR + elt_idx * REG_EM_BLE_RX_CTE_DESC_SIZE, (EM_BLE_RD(EM_BLE_RXCTECNTL_ADDR + elt_idx * REG_EM_BLE_RX_CTE_DESC_SIZE) & ~((uint16_t)0x00008000)) | ((uint16_t)rxdone << 15));
+}
+
+__INLINE uint16_t em_ble_rxctecntl_rxnextptr_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RXCTECNTL_ADDR + elt_idx * REG_EM_BLE_RX_CTE_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00003FFF)) >> 0);
+}
+
+__INLINE void em_ble_rxctecntl_rxnextptr_setf(int elt_idx, uint16_t rxnextptr)
+{
+    ASSERT_ERR((((uint16_t)rxnextptr << 0) & ~((uint16_t)0x00003FFF)) == 0);
+    EM_BLE_WR(EM_BLE_RXCTECNTL_ADDR + elt_idx * REG_EM_BLE_RX_CTE_DESC_SIZE, (EM_BLE_RD(EM_BLE_RXCTECNTL_ADDR + elt_idx * REG_EM_BLE_RX_CTE_DESC_SIZE) & ~((uint16_t)0x00003FFF)) | ((uint16_t)rxnextptr << 0));
+}
+
+/**
+ * @brief RXCTESAMPBUF register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  15:08                 RX_Q   0x0
+ *  07:00                 RX_I   0x0
+ * </pre>
+ */
+#define EM_BLE_RXCTESAMPBUF_ADDR   (0x53004004 + EM_BLE_RX_CTE_DESC_OFFSET)
+#define EM_BLE_RXCTESAMPBUF_INDEX  0x00000002
+#define EM_BLE_RXCTESAMPBUF_RESET  0x00000000
+#define EM_BLE_RXCTESAMPBUF_COUNT  82
+
+__INLINE uint16_t em_ble_rxctesampbuf_get(int elt_idx, int reg_idx)
+{
+    ASSERT_ERR(reg_idx <= 81);
+    return EM_BLE_RD(EM_BLE_RXCTESAMPBUF_ADDR + elt_idx * REG_EM_BLE_RX_CTE_DESC_SIZE + reg_idx * 2);
+}
+
+__INLINE void em_ble_rxctesampbuf_set(int elt_idx, int reg_idx, uint16_t value)
+{
+    ASSERT_ERR(reg_idx <= 81);
+    EM_BLE_WR(EM_BLE_RXCTESAMPBUF_ADDR + elt_idx * REG_EM_BLE_RX_CTE_DESC_SIZE + reg_idx * 2, value);
+}
+
+// field definitions
+#define EM_BLE_RX_Q_MASK   ((uint16_t)0x0000FF00)
+#define EM_BLE_RX_Q_LSB    8
+#define EM_BLE_RX_Q_WIDTH  ((uint16_t)0x00000008)
+#define EM_BLE_RX_I_MASK   ((uint16_t)0x000000FF)
+#define EM_BLE_RX_I_LSB    0
+#define EM_BLE_RX_I_WIDTH  ((uint16_t)0x00000008)
+
+#define EM_BLE_RX_Q_RST    0x0
+#define EM_BLE_RX_I_RST    0x0
+
+__INLINE void em_ble_rxctesampbuf_pack(int elt_idx, int reg_idx, uint8_t rxq, uint8_t rxi)
+{
+    ASSERT_ERR(reg_idx <= 81);
+    ASSERT_ERR((((uint16_t)rxq << 8) & ~((uint16_t)0x0000FF00)) == 0);
+    ASSERT_ERR((((uint16_t)rxi << 0) & ~((uint16_t)0x000000FF)) == 0);
+    EM_BLE_WR(EM_BLE_RXCTESAMPBUF_ADDR + elt_idx * REG_EM_BLE_RX_CTE_DESC_SIZE + reg_idx * 2,  ((uint16_t)rxq << 8) | ((uint16_t)rxi << 0));
+}
+
+__INLINE void em_ble_rxctesampbuf_unpack(int elt_idx, int reg_idx, uint8_t* rxq, uint8_t* rxi)
+{
+    ASSERT_ERR(reg_idx <= 81);
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RXCTESAMPBUF_ADDR + elt_idx * REG_EM_BLE_RX_CTE_DESC_SIZE + reg_idx * 2);
+
+    *rxq = (localVal & ((uint16_t)0x0000FF00)) >> 8;
+    *rxi = (localVal & ((uint16_t)0x000000FF)) >> 0;
+}
+
+__INLINE uint8_t em_ble_rxctesampbuf_rx_q_getf(int elt_idx, int reg_idx)
+{
+    ASSERT_ERR(reg_idx <= 81);
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RXCTESAMPBUF_ADDR + elt_idx * REG_EM_BLE_RX_CTE_DESC_SIZE + reg_idx * 2);
+    return ((localVal & ((uint16_t)0x0000FF00)) >> 8);
+}
+
+__INLINE void em_ble_rxctesampbuf_rx_q_setf(int elt_idx, int reg_idx, uint8_t rxq)
+{
+    ASSERT_ERR(reg_idx <= 81);
+    ASSERT_ERR((((uint16_t)rxq << 8) & ~((uint16_t)0x0000FF00)) == 0);
+    EM_BLE_WR(EM_BLE_RXCTESAMPBUF_ADDR + elt_idx * REG_EM_BLE_RX_CTE_DESC_SIZE + reg_idx * 2, (EM_BLE_RD(EM_BLE_RXCTESAMPBUF_ADDR + elt_idx * REG_EM_BLE_RX_CTE_DESC_SIZE + reg_idx * 2) & ~((uint16_t)0x0000FF00)) | ((uint16_t)rxq << 8));
+}
+
+__INLINE uint8_t em_ble_rxctesampbuf_rx_i_getf(int elt_idx, int reg_idx)
+{
+    ASSERT_ERR(reg_idx <= 81);
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RXCTESAMPBUF_ADDR + elt_idx * REG_EM_BLE_RX_CTE_DESC_SIZE + reg_idx * 2);
+    return ((localVal & ((uint16_t)0x000000FF)) >> 0);
+}
+
+__INLINE void em_ble_rxctesampbuf_rx_i_setf(int elt_idx, int reg_idx, uint8_t rxi)
+{
+    ASSERT_ERR(reg_idx <= 81);
+    ASSERT_ERR((((uint16_t)rxi << 0) & ~((uint16_t)0x000000FF)) == 0);
+    EM_BLE_WR(EM_BLE_RXCTESAMPBUF_ADDR + elt_idx * REG_EM_BLE_RX_CTE_DESC_SIZE + reg_idx * 2, (EM_BLE_RD(EM_BLE_RXCTESAMPBUF_ADDR + elt_idx * REG_EM_BLE_RX_CTE_DESC_SIZE + reg_idx * 2) & ~((uint16_t)0x000000FF)) | ((uint16_t)rxi << 0));
+}
+
+
+#endif // _REG_EM_BLE_RX_CTE_DESC_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/reg_em_ble_rx_iso_buf.h

@@ -0,0 +1,292 @@
+#ifndef _REG_EM_BLE_RX_ISO_BUF_H_
+#define _REG_EM_BLE_RX_ISO_BUF_H_
+
+#include <stdint.h>
+#include "_reg_em_ble_rx_iso_buf.h"
+#include "compiler.h"
+#include "arch.h"
+#include "em_map.h"
+#include "reg_access.h"
+
+#define REG_EM_BLE_RX_ISO_BUF_COUNT 4
+
+#define REG_EM_BLE_RX_ISO_BUF_DECODING_MASK 0x00000007
+
+#define REG_EM_BLE_RX_ISO_BUF_ADDR_GET(idx) (EM_BLE_RX_ISO_BUF_OFFSET + (idx) * REG_EM_BLE_RX_ISO_BUF_SIZE)
+
+/**
+ * @brief RXISOBUFSETUP register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  15:14                 INVL   0x0
+ *  09:08            RXISOLLID   0x0
+ *  07:00          RXISOLENGTH   0x0
+ * </pre>
+ */
+#define EM_BLE_RXISOBUFSETUP_ADDR   (0x53004000 + EM_BLE_RX_ISO_BUF_OFFSET)
+#define EM_BLE_RXISOBUFSETUP_INDEX  0x00000000
+#define EM_BLE_RXISOBUFSETUP_RESET  0x00000000
+
+__INLINE uint16_t em_ble_rxisobufsetup_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_RXISOBUFSETUP_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE);
+}
+
+__INLINE void em_ble_rxisobufsetup_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_RXISOBUFSETUP_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_INVL_MASK          ((uint16_t)0x0000C000)
+#define EM_BLE_INVL_LSB           14
+#define EM_BLE_INVL_WIDTH         ((uint16_t)0x00000002)
+#define EM_BLE_RXISOLLID_MASK     ((uint16_t)0x00000300)
+#define EM_BLE_RXISOLLID_LSB      8
+#define EM_BLE_RXISOLLID_WIDTH    ((uint16_t)0x00000002)
+#define EM_BLE_RXISOLENGTH_MASK   ((uint16_t)0x000000FF)
+#define EM_BLE_RXISOLENGTH_LSB    0
+#define EM_BLE_RXISOLENGTH_WIDTH  ((uint16_t)0x00000008)
+
+#define EM_BLE_INVL_RST           0x0
+#define EM_BLE_RXISOLLID_RST      0x0
+#define EM_BLE_RXISOLENGTH_RST    0x0
+
+__INLINE void em_ble_rxisobufsetup_pack(int elt_idx, uint8_t invl, uint8_t rxisollid, uint8_t rxisolength)
+{
+    ASSERT_ERR((((uint16_t)invl << 14) & ~((uint16_t)0x0000C000)) == 0);
+    ASSERT_ERR((((uint16_t)rxisollid << 8) & ~((uint16_t)0x00000300)) == 0);
+    ASSERT_ERR((((uint16_t)rxisolength << 0) & ~((uint16_t)0x000000FF)) == 0);
+    EM_BLE_WR(EM_BLE_RXISOBUFSETUP_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE,  ((uint16_t)invl << 14) | ((uint16_t)rxisollid << 8) | ((uint16_t)rxisolength << 0));
+}
+
+__INLINE void em_ble_rxisobufsetup_unpack(int elt_idx, uint8_t* invl, uint8_t* rxisollid, uint8_t* rxisolength)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RXISOBUFSETUP_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE);
+
+    *invl = (localVal & ((uint16_t)0x0000C000)) >> 14;
+    *rxisollid = (localVal & ((uint16_t)0x00000300)) >> 8;
+    *rxisolength = (localVal & ((uint16_t)0x000000FF)) >> 0;
+}
+
+__INLINE uint8_t em_ble_rxisobufsetup_invl_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RXISOBUFSETUP_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE);
+    return ((localVal & ((uint16_t)0x0000C000)) >> 14);
+}
+
+__INLINE void em_ble_rxisobufsetup_invl_setf(int elt_idx, uint8_t invl)
+{
+    ASSERT_ERR((((uint16_t)invl << 14) & ~((uint16_t)0x0000C000)) == 0);
+    EM_BLE_WR(EM_BLE_RXISOBUFSETUP_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE, (EM_BLE_RD(EM_BLE_RXISOBUFSETUP_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE) & ~((uint16_t)0x0000C000)) | ((uint16_t)invl << 14));
+}
+
+__INLINE uint8_t em_ble_rxisobufsetup_rxisollid_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RXISOBUFSETUP_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE);
+    return ((localVal & ((uint16_t)0x00000300)) >> 8);
+}
+
+__INLINE void em_ble_rxisobufsetup_rxisollid_setf(int elt_idx, uint8_t rxisollid)
+{
+    ASSERT_ERR((((uint16_t)rxisollid << 8) & ~((uint16_t)0x00000300)) == 0);
+    EM_BLE_WR(EM_BLE_RXISOBUFSETUP_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE, (EM_BLE_RD(EM_BLE_RXISOBUFSETUP_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE) & ~((uint16_t)0x00000300)) | ((uint16_t)rxisollid << 8));
+}
+
+__INLINE uint8_t em_ble_rxisobufsetup_rxisolength_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RXISOBUFSETUP_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE);
+    return ((localVal & ((uint16_t)0x000000FF)) >> 0);
+}
+
+__INLINE void em_ble_rxisobufsetup_rxisolength_setf(int elt_idx, uint8_t rxisolength)
+{
+    ASSERT_ERR((((uint16_t)rxisolength << 0) & ~((uint16_t)0x000000FF)) == 0);
+    EM_BLE_WR(EM_BLE_RXISOBUFSETUP_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE, (EM_BLE_RD(EM_BLE_RXISOBUFSETUP_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE) & ~((uint16_t)0x000000FF)) | ((uint16_t)rxisolength << 0));
+}
+
+/**
+ * @brief RXISOBUFLBL register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  12:08         RXBUFLINKLBL   0x0
+ *  07:03      RXBUFSTREAM_LBL   0x0
+ *  02:00       RXBUFGROUP_LBL   0x0
+ * </pre>
+ */
+#define EM_BLE_RXISOBUFLBL_ADDR   (0x53004002 + EM_BLE_RX_ISO_BUF_OFFSET)
+#define EM_BLE_RXISOBUFLBL_INDEX  0x00000001
+#define EM_BLE_RXISOBUFLBL_RESET  0x00000000
+
+__INLINE uint16_t em_ble_rxisobuflbl_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_RXISOBUFLBL_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE);
+}
+
+__INLINE void em_ble_rxisobuflbl_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_RXISOBUFLBL_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_RXBUFLINKLBL_MASK      ((uint16_t)0x00001F00)
+#define EM_BLE_RXBUFLINKLBL_LSB       8
+#define EM_BLE_RXBUFLINKLBL_WIDTH     ((uint16_t)0x00000005)
+#define EM_BLE_RXBUFSTREAM_LBL_MASK   ((uint16_t)0x000000F8)
+#define EM_BLE_RXBUFSTREAM_LBL_LSB    3
+#define EM_BLE_RXBUFSTREAM_LBL_WIDTH  ((uint16_t)0x00000005)
+#define EM_BLE_RXBUFGROUP_LBL_MASK    ((uint16_t)0x00000007)
+#define EM_BLE_RXBUFGROUP_LBL_LSB     0
+#define EM_BLE_RXBUFGROUP_LBL_WIDTH   ((uint16_t)0x00000003)
+
+#define EM_BLE_RXBUFLINKLBL_RST       0x0
+#define EM_BLE_RXBUFSTREAM_LBL_RST    0x0
+#define EM_BLE_RXBUFGROUP_LBL_RST     0x0
+
+__INLINE void em_ble_rxisobuflbl_pack(int elt_idx, uint8_t rxbuflinklbl, uint8_t rxbufstreamlbl, uint8_t rxbufgrouplbl)
+{
+    ASSERT_ERR((((uint16_t)rxbuflinklbl << 8) & ~((uint16_t)0x00001F00)) == 0);
+    ASSERT_ERR((((uint16_t)rxbufstreamlbl << 3) & ~((uint16_t)0x000000F8)) == 0);
+    ASSERT_ERR((((uint16_t)rxbufgrouplbl << 0) & ~((uint16_t)0x00000007)) == 0);
+    EM_BLE_WR(EM_BLE_RXISOBUFLBL_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE,  ((uint16_t)rxbuflinklbl << 8) | ((uint16_t)rxbufstreamlbl << 3) | ((uint16_t)rxbufgrouplbl << 0));
+}
+
+__INLINE void em_ble_rxisobuflbl_unpack(int elt_idx, uint8_t* rxbuflinklbl, uint8_t* rxbufstreamlbl, uint8_t* rxbufgrouplbl)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RXISOBUFLBL_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE);
+
+    *rxbuflinklbl = (localVal & ((uint16_t)0x00001F00)) >> 8;
+    *rxbufstreamlbl = (localVal & ((uint16_t)0x000000F8)) >> 3;
+    *rxbufgrouplbl = (localVal & ((uint16_t)0x00000007)) >> 0;
+}
+
+__INLINE uint8_t em_ble_rxisobuflbl_rxbuflinklbl_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RXISOBUFLBL_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE);
+    return ((localVal & ((uint16_t)0x00001F00)) >> 8);
+}
+
+__INLINE void em_ble_rxisobuflbl_rxbuflinklbl_setf(int elt_idx, uint8_t rxbuflinklbl)
+{
+    ASSERT_ERR((((uint16_t)rxbuflinklbl << 8) & ~((uint16_t)0x00001F00)) == 0);
+    EM_BLE_WR(EM_BLE_RXISOBUFLBL_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE, (EM_BLE_RD(EM_BLE_RXISOBUFLBL_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE) & ~((uint16_t)0x00001F00)) | ((uint16_t)rxbuflinklbl << 8));
+}
+
+__INLINE uint8_t em_ble_rxisobuflbl_rxbufstream_lbl_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RXISOBUFLBL_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE);
+    return ((localVal & ((uint16_t)0x000000F8)) >> 3);
+}
+
+__INLINE void em_ble_rxisobuflbl_rxbufstream_lbl_setf(int elt_idx, uint8_t rxbufstreamlbl)
+{
+    ASSERT_ERR((((uint16_t)rxbufstreamlbl << 3) & ~((uint16_t)0x000000F8)) == 0);
+    EM_BLE_WR(EM_BLE_RXISOBUFLBL_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE, (EM_BLE_RD(EM_BLE_RXISOBUFLBL_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE) & ~((uint16_t)0x000000F8)) | ((uint16_t)rxbufstreamlbl << 3));
+}
+
+__INLINE uint8_t em_ble_rxisobuflbl_rxbufgroup_lbl_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RXISOBUFLBL_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE);
+    return ((localVal & ((uint16_t)0x00000007)) >> 0);
+}
+
+__INLINE void em_ble_rxisobuflbl_rxbufgroup_lbl_setf(int elt_idx, uint8_t rxbufgrouplbl)
+{
+    ASSERT_ERR((((uint16_t)rxbufgrouplbl << 0) & ~((uint16_t)0x00000007)) == 0);
+    EM_BLE_WR(EM_BLE_RXISOBUFLBL_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE, (EM_BLE_RD(EM_BLE_RXISOBUFLBL_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE) & ~((uint16_t)0x00000007)) | ((uint16_t)rxbufgrouplbl << 0));
+}
+
+/**
+ * @brief RXISOSUBEVTCNT register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  07:00            SUBEVTCNT   0x0
+ * </pre>
+ */
+#define EM_BLE_RXISOSUBEVTCNT_ADDR   (0x53004004 + EM_BLE_RX_ISO_BUF_OFFSET)
+#define EM_BLE_RXISOSUBEVTCNT_INDEX  0x00000002
+#define EM_BLE_RXISOSUBEVTCNT_RESET  0x00000000
+
+__INLINE uint16_t em_ble_rxisosubevtcnt_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_RXISOSUBEVTCNT_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE);
+}
+
+__INLINE void em_ble_rxisosubevtcnt_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_RXISOSUBEVTCNT_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_SUBEVTCNT_MASK   ((uint16_t)0x000000FF)
+#define EM_BLE_SUBEVTCNT_LSB    0
+#define EM_BLE_SUBEVTCNT_WIDTH  ((uint16_t)0x00000008)
+
+#define EM_BLE_SUBEVTCNT_RST    0x0
+
+__INLINE uint8_t em_ble_rxisosubevtcnt_subevtcnt_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RXISOSUBEVTCNT_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE);
+    ASSERT_ERR((localVal & ~((uint16_t)0x000000FF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void em_ble_rxisosubevtcnt_subevtcnt_setf(int elt_idx, uint8_t subevtcnt)
+{
+    ASSERT_ERR((((uint16_t)subevtcnt << 0) & ~((uint16_t)0x000000FF)) == 0);
+    EM_BLE_WR(EM_BLE_RXISOSUBEVTCNT_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE, (uint16_t)subevtcnt << 0);
+}
+
+/**
+ * @brief RXISODATABUF register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  15:00         RXISODATABUF   0x0
+ * </pre>
+ */
+#define EM_BLE_RXISODATABUF_ADDR   (0x53004006 + EM_BLE_RX_ISO_BUF_OFFSET)
+#define EM_BLE_RXISODATABUF_INDEX  0x00000003
+#define EM_BLE_RXISODATABUF_RESET  0x00000000
+#define EM_BLE_RXISODATABUF_COUNT  127
+
+__INLINE uint16_t em_ble_rxisodatabuf_get(int elt_idx, int reg_idx)
+{
+    ASSERT_ERR(reg_idx <= 126);
+    return EM_BLE_RD(EM_BLE_RXISODATABUF_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE + reg_idx * 2);
+}
+
+__INLINE void em_ble_rxisodatabuf_set(int elt_idx, int reg_idx, uint16_t value)
+{
+    ASSERT_ERR(reg_idx <= 126);
+    EM_BLE_WR(EM_BLE_RXISODATABUF_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE + reg_idx * 2, value);
+}
+
+// field definitions
+#define EM_BLE_RXISODATABUF_MASK   ((uint16_t)0x0000FFFF)
+#define EM_BLE_RXISODATABUF_LSB    0
+#define EM_BLE_RXISODATABUF_WIDTH  ((uint16_t)0x00000010)
+
+#define EM_BLE_RXISODATABUF_RST    0x0
+
+__INLINE uint16_t em_ble_rxisodatabuf_getf(int elt_idx, int reg_idx)
+{
+    ASSERT_ERR(reg_idx <= 126);
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RXISODATABUF_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE + reg_idx * 2);
+    ASSERT_ERR((localVal & ~((uint16_t)0x0000FFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void em_ble_rxisodatabuf_setf(int elt_idx, int reg_idx, uint16_t rxisodatabuf)
+{
+    ASSERT_ERR(reg_idx <= 126);
+    ASSERT_ERR((((uint16_t)rxisodatabuf << 0) & ~((uint16_t)0x0000FFFF)) == 0);
+    EM_BLE_WR(EM_BLE_RXISODATABUF_ADDR + elt_idx * REG_EM_BLE_RX_ISO_BUF_SIZE + reg_idx * 2, (uint16_t)rxisodatabuf << 0);
+}
+
+
+#endif // _REG_EM_BLE_RX_ISO_BUF_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/reg_em_ble_rx_iso_desc.h

@@ -0,0 +1,332 @@
+#ifndef _REG_EM_BLE_RX_ISO_DESC_H_
+#define _REG_EM_BLE_RX_ISO_DESC_H_
+
+#include <stdint.h>
+#include "_reg_em_ble_rx_iso_desc.h"
+#include "compiler.h"
+#include "arch.h"
+#include "em_map.h"
+#include "reg_access.h"
+
+#define REG_EM_BLE_RX_ISO_DESC_COUNT 6
+
+#define REG_EM_BLE_RX_ISO_DESC_DECODING_MASK 0x0000000F
+
+#define REG_EM_BLE_RX_ISO_DESC_ADDR_GET(idx) (EM_BLE_RX_ISO_DESC_OFFSET + (idx) * REG_EM_BLE_RX_ISO_DESC_SIZE)
+
+/**
+ * @brief RXISOPTR register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     15               RXDONE   0
+ *  13:00              NEXTPTR   0x0
+ * </pre>
+ */
+#define EM_BLE_RXISOPTR_ADDR   (0x53004000 + EM_BLE_RX_ISO_DESC_OFFSET)
+#define EM_BLE_RXISOPTR_INDEX  0x00000000
+#define EM_BLE_RXISOPTR_RESET  0x00000000
+
+__INLINE uint16_t em_ble_rxisoptr_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_RXISOPTR_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE);
+}
+
+__INLINE void em_ble_rxisoptr_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_RXISOPTR_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_RXDONE_BIT     ((uint16_t)0x00008000)
+#define EM_BLE_RXDONE_POS     15
+#define EM_BLE_NEXTPTR_MASK   ((uint16_t)0x00003FFF)
+#define EM_BLE_NEXTPTR_LSB    0
+#define EM_BLE_NEXTPTR_WIDTH  ((uint16_t)0x0000000E)
+
+#define EM_BLE_RXDONE_RST     0x0
+#define EM_BLE_NEXTPTR_RST    0x0
+
+__INLINE void em_ble_rxisoptr_pack(int elt_idx, uint8_t rxdone, uint16_t nextptr)
+{
+    ASSERT_ERR((((uint16_t)rxdone << 15) & ~((uint16_t)0x00008000)) == 0);
+    ASSERT_ERR((((uint16_t)nextptr << 0) & ~((uint16_t)0x00003FFF)) == 0);
+    EM_BLE_WR(EM_BLE_RXISOPTR_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE,  ((uint16_t)rxdone << 15) | ((uint16_t)nextptr << 0));
+}
+
+__INLINE void em_ble_rxisoptr_unpack(int elt_idx, uint8_t* rxdone, uint16_t* nextptr)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RXISOPTR_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE);
+
+    *rxdone = (localVal & ((uint16_t)0x00008000)) >> 15;
+    *nextptr = (localVal & ((uint16_t)0x00003FFF)) >> 0;
+}
+
+__INLINE uint8_t em_ble_rxisoptr_rxdone_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RXISOPTR_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00008000)) >> 15);
+}
+
+__INLINE void em_ble_rxisoptr_rxdone_setf(int elt_idx, uint8_t rxdone)
+{
+    ASSERT_ERR((((uint16_t)rxdone << 15) & ~((uint16_t)0x00008000)) == 0);
+    EM_BLE_WR(EM_BLE_RXISOPTR_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE, (EM_BLE_RD(EM_BLE_RXISOPTR_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE) & ~((uint16_t)0x00008000)) | ((uint16_t)rxdone << 15));
+}
+
+__INLINE uint16_t em_ble_rxisoptr_nextptr_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RXISOPTR_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00003FFF)) >> 0);
+}
+
+__INLINE void em_ble_rxisoptr_nextptr_setf(int elt_idx, uint16_t nextptr)
+{
+    ASSERT_ERR((((uint16_t)nextptr << 0) & ~((uint16_t)0x00003FFF)) == 0);
+    EM_BLE_WR(EM_BLE_RXISOPTR_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE, (EM_BLE_RD(EM_BLE_RXISOPTR_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE) & ~((uint16_t)0x00003FFF)) | ((uint16_t)nextptr << 0));
+}
+
+/**
+ * @brief RXISOCNT0 register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  15:00           RXPLD_CNT0   0x0
+ * </pre>
+ */
+#define EM_BLE_RXISOCNT0_ADDR   (0x53004002 + EM_BLE_RX_ISO_DESC_OFFSET)
+#define EM_BLE_RXISOCNT0_INDEX  0x00000001
+#define EM_BLE_RXISOCNT0_RESET  0x00000000
+
+__INLINE uint16_t em_ble_rxisocnt0_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_RXISOCNT0_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE);
+}
+
+__INLINE void em_ble_rxisocnt0_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_RXISOCNT0_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_RXPLD_CNT0_MASK   ((uint16_t)0x0000FFFF)
+#define EM_BLE_RXPLD_CNT0_LSB    0
+#define EM_BLE_RXPLD_CNT0_WIDTH  ((uint16_t)0x00000010)
+
+#define EM_BLE_RXPLD_CNT0_RST    0x0
+
+__INLINE uint16_t em_ble_rxisocnt0_rxpld_cnt0_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RXISOCNT0_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE);
+    ASSERT_ERR((localVal & ~((uint16_t)0x0000FFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void em_ble_rxisocnt0_rxpld_cnt0_setf(int elt_idx, uint16_t rxpldcnt0)
+{
+    ASSERT_ERR((((uint16_t)rxpldcnt0 << 0) & ~((uint16_t)0x0000FFFF)) == 0);
+    EM_BLE_WR(EM_BLE_RXISOCNT0_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE, (uint16_t)rxpldcnt0 << 0);
+}
+
+/**
+ * @brief RXISOCNT1 register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  15:00           RXPLD_CNT1   0x0
+ * </pre>
+ */
+#define EM_BLE_RXISOCNT1_ADDR   (0x53004004 + EM_BLE_RX_ISO_DESC_OFFSET)
+#define EM_BLE_RXISOCNT1_INDEX  0x00000002
+#define EM_BLE_RXISOCNT1_RESET  0x00000000
+
+__INLINE uint16_t em_ble_rxisocnt1_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_RXISOCNT1_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE);
+}
+
+__INLINE void em_ble_rxisocnt1_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_RXISOCNT1_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_RXPLD_CNT1_MASK   ((uint16_t)0x0000FFFF)
+#define EM_BLE_RXPLD_CNT1_LSB    0
+#define EM_BLE_RXPLD_CNT1_WIDTH  ((uint16_t)0x00000010)
+
+#define EM_BLE_RXPLD_CNT1_RST    0x0
+
+__INLINE uint16_t em_ble_rxisocnt1_rxpld_cnt1_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RXISOCNT1_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE);
+    ASSERT_ERR((localVal & ~((uint16_t)0x0000FFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void em_ble_rxisocnt1_rxpld_cnt1_setf(int elt_idx, uint16_t rxpldcnt1)
+{
+    ASSERT_ERR((((uint16_t)rxpldcnt1 << 0) & ~((uint16_t)0x0000FFFF)) == 0);
+    EM_BLE_WR(EM_BLE_RXISOCNT1_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE, (uint16_t)rxpldcnt1 << 0);
+}
+
+/**
+ * @brief RXISOCNT2 register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  15:08       RXFLUSHINSTANT   0x0
+ *  06:00           RXPLD_CNT2   0x0
+ * </pre>
+ */
+#define EM_BLE_RXISOCNT2_ADDR   (0x53004006 + EM_BLE_RX_ISO_DESC_OFFSET)
+#define EM_BLE_RXISOCNT2_INDEX  0x00000003
+#define EM_BLE_RXISOCNT2_RESET  0x00000000
+
+__INLINE uint16_t em_ble_rxisocnt2_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_RXISOCNT2_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE);
+}
+
+__INLINE void em_ble_rxisocnt2_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_RXISOCNT2_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_RXFLUSHINSTANT_MASK   ((uint16_t)0x0000FF00)
+#define EM_BLE_RXFLUSHINSTANT_LSB    8
+#define EM_BLE_RXFLUSHINSTANT_WIDTH  ((uint16_t)0x00000008)
+#define EM_BLE_RXPLD_CNT2_MASK       ((uint16_t)0x0000007F)
+#define EM_BLE_RXPLD_CNT2_LSB        0
+#define EM_BLE_RXPLD_CNT2_WIDTH      ((uint16_t)0x00000007)
+
+#define EM_BLE_RXFLUSHINSTANT_RST    0x0
+#define EM_BLE_RXPLD_CNT2_RST        0x0
+
+__INLINE void em_ble_rxisocnt2_pack(int elt_idx, uint8_t rxflushinstant, uint8_t rxpldcnt2)
+{
+    ASSERT_ERR((((uint16_t)rxflushinstant << 8) & ~((uint16_t)0x0000FF00)) == 0);
+    ASSERT_ERR((((uint16_t)rxpldcnt2 << 0) & ~((uint16_t)0x0000007F)) == 0);
+    EM_BLE_WR(EM_BLE_RXISOCNT2_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE,  ((uint16_t)rxflushinstant << 8) | ((uint16_t)rxpldcnt2 << 0));
+}
+
+__INLINE void em_ble_rxisocnt2_unpack(int elt_idx, uint8_t* rxflushinstant, uint8_t* rxpldcnt2)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RXISOCNT2_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE);
+
+    *rxflushinstant = (localVal & ((uint16_t)0x0000FF00)) >> 8;
+    *rxpldcnt2 = (localVal & ((uint16_t)0x0000007F)) >> 0;
+}
+
+__INLINE uint8_t em_ble_rxisocnt2_rxflushinstant_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RXISOCNT2_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x0000FF00)) >> 8);
+}
+
+__INLINE void em_ble_rxisocnt2_rxflushinstant_setf(int elt_idx, uint8_t rxflushinstant)
+{
+    ASSERT_ERR((((uint16_t)rxflushinstant << 8) & ~((uint16_t)0x0000FF00)) == 0);
+    EM_BLE_WR(EM_BLE_RXISOCNT2_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE, (EM_BLE_RD(EM_BLE_RXISOCNT2_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE) & ~((uint16_t)0x0000FF00)) | ((uint16_t)rxflushinstant << 8));
+}
+
+__INLINE uint8_t em_ble_rxisocnt2_rxpld_cnt2_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RXISOCNT2_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x0000007F)) >> 0);
+}
+
+__INLINE void em_ble_rxisocnt2_rxpld_cnt2_setf(int elt_idx, uint8_t rxpldcnt2)
+{
+    ASSERT_ERR((((uint16_t)rxpldcnt2 << 0) & ~((uint16_t)0x0000007F)) == 0);
+    EM_BLE_WR(EM_BLE_RXISOCNT2_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE, (EM_BLE_RD(EM_BLE_RXISOCNT2_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE) & ~((uint16_t)0x0000007F)) | ((uint16_t)rxpldcnt2 << 0));
+}
+
+/**
+ * @brief RXISOBUFPTR register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  13:00          RXISOBUFPTR   0x0
+ * </pre>
+ */
+#define EM_BLE_RXISOBUFPTR_ADDR   (0x53004008 + EM_BLE_RX_ISO_DESC_OFFSET)
+#define EM_BLE_RXISOBUFPTR_INDEX  0x00000004
+#define EM_BLE_RXISOBUFPTR_RESET  0x00000000
+
+__INLINE uint16_t em_ble_rxisobufptr_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_RXISOBUFPTR_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE);
+}
+
+__INLINE void em_ble_rxisobufptr_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_RXISOBUFPTR_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_RXISOBUFPTR_MASK   ((uint16_t)0x00003FFF)
+#define EM_BLE_RXISOBUFPTR_LSB    0
+#define EM_BLE_RXISOBUFPTR_WIDTH  ((uint16_t)0x0000000E)
+
+#define EM_BLE_RXISOBUFPTR_RST    0x0
+
+__INLINE uint16_t em_ble_rxisobufptr_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RXISOBUFPTR_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE);
+    ASSERT_ERR((localVal & ~((uint16_t)0x00003FFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void em_ble_rxisobufptr_setf(int elt_idx, uint16_t rxisobufptr)
+{
+    ASSERT_ERR((((uint16_t)rxisobufptr << 0) & ~((uint16_t)0x00003FFF)) == 0);
+    EM_BLE_WR(EM_BLE_RXISOBUFPTR_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE, (uint16_t)rxisobufptr << 0);
+}
+
+/**
+ * @brief RXISORESERVED register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  15:00                 RSVD   0x0
+ * </pre>
+ */
+#define EM_BLE_RXISORESERVED_ADDR   (0x5300400A + EM_BLE_RX_ISO_DESC_OFFSET)
+#define EM_BLE_RXISORESERVED_INDEX  0x00000005
+#define EM_BLE_RXISORESERVED_RESET  0x00000000
+
+__INLINE uint16_t em_ble_rxisoreserved_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_RXISORESERVED_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE);
+}
+
+__INLINE void em_ble_rxisoreserved_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_RXISORESERVED_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_RSVD_MASK   ((uint16_t)0x0000FFFF)
+#define EM_BLE_RSVD_LSB    0
+#define EM_BLE_RSVD_WIDTH  ((uint16_t)0x00000010)
+
+#define EM_BLE_RSVD_RST    0x0
+
+__INLINE uint16_t em_ble_rxisoreserved_rsvd_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_RXISORESERVED_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE);
+    ASSERT_ERR((localVal & ~((uint16_t)0x0000FFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void em_ble_rxisoreserved_rsvd_setf(int elt_idx, uint16_t rsvd)
+{
+    ASSERT_ERR((((uint16_t)rsvd << 0) & ~((uint16_t)0x0000FFFF)) == 0);
+    EM_BLE_WR(EM_BLE_RXISORESERVED_ADDR + elt_idx * REG_EM_BLE_RX_ISO_DESC_SIZE, (uint16_t)rsvd << 0);
+}
+
+
+#endif // _REG_EM_BLE_RX_ISO_DESC_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/reg_em_ble_tx_desc.h

@@ -0,0 +1,974 @@
+#ifndef _REG_EM_BLE_TX_DESC_H_
+#define _REG_EM_BLE_TX_DESC_H_
+
+#include <stdint.h>
+#include "_reg_em_ble_tx_desc.h"
+#include "compiler.h"
+#include "arch.h"
+#include "em_map.h"
+#include "reg_access.h"
+
+#define REG_EM_BLE_TX_DESC_COUNT 8
+
+#define REG_EM_BLE_TX_DESC_DECODING_MASK 0x0000000F
+
+#define REG_EM_BLE_TX_DESC_ADDR_GET(idx) (EM_BLE_TX_DESC_OFFSET + (idx) * REG_EM_BLE_TX_DESC_SIZE)
+
+/**
+ * @brief TXCNTL register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     15               TXDONE   0
+ *  13:00              NEXTPTR   0x0
+ * </pre>
+ */
+#define EM_BLE_TXCNTL_ADDR   (0x53004000 + EM_BLE_TX_DESC_OFFSET)
+#define EM_BLE_TXCNTL_INDEX  0x00000000
+#define EM_BLE_TXCNTL_RESET  0x00000000
+
+__INLINE uint16_t em_ble_txcntl_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_TXCNTL_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+}
+
+__INLINE void em_ble_txcntl_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_TXCNTL_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_TXDONE_BIT     ((uint16_t)0x00008000)
+#define EM_BLE_TXDONE_POS     15
+#define EM_BLE_NEXTPTR_MASK   ((uint16_t)0x00003FFF)
+#define EM_BLE_NEXTPTR_LSB    0
+#define EM_BLE_NEXTPTR_WIDTH  ((uint16_t)0x0000000E)
+
+#define EM_BLE_TXDONE_RST     0x0
+#define EM_BLE_NEXTPTR_RST    0x0
+
+__INLINE void em_ble_txcntl_pack(int elt_idx, uint8_t txdone, uint16_t nextptr)
+{
+    ASSERT_ERR((((uint16_t)txdone << 15) & ~((uint16_t)0x00008000)) == 0);
+    ASSERT_ERR((((uint16_t)nextptr << 0) & ~((uint16_t)0x00003FFF)) == 0);
+    EM_BLE_WR(EM_BLE_TXCNTL_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE,  ((uint16_t)txdone << 15) | ((uint16_t)nextptr << 0));
+}
+
+__INLINE void em_ble_txcntl_unpack(int elt_idx, uint8_t* txdone, uint16_t* nextptr)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXCNTL_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+
+    *txdone = (localVal & ((uint16_t)0x00008000)) >> 15;
+    *nextptr = (localVal & ((uint16_t)0x00003FFF)) >> 0;
+}
+
+__INLINE uint8_t em_ble_txcntl_txdone_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXCNTL_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00008000)) >> 15);
+}
+
+__INLINE void em_ble_txcntl_txdone_setf(int elt_idx, uint8_t txdone)
+{
+    ASSERT_ERR((((uint16_t)txdone << 15) & ~((uint16_t)0x00008000)) == 0);
+    EM_BLE_WR(EM_BLE_TXCNTL_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXCNTL_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x00008000)) | ((uint16_t)txdone << 15));
+}
+
+__INLINE uint16_t em_ble_txcntl_nextptr_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXCNTL_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00003FFF)) >> 0);
+}
+
+__INLINE void em_ble_txcntl_nextptr_setf(int elt_idx, uint16_t nextptr)
+{
+    ASSERT_ERR((((uint16_t)nextptr << 0) & ~((uint16_t)0x00003FFF)) == 0);
+    EM_BLE_WR(EM_BLE_TXCNTL_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXCNTL_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x00003FFF)) | ((uint16_t)nextptr << 0));
+}
+
+/**
+ * @brief TXPHCE register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  15:08                TXLEN   0x0
+ *  07:06             TXACLRFU   0x0
+ *     05                 TXCP   0
+ *     04                 TXMD   0
+ *     03                 TXSN   0
+ *     02               TXNESN   0
+ *  01:00               TXLLID   0x0
+ * </pre>
+ */
+#define EM_BLE_TXPHCE_ADDR   (0x53004002 + EM_BLE_TX_DESC_OFFSET)
+#define EM_BLE_TXPHCE_INDEX  0x00000001
+#define EM_BLE_TXPHCE_RESET  0x00000000
+
+__INLINE uint16_t em_ble_txphce_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_TXPHCE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+}
+
+__INLINE void em_ble_txphce_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_TXPHCE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_TXLEN_MASK      ((uint16_t)0x0000FF00)
+#define EM_BLE_TXLEN_LSB       8
+#define EM_BLE_TXLEN_WIDTH     ((uint16_t)0x00000008)
+#define EM_BLE_TXACLRFU_MASK   ((uint16_t)0x000000C0)
+#define EM_BLE_TXACLRFU_LSB    6
+#define EM_BLE_TXACLRFU_WIDTH  ((uint16_t)0x00000002)
+#define EM_BLE_TXCP_BIT        ((uint16_t)0x00000020)
+#define EM_BLE_TXCP_POS        5
+#define EM_BLE_TXMD_BIT        ((uint16_t)0x00000010)
+#define EM_BLE_TXMD_POS        4
+#define EM_BLE_TXSN_BIT        ((uint16_t)0x00000008)
+#define EM_BLE_TXSN_POS        3
+#define EM_BLE_TXNESN_BIT      ((uint16_t)0x00000004)
+#define EM_BLE_TXNESN_POS      2
+#define EM_BLE_TXLLID_MASK     ((uint16_t)0x00000003)
+#define EM_BLE_TXLLID_LSB      0
+#define EM_BLE_TXLLID_WIDTH    ((uint16_t)0x00000002)
+
+#define EM_BLE_TXLEN_RST       0x0
+#define EM_BLE_TXACLRFU_RST    0x0
+#define EM_BLE_TXCP_RST        0x0
+#define EM_BLE_TXMD_RST        0x0
+#define EM_BLE_TXSN_RST        0x0
+#define EM_BLE_TXNESN_RST      0x0
+#define EM_BLE_TXLLID_RST      0x0
+
+__INLINE void em_ble_txphce_pack(int elt_idx, uint8_t txlen, uint8_t txaclrfu, uint8_t txcp, uint8_t txmd, uint8_t txsn, uint8_t txnesn, uint8_t txllid)
+{
+    ASSERT_ERR((((uint16_t)txlen << 8) & ~((uint16_t)0x0000FF00)) == 0);
+    ASSERT_ERR((((uint16_t)txaclrfu << 6) & ~((uint16_t)0x000000C0)) == 0);
+    ASSERT_ERR((((uint16_t)txcp << 5) & ~((uint16_t)0x00000020)) == 0);
+    ASSERT_ERR((((uint16_t)txmd << 4) & ~((uint16_t)0x00000010)) == 0);
+    ASSERT_ERR((((uint16_t)txsn << 3) & ~((uint16_t)0x00000008)) == 0);
+    ASSERT_ERR((((uint16_t)txnesn << 2) & ~((uint16_t)0x00000004)) == 0);
+    ASSERT_ERR((((uint16_t)txllid << 0) & ~((uint16_t)0x00000003)) == 0);
+    EM_BLE_WR(EM_BLE_TXPHCE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE,  ((uint16_t)txlen << 8) | ((uint16_t)txaclrfu << 6) | ((uint16_t)txcp << 5) | ((uint16_t)txmd << 4) | ((uint16_t)txsn << 3) | ((uint16_t)txnesn << 2) | ((uint16_t)txllid << 0));
+}
+
+__INLINE void em_ble_txphce_unpack(int elt_idx, uint8_t* txlen, uint8_t* txaclrfu, uint8_t* txcp, uint8_t* txmd, uint8_t* txsn, uint8_t* txnesn, uint8_t* txllid)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXPHCE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+
+    *txlen = (localVal & ((uint16_t)0x0000FF00)) >> 8;
+    *txaclrfu = (localVal & ((uint16_t)0x000000C0)) >> 6;
+    *txcp = (localVal & ((uint16_t)0x00000020)) >> 5;
+    *txmd = (localVal & ((uint16_t)0x00000010)) >> 4;
+    *txsn = (localVal & ((uint16_t)0x00000008)) >> 3;
+    *txnesn = (localVal & ((uint16_t)0x00000004)) >> 2;
+    *txllid = (localVal & ((uint16_t)0x00000003)) >> 0;
+}
+
+__INLINE uint8_t em_ble_txphce_txlen_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXPHCE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x0000FF00)) >> 8);
+}
+
+__INLINE void em_ble_txphce_txlen_setf(int elt_idx, uint8_t txlen)
+{
+    ASSERT_ERR((((uint16_t)txlen << 8) & ~((uint16_t)0x0000FF00)) == 0);
+    EM_BLE_WR(EM_BLE_TXPHCE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXPHCE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x0000FF00)) | ((uint16_t)txlen << 8));
+}
+
+__INLINE uint8_t em_ble_txphce_txaclrfu_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXPHCE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x000000C0)) >> 6);
+}
+
+__INLINE void em_ble_txphce_txaclrfu_setf(int elt_idx, uint8_t txaclrfu)
+{
+    ASSERT_ERR((((uint16_t)txaclrfu << 6) & ~((uint16_t)0x000000C0)) == 0);
+    EM_BLE_WR(EM_BLE_TXPHCE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXPHCE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x000000C0)) | ((uint16_t)txaclrfu << 6));
+}
+
+__INLINE uint8_t em_ble_txphce_txcp_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXPHCE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00000020)) >> 5);
+}
+
+__INLINE void em_ble_txphce_txcp_setf(int elt_idx, uint8_t txcp)
+{
+    ASSERT_ERR((((uint16_t)txcp << 5) & ~((uint16_t)0x00000020)) == 0);
+    EM_BLE_WR(EM_BLE_TXPHCE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXPHCE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x00000020)) | ((uint16_t)txcp << 5));
+}
+
+__INLINE uint8_t em_ble_txphce_txmd_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXPHCE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00000010)) >> 4);
+}
+
+__INLINE void em_ble_txphce_txmd_setf(int elt_idx, uint8_t txmd)
+{
+    ASSERT_ERR((((uint16_t)txmd << 4) & ~((uint16_t)0x00000010)) == 0);
+    EM_BLE_WR(EM_BLE_TXPHCE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXPHCE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x00000010)) | ((uint16_t)txmd << 4));
+}
+
+__INLINE uint8_t em_ble_txphce_txsn_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXPHCE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00000008)) >> 3);
+}
+
+__INLINE void em_ble_txphce_txsn_setf(int elt_idx, uint8_t txsn)
+{
+    ASSERT_ERR((((uint16_t)txsn << 3) & ~((uint16_t)0x00000008)) == 0);
+    EM_BLE_WR(EM_BLE_TXPHCE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXPHCE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x00000008)) | ((uint16_t)txsn << 3));
+}
+
+__INLINE uint8_t em_ble_txphce_txnesn_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXPHCE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00000004)) >> 2);
+}
+
+__INLINE void em_ble_txphce_txnesn_setf(int elt_idx, uint8_t txnesn)
+{
+    ASSERT_ERR((((uint16_t)txnesn << 2) & ~((uint16_t)0x00000004)) == 0);
+    EM_BLE_WR(EM_BLE_TXPHCE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXPHCE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x00000004)) | ((uint16_t)txnesn << 2));
+}
+
+__INLINE uint8_t em_ble_txphce_txllid_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXPHCE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00000003)) >> 0);
+}
+
+__INLINE void em_ble_txphce_txllid_setf(int elt_idx, uint8_t txllid)
+{
+    ASSERT_ERR((((uint16_t)txllid << 0) & ~((uint16_t)0x00000003)) == 0);
+    EM_BLE_WR(EM_BLE_TXPHCE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXPHCE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x00000003)) | ((uint16_t)txllid << 0));
+}
+
+/**
+ * @brief TXPHADV register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  15:08             TXADVLEN   0x0
+ *     07              TXRXADD   0
+ *     06              TXTXADD   0
+ *     05             TXCHSEL2   0
+ *     04             TXADVRFU   0
+ *  03:00               TXTYPE   0x0
+ * </pre>
+ */
+#define EM_BLE_TXPHADV_ADDR   (0x53004002 + EM_BLE_TX_DESC_OFFSET)
+#define EM_BLE_TXPHADV_INDEX  0x00000001
+#define EM_BLE_TXPHADV_RESET  0x00000000
+
+__INLINE uint16_t em_ble_txphadv_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_TXPHADV_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+}
+
+__INLINE void em_ble_txphadv_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_TXPHADV_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_TXADVLEN_MASK   ((uint16_t)0x0000FF00)
+#define EM_BLE_TXADVLEN_LSB    8
+#define EM_BLE_TXADVLEN_WIDTH  ((uint16_t)0x00000008)
+#define EM_BLE_TXRXADD_BIT     ((uint16_t)0x00000080)
+#define EM_BLE_TXRXADD_POS     7
+#define EM_BLE_TXTXADD_BIT     ((uint16_t)0x00000040)
+#define EM_BLE_TXTXADD_POS     6
+#define EM_BLE_TXCHSEL2_BIT    ((uint16_t)0x00000020)
+#define EM_BLE_TXCHSEL2_POS    5
+#define EM_BLE_TXADVRFU_BIT    ((uint16_t)0x00000010)
+#define EM_BLE_TXADVRFU_POS    4
+#define EM_BLE_TXTYPE_MASK     ((uint16_t)0x0000000F)
+#define EM_BLE_TXTYPE_LSB      0
+#define EM_BLE_TXTYPE_WIDTH    ((uint16_t)0x00000004)
+
+#define EM_BLE_TXADVLEN_RST    0x0
+#define EM_BLE_TXRXADD_RST     0x0
+#define EM_BLE_TXTXADD_RST     0x0
+#define EM_BLE_TXCHSEL2_RST    0x0
+#define EM_BLE_TXADVRFU_RST    0x0
+#define EM_BLE_TXTYPE_RST      0x0
+
+__INLINE void em_ble_txphadv_pack(int elt_idx, uint8_t txadvlen, uint8_t txrxadd, uint8_t txtxadd, uint8_t txchsel2, uint8_t txadvrfu, uint8_t txtype)
+{
+    ASSERT_ERR((((uint16_t)txadvlen << 8) & ~((uint16_t)0x0000FF00)) == 0);
+    ASSERT_ERR((((uint16_t)txrxadd << 7) & ~((uint16_t)0x00000080)) == 0);
+    ASSERT_ERR((((uint16_t)txtxadd << 6) & ~((uint16_t)0x00000040)) == 0);
+    ASSERT_ERR((((uint16_t)txchsel2 << 5) & ~((uint16_t)0x00000020)) == 0);
+    ASSERT_ERR((((uint16_t)txadvrfu << 4) & ~((uint16_t)0x00000010)) == 0);
+    ASSERT_ERR((((uint16_t)txtype << 0) & ~((uint16_t)0x0000000F)) == 0);
+    EM_BLE_WR(EM_BLE_TXPHADV_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE,  ((uint16_t)txadvlen << 8) | ((uint16_t)txrxadd << 7) | ((uint16_t)txtxadd << 6) | ((uint16_t)txchsel2 << 5) | ((uint16_t)txadvrfu << 4) | ((uint16_t)txtype << 0));
+}
+
+__INLINE void em_ble_txphadv_unpack(int elt_idx, uint8_t* txadvlen, uint8_t* txrxadd, uint8_t* txtxadd, uint8_t* txchsel2, uint8_t* txadvrfu, uint8_t* txtype)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXPHADV_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+
+    *txadvlen = (localVal & ((uint16_t)0x0000FF00)) >> 8;
+    *txrxadd = (localVal & ((uint16_t)0x00000080)) >> 7;
+    *txtxadd = (localVal & ((uint16_t)0x00000040)) >> 6;
+    *txchsel2 = (localVal & ((uint16_t)0x00000020)) >> 5;
+    *txadvrfu = (localVal & ((uint16_t)0x00000010)) >> 4;
+    *txtype = (localVal & ((uint16_t)0x0000000F)) >> 0;
+}
+
+__INLINE uint8_t em_ble_txphadv_txadvlen_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXPHADV_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x0000FF00)) >> 8);
+}
+
+__INLINE void em_ble_txphadv_txadvlen_setf(int elt_idx, uint8_t txadvlen)
+{
+    ASSERT_ERR((((uint16_t)txadvlen << 8) & ~((uint16_t)0x0000FF00)) == 0);
+    EM_BLE_WR(EM_BLE_TXPHADV_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXPHADV_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x0000FF00)) | ((uint16_t)txadvlen << 8));
+}
+
+__INLINE uint8_t em_ble_txphadv_txrxadd_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXPHADV_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00000080)) >> 7);
+}
+
+__INLINE void em_ble_txphadv_txrxadd_setf(int elt_idx, uint8_t txrxadd)
+{
+    ASSERT_ERR((((uint16_t)txrxadd << 7) & ~((uint16_t)0x00000080)) == 0);
+    EM_BLE_WR(EM_BLE_TXPHADV_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXPHADV_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x00000080)) | ((uint16_t)txrxadd << 7));
+}
+
+__INLINE uint8_t em_ble_txphadv_txtxadd_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXPHADV_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00000040)) >> 6);
+}
+
+__INLINE void em_ble_txphadv_txtxadd_setf(int elt_idx, uint8_t txtxadd)
+{
+    ASSERT_ERR((((uint16_t)txtxadd << 6) & ~((uint16_t)0x00000040)) == 0);
+    EM_BLE_WR(EM_BLE_TXPHADV_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXPHADV_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x00000040)) | ((uint16_t)txtxadd << 6));
+}
+
+__INLINE uint8_t em_ble_txphadv_txchsel2_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXPHADV_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00000020)) >> 5);
+}
+
+__INLINE void em_ble_txphadv_txchsel2_setf(int elt_idx, uint8_t txchsel2)
+{
+    ASSERT_ERR((((uint16_t)txchsel2 << 5) & ~((uint16_t)0x00000020)) == 0);
+    EM_BLE_WR(EM_BLE_TXPHADV_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXPHADV_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x00000020)) | ((uint16_t)txchsel2 << 5));
+}
+
+__INLINE uint8_t em_ble_txphadv_txadvrfu_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXPHADV_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00000010)) >> 4);
+}
+
+__INLINE void em_ble_txphadv_txadvrfu_setf(int elt_idx, uint8_t txadvrfu)
+{
+    ASSERT_ERR((((uint16_t)txadvrfu << 4) & ~((uint16_t)0x00000010)) == 0);
+    EM_BLE_WR(EM_BLE_TXPHADV_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXPHADV_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x00000010)) | ((uint16_t)txadvrfu << 4));
+}
+
+__INLINE uint8_t em_ble_txphadv_txtype_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXPHADV_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x0000000F)) >> 0);
+}
+
+__INLINE void em_ble_txphadv_txtype_setf(int elt_idx, uint8_t txtype)
+{
+    ASSERT_ERR((((uint16_t)txtype << 0) & ~((uint16_t)0x0000000F)) == 0);
+    EM_BLE_WR(EM_BLE_TXPHADV_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXPHADV_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x0000000F)) | ((uint16_t)txtype << 0));
+}
+
+/**
+ * @brief TXDATAPTR register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  15:00            TXDATAPTR   0x0
+ * </pre>
+ */
+#define EM_BLE_TXDATAPTR_ADDR   (0x53004004 + EM_BLE_TX_DESC_OFFSET)
+#define EM_BLE_TXDATAPTR_INDEX  0x00000002
+#define EM_BLE_TXDATAPTR_RESET  0x00000000
+
+__INLINE uint16_t em_ble_txdataptr_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_TXDATAPTR_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+}
+
+__INLINE void em_ble_txdataptr_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_TXDATAPTR_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_TXDATAPTR_MASK   ((uint16_t)0x0000FFFF)
+#define EM_BLE_TXDATAPTR_LSB    0
+#define EM_BLE_TXDATAPTR_WIDTH  ((uint16_t)0x00000010)
+
+#define EM_BLE_TXDATAPTR_RST    0x0
+
+__INLINE uint16_t em_ble_txdataptr_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXDATAPTR_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    ASSERT_ERR((localVal & ~((uint16_t)0x0000FFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void em_ble_txdataptr_setf(int elt_idx, uint16_t txdataptr)
+{
+    ASSERT_ERR((((uint16_t)txdataptr << 0) & ~((uint16_t)0x0000FFFF)) == 0);
+    EM_BLE_WR(EM_BLE_TXDATAPTR_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (uint16_t)txdataptr << 0);
+}
+
+/**
+ * @brief TXAEHEADER register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     15               TXRSVD   0
+ *     14                TXPOW   0
+ *     13               TXSYNC   0
+ *     12             TXAUXPTR   0
+ *     11                TXADI   0
+ *     10               TXSUPP   0
+ *     09               TXTGTA   0
+ *     08               TXADVA   0
+ *  07:06             TXAEMODE   0x0
+ *  05:00           TXAELENGTH   0x0
+ * </pre>
+ */
+#define EM_BLE_TXAEHEADER_ADDR   (0x53004006 + EM_BLE_TX_DESC_OFFSET)
+#define EM_BLE_TXAEHEADER_INDEX  0x00000003
+#define EM_BLE_TXAEHEADER_RESET  0x00000000
+
+__INLINE uint16_t em_ble_txaeheader_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+}
+
+__INLINE void em_ble_txaeheader_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_TXRSVD_BIT        ((uint16_t)0x00008000)
+#define EM_BLE_TXRSVD_POS        15
+#define EM_BLE_TXPOW_BIT         ((uint16_t)0x00004000)
+#define EM_BLE_TXPOW_POS         14
+#define EM_BLE_TXSYNC_BIT        ((uint16_t)0x00002000)
+#define EM_BLE_TXSYNC_POS        13
+#define EM_BLE_TXAUXPTR_BIT      ((uint16_t)0x00001000)
+#define EM_BLE_TXAUXPTR_POS      12
+#define EM_BLE_TXADI_BIT         ((uint16_t)0x00000800)
+#define EM_BLE_TXADI_POS         11
+#define EM_BLE_TXSUPP_BIT        ((uint16_t)0x00000400)
+#define EM_BLE_TXSUPP_POS        10
+#define EM_BLE_TXTGTA_BIT        ((uint16_t)0x00000200)
+#define EM_BLE_TXTGTA_POS        9
+#define EM_BLE_TXADVA_BIT        ((uint16_t)0x00000100)
+#define EM_BLE_TXADVA_POS        8
+#define EM_BLE_TXAEMODE_MASK     ((uint16_t)0x000000C0)
+#define EM_BLE_TXAEMODE_LSB      6
+#define EM_BLE_TXAEMODE_WIDTH    ((uint16_t)0x00000002)
+#define EM_BLE_TXAELENGTH_MASK   ((uint16_t)0x0000003F)
+#define EM_BLE_TXAELENGTH_LSB    0
+#define EM_BLE_TXAELENGTH_WIDTH  ((uint16_t)0x00000006)
+
+#define EM_BLE_TXRSVD_RST        0x0
+#define EM_BLE_TXPOW_RST         0x0
+#define EM_BLE_TXSYNC_RST        0x0
+#define EM_BLE_TXAUXPTR_RST      0x0
+#define EM_BLE_TXADI_RST         0x0
+#define EM_BLE_TXSUPP_RST        0x0
+#define EM_BLE_TXTGTA_RST        0x0
+#define EM_BLE_TXADVA_RST        0x0
+#define EM_BLE_TXAEMODE_RST      0x0
+#define EM_BLE_TXAELENGTH_RST    0x0
+
+__INLINE void em_ble_txaeheader_pack(int elt_idx, uint8_t txrsvd, uint8_t txpow, uint8_t txsync, uint8_t txauxptr, uint8_t txadi, uint8_t txsupp, uint8_t txtgta, uint8_t txadva, uint8_t txaemode, uint8_t txaelength)
+{
+    ASSERT_ERR((((uint16_t)txrsvd << 15) & ~((uint16_t)0x00008000)) == 0);
+    ASSERT_ERR((((uint16_t)txpow << 14) & ~((uint16_t)0x00004000)) == 0);
+    ASSERT_ERR((((uint16_t)txsync << 13) & ~((uint16_t)0x00002000)) == 0);
+    ASSERT_ERR((((uint16_t)txauxptr << 12) & ~((uint16_t)0x00001000)) == 0);
+    ASSERT_ERR((((uint16_t)txadi << 11) & ~((uint16_t)0x00000800)) == 0);
+    ASSERT_ERR((((uint16_t)txsupp << 10) & ~((uint16_t)0x00000400)) == 0);
+    ASSERT_ERR((((uint16_t)txtgta << 9) & ~((uint16_t)0x00000200)) == 0);
+    ASSERT_ERR((((uint16_t)txadva << 8) & ~((uint16_t)0x00000100)) == 0);
+    ASSERT_ERR((((uint16_t)txaemode << 6) & ~((uint16_t)0x000000C0)) == 0);
+    ASSERT_ERR((((uint16_t)txaelength << 0) & ~((uint16_t)0x0000003F)) == 0);
+    EM_BLE_WR(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE,  ((uint16_t)txrsvd << 15) | ((uint16_t)txpow << 14) | ((uint16_t)txsync << 13) | ((uint16_t)txauxptr << 12) | ((uint16_t)txadi << 11) | ((uint16_t)txsupp << 10) | ((uint16_t)txtgta << 9) | ((uint16_t)txadva << 8) | ((uint16_t)txaemode << 6) | ((uint16_t)txaelength << 0));
+}
+
+__INLINE void em_ble_txaeheader_unpack(int elt_idx, uint8_t* txrsvd, uint8_t* txpow, uint8_t* txsync, uint8_t* txauxptr, uint8_t* txadi, uint8_t* txsupp, uint8_t* txtgta, uint8_t* txadva, uint8_t* txaemode, uint8_t* txaelength)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+
+    *txrsvd = (localVal & ((uint16_t)0x00008000)) >> 15;
+    *txpow = (localVal & ((uint16_t)0x00004000)) >> 14;
+    *txsync = (localVal & ((uint16_t)0x00002000)) >> 13;
+    *txauxptr = (localVal & ((uint16_t)0x00001000)) >> 12;
+    *txadi = (localVal & ((uint16_t)0x00000800)) >> 11;
+    *txsupp = (localVal & ((uint16_t)0x00000400)) >> 10;
+    *txtgta = (localVal & ((uint16_t)0x00000200)) >> 9;
+    *txadva = (localVal & ((uint16_t)0x00000100)) >> 8;
+    *txaemode = (localVal & ((uint16_t)0x000000C0)) >> 6;
+    *txaelength = (localVal & ((uint16_t)0x0000003F)) >> 0;
+}
+
+__INLINE uint8_t em_ble_txaeheader_txrsvd_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00008000)) >> 15);
+}
+
+__INLINE void em_ble_txaeheader_txrsvd_setf(int elt_idx, uint8_t txrsvd)
+{
+    ASSERT_ERR((((uint16_t)txrsvd << 15) & ~((uint16_t)0x00008000)) == 0);
+    EM_BLE_WR(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x00008000)) | ((uint16_t)txrsvd << 15));
+}
+
+__INLINE uint8_t em_ble_txaeheader_txpow_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00004000)) >> 14);
+}
+
+__INLINE void em_ble_txaeheader_txpow_setf(int elt_idx, uint8_t txpow)
+{
+    ASSERT_ERR((((uint16_t)txpow << 14) & ~((uint16_t)0x00004000)) == 0);
+    EM_BLE_WR(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x00004000)) | ((uint16_t)txpow << 14));
+}
+
+__INLINE uint8_t em_ble_txaeheader_txsync_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00002000)) >> 13);
+}
+
+__INLINE void em_ble_txaeheader_txsync_setf(int elt_idx, uint8_t txsync)
+{
+    ASSERT_ERR((((uint16_t)txsync << 13) & ~((uint16_t)0x00002000)) == 0);
+    EM_BLE_WR(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x00002000)) | ((uint16_t)txsync << 13));
+}
+
+__INLINE uint8_t em_ble_txaeheader_txauxptr_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00001000)) >> 12);
+}
+
+__INLINE void em_ble_txaeheader_txauxptr_setf(int elt_idx, uint8_t txauxptr)
+{
+    ASSERT_ERR((((uint16_t)txauxptr << 12) & ~((uint16_t)0x00001000)) == 0);
+    EM_BLE_WR(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x00001000)) | ((uint16_t)txauxptr << 12));
+}
+
+__INLINE uint8_t em_ble_txaeheader_txadi_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00000800)) >> 11);
+}
+
+__INLINE void em_ble_txaeheader_txadi_setf(int elt_idx, uint8_t txadi)
+{
+    ASSERT_ERR((((uint16_t)txadi << 11) & ~((uint16_t)0x00000800)) == 0);
+    EM_BLE_WR(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x00000800)) | ((uint16_t)txadi << 11));
+}
+
+__INLINE uint8_t em_ble_txaeheader_txsupp_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00000400)) >> 10);
+}
+
+__INLINE void em_ble_txaeheader_txsupp_setf(int elt_idx, uint8_t txsupp)
+{
+    ASSERT_ERR((((uint16_t)txsupp << 10) & ~((uint16_t)0x00000400)) == 0);
+    EM_BLE_WR(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x00000400)) | ((uint16_t)txsupp << 10));
+}
+
+__INLINE uint8_t em_ble_txaeheader_txtgta_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00000200)) >> 9);
+}
+
+__INLINE void em_ble_txaeheader_txtgta_setf(int elt_idx, uint8_t txtgta)
+{
+    ASSERT_ERR((((uint16_t)txtgta << 9) & ~((uint16_t)0x00000200)) == 0);
+    EM_BLE_WR(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x00000200)) | ((uint16_t)txtgta << 9));
+}
+
+__INLINE uint8_t em_ble_txaeheader_txadva_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00000100)) >> 8);
+}
+
+__INLINE void em_ble_txaeheader_txadva_setf(int elt_idx, uint8_t txadva)
+{
+    ASSERT_ERR((((uint16_t)txadva << 8) & ~((uint16_t)0x00000100)) == 0);
+    EM_BLE_WR(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x00000100)) | ((uint16_t)txadva << 8));
+}
+
+__INLINE uint8_t em_ble_txaeheader_txaemode_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x000000C0)) >> 6);
+}
+
+__INLINE void em_ble_txaeheader_txaemode_setf(int elt_idx, uint8_t txaemode)
+{
+    ASSERT_ERR((((uint16_t)txaemode << 6) & ~((uint16_t)0x000000C0)) == 0);
+    EM_BLE_WR(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x000000C0)) | ((uint16_t)txaemode << 6));
+}
+
+__INLINE uint8_t em_ble_txaeheader_txaelength_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x0000003F)) >> 0);
+}
+
+__INLINE void em_ble_txaeheader_txaelength_setf(int elt_idx, uint8_t txaelength)
+{
+    ASSERT_ERR((((uint16_t)txaelength << 0) & ~((uint16_t)0x0000003F)) == 0);
+    EM_BLE_WR(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXAEHEADER_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x0000003F)) | ((uint16_t)txaelength << 0));
+}
+
+/**
+ * @brief TXAUXPTR0 register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  15:08      TXAUXOFFSET_LSB   0x0
+ *     07     TXAUXOFFSET_UNIT   0
+ *     06             TXAUX_CA   0
+ *  05:00             TX_LL_CH   0x0
+ * </pre>
+ */
+#define EM_BLE_TXAUXPTR0_ADDR   (0x53004008 + EM_BLE_TX_DESC_OFFSET)
+#define EM_BLE_TXAUXPTR0_INDEX  0x00000004
+#define EM_BLE_TXAUXPTR0_RESET  0x00000000
+
+__INLINE uint16_t em_ble_txauxptr0_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_TXAUXPTR0_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+}
+
+__INLINE void em_ble_txauxptr0_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_TXAUXPTR0_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_TXAUXOFFSET_LSB_MASK    ((uint16_t)0x0000FF00)
+#define EM_BLE_TXAUXOFFSET_LSB_LSB     8
+#define EM_BLE_TXAUXOFFSET_LSB_WIDTH   ((uint16_t)0x00000008)
+#define EM_BLE_TXAUXOFFSET_UNIT_BIT    ((uint16_t)0x00000080)
+#define EM_BLE_TXAUXOFFSET_UNIT_POS    7
+#define EM_BLE_TXAUX_CA_BIT            ((uint16_t)0x00000040)
+#define EM_BLE_TXAUX_CA_POS            6
+#define EM_BLE_TX_LL_CH_MASK           ((uint16_t)0x0000003F)
+#define EM_BLE_TX_LL_CH_LSB            0
+#define EM_BLE_TX_LL_CH_WIDTH          ((uint16_t)0x00000006)
+
+#define EM_BLE_TXAUXOFFSET_LSB_RST     0x0
+#define EM_BLE_TXAUXOFFSET_UNIT_RST    0x0
+#define EM_BLE_TXAUX_CA_RST            0x0
+#define EM_BLE_TX_LL_CH_RST            0x0
+
+__INLINE void em_ble_txauxptr0_pack(int elt_idx, uint8_t txauxoffsetlsb, uint8_t txauxoffsetunit, uint8_t txauxca, uint8_t txllch)
+{
+    ASSERT_ERR((((uint16_t)txauxoffsetlsb << 8) & ~((uint16_t)0x0000FF00)) == 0);
+    ASSERT_ERR((((uint16_t)txauxoffsetunit << 7) & ~((uint16_t)0x00000080)) == 0);
+    ASSERT_ERR((((uint16_t)txauxca << 6) & ~((uint16_t)0x00000040)) == 0);
+    ASSERT_ERR((((uint16_t)txllch << 0) & ~((uint16_t)0x0000003F)) == 0);
+    EM_BLE_WR(EM_BLE_TXAUXPTR0_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE,  ((uint16_t)txauxoffsetlsb << 8) | ((uint16_t)txauxoffsetunit << 7) | ((uint16_t)txauxca << 6) | ((uint16_t)txllch << 0));
+}
+
+__INLINE void em_ble_txauxptr0_unpack(int elt_idx, uint8_t* txauxoffsetlsb, uint8_t* txauxoffsetunit, uint8_t* txauxca, uint8_t* txllch)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXAUXPTR0_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+
+    *txauxoffsetlsb = (localVal & ((uint16_t)0x0000FF00)) >> 8;
+    *txauxoffsetunit = (localVal & ((uint16_t)0x00000080)) >> 7;
+    *txauxca = (localVal & ((uint16_t)0x00000040)) >> 6;
+    *txllch = (localVal & ((uint16_t)0x0000003F)) >> 0;
+}
+
+__INLINE uint8_t em_ble_txauxptr0_txauxoffset_lsb_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXAUXPTR0_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x0000FF00)) >> 8);
+}
+
+__INLINE void em_ble_txauxptr0_txauxoffset_lsb_setf(int elt_idx, uint8_t txauxoffsetlsb)
+{
+    ASSERT_ERR((((uint16_t)txauxoffsetlsb << 8) & ~((uint16_t)0x0000FF00)) == 0);
+    EM_BLE_WR(EM_BLE_TXAUXPTR0_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXAUXPTR0_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x0000FF00)) | ((uint16_t)txauxoffsetlsb << 8));
+}
+
+__INLINE uint8_t em_ble_txauxptr0_txauxoffset_unit_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXAUXPTR0_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00000080)) >> 7);
+}
+
+__INLINE void em_ble_txauxptr0_txauxoffset_unit_setf(int elt_idx, uint8_t txauxoffsetunit)
+{
+    ASSERT_ERR((((uint16_t)txauxoffsetunit << 7) & ~((uint16_t)0x00000080)) == 0);
+    EM_BLE_WR(EM_BLE_TXAUXPTR0_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXAUXPTR0_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x00000080)) | ((uint16_t)txauxoffsetunit << 7));
+}
+
+__INLINE uint8_t em_ble_txauxptr0_txaux_ca_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXAUXPTR0_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00000040)) >> 6);
+}
+
+__INLINE void em_ble_txauxptr0_txaux_ca_setf(int elt_idx, uint8_t txauxca)
+{
+    ASSERT_ERR((((uint16_t)txauxca << 6) & ~((uint16_t)0x00000040)) == 0);
+    EM_BLE_WR(EM_BLE_TXAUXPTR0_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXAUXPTR0_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x00000040)) | ((uint16_t)txauxca << 6));
+}
+
+__INLINE uint8_t em_ble_txauxptr0_tx_ll_ch_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXAUXPTR0_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x0000003F)) >> 0);
+}
+
+__INLINE void em_ble_txauxptr0_tx_ll_ch_setf(int elt_idx, uint8_t txllch)
+{
+    ASSERT_ERR((((uint16_t)txllch << 0) & ~((uint16_t)0x0000003F)) == 0);
+    EM_BLE_WR(EM_BLE_TXAUXPTR0_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXAUXPTR0_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x0000003F)) | ((uint16_t)txllch << 0));
+}
+
+/**
+ * @brief TXAUXPTR1 register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  07:05            TXAUX_PHY   0x0
+ *  04:00      TXAUXOFFSET_MSB   0x0
+ * </pre>
+ */
+#define EM_BLE_TXAUXPTR1_ADDR   (0x5300400A + EM_BLE_TX_DESC_OFFSET)
+#define EM_BLE_TXAUXPTR1_INDEX  0x00000005
+#define EM_BLE_TXAUXPTR1_RESET  0x00000000
+
+__INLINE uint16_t em_ble_txauxptr1_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_TXAUXPTR1_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+}
+
+__INLINE void em_ble_txauxptr1_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_TXAUXPTR1_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_TXAUX_PHY_MASK         ((uint16_t)0x000000E0)
+#define EM_BLE_TXAUX_PHY_LSB          5
+#define EM_BLE_TXAUX_PHY_WIDTH        ((uint16_t)0x00000003)
+#define EM_BLE_TXAUXOFFSET_MSB_MASK   ((uint16_t)0x0000001F)
+#define EM_BLE_TXAUXOFFSET_MSB_LSB    0
+#define EM_BLE_TXAUXOFFSET_MSB_WIDTH  ((uint16_t)0x00000005)
+
+#define EM_BLE_TXAUX_PHY_RST          0x0
+#define EM_BLE_TXAUXOFFSET_MSB_RST    0x0
+
+__INLINE void em_ble_txauxptr1_pack(int elt_idx, uint8_t txauxphy, uint8_t txauxoffsetmsb)
+{
+    ASSERT_ERR((((uint16_t)txauxphy << 5) & ~((uint16_t)0x000000E0)) == 0);
+    ASSERT_ERR((((uint16_t)txauxoffsetmsb << 0) & ~((uint16_t)0x0000001F)) == 0);
+    EM_BLE_WR(EM_BLE_TXAUXPTR1_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE,  ((uint16_t)txauxphy << 5) | ((uint16_t)txauxoffsetmsb << 0));
+}
+
+__INLINE void em_ble_txauxptr1_unpack(int elt_idx, uint8_t* txauxphy, uint8_t* txauxoffsetmsb)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXAUXPTR1_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+
+    *txauxphy = (localVal & ((uint16_t)0x000000E0)) >> 5;
+    *txauxoffsetmsb = (localVal & ((uint16_t)0x0000001F)) >> 0;
+}
+
+__INLINE uint8_t em_ble_txauxptr1_txaux_phy_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXAUXPTR1_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x000000E0)) >> 5);
+}
+
+__INLINE void em_ble_txauxptr1_txaux_phy_setf(int elt_idx, uint8_t txauxphy)
+{
+    ASSERT_ERR((((uint16_t)txauxphy << 5) & ~((uint16_t)0x000000E0)) == 0);
+    EM_BLE_WR(EM_BLE_TXAUXPTR1_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXAUXPTR1_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x000000E0)) | ((uint16_t)txauxphy << 5));
+}
+
+__INLINE uint8_t em_ble_txauxptr1_txauxoffset_msb_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXAUXPTR1_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x0000001F)) >> 0);
+}
+
+__INLINE void em_ble_txauxptr1_txauxoffset_msb_setf(int elt_idx, uint8_t txauxoffsetmsb)
+{
+    ASSERT_ERR((((uint16_t)txauxoffsetmsb << 0) & ~((uint16_t)0x0000001F)) == 0);
+    EM_BLE_WR(EM_BLE_TXAUXPTR1_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXAUXPTR1_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x0000001F)) | ((uint16_t)txauxoffsetmsb << 0));
+}
+
+/**
+ * @brief TXAEDATAPTR register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  15:00          TXAEDATAPTR   0x0
+ * </pre>
+ */
+#define EM_BLE_TXAEDATAPTR_ADDR   (0x5300400C + EM_BLE_TX_DESC_OFFSET)
+#define EM_BLE_TXAEDATAPTR_INDEX  0x00000006
+#define EM_BLE_TXAEDATAPTR_RESET  0x00000000
+
+__INLINE uint16_t em_ble_txaedataptr_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_TXAEDATAPTR_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+}
+
+__INLINE void em_ble_txaedataptr_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_TXAEDATAPTR_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_TXAEDATAPTR_MASK   ((uint16_t)0x0000FFFF)
+#define EM_BLE_TXAEDATAPTR_LSB    0
+#define EM_BLE_TXAEDATAPTR_WIDTH  ((uint16_t)0x00000010)
+
+#define EM_BLE_TXAEDATAPTR_RST    0x0
+
+__INLINE uint16_t em_ble_txaedataptr_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXAEDATAPTR_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    ASSERT_ERR((localVal & ~((uint16_t)0x0000FFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void em_ble_txaedataptr_setf(int elt_idx, uint16_t txaedataptr)
+{
+    ASSERT_ERR((((uint16_t)txaedataptr << 0) & ~((uint16_t)0x0000FFFF)) == 0);
+    EM_BLE_WR(EM_BLE_TXAEDATAPTR_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (uint16_t)txaedataptr << 0);
+}
+
+/**
+ * @brief TXPHCTE register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  07:06            TXCTETYPE   0x0
+ *     05             TXCTERFU   0
+ *  04:00            TXCTETIME   0x0
+ * </pre>
+ */
+#define EM_BLE_TXPHCTE_ADDR   (0x5300400E + EM_BLE_TX_DESC_OFFSET)
+#define EM_BLE_TXPHCTE_INDEX  0x00000007
+#define EM_BLE_TXPHCTE_RESET  0x00000000
+
+__INLINE uint16_t em_ble_txphcte_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_TXPHCTE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+}
+
+__INLINE void em_ble_txphcte_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_TXPHCTE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_TXCTETYPE_MASK   ((uint16_t)0x000000C0)
+#define EM_BLE_TXCTETYPE_LSB    6
+#define EM_BLE_TXCTETYPE_WIDTH  ((uint16_t)0x00000002)
+#define EM_BLE_TXCTERFU_BIT     ((uint16_t)0x00000020)
+#define EM_BLE_TXCTERFU_POS     5
+#define EM_BLE_TXCTETIME_MASK   ((uint16_t)0x0000001F)
+#define EM_BLE_TXCTETIME_LSB    0
+#define EM_BLE_TXCTETIME_WIDTH  ((uint16_t)0x00000005)
+
+#define EM_BLE_TXCTETYPE_RST    0x0
+#define EM_BLE_TXCTERFU_RST     0x0
+#define EM_BLE_TXCTETIME_RST    0x0
+
+__INLINE void em_ble_txphcte_pack(int elt_idx, uint8_t txctetype, uint8_t txcterfu, uint8_t txctetime)
+{
+    ASSERT_ERR((((uint16_t)txctetype << 6) & ~((uint16_t)0x000000C0)) == 0);
+    ASSERT_ERR((((uint16_t)txcterfu << 5) & ~((uint16_t)0x00000020)) == 0);
+    ASSERT_ERR((((uint16_t)txctetime << 0) & ~((uint16_t)0x0000001F)) == 0);
+    EM_BLE_WR(EM_BLE_TXPHCTE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE,  ((uint16_t)txctetype << 6) | ((uint16_t)txcterfu << 5) | ((uint16_t)txctetime << 0));
+}
+
+__INLINE void em_ble_txphcte_unpack(int elt_idx, uint8_t* txctetype, uint8_t* txcterfu, uint8_t* txctetime)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXPHCTE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+
+    *txctetype = (localVal & ((uint16_t)0x000000C0)) >> 6;
+    *txcterfu = (localVal & ((uint16_t)0x00000020)) >> 5;
+    *txctetime = (localVal & ((uint16_t)0x0000001F)) >> 0;
+}
+
+__INLINE uint8_t em_ble_txphcte_txctetype_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXPHCTE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x000000C0)) >> 6);
+}
+
+__INLINE void em_ble_txphcte_txctetype_setf(int elt_idx, uint8_t txctetype)
+{
+    ASSERT_ERR((((uint16_t)txctetype << 6) & ~((uint16_t)0x000000C0)) == 0);
+    EM_BLE_WR(EM_BLE_TXPHCTE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXPHCTE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x000000C0)) | ((uint16_t)txctetype << 6));
+}
+
+__INLINE uint8_t em_ble_txphcte_txcterfu_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXPHCTE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00000020)) >> 5);
+}
+
+__INLINE void em_ble_txphcte_txcterfu_setf(int elt_idx, uint8_t txcterfu)
+{
+    ASSERT_ERR((((uint16_t)txcterfu << 5) & ~((uint16_t)0x00000020)) == 0);
+    EM_BLE_WR(EM_BLE_TXPHCTE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXPHCTE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x00000020)) | ((uint16_t)txcterfu << 5));
+}
+
+__INLINE uint8_t em_ble_txphcte_txctetime_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXPHCTE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x0000001F)) >> 0);
+}
+
+__INLINE void em_ble_txphcte_txctetime_setf(int elt_idx, uint8_t txctetime)
+{
+    ASSERT_ERR((((uint16_t)txctetime << 0) & ~((uint16_t)0x0000001F)) == 0);
+    EM_BLE_WR(EM_BLE_TXPHCTE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXPHCTE_ADDR + elt_idx * REG_EM_BLE_TX_DESC_SIZE) & ~((uint16_t)0x0000001F)) | ((uint16_t)txctetime << 0));
+}
+
+
+#endif // _REG_EM_BLE_TX_DESC_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/reg_em_ble_tx_iso_buf.h

@@ -0,0 +1,157 @@
+#ifndef _REG_EM_BLE_TX_ISO_BUF_H_
+#define _REG_EM_BLE_TX_ISO_BUF_H_
+
+#include <stdint.h>
+#include "_reg_em_ble_tx_iso_buf.h"
+#include "compiler.h"
+#include "arch.h"
+#include "em_map.h"
+#include "reg_access.h"
+
+#define REG_EM_BLE_TX_ISO_BUF_COUNT 2
+
+#define REG_EM_BLE_TX_ISO_BUF_DECODING_MASK 0x00000003
+
+#define REG_EM_BLE_TX_ISO_BUF_ADDR_GET(idx) (EM_BLE_TX_ISO_BUF_OFFSET + (idx) * REG_EM_BLE_TX_ISO_BUF_SIZE)
+
+/**
+ * @brief TXISOBUFSETUP register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     15            TXISOMUTE   0
+ *  09:08            TXISOLLID   0x0
+ *  07:00          TXISOLENGTH   0x0
+ * </pre>
+ */
+#define EM_BLE_TXISOBUFSETUP_ADDR   (0x53004000 + EM_BLE_TX_ISO_BUF_OFFSET)
+#define EM_BLE_TXISOBUFSETUP_INDEX  0x00000000
+#define EM_BLE_TXISOBUFSETUP_RESET  0x00000000
+
+__INLINE uint16_t em_ble_txisobufsetup_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_TXISOBUFSETUP_ADDR + elt_idx * REG_EM_BLE_TX_ISO_BUF_SIZE);
+}
+
+__INLINE void em_ble_txisobufsetup_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_TXISOBUFSETUP_ADDR + elt_idx * REG_EM_BLE_TX_ISO_BUF_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_TXISOMUTE_BIT      ((uint16_t)0x00008000)
+#define EM_BLE_TXISOMUTE_POS      15
+#define EM_BLE_TXISOLLID_MASK     ((uint16_t)0x00000300)
+#define EM_BLE_TXISOLLID_LSB      8
+#define EM_BLE_TXISOLLID_WIDTH    ((uint16_t)0x00000002)
+#define EM_BLE_TXISOLENGTH_MASK   ((uint16_t)0x000000FF)
+#define EM_BLE_TXISOLENGTH_LSB    0
+#define EM_BLE_TXISOLENGTH_WIDTH  ((uint16_t)0x00000008)
+
+#define EM_BLE_TXISOMUTE_RST      0x0
+#define EM_BLE_TXISOLLID_RST      0x0
+#define EM_BLE_TXISOLENGTH_RST    0x0
+
+__INLINE void em_ble_txisobufsetup_pack(int elt_idx, uint8_t txisomute, uint8_t txisollid, uint8_t txisolength)
+{
+    ASSERT_ERR((((uint16_t)txisomute << 15) & ~((uint16_t)0x00008000)) == 0);
+    ASSERT_ERR((((uint16_t)txisollid << 8) & ~((uint16_t)0x00000300)) == 0);
+    ASSERT_ERR((((uint16_t)txisolength << 0) & ~((uint16_t)0x000000FF)) == 0);
+    EM_BLE_WR(EM_BLE_TXISOBUFSETUP_ADDR + elt_idx * REG_EM_BLE_TX_ISO_BUF_SIZE,  ((uint16_t)txisomute << 15) | ((uint16_t)txisollid << 8) | ((uint16_t)txisolength << 0));
+}
+
+__INLINE void em_ble_txisobufsetup_unpack(int elt_idx, uint8_t* txisomute, uint8_t* txisollid, uint8_t* txisolength)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXISOBUFSETUP_ADDR + elt_idx * REG_EM_BLE_TX_ISO_BUF_SIZE);
+
+    *txisomute = (localVal & ((uint16_t)0x00008000)) >> 15;
+    *txisollid = (localVal & ((uint16_t)0x00000300)) >> 8;
+    *txisolength = (localVal & ((uint16_t)0x000000FF)) >> 0;
+}
+
+__INLINE uint8_t em_ble_txisobufsetup_txisomute_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXISOBUFSETUP_ADDR + elt_idx * REG_EM_BLE_TX_ISO_BUF_SIZE);
+    return ((localVal & ((uint16_t)0x00008000)) >> 15);
+}
+
+__INLINE void em_ble_txisobufsetup_txisomute_setf(int elt_idx, uint8_t txisomute)
+{
+    ASSERT_ERR((((uint16_t)txisomute << 15) & ~((uint16_t)0x00008000)) == 0);
+    EM_BLE_WR(EM_BLE_TXISOBUFSETUP_ADDR + elt_idx * REG_EM_BLE_TX_ISO_BUF_SIZE, (EM_BLE_RD(EM_BLE_TXISOBUFSETUP_ADDR + elt_idx * REG_EM_BLE_TX_ISO_BUF_SIZE) & ~((uint16_t)0x00008000)) | ((uint16_t)txisomute << 15));
+}
+
+__INLINE uint8_t em_ble_txisobufsetup_txisollid_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXISOBUFSETUP_ADDR + elt_idx * REG_EM_BLE_TX_ISO_BUF_SIZE);
+    return ((localVal & ((uint16_t)0x00000300)) >> 8);
+}
+
+__INLINE void em_ble_txisobufsetup_txisollid_setf(int elt_idx, uint8_t txisollid)
+{
+    ASSERT_ERR((((uint16_t)txisollid << 8) & ~((uint16_t)0x00000300)) == 0);
+    EM_BLE_WR(EM_BLE_TXISOBUFSETUP_ADDR + elt_idx * REG_EM_BLE_TX_ISO_BUF_SIZE, (EM_BLE_RD(EM_BLE_TXISOBUFSETUP_ADDR + elt_idx * REG_EM_BLE_TX_ISO_BUF_SIZE) & ~((uint16_t)0x00000300)) | ((uint16_t)txisollid << 8));
+}
+
+__INLINE uint8_t em_ble_txisobufsetup_txisolength_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXISOBUFSETUP_ADDR + elt_idx * REG_EM_BLE_TX_ISO_BUF_SIZE);
+    return ((localVal & ((uint16_t)0x000000FF)) >> 0);
+}
+
+__INLINE void em_ble_txisobufsetup_txisolength_setf(int elt_idx, uint8_t txisolength)
+{
+    ASSERT_ERR((((uint16_t)txisolength << 0) & ~((uint16_t)0x000000FF)) == 0);
+    EM_BLE_WR(EM_BLE_TXISOBUFSETUP_ADDR + elt_idx * REG_EM_BLE_TX_ISO_BUF_SIZE, (EM_BLE_RD(EM_BLE_TXISOBUFSETUP_ADDR + elt_idx * REG_EM_BLE_TX_ISO_BUF_SIZE) & ~((uint16_t)0x000000FF)) | ((uint16_t)txisolength << 0));
+}
+
+/**
+ * @brief TXISODATABUF register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  15:00         TXISODATABUF   0x0
+ * </pre>
+ */
+#define EM_BLE_TXISODATABUF_ADDR   (0x53004002 + EM_BLE_TX_ISO_BUF_OFFSET)
+#define EM_BLE_TXISODATABUF_INDEX  0x00000001
+#define EM_BLE_TXISODATABUF_RESET  0x00000000
+#define EM_BLE_TXISODATABUF_COUNT  129
+
+__INLINE uint16_t em_ble_txisodatabuf_get(int elt_idx, int reg_idx)
+{
+    ASSERT_ERR(reg_idx <= 128);
+    return EM_BLE_RD(EM_BLE_TXISODATABUF_ADDR + elt_idx * REG_EM_BLE_TX_ISO_BUF_SIZE + reg_idx * 2);
+}
+
+__INLINE void em_ble_txisodatabuf_set(int elt_idx, int reg_idx, uint16_t value)
+{
+    ASSERT_ERR(reg_idx <= 128);
+    EM_BLE_WR(EM_BLE_TXISODATABUF_ADDR + elt_idx * REG_EM_BLE_TX_ISO_BUF_SIZE + reg_idx * 2, value);
+}
+
+// field definitions
+#define EM_BLE_TXISODATABUF_MASK   ((uint16_t)0x0000FFFF)
+#define EM_BLE_TXISODATABUF_LSB    0
+#define EM_BLE_TXISODATABUF_WIDTH  ((uint16_t)0x00000010)
+
+#define EM_BLE_TXISODATABUF_RST    0x0
+
+__INLINE uint16_t em_ble_txisodatabuf_getf(int elt_idx, int reg_idx)
+{
+    ASSERT_ERR(reg_idx <= 128);
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXISODATABUF_ADDR + elt_idx * REG_EM_BLE_TX_ISO_BUF_SIZE + reg_idx * 2);
+    ASSERT_ERR((localVal & ~((uint16_t)0x0000FFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void em_ble_txisodatabuf_setf(int elt_idx, int reg_idx, uint16_t txisodatabuf)
+{
+    ASSERT_ERR(reg_idx <= 128);
+    ASSERT_ERR((((uint16_t)txisodatabuf << 0) & ~((uint16_t)0x0000FFFF)) == 0);
+    EM_BLE_WR(EM_BLE_TXISODATABUF_ADDR + elt_idx * REG_EM_BLE_TX_ISO_BUF_SIZE + reg_idx * 2, (uint16_t)txisodatabuf << 0);
+}
+
+
+#endif // _REG_EM_BLE_TX_ISO_BUF_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/reg_em_ble_tx_iso_desc.h

@@ -0,0 +1,650 @@
+#ifndef _REG_EM_BLE_TX_ISO_DESC_H_
+#define _REG_EM_BLE_TX_ISO_DESC_H_
+
+#include <stdint.h>
+#include "_reg_em_ble_tx_iso_desc.h"
+#include "compiler.h"
+#include "arch.h"
+#include "em_map.h"
+#include "reg_access.h"
+
+#define REG_EM_BLE_TX_ISO_DESC_COUNT 6
+
+#define REG_EM_BLE_TX_ISO_DESC_DECODING_MASK 0x0000000F
+
+#define REG_EM_BLE_TX_ISO_DESC_ADDR_GET(idx) (EM_BLE_TX_ISO_DESC_OFFSET + (idx) * REG_EM_BLE_TX_ISO_DESC_SIZE)
+
+/**
+ * @brief TXISOPTR register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     15               TXDONE   0
+ *     14               TXSENT   0
+ *  13:00              NEXTPTR   0x0
+ * </pre>
+ */
+#define EM_BLE_TXISOPTR_ADDR   (0x53004000 + EM_BLE_TX_ISO_DESC_OFFSET)
+#define EM_BLE_TXISOPTR_INDEX  0x00000000
+#define EM_BLE_TXISOPTR_RESET  0x00000000
+
+__INLINE uint16_t em_ble_txisoptr_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_TXISOPTR_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+}
+
+__INLINE void em_ble_txisoptr_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_TXISOPTR_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_TXDONE_BIT     ((uint16_t)0x00008000)
+#define EM_BLE_TXDONE_POS     15
+#define EM_BLE_TXSENT_BIT     ((uint16_t)0x00004000)
+#define EM_BLE_TXSENT_POS     14
+#define EM_BLE_NEXTPTR_MASK   ((uint16_t)0x00003FFF)
+#define EM_BLE_NEXTPTR_LSB    0
+#define EM_BLE_NEXTPTR_WIDTH  ((uint16_t)0x0000000E)
+
+#define EM_BLE_TXDONE_RST     0x0
+#define EM_BLE_TXSENT_RST     0x0
+#define EM_BLE_NEXTPTR_RST    0x0
+
+__INLINE void em_ble_txisoptr_pack(int elt_idx, uint8_t txdone, uint8_t txsent, uint16_t nextptr)
+{
+    ASSERT_ERR((((uint16_t)txdone << 15) & ~((uint16_t)0x00008000)) == 0);
+    ASSERT_ERR((((uint16_t)txsent << 14) & ~((uint16_t)0x00004000)) == 0);
+    ASSERT_ERR((((uint16_t)nextptr << 0) & ~((uint16_t)0x00003FFF)) == 0);
+    EM_BLE_WR(EM_BLE_TXISOPTR_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE,  ((uint16_t)txdone << 15) | ((uint16_t)txsent << 14) | ((uint16_t)nextptr << 0));
+}
+
+__INLINE void em_ble_txisoptr_unpack(int elt_idx, uint8_t* txdone, uint8_t* txsent, uint16_t* nextptr)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXISOPTR_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+
+    *txdone = (localVal & ((uint16_t)0x00008000)) >> 15;
+    *txsent = (localVal & ((uint16_t)0x00004000)) >> 14;
+    *nextptr = (localVal & ((uint16_t)0x00003FFF)) >> 0;
+}
+
+__INLINE uint8_t em_ble_txisoptr_txdone_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXISOPTR_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00008000)) >> 15);
+}
+
+__INLINE void em_ble_txisoptr_txdone_setf(int elt_idx, uint8_t txdone)
+{
+    ASSERT_ERR((((uint16_t)txdone << 15) & ~((uint16_t)0x00008000)) == 0);
+    EM_BLE_WR(EM_BLE_TXISOPTR_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXISOPTR_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE) & ~((uint16_t)0x00008000)) | ((uint16_t)txdone << 15));
+}
+
+__INLINE uint8_t em_ble_txisoptr_txsent_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXISOPTR_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00004000)) >> 14);
+}
+
+__INLINE void em_ble_txisoptr_txsent_setf(int elt_idx, uint8_t txsent)
+{
+    ASSERT_ERR((((uint16_t)txsent << 14) & ~((uint16_t)0x00004000)) == 0);
+    EM_BLE_WR(EM_BLE_TXISOPTR_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXISOPTR_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE) & ~((uint16_t)0x00004000)) | ((uint16_t)txsent << 14));
+}
+
+__INLINE uint16_t em_ble_txisoptr_nextptr_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXISOPTR_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00003FFF)) >> 0);
+}
+
+__INLINE void em_ble_txisoptr_nextptr_setf(int elt_idx, uint16_t nextptr)
+{
+    ASSERT_ERR((((uint16_t)nextptr << 0) & ~((uint16_t)0x00003FFF)) == 0);
+    EM_BLE_WR(EM_BLE_TXISOPTR_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXISOPTR_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE) & ~((uint16_t)0x00003FFF)) | ((uint16_t)nextptr << 0));
+}
+
+/**
+ * @brief TXISOCNT0 register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  15:00           TXPLD_CNT0   0x0
+ * </pre>
+ */
+#define EM_BLE_TXISOCNT0_ADDR   (0x53004002 + EM_BLE_TX_ISO_DESC_OFFSET)
+#define EM_BLE_TXISOCNT0_INDEX  0x00000001
+#define EM_BLE_TXISOCNT0_RESET  0x00000000
+
+__INLINE uint16_t em_ble_txisocnt0_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_TXISOCNT0_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+}
+
+__INLINE void em_ble_txisocnt0_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_TXISOCNT0_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_TXPLD_CNT0_MASK   ((uint16_t)0x0000FFFF)
+#define EM_BLE_TXPLD_CNT0_LSB    0
+#define EM_BLE_TXPLD_CNT0_WIDTH  ((uint16_t)0x00000010)
+
+#define EM_BLE_TXPLD_CNT0_RST    0x0
+
+__INLINE uint16_t em_ble_txisocnt0_txpld_cnt0_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXISOCNT0_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+    ASSERT_ERR((localVal & ~((uint16_t)0x0000FFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void em_ble_txisocnt0_txpld_cnt0_setf(int elt_idx, uint16_t txpldcnt0)
+{
+    ASSERT_ERR((((uint16_t)txpldcnt0 << 0) & ~((uint16_t)0x0000FFFF)) == 0);
+    EM_BLE_WR(EM_BLE_TXISOCNT0_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE, (uint16_t)txpldcnt0 << 0);
+}
+
+/**
+ * @brief TXISOCNT1 register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  15:00           TXPLD_CNT1   0x0
+ * </pre>
+ */
+#define EM_BLE_TXISOCNT1_ADDR   (0x53004004 + EM_BLE_TX_ISO_DESC_OFFSET)
+#define EM_BLE_TXISOCNT1_INDEX  0x00000002
+#define EM_BLE_TXISOCNT1_RESET  0x00000000
+
+__INLINE uint16_t em_ble_txisocnt1_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_TXISOCNT1_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+}
+
+__INLINE void em_ble_txisocnt1_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_TXISOCNT1_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_TXPLD_CNT1_MASK   ((uint16_t)0x0000FFFF)
+#define EM_BLE_TXPLD_CNT1_LSB    0
+#define EM_BLE_TXPLD_CNT1_WIDTH  ((uint16_t)0x00000010)
+
+#define EM_BLE_TXPLD_CNT1_RST    0x0
+
+__INLINE uint16_t em_ble_txisocnt1_txpld_cnt1_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXISOCNT1_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+    ASSERT_ERR((localVal & ~((uint16_t)0x0000FFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void em_ble_txisocnt1_txpld_cnt1_setf(int elt_idx, uint16_t txpldcnt1)
+{
+    ASSERT_ERR((((uint16_t)txpldcnt1 << 0) & ~((uint16_t)0x0000FFFF)) == 0);
+    EM_BLE_WR(EM_BLE_TXISOCNT1_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE, (uint16_t)txpldcnt1 << 0);
+}
+
+/**
+ * @brief TXISOCNT2 register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  15:08       TXFLUSHINSTANT   0x0
+ *  06:00           TXPLD_CNT2   0x0
+ * </pre>
+ */
+#define EM_BLE_TXISOCNT2_ADDR   (0x53004006 + EM_BLE_TX_ISO_DESC_OFFSET)
+#define EM_BLE_TXISOCNT2_INDEX  0x00000003
+#define EM_BLE_TXISOCNT2_RESET  0x00000000
+
+__INLINE uint16_t em_ble_txisocnt2_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_TXISOCNT2_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+}
+
+__INLINE void em_ble_txisocnt2_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_TXISOCNT2_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_TXFLUSHINSTANT_MASK   ((uint16_t)0x0000FF00)
+#define EM_BLE_TXFLUSHINSTANT_LSB    8
+#define EM_BLE_TXFLUSHINSTANT_WIDTH  ((uint16_t)0x00000008)
+#define EM_BLE_TXPLD_CNT2_MASK       ((uint16_t)0x0000007F)
+#define EM_BLE_TXPLD_CNT2_LSB        0
+#define EM_BLE_TXPLD_CNT2_WIDTH      ((uint16_t)0x00000007)
+
+#define EM_BLE_TXFLUSHINSTANT_RST    0x0
+#define EM_BLE_TXPLD_CNT2_RST        0x0
+
+__INLINE void em_ble_txisocnt2_pack(int elt_idx, uint8_t txflushinstant, uint8_t txpldcnt2)
+{
+    ASSERT_ERR((((uint16_t)txflushinstant << 8) & ~((uint16_t)0x0000FF00)) == 0);
+    ASSERT_ERR((((uint16_t)txpldcnt2 << 0) & ~((uint16_t)0x0000007F)) == 0);
+    EM_BLE_WR(EM_BLE_TXISOCNT2_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE,  ((uint16_t)txflushinstant << 8) | ((uint16_t)txpldcnt2 << 0));
+}
+
+__INLINE void em_ble_txisocnt2_unpack(int elt_idx, uint8_t* txflushinstant, uint8_t* txpldcnt2)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXISOCNT2_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+
+    *txflushinstant = (localVal & ((uint16_t)0x0000FF00)) >> 8;
+    *txpldcnt2 = (localVal & ((uint16_t)0x0000007F)) >> 0;
+}
+
+__INLINE uint8_t em_ble_txisocnt2_txflushinstant_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXISOCNT2_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x0000FF00)) >> 8);
+}
+
+__INLINE void em_ble_txisocnt2_txflushinstant_setf(int elt_idx, uint8_t txflushinstant)
+{
+    ASSERT_ERR((((uint16_t)txflushinstant << 8) & ~((uint16_t)0x0000FF00)) == 0);
+    EM_BLE_WR(EM_BLE_TXISOCNT2_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXISOCNT2_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE) & ~((uint16_t)0x0000FF00)) | ((uint16_t)txflushinstant << 8));
+}
+
+__INLINE uint8_t em_ble_txisocnt2_txpld_cnt2_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXISOCNT2_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x0000007F)) >> 0);
+}
+
+__INLINE void em_ble_txisocnt2_txpld_cnt2_setf(int elt_idx, uint8_t txpldcnt2)
+{
+    ASSERT_ERR((((uint16_t)txpldcnt2 << 0) & ~((uint16_t)0x0000007F)) == 0);
+    EM_BLE_WR(EM_BLE_TXISOCNT2_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXISOCNT2_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE) & ~((uint16_t)0x0000007F)) | ((uint16_t)txpldcnt2 << 0));
+}
+
+/**
+ * @brief TXISOPHM0 register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  07:05           TXISOM0RFU   0x0
+ *     04                 TXMD   0
+ *     03                 TXSN   0
+ *     02               TXNESN   0
+ * </pre>
+ */
+#define EM_BLE_TXISOPHM0_ADDR   (0x53004008 + EM_BLE_TX_ISO_DESC_OFFSET)
+#define EM_BLE_TXISOPHM0_INDEX  0x00000004
+#define EM_BLE_TXISOPHM0_RESET  0x00000000
+
+__INLINE uint16_t em_ble_txisophm0_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_TXISOPHM0_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+}
+
+__INLINE void em_ble_txisophm0_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_TXISOPHM0_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_TXISOM0RFU_MASK   ((uint16_t)0x000000E0)
+#define EM_BLE_TXISOM0RFU_LSB    5
+#define EM_BLE_TXISOM0RFU_WIDTH  ((uint16_t)0x00000003)
+#define EM_BLE_TXMD_BIT          ((uint16_t)0x00000010)
+#define EM_BLE_TXMD_POS          4
+#define EM_BLE_TXSN_BIT          ((uint16_t)0x00000008)
+#define EM_BLE_TXSN_POS          3
+#define EM_BLE_TXNESN_BIT        ((uint16_t)0x00000004)
+#define EM_BLE_TXNESN_POS        2
+
+#define EM_BLE_TXISOM0RFU_RST    0x0
+#define EM_BLE_TXMD_RST          0x0
+#define EM_BLE_TXSN_RST          0x0
+#define EM_BLE_TXNESN_RST        0x0
+
+__INLINE void em_ble_txisophm0_pack(int elt_idx, uint8_t txisom0rfu, uint8_t txmd, uint8_t txsn, uint8_t txnesn)
+{
+    ASSERT_ERR((((uint16_t)txisom0rfu << 5) & ~((uint16_t)0x000000E0)) == 0);
+    ASSERT_ERR((((uint16_t)txmd << 4) & ~((uint16_t)0x00000010)) == 0);
+    ASSERT_ERR((((uint16_t)txsn << 3) & ~((uint16_t)0x00000008)) == 0);
+    ASSERT_ERR((((uint16_t)txnesn << 2) & ~((uint16_t)0x00000004)) == 0);
+    EM_BLE_WR(EM_BLE_TXISOPHM0_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE,  ((uint16_t)txisom0rfu << 5) | ((uint16_t)txmd << 4) | ((uint16_t)txsn << 3) | ((uint16_t)txnesn << 2));
+}
+
+__INLINE void em_ble_txisophm0_unpack(int elt_idx, uint8_t* txisom0rfu, uint8_t* txmd, uint8_t* txsn, uint8_t* txnesn)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXISOPHM0_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+
+    *txisom0rfu = (localVal & ((uint16_t)0x000000E0)) >> 5;
+    *txmd = (localVal & ((uint16_t)0x00000010)) >> 4;
+    *txsn = (localVal & ((uint16_t)0x00000008)) >> 3;
+    *txnesn = (localVal & ((uint16_t)0x00000004)) >> 2;
+}
+
+__INLINE uint8_t em_ble_txisophm0_txisom0rfu_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXISOPHM0_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x000000E0)) >> 5);
+}
+
+__INLINE void em_ble_txisophm0_txisom0rfu_setf(int elt_idx, uint8_t txisom0rfu)
+{
+    ASSERT_ERR((((uint16_t)txisom0rfu << 5) & ~((uint16_t)0x000000E0)) == 0);
+    EM_BLE_WR(EM_BLE_TXISOPHM0_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXISOPHM0_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE) & ~((uint16_t)0x000000E0)) | ((uint16_t)txisom0rfu << 5));
+}
+
+__INLINE uint8_t em_ble_txisophm0_txmd_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXISOPHM0_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00000010)) >> 4);
+}
+
+__INLINE void em_ble_txisophm0_txmd_setf(int elt_idx, uint8_t txmd)
+{
+    ASSERT_ERR((((uint16_t)txmd << 4) & ~((uint16_t)0x00000010)) == 0);
+    EM_BLE_WR(EM_BLE_TXISOPHM0_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXISOPHM0_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE) & ~((uint16_t)0x00000010)) | ((uint16_t)txmd << 4));
+}
+
+__INLINE uint8_t em_ble_txisophm0_txsn_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXISOPHM0_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00000008)) >> 3);
+}
+
+__INLINE void em_ble_txisophm0_txsn_setf(int elt_idx, uint8_t txsn)
+{
+    ASSERT_ERR((((uint16_t)txsn << 3) & ~((uint16_t)0x00000008)) == 0);
+    EM_BLE_WR(EM_BLE_TXISOPHM0_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXISOPHM0_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE) & ~((uint16_t)0x00000008)) | ((uint16_t)txsn << 3));
+}
+
+__INLINE uint8_t em_ble_txisophm0_txnesn_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXISOPHM0_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00000004)) >> 2);
+}
+
+__INLINE void em_ble_txisophm0_txnesn_setf(int elt_idx, uint8_t txnesn)
+{
+    ASSERT_ERR((((uint16_t)txnesn << 2) & ~((uint16_t)0x00000004)) == 0);
+    EM_BLE_WR(EM_BLE_TXISOPHM0_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXISOPHM0_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE) & ~((uint16_t)0x00000004)) | ((uint16_t)txnesn << 2));
+}
+
+/**
+ * @brief TXCISPH register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     07            TXCISRFU1   0
+ *     06             TXCISNPI   0
+ *     05            TXCISRFU0   0
+ *     04                TXCIE   0
+ *     03                 TXSN   0
+ *     02               TXNESN   0
+ * </pre>
+ */
+#define EM_BLE_TXCISPH_ADDR   (0x53004008 + EM_BLE_TX_ISO_DESC_OFFSET)
+#define EM_BLE_TXCISPH_INDEX  0x00000004
+#define EM_BLE_TXCISPH_RESET  0x00000000
+
+__INLINE uint16_t em_ble_txcisph_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_TXCISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+}
+
+__INLINE void em_ble_txcisph_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_TXCISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_TXCISRFU1_BIT    ((uint16_t)0x00000080)
+#define EM_BLE_TXCISRFU1_POS    7
+#define EM_BLE_TXCISNPI_BIT     ((uint16_t)0x00000040)
+#define EM_BLE_TXCISNPI_POS     6
+#define EM_BLE_TXCISRFU0_BIT    ((uint16_t)0x00000020)
+#define EM_BLE_TXCISRFU0_POS    5
+#define EM_BLE_TXCIE_BIT        ((uint16_t)0x00000010)
+#define EM_BLE_TXCIE_POS        4
+#define EM_BLE_TXSN_BIT         ((uint16_t)0x00000008)
+#define EM_BLE_TXSN_POS         3
+#define EM_BLE_TXNESN_BIT       ((uint16_t)0x00000004)
+#define EM_BLE_TXNESN_POS       2
+
+#define EM_BLE_TXCISRFU1_RST    0x0
+#define EM_BLE_TXCISNPI_RST     0x0
+#define EM_BLE_TXCISRFU0_RST    0x0
+#define EM_BLE_TXCIE_RST        0x0
+#define EM_BLE_TXSN_RST         0x0
+#define EM_BLE_TXNESN_RST       0x0
+
+__INLINE void em_ble_txcisph_pack(int elt_idx, uint8_t txcisrfu1, uint8_t txcisnpi, uint8_t txcisrfu0, uint8_t txcie, uint8_t txsn, uint8_t txnesn)
+{
+    ASSERT_ERR((((uint16_t)txcisrfu1 << 7) & ~((uint16_t)0x00000080)) == 0);
+    ASSERT_ERR((((uint16_t)txcisnpi << 6) & ~((uint16_t)0x00000040)) == 0);
+    ASSERT_ERR((((uint16_t)txcisrfu0 << 5) & ~((uint16_t)0x00000020)) == 0);
+    ASSERT_ERR((((uint16_t)txcie << 4) & ~((uint16_t)0x00000010)) == 0);
+    ASSERT_ERR((((uint16_t)txsn << 3) & ~((uint16_t)0x00000008)) == 0);
+    ASSERT_ERR((((uint16_t)txnesn << 2) & ~((uint16_t)0x00000004)) == 0);
+    EM_BLE_WR(EM_BLE_TXCISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE,  ((uint16_t)txcisrfu1 << 7) | ((uint16_t)txcisnpi << 6) | ((uint16_t)txcisrfu0 << 5) | ((uint16_t)txcie << 4) | ((uint16_t)txsn << 3) | ((uint16_t)txnesn << 2));
+}
+
+__INLINE void em_ble_txcisph_unpack(int elt_idx, uint8_t* txcisrfu1, uint8_t* txcisnpi, uint8_t* txcisrfu0, uint8_t* txcie, uint8_t* txsn, uint8_t* txnesn)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXCISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+
+    *txcisrfu1 = (localVal & ((uint16_t)0x00000080)) >> 7;
+    *txcisnpi = (localVal & ((uint16_t)0x00000040)) >> 6;
+    *txcisrfu0 = (localVal & ((uint16_t)0x00000020)) >> 5;
+    *txcie = (localVal & ((uint16_t)0x00000010)) >> 4;
+    *txsn = (localVal & ((uint16_t)0x00000008)) >> 3;
+    *txnesn = (localVal & ((uint16_t)0x00000004)) >> 2;
+}
+
+__INLINE uint8_t em_ble_txcisph_txcisrfu1_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXCISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00000080)) >> 7);
+}
+
+__INLINE void em_ble_txcisph_txcisrfu1_setf(int elt_idx, uint8_t txcisrfu1)
+{
+    ASSERT_ERR((((uint16_t)txcisrfu1 << 7) & ~((uint16_t)0x00000080)) == 0);
+    EM_BLE_WR(EM_BLE_TXCISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXCISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE) & ~((uint16_t)0x00000080)) | ((uint16_t)txcisrfu1 << 7));
+}
+
+__INLINE uint8_t em_ble_txcisph_txcisnpi_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXCISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00000040)) >> 6);
+}
+
+__INLINE void em_ble_txcisph_txcisnpi_setf(int elt_idx, uint8_t txcisnpi)
+{
+    ASSERT_ERR((((uint16_t)txcisnpi << 6) & ~((uint16_t)0x00000040)) == 0);
+    EM_BLE_WR(EM_BLE_TXCISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXCISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE) & ~((uint16_t)0x00000040)) | ((uint16_t)txcisnpi << 6));
+}
+
+__INLINE uint8_t em_ble_txcisph_txcisrfu0_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXCISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00000020)) >> 5);
+}
+
+__INLINE void em_ble_txcisph_txcisrfu0_setf(int elt_idx, uint8_t txcisrfu0)
+{
+    ASSERT_ERR((((uint16_t)txcisrfu0 << 5) & ~((uint16_t)0x00000020)) == 0);
+    EM_BLE_WR(EM_BLE_TXCISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXCISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE) & ~((uint16_t)0x00000020)) | ((uint16_t)txcisrfu0 << 5));
+}
+
+__INLINE uint8_t em_ble_txcisph_txcie_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXCISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00000010)) >> 4);
+}
+
+__INLINE void em_ble_txcisph_txcie_setf(int elt_idx, uint8_t txcie)
+{
+    ASSERT_ERR((((uint16_t)txcie << 4) & ~((uint16_t)0x00000010)) == 0);
+    EM_BLE_WR(EM_BLE_TXCISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXCISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE) & ~((uint16_t)0x00000010)) | ((uint16_t)txcie << 4));
+}
+
+__INLINE uint8_t em_ble_txcisph_txsn_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXCISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00000008)) >> 3);
+}
+
+__INLINE void em_ble_txcisph_txsn_setf(int elt_idx, uint8_t txsn)
+{
+    ASSERT_ERR((((uint16_t)txsn << 3) & ~((uint16_t)0x00000008)) == 0);
+    EM_BLE_WR(EM_BLE_TXCISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXCISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE) & ~((uint16_t)0x00000008)) | ((uint16_t)txsn << 3));
+}
+
+__INLINE uint8_t em_ble_txcisph_txnesn_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXCISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00000004)) >> 2);
+}
+
+__INLINE void em_ble_txcisph_txnesn_setf(int elt_idx, uint8_t txnesn)
+{
+    ASSERT_ERR((((uint16_t)txnesn << 2) & ~((uint16_t)0x00000004)) == 0);
+    EM_BLE_WR(EM_BLE_TXCISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXCISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE) & ~((uint16_t)0x00000004)) | ((uint16_t)txnesn << 2));
+}
+
+/**
+ * @brief TXBISPH register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  07:06             TXBISRFU   0x0
+ *     05               TXCSTF   0
+ *  04:02               TXCSSN   0x0
+ * </pre>
+ */
+#define EM_BLE_TXBISPH_ADDR   (0x53004008 + EM_BLE_TX_ISO_DESC_OFFSET)
+#define EM_BLE_TXBISPH_INDEX  0x00000004
+#define EM_BLE_TXBISPH_RESET  0x00000000
+
+__INLINE uint16_t em_ble_txbisph_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_TXBISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+}
+
+__INLINE void em_ble_txbisph_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_TXBISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_TXBISRFU_MASK   ((uint16_t)0x000000C0)
+#define EM_BLE_TXBISRFU_LSB    6
+#define EM_BLE_TXBISRFU_WIDTH  ((uint16_t)0x00000002)
+#define EM_BLE_TXCSTF_BIT      ((uint16_t)0x00000020)
+#define EM_BLE_TXCSTF_POS      5
+#define EM_BLE_TXCSSN_MASK     ((uint16_t)0x0000001C)
+#define EM_BLE_TXCSSN_LSB      2
+#define EM_BLE_TXCSSN_WIDTH    ((uint16_t)0x00000003)
+
+#define EM_BLE_TXBISRFU_RST    0x0
+#define EM_BLE_TXCSTF_RST      0x0
+#define EM_BLE_TXCSSN_RST      0x0
+
+__INLINE void em_ble_txbisph_pack(int elt_idx, uint8_t txbisrfu, uint8_t txcstf, uint8_t txcssn)
+{
+    ASSERT_ERR((((uint16_t)txbisrfu << 6) & ~((uint16_t)0x000000C0)) == 0);
+    ASSERT_ERR((((uint16_t)txcstf << 5) & ~((uint16_t)0x00000020)) == 0);
+    ASSERT_ERR((((uint16_t)txcssn << 2) & ~((uint16_t)0x0000001C)) == 0);
+    EM_BLE_WR(EM_BLE_TXBISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE,  ((uint16_t)txbisrfu << 6) | ((uint16_t)txcstf << 5) | ((uint16_t)txcssn << 2));
+}
+
+__INLINE void em_ble_txbisph_unpack(int elt_idx, uint8_t* txbisrfu, uint8_t* txcstf, uint8_t* txcssn)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXBISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+
+    *txbisrfu = (localVal & ((uint16_t)0x000000C0)) >> 6;
+    *txcstf = (localVal & ((uint16_t)0x00000020)) >> 5;
+    *txcssn = (localVal & ((uint16_t)0x0000001C)) >> 2;
+}
+
+__INLINE uint8_t em_ble_txbisph_txbisrfu_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXBISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x000000C0)) >> 6);
+}
+
+__INLINE void em_ble_txbisph_txbisrfu_setf(int elt_idx, uint8_t txbisrfu)
+{
+    ASSERT_ERR((((uint16_t)txbisrfu << 6) & ~((uint16_t)0x000000C0)) == 0);
+    EM_BLE_WR(EM_BLE_TXBISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXBISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE) & ~((uint16_t)0x000000C0)) | ((uint16_t)txbisrfu << 6));
+}
+
+__INLINE uint8_t em_ble_txbisph_txcstf_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXBISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x00000020)) >> 5);
+}
+
+__INLINE void em_ble_txbisph_txcstf_setf(int elt_idx, uint8_t txcstf)
+{
+    ASSERT_ERR((((uint16_t)txcstf << 5) & ~((uint16_t)0x00000020)) == 0);
+    EM_BLE_WR(EM_BLE_TXBISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXBISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE) & ~((uint16_t)0x00000020)) | ((uint16_t)txcstf << 5));
+}
+
+__INLINE uint8_t em_ble_txbisph_txcssn_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXBISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+    return ((localVal & ((uint16_t)0x0000001C)) >> 2);
+}
+
+__INLINE void em_ble_txbisph_txcssn_setf(int elt_idx, uint8_t txcssn)
+{
+    ASSERT_ERR((((uint16_t)txcssn << 2) & ~((uint16_t)0x0000001C)) == 0);
+    EM_BLE_WR(EM_BLE_TXBISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE, (EM_BLE_RD(EM_BLE_TXBISPH_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE) & ~((uint16_t)0x0000001C)) | ((uint16_t)txcssn << 2));
+}
+
+/**
+ * @brief TXISOBUFPTR register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  13:00          TXISOBUFPTR   0x0
+ * </pre>
+ */
+#define EM_BLE_TXISOBUFPTR_ADDR   (0x5300400A + EM_BLE_TX_ISO_DESC_OFFSET)
+#define EM_BLE_TXISOBUFPTR_INDEX  0x00000005
+#define EM_BLE_TXISOBUFPTR_RESET  0x00000000
+
+__INLINE uint16_t em_ble_txisobufptr_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_TXISOBUFPTR_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+}
+
+__INLINE void em_ble_txisobufptr_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_TXISOBUFPTR_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_TXISOBUFPTR_MASK   ((uint16_t)0x00003FFF)
+#define EM_BLE_TXISOBUFPTR_LSB    0
+#define EM_BLE_TXISOBUFPTR_WIDTH  ((uint16_t)0x0000000E)
+
+#define EM_BLE_TXISOBUFPTR_RST    0x0
+
+__INLINE uint16_t em_ble_txisobufptr_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_TXISOBUFPTR_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE);
+    ASSERT_ERR((localVal & ~((uint16_t)0x00003FFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void em_ble_txisobufptr_setf(int elt_idx, uint16_t txisobufptr)
+{
+    ASSERT_ERR((((uint16_t)txisobufptr << 0) & ~((uint16_t)0x00003FFF)) == 0);
+    EM_BLE_WR(EM_BLE_TXISOBUFPTR_ADDR + elt_idx * REG_EM_BLE_TX_ISO_DESC_SIZE, (uint16_t)txisobufptr << 0);
+}
+
+
+#endif // _REG_EM_BLE_TX_ISO_DESC_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/reg_em_ble_wpal.h

@@ -0,0 +1,215 @@
+#ifndef _REG_EM_BLE_WPAL_H_
+#define _REG_EM_BLE_WPAL_H_
+
+#include <stdint.h>
+#include "_reg_em_ble_wpal.h"
+#include "compiler.h"
+#include "arch.h"
+#include "em_map.h"
+#include "reg_access.h"
+
+#define REG_EM_BLE_WPAL_COUNT 6
+
+#define REG_EM_BLE_WPAL_DECODING_MASK 0x0000000F
+
+#define REG_EM_BLE_WPAL_ADDR_GET(idx) (EM_BLE_WPAL_OFFSET + (idx) * REG_EM_BLE_WPAL_SIZE)
+
+/**
+ * @brief LIST_INFO register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     15          ENTRY_VALID   0
+ *     14               IDTYPE   0
+ *     01                IN_WL   0
+ *     00           IN_PERADVL   0
+ * </pre>
+ */
+#define EM_BLE_LIST_INFO_ADDR   (0x53004000 + EM_BLE_WPAL_OFFSET)
+#define EM_BLE_LIST_INFO_INDEX  0x00000000
+#define EM_BLE_LIST_INFO_RESET  0x00000000
+
+__INLINE uint16_t em_ble_list_info_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_LIST_INFO_ADDR + elt_idx * REG_EM_BLE_WPAL_SIZE);
+}
+
+__INLINE void em_ble_list_info_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_LIST_INFO_ADDR + elt_idx * REG_EM_BLE_WPAL_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_ENTRY_VALID_BIT    ((uint16_t)0x00008000)
+#define EM_BLE_ENTRY_VALID_POS    15
+#define EM_BLE_IDTYPE_BIT         ((uint16_t)0x00004000)
+#define EM_BLE_IDTYPE_POS         14
+#define EM_BLE_IN_WL_BIT          ((uint16_t)0x00000002)
+#define EM_BLE_IN_WL_POS          1
+#define EM_BLE_IN_PERADVL_BIT     ((uint16_t)0x00000001)
+#define EM_BLE_IN_PERADVL_POS     0
+
+#define EM_BLE_ENTRY_VALID_RST    0x0
+#define EM_BLE_IDTYPE_RST         0x0
+#define EM_BLE_IN_WL_RST          0x0
+#define EM_BLE_IN_PERADVL_RST     0x0
+
+__INLINE void em_ble_list_info_pack(int elt_idx, uint8_t entryvalid, uint8_t idtype, uint8_t inwl, uint8_t inperadvl)
+{
+    ASSERT_ERR((((uint16_t)entryvalid << 15) & ~((uint16_t)0x00008000)) == 0);
+    ASSERT_ERR((((uint16_t)idtype << 14) & ~((uint16_t)0x00004000)) == 0);
+    ASSERT_ERR((((uint16_t)inwl << 1) & ~((uint16_t)0x00000002)) == 0);
+    ASSERT_ERR((((uint16_t)inperadvl << 0) & ~((uint16_t)0x00000001)) == 0);
+    EM_BLE_WR(EM_BLE_LIST_INFO_ADDR + elt_idx * REG_EM_BLE_WPAL_SIZE,  ((uint16_t)entryvalid << 15) | ((uint16_t)idtype << 14) | ((uint16_t)inwl << 1) | ((uint16_t)inperadvl << 0));
+}
+
+__INLINE void em_ble_list_info_unpack(int elt_idx, uint8_t* entryvalid, uint8_t* idtype, uint8_t* inwl, uint8_t* inperadvl)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_LIST_INFO_ADDR + elt_idx * REG_EM_BLE_WPAL_SIZE);
+
+    *entryvalid = (localVal & ((uint16_t)0x00008000)) >> 15;
+    *idtype = (localVal & ((uint16_t)0x00004000)) >> 14;
+    *inwl = (localVal & ((uint16_t)0x00000002)) >> 1;
+    *inperadvl = (localVal & ((uint16_t)0x00000001)) >> 0;
+}
+
+__INLINE uint8_t em_ble_list_info_entry_valid_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_LIST_INFO_ADDR + elt_idx * REG_EM_BLE_WPAL_SIZE);
+    return ((localVal & ((uint16_t)0x00008000)) >> 15);
+}
+
+__INLINE void em_ble_list_info_entry_valid_setf(int elt_idx, uint8_t entryvalid)
+{
+    ASSERT_ERR((((uint16_t)entryvalid << 15) & ~((uint16_t)0x00008000)) == 0);
+    EM_BLE_WR(EM_BLE_LIST_INFO_ADDR + elt_idx * REG_EM_BLE_WPAL_SIZE, (EM_BLE_RD(EM_BLE_LIST_INFO_ADDR + elt_idx * REG_EM_BLE_WPAL_SIZE) & ~((uint16_t)0x00008000)) | ((uint16_t)entryvalid << 15));
+}
+
+__INLINE uint8_t em_ble_list_info_idtype_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_LIST_INFO_ADDR + elt_idx * REG_EM_BLE_WPAL_SIZE);
+    return ((localVal & ((uint16_t)0x00004000)) >> 14);
+}
+
+__INLINE void em_ble_list_info_idtype_setf(int elt_idx, uint8_t idtype)
+{
+    ASSERT_ERR((((uint16_t)idtype << 14) & ~((uint16_t)0x00004000)) == 0);
+    EM_BLE_WR(EM_BLE_LIST_INFO_ADDR + elt_idx * REG_EM_BLE_WPAL_SIZE, (EM_BLE_RD(EM_BLE_LIST_INFO_ADDR + elt_idx * REG_EM_BLE_WPAL_SIZE) & ~((uint16_t)0x00004000)) | ((uint16_t)idtype << 14));
+}
+
+__INLINE uint8_t em_ble_list_info_in_wl_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_LIST_INFO_ADDR + elt_idx * REG_EM_BLE_WPAL_SIZE);
+    return ((localVal & ((uint16_t)0x00000002)) >> 1);
+}
+
+__INLINE void em_ble_list_info_in_wl_setf(int elt_idx, uint8_t inwl)
+{
+    ASSERT_ERR((((uint16_t)inwl << 1) & ~((uint16_t)0x00000002)) == 0);
+    EM_BLE_WR(EM_BLE_LIST_INFO_ADDR + elt_idx * REG_EM_BLE_WPAL_SIZE, (EM_BLE_RD(EM_BLE_LIST_INFO_ADDR + elt_idx * REG_EM_BLE_WPAL_SIZE) & ~((uint16_t)0x00000002)) | ((uint16_t)inwl << 1));
+}
+
+__INLINE uint8_t em_ble_list_info_in_peradvl_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_LIST_INFO_ADDR + elt_idx * REG_EM_BLE_WPAL_SIZE);
+    return ((localVal & ((uint16_t)0x00000001)) >> 0);
+}
+
+__INLINE void em_ble_list_info_in_peradvl_setf(int elt_idx, uint8_t inperadvl)
+{
+    ASSERT_ERR((((uint16_t)inperadvl << 0) & ~((uint16_t)0x00000001)) == 0);
+    EM_BLE_WR(EM_BLE_LIST_INFO_ADDR + elt_idx * REG_EM_BLE_WPAL_SIZE, (EM_BLE_RD(EM_BLE_LIST_INFO_ADDR + elt_idx * REG_EM_BLE_WPAL_SIZE) & ~((uint16_t)0x00000001)) | ((uint16_t)inperadvl << 0));
+}
+
+/**
+ * @brief LIST_BDADDR register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  15:00              LBDADDR   0x0
+ * </pre>
+ */
+#define EM_BLE_LIST_BDADDR_ADDR   (0x53004002 + EM_BLE_WPAL_OFFSET)
+#define EM_BLE_LIST_BDADDR_INDEX  0x00000001
+#define EM_BLE_LIST_BDADDR_RESET  0x00000000
+#define EM_BLE_LIST_BDADDR_COUNT  3
+
+__INLINE uint16_t em_ble_list_bdaddr_get(int elt_idx, int reg_idx)
+{
+    ASSERT_ERR(reg_idx <= 2);
+    return EM_BLE_RD(EM_BLE_LIST_BDADDR_ADDR + elt_idx * REG_EM_BLE_WPAL_SIZE + reg_idx * 2);
+}
+
+__INLINE void em_ble_list_bdaddr_set(int elt_idx, int reg_idx, uint16_t value)
+{
+    ASSERT_ERR(reg_idx <= 2);
+    EM_BLE_WR(EM_BLE_LIST_BDADDR_ADDR + elt_idx * REG_EM_BLE_WPAL_SIZE + reg_idx * 2, value);
+}
+
+// field definitions
+#define EM_BLE_LBDADDR_MASK   ((uint16_t)0x0000FFFF)
+#define EM_BLE_LBDADDR_LSB    0
+#define EM_BLE_LBDADDR_WIDTH  ((uint16_t)0x00000010)
+
+#define EM_BLE_LBDADDR_RST    0x0
+
+__INLINE uint16_t em_ble_list_bdaddr_lbdaddr_getf(int elt_idx, int reg_idx)
+{
+    ASSERT_ERR(reg_idx <= 2);
+    uint16_t localVal = EM_BLE_RD(EM_BLE_LIST_BDADDR_ADDR + elt_idx * REG_EM_BLE_WPAL_SIZE + reg_idx * 2);
+    ASSERT_ERR((localVal & ~((uint16_t)0x0000FFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void em_ble_list_bdaddr_lbdaddr_setf(int elt_idx, int reg_idx, uint16_t lbdaddr)
+{
+    ASSERT_ERR(reg_idx <= 2);
+    ASSERT_ERR((((uint16_t)lbdaddr << 0) & ~((uint16_t)0x0000FFFF)) == 0);
+    EM_BLE_WR(EM_BLE_LIST_BDADDR_ADDR + elt_idx * REG_EM_BLE_WPAL_SIZE + reg_idx * 2, (uint16_t)lbdaddr << 0);
+}
+
+/**
+ * @brief LIST_SID register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  15:00                 LSID   0x0
+ * </pre>
+ */
+#define EM_BLE_LIST_SID_ADDR   (0x53004008 + EM_BLE_WPAL_OFFSET)
+#define EM_BLE_LIST_SID_INDEX  0x00000004
+#define EM_BLE_LIST_SID_RESET  0x00000000
+
+__INLINE uint16_t em_ble_list_sid_get(int elt_idx)
+{
+    return EM_BLE_RD(EM_BLE_LIST_SID_ADDR + elt_idx * REG_EM_BLE_WPAL_SIZE);
+}
+
+__INLINE void em_ble_list_sid_set(int elt_idx, uint16_t value)
+{
+    EM_BLE_WR(EM_BLE_LIST_SID_ADDR + elt_idx * REG_EM_BLE_WPAL_SIZE, value);
+}
+
+// field definitions
+#define EM_BLE_LSID_MASK   ((uint16_t)0x0000FFFF)
+#define EM_BLE_LSID_LSB    0
+#define EM_BLE_LSID_WIDTH  ((uint16_t)0x00000010)
+
+#define EM_BLE_LSID_RST    0x0
+
+__INLINE uint16_t em_ble_list_sid_lsid_getf(int elt_idx)
+{
+    uint16_t localVal = EM_BLE_RD(EM_BLE_LIST_SID_ADDR + elt_idx * REG_EM_BLE_WPAL_SIZE);
+    ASSERT_ERR((localVal & ~((uint16_t)0x0000FFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void em_ble_list_sid_lsid_setf(int elt_idx, uint16_t lsid)
+{
+    ASSERT_ERR((((uint16_t)lsid << 0) & ~((uint16_t)0x0000FFFF)) == 0);
+    EM_BLE_WR(EM_BLE_LIST_SID_ADDR + elt_idx * REG_EM_BLE_WPAL_SIZE, (uint16_t)lsid << 0);
+}
+
+
+#endif // _REG_EM_BLE_WPAL_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/reg_em_et.h

@@ -0,0 +1,769 @@
+#ifndef _REG_EM_ET_H_
+#define _REG_EM_ET_H_
+
+#include <stdint.h>
+#include "_reg_em_et.h"
+#include "compiler.h"
+#include "arch.h"
+#include "em_map.h"
+#include "reg_access.h"
+
+#define REG_EM_ET_COUNT 8
+
+#define REG_EM_ET_DECODING_MASK 0x0000000F
+
+#define REG_EM_ET_ADDR_GET(idx) (EM_ET_OFFSET + (idx) * REG_EM_ET_SIZE)
+
+/**
+ * @brief BT_EXTAB register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  15:11            SCH_PRIO1   0x0
+ *     10                  SPA   0
+ *     09                  CSB   0
+ *     08                SNIFF   0
+ *     07                 RSVD   0
+ *     06                 eSCO   0
+ *  05:03               STATUS   0x0
+ *  02:00                 MODE   0x0
+ * </pre>
+ */
+#define EM_BT_EXTAB_ADDR   (0x53004000 + EM_ET_OFFSET)
+#define EM_BT_EXTAB_INDEX  0x00000000
+#define EM_BT_EXTAB_RESET  0x00000000
+
+__INLINE uint16_t em_bt_extab_get(int elt_idx)
+{
+    return EM_RD(EM_BT_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE);
+}
+
+__INLINE void em_bt_extab_set(int elt_idx, uint16_t value)
+{
+    EM_WR(EM_BT_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE, value);
+}
+
+// field definitions
+#define EM_SCH_PRIO1_MASK   ((uint16_t)0x0000F800)
+#define EM_SCH_PRIO1_LSB    11
+#define EM_SCH_PRIO1_WIDTH  ((uint16_t)0x00000005)
+#define EM_SPA_BIT          ((uint16_t)0x00000400)
+#define EM_SPA_POS          10
+#define EM_CSB_BIT          ((uint16_t)0x00000200)
+#define EM_CSB_POS          9
+#define EM_SNIFF_BIT        ((uint16_t)0x00000100)
+#define EM_SNIFF_POS        8
+#define EM_RSVD_BIT         ((uint16_t)0x00000080)
+#define EM_RSVD_POS         7
+#define EM_E_SCO_BIT        ((uint16_t)0x00000040)
+#define EM_E_SCO_POS        6
+#define EM_STATUS_MASK      ((uint16_t)0x00000038)
+#define EM_STATUS_LSB       3
+#define EM_STATUS_WIDTH     ((uint16_t)0x00000003)
+#define EM_MODE_MASK        ((uint16_t)0x00000007)
+#define EM_MODE_LSB         0
+#define EM_MODE_WIDTH       ((uint16_t)0x00000003)
+
+#define EM_SCH_PRIO1_RST    0x0
+#define EM_SPA_RST          0x0
+#define EM_CSB_RST          0x0
+#define EM_SNIFF_RST        0x0
+#define EM_RSVD_RST         0x0
+#define EM_E_SCO_RST        0x0
+#define EM_STATUS_RST       0x0
+#define EM_MODE_RST         0x0
+
+__INLINE void em_bt_extab_pack(int elt_idx, uint8_t schprio1, uint8_t spa, uint8_t csb, uint8_t sniff, uint8_t rsvd, uint8_t esco, uint8_t status, uint8_t mode)
+{
+    ASSERT_ERR((((uint16_t)schprio1 << 11) & ~((uint16_t)0x0000F800)) == 0);
+    ASSERT_ERR((((uint16_t)spa << 10) & ~((uint16_t)0x00000400)) == 0);
+    ASSERT_ERR((((uint16_t)csb << 9) & ~((uint16_t)0x00000200)) == 0);
+    ASSERT_ERR((((uint16_t)sniff << 8) & ~((uint16_t)0x00000100)) == 0);
+    ASSERT_ERR((((uint16_t)rsvd << 7) & ~((uint16_t)0x00000080)) == 0);
+    ASSERT_ERR((((uint16_t)esco << 6) & ~((uint16_t)0x00000040)) == 0);
+    ASSERT_ERR((((uint16_t)status << 3) & ~((uint16_t)0x00000038)) == 0);
+    ASSERT_ERR((((uint16_t)mode << 0) & ~((uint16_t)0x00000007)) == 0);
+    EM_WR(EM_BT_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE,  ((uint16_t)schprio1 << 11) | ((uint16_t)spa << 10) | ((uint16_t)csb << 9) | ((uint16_t)sniff << 8) | ((uint16_t)rsvd << 7) | ((uint16_t)esco << 6) | ((uint16_t)status << 3) | ((uint16_t)mode << 0));
+}
+
+__INLINE void em_bt_extab_unpack(int elt_idx, uint8_t* schprio1, uint8_t* spa, uint8_t* csb, uint8_t* sniff, uint8_t* rsvd, uint8_t* esco, uint8_t* status, uint8_t* mode)
+{
+    uint16_t localVal = EM_RD(EM_BT_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE);
+
+    *schprio1 = (localVal & ((uint16_t)0x0000F800)) >> 11;
+    *spa = (localVal & ((uint16_t)0x00000400)) >> 10;
+    *csb = (localVal & ((uint16_t)0x00000200)) >> 9;
+    *sniff = (localVal & ((uint16_t)0x00000100)) >> 8;
+    *rsvd = (localVal & ((uint16_t)0x00000080)) >> 7;
+    *esco = (localVal & ((uint16_t)0x00000040)) >> 6;
+    *status = (localVal & ((uint16_t)0x00000038)) >> 3;
+    *mode = (localVal & ((uint16_t)0x00000007)) >> 0;
+}
+
+__INLINE uint8_t em_bt_extab_sch_prio1_getf(int elt_idx)
+{
+    uint16_t localVal = EM_RD(EM_BT_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE);
+    return ((localVal & ((uint16_t)0x0000F800)) >> 11);
+}
+
+__INLINE void em_bt_extab_sch_prio1_setf(int elt_idx, uint8_t schprio1)
+{
+    ASSERT_ERR((((uint16_t)schprio1 << 11) & ~((uint16_t)0x0000F800)) == 0);
+    EM_WR(EM_BT_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE, (EM_RD(EM_BT_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE) & ~((uint16_t)0x0000F800)) | ((uint16_t)schprio1 << 11));
+}
+
+__INLINE uint8_t em_bt_extab_spa_getf(int elt_idx)
+{
+    uint16_t localVal = EM_RD(EM_BT_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE);
+    return ((localVal & ((uint16_t)0x00000400)) >> 10);
+}
+
+__INLINE void em_bt_extab_spa_setf(int elt_idx, uint8_t spa)
+{
+    ASSERT_ERR((((uint16_t)spa << 10) & ~((uint16_t)0x00000400)) == 0);
+    EM_WR(EM_BT_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE, (EM_RD(EM_BT_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE) & ~((uint16_t)0x00000400)) | ((uint16_t)spa << 10));
+}
+
+__INLINE uint8_t em_bt_extab_csb_getf(int elt_idx)
+{
+    uint16_t localVal = EM_RD(EM_BT_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE);
+    return ((localVal & ((uint16_t)0x00000200)) >> 9);
+}
+
+__INLINE void em_bt_extab_csb_setf(int elt_idx, uint8_t csb)
+{
+    ASSERT_ERR((((uint16_t)csb << 9) & ~((uint16_t)0x00000200)) == 0);
+    EM_WR(EM_BT_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE, (EM_RD(EM_BT_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE) & ~((uint16_t)0x00000200)) | ((uint16_t)csb << 9));
+}
+
+__INLINE uint8_t em_bt_extab_sniff_getf(int elt_idx)
+{
+    uint16_t localVal = EM_RD(EM_BT_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE);
+    return ((localVal & ((uint16_t)0x00000100)) >> 8);
+}
+
+__INLINE void em_bt_extab_sniff_setf(int elt_idx, uint8_t sniff)
+{
+    ASSERT_ERR((((uint16_t)sniff << 8) & ~((uint16_t)0x00000100)) == 0);
+    EM_WR(EM_BT_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE, (EM_RD(EM_BT_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE) & ~((uint16_t)0x00000100)) | ((uint16_t)sniff << 8));
+}
+
+__INLINE uint8_t em_bt_extab_rsvd_getf(int elt_idx)
+{
+    uint16_t localVal = EM_RD(EM_BT_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE);
+    return ((localVal & ((uint16_t)0x00000080)) >> 7);
+}
+
+__INLINE void em_bt_extab_rsvd_setf(int elt_idx, uint8_t rsvd)
+{
+    ASSERT_ERR((((uint16_t)rsvd << 7) & ~((uint16_t)0x00000080)) == 0);
+    EM_WR(EM_BT_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE, (EM_RD(EM_BT_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE) & ~((uint16_t)0x00000080)) | ((uint16_t)rsvd << 7));
+}
+
+__INLINE uint8_t em_bt_extab_e_sco_getf(int elt_idx)
+{
+    uint16_t localVal = EM_RD(EM_BT_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE);
+    return ((localVal & ((uint16_t)0x00000040)) >> 6);
+}
+
+__INLINE void em_bt_extab_e_sco_setf(int elt_idx, uint8_t esco)
+{
+    ASSERT_ERR((((uint16_t)esco << 6) & ~((uint16_t)0x00000040)) == 0);
+    EM_WR(EM_BT_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE, (EM_RD(EM_BT_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE) & ~((uint16_t)0x00000040)) | ((uint16_t)esco << 6));
+}
+
+__INLINE uint8_t em_bt_extab_status_getf(int elt_idx)
+{
+    uint16_t localVal = EM_RD(EM_BT_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE);
+    return ((localVal & ((uint16_t)0x00000038)) >> 3);
+}
+
+__INLINE void em_bt_extab_status_setf(int elt_idx, uint8_t status)
+{
+    ASSERT_ERR((((uint16_t)status << 3) & ~((uint16_t)0x00000038)) == 0);
+    EM_WR(EM_BT_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE, (EM_RD(EM_BT_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE) & ~((uint16_t)0x00000038)) | ((uint16_t)status << 3));
+}
+
+__INLINE uint8_t em_bt_extab_mode_getf(int elt_idx)
+{
+    uint16_t localVal = EM_RD(EM_BT_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE);
+    return ((localVal & ((uint16_t)0x00000007)) >> 0);
+}
+
+__INLINE void em_bt_extab_mode_setf(int elt_idx, uint8_t mode)
+{
+    ASSERT_ERR((((uint16_t)mode << 0) & ~((uint16_t)0x00000007)) == 0);
+    EM_WR(EM_BT_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE, (EM_RD(EM_BT_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE) & ~((uint16_t)0x00000007)) | ((uint16_t)mode << 0));
+}
+
+/**
+ * @brief LE_EXTAB register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  15:11            SCH_PRIO1   0x0
+ *     10                  SPA   0
+ *     09                  SIC   0
+ *     08               AE_NPS   0
+ *     07                 RSVD   0
+ *     06                  ISO   0
+ *  05:03               STATUS   0x0
+ *  02:00                 MODE   0x0
+ * </pre>
+ */
+#define EM_LE_EXTAB_ADDR   (0x53004000 + EM_ET_OFFSET)
+#define EM_LE_EXTAB_INDEX  0x00000000
+#define EM_LE_EXTAB_RESET  0x00000000
+
+__INLINE uint16_t em_le_extab_get(int elt_idx)
+{
+    return EM_RD(EM_LE_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE);
+}
+
+__INLINE void em_le_extab_set(int elt_idx, uint16_t value)
+{
+    EM_WR(EM_LE_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE, value);
+}
+
+// field definitions
+#define EM_SCH_PRIO1_MASK   ((uint16_t)0x0000F800)
+#define EM_SCH_PRIO1_LSB    11
+#define EM_SCH_PRIO1_WIDTH  ((uint16_t)0x00000005)
+#define EM_SPA_BIT          ((uint16_t)0x00000400)
+#define EM_SPA_POS          10
+#define EM_SIC_BIT          ((uint16_t)0x00000200)
+#define EM_SIC_POS          9
+#define EM_AE_NPS_BIT       ((uint16_t)0x00000100)
+#define EM_AE_NPS_POS       8
+#define EM_RSVD_BIT         ((uint16_t)0x00000080)
+#define EM_RSVD_POS         7
+#define EM_ISO_BIT          ((uint16_t)0x00000040)
+#define EM_ISO_POS          6
+#define EM_STATUS_MASK      ((uint16_t)0x00000038)
+#define EM_STATUS_LSB       3
+#define EM_STATUS_WIDTH     ((uint16_t)0x00000003)
+#define EM_MODE_MASK        ((uint16_t)0x00000007)
+#define EM_MODE_LSB         0
+#define EM_MODE_WIDTH       ((uint16_t)0x00000003)
+
+#define EM_SCH_PRIO1_RST    0x0
+#define EM_SPA_RST          0x0
+#define EM_SIC_RST          0x0
+#define EM_AE_NPS_RST       0x0
+#define EM_RSVD_RST         0x0
+#define EM_ISO_RST          0x0
+#define EM_STATUS_RST       0x0
+#define EM_MODE_RST         0x0
+
+__INLINE void em_le_extab_pack(int elt_idx, uint8_t schprio1, uint8_t spa, uint8_t sic, uint8_t aenps, uint8_t rsvd, uint8_t iso, uint8_t status, uint8_t mode)
+{
+    ASSERT_ERR((((uint16_t)schprio1 << 11) & ~((uint16_t)0x0000F800)) == 0);
+    ASSERT_ERR((((uint16_t)spa << 10) & ~((uint16_t)0x00000400)) == 0);
+    ASSERT_ERR((((uint16_t)sic << 9) & ~((uint16_t)0x00000200)) == 0);
+    ASSERT_ERR((((uint16_t)aenps << 8) & ~((uint16_t)0x00000100)) == 0);
+    ASSERT_ERR((((uint16_t)rsvd << 7) & ~((uint16_t)0x00000080)) == 0);
+    ASSERT_ERR((((uint16_t)iso << 6) & ~((uint16_t)0x00000040)) == 0);
+    ASSERT_ERR((((uint16_t)status << 3) & ~((uint16_t)0x00000038)) == 0);
+    ASSERT_ERR((((uint16_t)mode << 0) & ~((uint16_t)0x00000007)) == 0);
+    EM_WR(EM_LE_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE,  ((uint16_t)schprio1 << 11) | ((uint16_t)spa << 10) | ((uint16_t)sic << 9) | ((uint16_t)aenps << 8) | ((uint16_t)rsvd << 7) | ((uint16_t)iso << 6) | ((uint16_t)status << 3) | ((uint16_t)mode << 0));
+}
+
+__INLINE void em_le_extab_unpack(int elt_idx, uint8_t* schprio1, uint8_t* spa, uint8_t* sic, uint8_t* aenps, uint8_t* rsvd, uint8_t* iso, uint8_t* status, uint8_t* mode)
+{
+    uint16_t localVal = EM_RD(EM_LE_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE);
+
+    *schprio1 = (localVal & ((uint16_t)0x0000F800)) >> 11;
+    *spa = (localVal & ((uint16_t)0x00000400)) >> 10;
+    *sic = (localVal & ((uint16_t)0x00000200)) >> 9;
+    *aenps = (localVal & ((uint16_t)0x00000100)) >> 8;
+    *rsvd = (localVal & ((uint16_t)0x00000080)) >> 7;
+    *iso = (localVal & ((uint16_t)0x00000040)) >> 6;
+    *status = (localVal & ((uint16_t)0x00000038)) >> 3;
+    *mode = (localVal & ((uint16_t)0x00000007)) >> 0;
+}
+
+__INLINE uint8_t em_le_extab_sch_prio1_getf(int elt_idx)
+{
+    uint16_t localVal = EM_RD(EM_LE_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE);
+    return ((localVal & ((uint16_t)0x0000F800)) >> 11);
+}
+
+__INLINE void em_le_extab_sch_prio1_setf(int elt_idx, uint8_t schprio1)
+{
+    ASSERT_ERR((((uint16_t)schprio1 << 11) & ~((uint16_t)0x0000F800)) == 0);
+    EM_WR(EM_LE_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE, (EM_RD(EM_LE_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE) & ~((uint16_t)0x0000F800)) | ((uint16_t)schprio1 << 11));
+}
+
+__INLINE uint8_t em_le_extab_spa_getf(int elt_idx)
+{
+    uint16_t localVal = EM_RD(EM_LE_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE);
+    return ((localVal & ((uint16_t)0x00000400)) >> 10);
+}
+
+__INLINE void em_le_extab_spa_setf(int elt_idx, uint8_t spa)
+{
+    ASSERT_ERR((((uint16_t)spa << 10) & ~((uint16_t)0x00000400)) == 0);
+    EM_WR(EM_LE_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE, (EM_RD(EM_LE_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE) & ~((uint16_t)0x00000400)) | ((uint16_t)spa << 10));
+}
+
+__INLINE uint8_t em_le_extab_sic_getf(int elt_idx)
+{
+    uint16_t localVal = EM_RD(EM_LE_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE);
+    return ((localVal & ((uint16_t)0x00000200)) >> 9);
+}
+
+__INLINE void em_le_extab_sic_setf(int elt_idx, uint8_t sic)
+{
+    ASSERT_ERR((((uint16_t)sic << 9) & ~((uint16_t)0x00000200)) == 0);
+    EM_WR(EM_LE_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE, (EM_RD(EM_LE_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE) & ~((uint16_t)0x00000200)) | ((uint16_t)sic << 9));
+}
+
+__INLINE uint8_t em_le_extab_ae_nps_getf(int elt_idx)
+{
+    uint16_t localVal = EM_RD(EM_LE_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE);
+    return ((localVal & ((uint16_t)0x00000100)) >> 8);
+}
+
+__INLINE void em_le_extab_ae_nps_setf(int elt_idx, uint8_t aenps)
+{
+    ASSERT_ERR((((uint16_t)aenps << 8) & ~((uint16_t)0x00000100)) == 0);
+    EM_WR(EM_LE_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE, (EM_RD(EM_LE_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE) & ~((uint16_t)0x00000100)) | ((uint16_t)aenps << 8));
+}
+
+__INLINE uint8_t em_le_extab_rsvd_getf(int elt_idx)
+{
+    uint16_t localVal = EM_RD(EM_LE_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE);
+    return ((localVal & ((uint16_t)0x00000080)) >> 7);
+}
+
+__INLINE void em_le_extab_rsvd_setf(int elt_idx, uint8_t rsvd)
+{
+    ASSERT_ERR((((uint16_t)rsvd << 7) & ~((uint16_t)0x00000080)) == 0);
+    EM_WR(EM_LE_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE, (EM_RD(EM_LE_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE) & ~((uint16_t)0x00000080)) | ((uint16_t)rsvd << 7));
+}
+
+__INLINE uint8_t em_le_extab_iso_getf(int elt_idx)
+{
+    uint16_t localVal = EM_RD(EM_LE_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE);
+    return ((localVal & ((uint16_t)0x00000040)) >> 6);
+}
+
+__INLINE void em_le_extab_iso_setf(int elt_idx, uint8_t iso)
+{
+    ASSERT_ERR((((uint16_t)iso << 6) & ~((uint16_t)0x00000040)) == 0);
+    EM_WR(EM_LE_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE, (EM_RD(EM_LE_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE) & ~((uint16_t)0x00000040)) | ((uint16_t)iso << 6));
+}
+
+__INLINE uint8_t em_le_extab_status_getf(int elt_idx)
+{
+    uint16_t localVal = EM_RD(EM_LE_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE);
+    return ((localVal & ((uint16_t)0x00000038)) >> 3);
+}
+
+__INLINE void em_le_extab_status_setf(int elt_idx, uint8_t status)
+{
+    ASSERT_ERR((((uint16_t)status << 3) & ~((uint16_t)0x00000038)) == 0);
+    EM_WR(EM_LE_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE, (EM_RD(EM_LE_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE) & ~((uint16_t)0x00000038)) | ((uint16_t)status << 3));
+}
+
+__INLINE uint8_t em_le_extab_mode_getf(int elt_idx)
+{
+    uint16_t localVal = EM_RD(EM_LE_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE);
+    return ((localVal & ((uint16_t)0x00000007)) >> 0);
+}
+
+__INLINE void em_le_extab_mode_setf(int elt_idx, uint8_t mode)
+{
+    ASSERT_ERR((((uint16_t)mode << 0) & ~((uint16_t)0x00000007)) == 0);
+    EM_WR(EM_LE_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE, (EM_RD(EM_LE_EXTAB_ADDR + elt_idx * REG_EM_ET_SIZE) & ~((uint16_t)0x00000007)) | ((uint16_t)mode << 0));
+}
+
+/**
+ * @brief RAWSTP0 register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  15:00              RAWSTP0   0x0
+ * </pre>
+ */
+#define EM_RAWSTP0_ADDR   (0x53004002 + EM_ET_OFFSET)
+#define EM_RAWSTP0_INDEX  0x00000001
+#define EM_RAWSTP0_RESET  0x00000000
+
+__INLINE uint16_t em_rawstp0_get(int elt_idx)
+{
+    return EM_RD(EM_RAWSTP0_ADDR + elt_idx * REG_EM_ET_SIZE);
+}
+
+__INLINE void em_rawstp0_set(int elt_idx, uint16_t value)
+{
+    EM_WR(EM_RAWSTP0_ADDR + elt_idx * REG_EM_ET_SIZE, value);
+}
+
+// field definitions
+#define EM_RAWSTP0_MASK   ((uint16_t)0x0000FFFF)
+#define EM_RAWSTP0_LSB    0
+#define EM_RAWSTP0_WIDTH  ((uint16_t)0x00000010)
+
+#define EM_RAWSTP0_RST    0x0
+
+__INLINE uint16_t em_rawstp0_getf(int elt_idx)
+{
+    uint16_t localVal = EM_RD(EM_RAWSTP0_ADDR + elt_idx * REG_EM_ET_SIZE);
+    ASSERT_ERR((localVal & ~((uint16_t)0x0000FFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void em_rawstp0_setf(int elt_idx, uint16_t rawstp0)
+{
+    ASSERT_ERR((((uint16_t)rawstp0 << 0) & ~((uint16_t)0x0000FFFF)) == 0);
+    EM_WR(EM_RAWSTP0_ADDR + elt_idx * REG_EM_ET_SIZE, (uint16_t)rawstp0 << 0);
+}
+
+/**
+ * @brief RAWSTP1 register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  11:00              RAWSTP1   0x0
+ * </pre>
+ */
+#define EM_RAWSTP1_ADDR   (0x53004004 + EM_ET_OFFSET)
+#define EM_RAWSTP1_INDEX  0x00000002
+#define EM_RAWSTP1_RESET  0x00000000
+
+__INLINE uint16_t em_rawstp1_get(int elt_idx)
+{
+    return EM_RD(EM_RAWSTP1_ADDR + elt_idx * REG_EM_ET_SIZE);
+}
+
+__INLINE void em_rawstp1_set(int elt_idx, uint16_t value)
+{
+    EM_WR(EM_RAWSTP1_ADDR + elt_idx * REG_EM_ET_SIZE, value);
+}
+
+// field definitions
+#define EM_RAWSTP1_MASK   ((uint16_t)0x00000FFF)
+#define EM_RAWSTP1_LSB    0
+#define EM_RAWSTP1_WIDTH  ((uint16_t)0x0000000C)
+
+#define EM_RAWSTP1_RST    0x0
+
+__INLINE uint16_t em_rawstp1_getf(int elt_idx)
+{
+    uint16_t localVal = EM_RD(EM_RAWSTP1_ADDR + elt_idx * REG_EM_ET_SIZE);
+    ASSERT_ERR((localVal & ~((uint16_t)0x00000FFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void em_rawstp1_setf(int elt_idx, uint16_t rawstp1)
+{
+    ASSERT_ERR((((uint16_t)rawstp1 << 0) & ~((uint16_t)0x00000FFF)) == 0);
+    EM_WR(EM_RAWSTP1_ADDR + elt_idx * REG_EM_ET_SIZE, (uint16_t)rawstp1 << 0);
+}
+
+/**
+ * @brief FINESTP register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  09:00              FINESTP   0x0
+ * </pre>
+ */
+#define EM_FINESTP_ADDR   (0x53004006 + EM_ET_OFFSET)
+#define EM_FINESTP_INDEX  0x00000003
+#define EM_FINESTP_RESET  0x00000000
+
+__INLINE uint16_t em_finestp_get(int elt_idx)
+{
+    return EM_RD(EM_FINESTP_ADDR + elt_idx * REG_EM_ET_SIZE);
+}
+
+__INLINE void em_finestp_set(int elt_idx, uint16_t value)
+{
+    EM_WR(EM_FINESTP_ADDR + elt_idx * REG_EM_ET_SIZE, value);
+}
+
+// field definitions
+#define EM_FINESTP_MASK   ((uint16_t)0x000003FF)
+#define EM_FINESTP_LSB    0
+#define EM_FINESTP_WIDTH  ((uint16_t)0x0000000A)
+
+#define EM_FINESTP_RST    0x0
+
+__INLINE uint16_t em_finestp_getf(int elt_idx)
+{
+    uint16_t localVal = EM_RD(EM_FINESTP_ADDR + elt_idx * REG_EM_ET_SIZE);
+    ASSERT_ERR((localVal & ~((uint16_t)0x000003FF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void em_finestp_setf(int elt_idx, uint16_t finestp)
+{
+    ASSERT_ERR((((uint16_t)finestp << 0) & ~((uint16_t)0x000003FF)) == 0);
+    EM_WR(EM_FINESTP_ADDR + elt_idx * REG_EM_ET_SIZE, (uint16_t)finestp << 0);
+}
+
+/**
+ * @brief CSPTR register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  13:00                CSPTR   0x0
+ * </pre>
+ */
+#define EM_CSPTR_ADDR   (0x53004008 + EM_ET_OFFSET)
+#define EM_CSPTR_INDEX  0x00000004
+#define EM_CSPTR_RESET  0x00000000
+
+__INLINE uint16_t em_csptr_get(int elt_idx)
+{
+    return EM_RD(EM_CSPTR_ADDR + elt_idx * REG_EM_ET_SIZE);
+}
+
+__INLINE void em_csptr_set(int elt_idx, uint16_t value)
+{
+    EM_WR(EM_CSPTR_ADDR + elt_idx * REG_EM_ET_SIZE, value);
+}
+
+// field definitions
+#define EM_CSPTR_MASK   ((uint16_t)0x00003FFF)
+#define EM_CSPTR_LSB    0
+#define EM_CSPTR_WIDTH  ((uint16_t)0x0000000E)
+
+#define EM_CSPTR_RST    0x0
+
+__INLINE uint16_t em_csptr_getf(int elt_idx)
+{
+    uint16_t localVal = EM_RD(EM_CSPTR_ADDR + elt_idx * REG_EM_ET_SIZE);
+    ASSERT_ERR((localVal & ~((uint16_t)0x00003FFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void em_csptr_setf(int elt_idx, uint16_t csptr)
+{
+    ASSERT_ERR((((uint16_t)csptr << 0) & ~((uint16_t)0x00003FFF)) == 0);
+    EM_WR(EM_CSPTR_ADDR + elt_idx * REG_EM_ET_SIZE, (uint16_t)csptr << 0);
+}
+
+/**
+ * @brief PRIOBW register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     15          PRIO1D_UNIT   0
+ *  14:00               PRIO1D   0x0
+ * </pre>
+ */
+#define EM_PRIOBW_ADDR   (0x5300400A + EM_ET_OFFSET)
+#define EM_PRIOBW_INDEX  0x00000005
+#define EM_PRIOBW_RESET  0x00000000
+
+__INLINE uint16_t em_priobw_get(int elt_idx)
+{
+    return EM_RD(EM_PRIOBW_ADDR + elt_idx * REG_EM_ET_SIZE);
+}
+
+__INLINE void em_priobw_set(int elt_idx, uint16_t value)
+{
+    EM_WR(EM_PRIOBW_ADDR + elt_idx * REG_EM_ET_SIZE, value);
+}
+
+// field definitions
+#define EM_PRIO1D_UNIT_BIT    ((uint16_t)0x00008000)
+#define EM_PRIO1D_UNIT_POS    15
+#define EM_PRIO1D_MASK        ((uint16_t)0x00007FFF)
+#define EM_PRIO1D_LSB         0
+#define EM_PRIO1D_WIDTH       ((uint16_t)0x0000000F)
+
+#define EM_PRIO1D_UNIT_RST    0x0
+#define EM_PRIO1D_RST         0x0
+
+__INLINE void em_priobw_pack(int elt_idx, uint8_t prio1dunit, uint16_t prio1d)
+{
+    ASSERT_ERR((((uint16_t)prio1dunit << 15) & ~((uint16_t)0x00008000)) == 0);
+    ASSERT_ERR((((uint16_t)prio1d << 0) & ~((uint16_t)0x00007FFF)) == 0);
+    EM_WR(EM_PRIOBW_ADDR + elt_idx * REG_EM_ET_SIZE,  ((uint16_t)prio1dunit << 15) | ((uint16_t)prio1d << 0));
+}
+
+__INLINE void em_priobw_unpack(int elt_idx, uint8_t* prio1dunit, uint16_t* prio1d)
+{
+    uint16_t localVal = EM_RD(EM_PRIOBW_ADDR + elt_idx * REG_EM_ET_SIZE);
+
+    *prio1dunit = (localVal & ((uint16_t)0x00008000)) >> 15;
+    *prio1d = (localVal & ((uint16_t)0x00007FFF)) >> 0;
+}
+
+__INLINE uint8_t em_priobw_prio1d_unit_getf(int elt_idx)
+{
+    uint16_t localVal = EM_RD(EM_PRIOBW_ADDR + elt_idx * REG_EM_ET_SIZE);
+    return ((localVal & ((uint16_t)0x00008000)) >> 15);
+}
+
+__INLINE void em_priobw_prio1d_unit_setf(int elt_idx, uint8_t prio1dunit)
+{
+    ASSERT_ERR((((uint16_t)prio1dunit << 15) & ~((uint16_t)0x00008000)) == 0);
+    EM_WR(EM_PRIOBW_ADDR + elt_idx * REG_EM_ET_SIZE, (EM_RD(EM_PRIOBW_ADDR + elt_idx * REG_EM_ET_SIZE) & ~((uint16_t)0x00008000)) | ((uint16_t)prio1dunit << 15));
+}
+
+__INLINE uint16_t em_priobw_prio1d_getf(int elt_idx)
+{
+    uint16_t localVal = EM_RD(EM_PRIOBW_ADDR + elt_idx * REG_EM_ET_SIZE);
+    return ((localVal & ((uint16_t)0x00007FFF)) >> 0);
+}
+
+__INLINE void em_priobw_prio1d_setf(int elt_idx, uint16_t prio1d)
+{
+    ASSERT_ERR((((uint16_t)prio1d << 0) & ~((uint16_t)0x00007FFF)) == 0);
+    EM_WR(EM_PRIOBW_ADDR + elt_idx * REG_EM_ET_SIZE, (EM_RD(EM_PRIOBW_ADDR + elt_idx * REG_EM_ET_SIZE) & ~((uint16_t)0x00007FFF)) | ((uint16_t)prio1d << 0));
+}
+
+/**
+ * @brief PRIOLVL register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  12:08            SCH_PRIO3   0x0
+ *  04:00            SCH_PRIO2   0x0
+ * </pre>
+ */
+#define EM_PRIOLVL_ADDR   (0x5300400C + EM_ET_OFFSET)
+#define EM_PRIOLVL_INDEX  0x00000006
+#define EM_PRIOLVL_RESET  0x00000000
+
+__INLINE uint16_t em_priolvl_get(int elt_idx)
+{
+    return EM_RD(EM_PRIOLVL_ADDR + elt_idx * REG_EM_ET_SIZE);
+}
+
+__INLINE void em_priolvl_set(int elt_idx, uint16_t value)
+{
+    EM_WR(EM_PRIOLVL_ADDR + elt_idx * REG_EM_ET_SIZE, value);
+}
+
+// field definitions
+#define EM_SCH_PRIO3_MASK   ((uint16_t)0x00001F00)
+#define EM_SCH_PRIO3_LSB    8
+#define EM_SCH_PRIO3_WIDTH  ((uint16_t)0x00000005)
+#define EM_SCH_PRIO2_MASK   ((uint16_t)0x0000001F)
+#define EM_SCH_PRIO2_LSB    0
+#define EM_SCH_PRIO2_WIDTH  ((uint16_t)0x00000005)
+
+#define EM_SCH_PRIO3_RST    0x0
+#define EM_SCH_PRIO2_RST    0x0
+
+__INLINE void em_priolvl_pack(int elt_idx, uint8_t schprio3, uint8_t schprio2)
+{
+    ASSERT_ERR((((uint16_t)schprio3 << 8) & ~((uint16_t)0x00001F00)) == 0);
+    ASSERT_ERR((((uint16_t)schprio2 << 0) & ~((uint16_t)0x0000001F)) == 0);
+    EM_WR(EM_PRIOLVL_ADDR + elt_idx * REG_EM_ET_SIZE,  ((uint16_t)schprio3 << 8) | ((uint16_t)schprio2 << 0));
+}
+
+__INLINE void em_priolvl_unpack(int elt_idx, uint8_t* schprio3, uint8_t* schprio2)
+{
+    uint16_t localVal = EM_RD(EM_PRIOLVL_ADDR + elt_idx * REG_EM_ET_SIZE);
+
+    *schprio3 = (localVal & ((uint16_t)0x00001F00)) >> 8;
+    *schprio2 = (localVal & ((uint16_t)0x0000001F)) >> 0;
+}
+
+__INLINE uint8_t em_priolvl_sch_prio3_getf(int elt_idx)
+{
+    uint16_t localVal = EM_RD(EM_PRIOLVL_ADDR + elt_idx * REG_EM_ET_SIZE);
+    return ((localVal & ((uint16_t)0x00001F00)) >> 8);
+}
+
+__INLINE void em_priolvl_sch_prio3_setf(int elt_idx, uint8_t schprio3)
+{
+    ASSERT_ERR((((uint16_t)schprio3 << 8) & ~((uint16_t)0x00001F00)) == 0);
+    EM_WR(EM_PRIOLVL_ADDR + elt_idx * REG_EM_ET_SIZE, (EM_RD(EM_PRIOLVL_ADDR + elt_idx * REG_EM_ET_SIZE) & ~((uint16_t)0x00001F00)) | ((uint16_t)schprio3 << 8));
+}
+
+__INLINE uint8_t em_priolvl_sch_prio2_getf(int elt_idx)
+{
+    uint16_t localVal = EM_RD(EM_PRIOLVL_ADDR + elt_idx * REG_EM_ET_SIZE);
+    return ((localVal & ((uint16_t)0x0000001F)) >> 0);
+}
+
+__INLINE void em_priolvl_sch_prio2_setf(int elt_idx, uint8_t schprio2)
+{
+    ASSERT_ERR((((uint16_t)schprio2 << 0) & ~((uint16_t)0x0000001F)) == 0);
+    EM_WR(EM_PRIOLVL_ADDR + elt_idx * REG_EM_ET_SIZE, (EM_RD(EM_PRIOLVL_ADDR + elt_idx * REG_EM_ET_SIZE) & ~((uint16_t)0x0000001F)) | ((uint16_t)schprio2 << 0));
+}
+
+/**
+ * @brief PTI_VXCHAN register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  12:08             PTI_PRIO   0x0
+ *  01:00               VXCHAN   0x0
+ * </pre>
+ */
+#define EM_PTI_VXCHAN_ADDR   (0x5300400E + EM_ET_OFFSET)
+#define EM_PTI_VXCHAN_INDEX  0x00000007
+#define EM_PTI_VXCHAN_RESET  0x00000000
+
+__INLINE uint16_t em_pti_vxchan_get(int elt_idx)
+{
+    return EM_RD(EM_PTI_VXCHAN_ADDR + elt_idx * REG_EM_ET_SIZE);
+}
+
+__INLINE void em_pti_vxchan_set(int elt_idx, uint16_t value)
+{
+    EM_WR(EM_PTI_VXCHAN_ADDR + elt_idx * REG_EM_ET_SIZE, value);
+}
+
+// field definitions
+#define EM_PTI_PRIO_MASK   ((uint16_t)0x00001F00)
+#define EM_PTI_PRIO_LSB    8
+#define EM_PTI_PRIO_WIDTH  ((uint16_t)0x00000005)
+#define EM_VXCHAN_MASK     ((uint16_t)0x00000003)
+#define EM_VXCHAN_LSB      0
+#define EM_VXCHAN_WIDTH    ((uint16_t)0x00000002)
+
+#define EM_PTI_PRIO_RST    0x0
+#define EM_VXCHAN_RST      0x0
+
+__INLINE void em_pti_vxchan_pack(int elt_idx, uint8_t ptiprio, uint8_t vxchan)
+{
+    ASSERT_ERR((((uint16_t)ptiprio << 8) & ~((uint16_t)0x00001F00)) == 0);
+    ASSERT_ERR((((uint16_t)vxchan << 0) & ~((uint16_t)0x00000003)) == 0);
+    EM_WR(EM_PTI_VXCHAN_ADDR + elt_idx * REG_EM_ET_SIZE,  ((uint16_t)ptiprio << 8) | ((uint16_t)vxchan << 0));
+}
+
+__INLINE void em_pti_vxchan_unpack(int elt_idx, uint8_t* ptiprio, uint8_t* vxchan)
+{
+    uint16_t localVal = EM_RD(EM_PTI_VXCHAN_ADDR + elt_idx * REG_EM_ET_SIZE);
+
+    *ptiprio = (localVal & ((uint16_t)0x00001F00)) >> 8;
+    *vxchan = (localVal & ((uint16_t)0x00000003)) >> 0;
+}
+
+__INLINE uint8_t em_pti_vxchan_pti_prio_getf(int elt_idx)
+{
+    uint16_t localVal = EM_RD(EM_PTI_VXCHAN_ADDR + elt_idx * REG_EM_ET_SIZE);
+    return ((localVal & ((uint16_t)0x00001F00)) >> 8);
+}
+
+__INLINE void em_pti_vxchan_pti_prio_setf(int elt_idx, uint8_t ptiprio)
+{
+    ASSERT_ERR((((uint16_t)ptiprio << 8) & ~((uint16_t)0x00001F00)) == 0);
+    EM_WR(EM_PTI_VXCHAN_ADDR + elt_idx * REG_EM_ET_SIZE, (EM_RD(EM_PTI_VXCHAN_ADDR + elt_idx * REG_EM_ET_SIZE) & ~((uint16_t)0x00001F00)) | ((uint16_t)ptiprio << 8));
+}
+
+__INLINE uint8_t em_pti_vxchan_vxchan_getf(int elt_idx)
+{
+    uint16_t localVal = EM_RD(EM_PTI_VXCHAN_ADDR + elt_idx * REG_EM_ET_SIZE);
+    return ((localVal & ((uint16_t)0x00000003)) >> 0);
+}
+
+__INLINE void em_pti_vxchan_vxchan_setf(int elt_idx, uint8_t vxchan)
+{
+    ASSERT_ERR((((uint16_t)vxchan << 0) & ~((uint16_t)0x00000003)) == 0);
+    EM_WR(EM_PTI_VXCHAN_ADDR + elt_idx * REG_EM_ET_SIZE, (EM_RD(EM_PTI_VXCHAN_ADDR + elt_idx * REG_EM_ET_SIZE) & ~((uint16_t)0x00000003)) | ((uint16_t)vxchan << 0));
+}
+
+
+#endif // _REG_EM_ET_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/reg_intc.h

@@ -0,0 +1,458 @@
+#ifndef _REG_INTC_H_
+#define _REG_INTC_H_
+
+#include <stdint.h>
+#include "_reg_intc.h"
+#include "compiler.h"
+#include "arch.h"
+#include "reg_access.h"
+
+#define REG_INTC_COUNT 70
+
+#define REG_INTC_DECODING_MASK 0x000001FF
+
+/**
+ * @brief IRQSTATUS register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00              IRQSTAT   0x0
+ * </pre>
+ */
+#define INTC_IRQSTATUS_ADDR   0x10001000
+#define INTC_IRQSTATUS_OFFSET 0x00000000
+#define INTC_IRQSTATUS_INDEX  0x00000000
+#define INTC_IRQSTATUS_RESET  0x00000000
+
+__INLINE uint32_t intc_irqstatus_get(void)
+{
+    return REG_PL_RD(INTC_IRQSTATUS_ADDR);
+}
+
+// field definitions
+#define INTC_IRQSTAT_MASK   ((uint32_t)0xFFFFFFFF)
+#define INTC_IRQSTAT_LSB    0
+#define INTC_IRQSTAT_WIDTH  ((uint32_t)0x00000020)
+
+#define INTC_IRQSTAT_RST    0x0
+
+__INLINE uint32_t intc_irqstatus_irqstat_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(INTC_IRQSTATUS_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+/**
+ * @brief IRQRAWSTATUS register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00           IRQRAWSTAT   0x0
+ * </pre>
+ */
+#define INTC_IRQRAWSTATUS_ADDR   0x10001004
+#define INTC_IRQRAWSTATUS_OFFSET 0x00000004
+#define INTC_IRQRAWSTATUS_INDEX  0x00000001
+#define INTC_IRQRAWSTATUS_RESET  0x00000000
+
+__INLINE uint32_t intc_irqrawstatus_get(void)
+{
+    return REG_PL_RD(INTC_IRQRAWSTATUS_ADDR);
+}
+
+// field definitions
+#define INTC_IRQRAWSTAT_MASK   ((uint32_t)0xFFFFFFFF)
+#define INTC_IRQRAWSTAT_LSB    0
+#define INTC_IRQRAWSTAT_WIDTH  ((uint32_t)0x00000020)
+
+#define INTC_IRQRAWSTAT_RST    0x0
+
+__INLINE uint32_t intc_irqrawstatus_irqrawstat_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(INTC_IRQRAWSTATUS_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+/**
+ * @brief IRQENABLESET register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00         IRQENABLESET   0x0
+ * </pre>
+ */
+#define INTC_IRQENABLESET_ADDR   0x10001008
+#define INTC_IRQENABLESET_OFFSET 0x00000008
+#define INTC_IRQENABLESET_INDEX  0x00000002
+#define INTC_IRQENABLESET_RESET  0x00000000
+
+__INLINE uint32_t intc_irqenableset_get(void)
+{
+    return REG_PL_RD(INTC_IRQENABLESET_ADDR);
+}
+
+__INLINE void intc_irqenableset_set(uint32_t value)
+{
+    REG_PL_WR(INTC_IRQENABLESET_ADDR, value);
+}
+
+// field definitions
+#define INTC_IRQENABLESET_MASK   ((uint32_t)0xFFFFFFFF)
+#define INTC_IRQENABLESET_LSB    0
+#define INTC_IRQENABLESET_WIDTH  ((uint32_t)0x00000020)
+
+#define INTC_IRQENABLESET_RST    0x0
+
+__INLINE uint32_t intc_irqenableset_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(INTC_IRQENABLESET_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void intc_irqenableset_setf(uint32_t irqenableset)
+{
+    ASSERT_ERR((((uint32_t)irqenableset << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
+    REG_PL_WR(INTC_IRQENABLESET_ADDR, (uint32_t)irqenableset << 0);
+}
+
+/**
+ * @brief IRQENABLECLEAR register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00       IRQENABLECLEAR   0x0
+ * </pre>
+ */
+#define INTC_IRQENABLECLEAR_ADDR   0x1000100C
+#define INTC_IRQENABLECLEAR_OFFSET 0x0000000C
+#define INTC_IRQENABLECLEAR_INDEX  0x00000003
+#define INTC_IRQENABLECLEAR_RESET  0x00000000
+
+__INLINE void intc_irqenableclear_set(uint32_t value)
+{
+    REG_PL_WR(INTC_IRQENABLECLEAR_ADDR, value);
+}
+
+// field definitions
+#define INTC_IRQENABLECLEAR_MASK   ((uint32_t)0xFFFFFFFF)
+#define INTC_IRQENABLECLEAR_LSB    0
+#define INTC_IRQENABLECLEAR_WIDTH  ((uint32_t)0x00000020)
+
+#define INTC_IRQENABLECLEAR_RST    0x0
+
+__INLINE void intc_irqenableclear_setf(uint32_t irqenableclear)
+{
+    ASSERT_ERR((((uint32_t)irqenableclear << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
+    REG_PL_WR(INTC_IRQENABLECLEAR_ADDR, (uint32_t)irqenableclear << 0);
+}
+
+/**
+ * @brief IRQSOFT register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     02               IRQSFT   0
+ * </pre>
+ */
+#define INTC_IRQSOFT_ADDR   0x10001010
+#define INTC_IRQSOFT_OFFSET 0x00000010
+#define INTC_IRQSOFT_INDEX  0x00000004
+#define INTC_IRQSOFT_RESET  0x00000000
+
+__INLINE uint32_t intc_irqsoft_get(void)
+{
+    return REG_PL_RD(INTC_IRQSOFT_ADDR);
+}
+
+__INLINE void intc_irqsoft_set(uint32_t value)
+{
+    REG_PL_WR(INTC_IRQSOFT_ADDR, value);
+}
+
+// field definitions
+#define INTC_IRQSFT_BIT    ((uint32_t)0x00000004)
+#define INTC_IRQSFT_POS    2
+
+#define INTC_IRQSFT_RST    0x0
+
+__INLINE void intc_irqsoft_irqsft_setf(uint8_t irqsft)
+{
+    ASSERT_ERR((((uint32_t)irqsft << 2) & ~((uint32_t)0x00000004)) == 0);
+    REG_PL_WR(INTC_IRQSOFT_ADDR, (uint32_t)irqsft << 2);
+}
+
+/**
+ * @brief IRQACK register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00               IRQACK   0x0
+ * </pre>
+ */
+#define INTC_IRQACK_ADDR   0x10001014
+#define INTC_IRQACK_OFFSET 0x00000014
+#define INTC_IRQACK_INDEX  0x00000005
+#define INTC_IRQACK_RESET  0x00000000
+
+__INLINE void intc_irqack_set(uint32_t value)
+{
+    REG_PL_WR(INTC_IRQACK_ADDR, value);
+}
+
+// field definitions
+#define INTC_IRQACK_MASK   ((uint32_t)0xFFFFFFFF)
+#define INTC_IRQACK_LSB    0
+#define INTC_IRQACK_WIDTH  ((uint32_t)0x00000020)
+
+#define INTC_IRQACK_RST    0x0
+
+__INLINE void intc_irqack_setf(uint32_t irqack)
+{
+    ASSERT_ERR((((uint32_t)irqack << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
+    REG_PL_WR(INTC_IRQACK_ADDR, (uint32_t)irqack << 0);
+}
+
+/**
+ * @brief IRQINDEX register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  04:00             IRQINDEX   0x0
+ * </pre>
+ */
+#define INTC_IRQINDEX_ADDR   0x1000101C
+#define INTC_IRQINDEX_OFFSET 0x0000001C
+#define INTC_IRQINDEX_INDEX  0x00000007
+#define INTC_IRQINDEX_RESET  0x00000000
+
+__INLINE uint32_t intc_irqindex_get(void)
+{
+    return REG_PL_RD(INTC_IRQINDEX_ADDR);
+}
+
+// field definitions
+#define INTC_IRQINDEX_MASK   ((uint32_t)0x0000001F)
+#define INTC_IRQINDEX_LSB    0
+#define INTC_IRQINDEX_WIDTH  ((uint32_t)0x00000005)
+
+#define INTC_IRQINDEX_RST    0x0
+
+__INLINE uint8_t intc_irqindex_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(INTC_IRQINDEX_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0x0000001F)) == 0);
+    return (localVal >> 0);
+}
+
+/**
+ * @brief FIQSTATUS register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00              FIQSTAT   0x0
+ * </pre>
+ */
+#define INTC_FIQSTATUS_ADDR   0x10001100
+#define INTC_FIQSTATUS_OFFSET 0x00000100
+#define INTC_FIQSTATUS_INDEX  0x00000040
+#define INTC_FIQSTATUS_RESET  0x00000000
+
+__INLINE uint32_t intc_fiqstatus_get(void)
+{
+    return REG_PL_RD(INTC_FIQSTATUS_ADDR);
+}
+
+// field definitions
+#define INTC_FIQSTAT_MASK   ((uint32_t)0xFFFFFFFF)
+#define INTC_FIQSTAT_LSB    0
+#define INTC_FIQSTAT_WIDTH  ((uint32_t)0x00000020)
+
+#define INTC_FIQSTAT_RST    0x0
+
+__INLINE uint32_t intc_fiqstatus_fiqstat_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(INTC_FIQSTATUS_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+/**
+ * @brief FIQRAWSTATUS register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00           FIQRAWSTAT   0x0
+ * </pre>
+ */
+#define INTC_FIQRAWSTATUS_ADDR   0x10001104
+#define INTC_FIQRAWSTATUS_OFFSET 0x00000104
+#define INTC_FIQRAWSTATUS_INDEX  0x00000041
+#define INTC_FIQRAWSTATUS_RESET  0x00000000
+
+__INLINE uint32_t intc_fiqrawstatus_get(void)
+{
+    return REG_PL_RD(INTC_FIQRAWSTATUS_ADDR);
+}
+
+// field definitions
+#define INTC_FIQRAWSTAT_MASK   ((uint32_t)0xFFFFFFFF)
+#define INTC_FIQRAWSTAT_LSB    0
+#define INTC_FIQRAWSTAT_WIDTH  ((uint32_t)0x00000020)
+
+#define INTC_FIQRAWSTAT_RST    0x0
+
+__INLINE uint32_t intc_fiqrawstatus_fiqrawstat_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(INTC_FIQRAWSTATUS_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+/**
+ * @brief FIQENABLESET register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00         FIQENABLESET   0x0
+ * </pre>
+ */
+#define INTC_FIQENABLESET_ADDR   0x10001108
+#define INTC_FIQENABLESET_OFFSET 0x00000108
+#define INTC_FIQENABLESET_INDEX  0x00000042
+#define INTC_FIQENABLESET_RESET  0x00000000
+
+__INLINE uint32_t intc_fiqenableset_get(void)
+{
+    return REG_PL_RD(INTC_FIQENABLESET_ADDR);
+}
+
+__INLINE void intc_fiqenableset_set(uint32_t value)
+{
+    REG_PL_WR(INTC_FIQENABLESET_ADDR, value);
+}
+
+// field definitions
+#define INTC_FIQENABLESET_MASK   ((uint32_t)0xFFFFFFFF)
+#define INTC_FIQENABLESET_LSB    0
+#define INTC_FIQENABLESET_WIDTH  ((uint32_t)0x00000020)
+
+#define INTC_FIQENABLESET_RST    0x0
+
+__INLINE uint32_t intc_fiqenableset_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(INTC_FIQENABLESET_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void intc_fiqenableset_setf(uint32_t fiqenableset)
+{
+    ASSERT_ERR((((uint32_t)fiqenableset << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
+    REG_PL_WR(INTC_FIQENABLESET_ADDR, (uint32_t)fiqenableset << 0);
+}
+
+/**
+ * @brief FIQENABLECLEAR register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00       FIQENABLECLEAR   0x0
+ * </pre>
+ */
+#define INTC_FIQENABLECLEAR_ADDR   0x1000110C
+#define INTC_FIQENABLECLEAR_OFFSET 0x0000010C
+#define INTC_FIQENABLECLEAR_INDEX  0x00000043
+#define INTC_FIQENABLECLEAR_RESET  0x00000000
+
+__INLINE void intc_fiqenableclear_set(uint32_t value)
+{
+    REG_PL_WR(INTC_FIQENABLECLEAR_ADDR, value);
+}
+
+// field definitions
+#define INTC_FIQENABLECLEAR_MASK   ((uint32_t)0xFFFFFFFF)
+#define INTC_FIQENABLECLEAR_LSB    0
+#define INTC_FIQENABLECLEAR_WIDTH  ((uint32_t)0x00000020)
+
+#define INTC_FIQENABLECLEAR_RST    0x0
+
+__INLINE void intc_fiqenableclear_setf(uint32_t fiqenableclear)
+{
+    ASSERT_ERR((((uint32_t)fiqenableclear << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
+    REG_PL_WR(INTC_FIQENABLECLEAR_ADDR, (uint32_t)fiqenableclear << 0);
+}
+
+/**
+ * @brief FIQACK register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00               FIQACK   0x0
+ * </pre>
+ */
+#define INTC_FIQACK_ADDR   0x10001110
+#define INTC_FIQACK_OFFSET 0x00000110
+#define INTC_FIQACK_INDEX  0x00000044
+#define INTC_FIQACK_RESET  0x00000000
+
+__INLINE void intc_fiqack_set(uint32_t value)
+{
+    REG_PL_WR(INTC_FIQACK_ADDR, value);
+}
+
+// field definitions
+#define INTC_FIQACK_MASK   ((uint32_t)0xFFFFFFFF)
+#define INTC_FIQACK_LSB    0
+#define INTC_FIQACK_WIDTH  ((uint32_t)0x00000020)
+
+#define INTC_FIQACK_RST    0x0
+
+__INLINE void intc_fiqack_setf(uint32_t fiqack)
+{
+    ASSERT_ERR((((uint32_t)fiqack << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
+    REG_PL_WR(INTC_FIQACK_ADDR, (uint32_t)fiqack << 0);
+}
+
+/**
+ * @brief FIQINDEX register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  04:00             FIQINDEX   0x0
+ * </pre>
+ */
+#define INTC_FIQINDEX_ADDR   0x10001114
+#define INTC_FIQINDEX_OFFSET 0x00000114
+#define INTC_FIQINDEX_INDEX  0x00000045
+#define INTC_FIQINDEX_RESET  0x00000000
+
+__INLINE uint32_t intc_fiqindex_get(void)
+{
+    return REG_PL_RD(INTC_FIQINDEX_ADDR);
+}
+
+__INLINE void intc_fiqindex_set(uint32_t value)
+{
+    REG_PL_WR(INTC_FIQINDEX_ADDR, value);
+}
+
+// field definitions
+#define INTC_FIQINDEX_MASK   ((uint32_t)0x0000001F)
+#define INTC_FIQINDEX_LSB    0
+#define INTC_FIQINDEX_WIDTH  ((uint32_t)0x00000005)
+
+#define INTC_FIQINDEX_RST    0x0
+
+__INLINE uint8_t intc_fiqindex_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(INTC_FIQINDEX_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0x0000001F)) == 0);
+    return (localVal >> 0);
+}
+
+
+#endif // _REG_INTC_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/reg_ipcore_bts.h

@@ -0,0 +1,467 @@
+#ifndef _REG_IPCORE_BTS_H_
+#define _REG_IPCORE_BTS_H_
+
+#include <stdint.h>
+#include "_reg_ipcore_bts.h"
+#include "compiler.h"
+#include "arch.h"
+#include "reg_access.h"
+
+#define REG_IPCORE_BTS_COUNT 125
+
+#define REG_IPCORE_BTS_DECODING_MASK 0x000001FF
+
+/**
+ * @brief ISOCNTCNTL register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     31              ISOSAMP   0
+ *     30              ISO_UPD   0
+ *     02    ISO_CLKSHIFT_MODE   0
+ *     01   ISO_PHASE_SHIFT_MODE   0
+ *     00          ISOCORRMODE   0
+ * </pre>
+ */
+#define IP_ISOCNTCNTL_ADDR   0x530001C0
+#define IP_ISOCNTCNTL_OFFSET 0x000001C0
+#define IP_ISOCNTCNTL_INDEX  0x00000070
+#define IP_ISOCNTCNTL_RESET  0x00000000
+
+__INLINE uint32_t ip_isocntcntl_get(void)
+{
+    return REG_IP_RD(IP_ISOCNTCNTL_ADDR);
+}
+
+__INLINE void ip_isocntcntl_set(uint32_t value)
+{
+    REG_IP_WR(IP_ISOCNTCNTL_ADDR, value);
+}
+
+// field definitions
+#define IP_ISOSAMP_BIT                 ((uint32_t)0x80000000)
+#define IP_ISOSAMP_POS                 31
+#define IP_ISO_UPD_BIT                 ((uint32_t)0x40000000)
+#define IP_ISO_UPD_POS                 30
+#define IP_ISO_CLKSHIFT_MODE_BIT       ((uint32_t)0x00000004)
+#define IP_ISO_CLKSHIFT_MODE_POS       2
+#define IP_ISO_PHASE_SHIFT_MODE_BIT    ((uint32_t)0x00000002)
+#define IP_ISO_PHASE_SHIFT_MODE_POS    1
+#define IP_ISOCORRMODE_BIT             ((uint32_t)0x00000001)
+#define IP_ISOCORRMODE_POS             0
+
+#define IP_ISOSAMP_RST                 0x0
+#define IP_ISO_UPD_RST                 0x0
+#define IP_ISO_CLKSHIFT_MODE_RST       0x0
+#define IP_ISO_PHASE_SHIFT_MODE_RST    0x0
+#define IP_ISOCORRMODE_RST             0x0
+
+__INLINE void ip_isocntcntl_pack(uint8_t isosamp, uint8_t isoupd, uint8_t isoclkshiftmode, uint8_t isophaseshiftmode, uint8_t isocorrmode)
+{
+    ASSERT_ERR((((uint32_t)isosamp << 31) & ~((uint32_t)0x80000000)) == 0);
+    ASSERT_ERR((((uint32_t)isoupd << 30) & ~((uint32_t)0x40000000)) == 0);
+    ASSERT_ERR((((uint32_t)isoclkshiftmode << 2) & ~((uint32_t)0x00000004)) == 0);
+    ASSERT_ERR((((uint32_t)isophaseshiftmode << 1) & ~((uint32_t)0x00000002)) == 0);
+    ASSERT_ERR((((uint32_t)isocorrmode << 0) & ~((uint32_t)0x00000001)) == 0);
+    REG_IP_WR(IP_ISOCNTCNTL_ADDR,  ((uint32_t)isosamp << 31) | ((uint32_t)isoupd << 30) | ((uint32_t)isoclkshiftmode << 2) | ((uint32_t)isophaseshiftmode << 1) | ((uint32_t)isocorrmode << 0));
+}
+
+__INLINE void ip_isocntcntl_unpack(uint8_t* isosamp, uint8_t* isoupd, uint8_t* isoclkshiftmode, uint8_t* isophaseshiftmode, uint8_t* isocorrmode)
+{
+    uint32_t localVal = REG_IP_RD(IP_ISOCNTCNTL_ADDR);
+
+    *isosamp = (localVal & ((uint32_t)0x80000000)) >> 31;
+    *isoupd = (localVal & ((uint32_t)0x40000000)) >> 30;
+    *isoclkshiftmode = (localVal & ((uint32_t)0x00000004)) >> 2;
+    *isophaseshiftmode = (localVal & ((uint32_t)0x00000002)) >> 1;
+    *isocorrmode = (localVal & ((uint32_t)0x00000001)) >> 0;
+}
+
+__INLINE uint8_t ip_isocntcntl_isosamp_getf(void)
+{
+    uint32_t localVal = REG_IP_RD(IP_ISOCNTCNTL_ADDR);
+    return ((localVal & ((uint32_t)0x80000000)) >> 31);
+}
+
+__INLINE void ip_isocntcntl_isosamp_setf(uint8_t isosamp)
+{
+    ASSERT_ERR((((uint32_t)isosamp << 31) & ~((uint32_t)0x80000000)) == 0);
+    REG_IP_WR(IP_ISOCNTCNTL_ADDR, (REG_IP_RD(IP_ISOCNTCNTL_ADDR) & ~((uint32_t)0x80000000)) | ((uint32_t)isosamp << 31));
+}
+
+__INLINE uint8_t ip_isocntcntl_iso_upd_getf(void)
+{
+    uint32_t localVal = REG_IP_RD(IP_ISOCNTCNTL_ADDR);
+    return ((localVal & ((uint32_t)0x40000000)) >> 30);
+}
+
+__INLINE void ip_isocntcntl_iso_upd_setf(uint8_t isoupd)
+{
+    ASSERT_ERR((((uint32_t)isoupd << 30) & ~((uint32_t)0x40000000)) == 0);
+    REG_IP_WR(IP_ISOCNTCNTL_ADDR, (REG_IP_RD(IP_ISOCNTCNTL_ADDR) & ~((uint32_t)0x40000000)) | ((uint32_t)isoupd << 30));
+}
+
+__INLINE uint8_t ip_isocntcntl_iso_clkshift_mode_getf(void)
+{
+    uint32_t localVal = REG_IP_RD(IP_ISOCNTCNTL_ADDR);
+    return ((localVal & ((uint32_t)0x00000004)) >> 2);
+}
+
+__INLINE void ip_isocntcntl_iso_clkshift_mode_setf(uint8_t isoclkshiftmode)
+{
+    ASSERT_ERR((((uint32_t)isoclkshiftmode << 2) & ~((uint32_t)0x00000004)) == 0);
+    REG_IP_WR(IP_ISOCNTCNTL_ADDR, (REG_IP_RD(IP_ISOCNTCNTL_ADDR) & ~((uint32_t)0x00000004)) | ((uint32_t)isoclkshiftmode << 2));
+}
+
+__INLINE uint8_t ip_isocntcntl_iso_phase_shift_mode_getf(void)
+{
+    uint32_t localVal = REG_IP_RD(IP_ISOCNTCNTL_ADDR);
+    return ((localVal & ((uint32_t)0x00000002)) >> 1);
+}
+
+__INLINE void ip_isocntcntl_iso_phase_shift_mode_setf(uint8_t isophaseshiftmode)
+{
+    ASSERT_ERR((((uint32_t)isophaseshiftmode << 1) & ~((uint32_t)0x00000002)) == 0);
+    REG_IP_WR(IP_ISOCNTCNTL_ADDR, (REG_IP_RD(IP_ISOCNTCNTL_ADDR) & ~((uint32_t)0x00000002)) | ((uint32_t)isophaseshiftmode << 1));
+}
+
+__INLINE uint8_t ip_isocntcntl_isocorrmode_getf(void)
+{
+    uint32_t localVal = REG_IP_RD(IP_ISOCNTCNTL_ADDR);
+    return ((localVal & ((uint32_t)0x00000001)) >> 0);
+}
+
+__INLINE void ip_isocntcntl_isocorrmode_setf(uint8_t isocorrmode)
+{
+    ASSERT_ERR((((uint32_t)isocorrmode << 0) & ~((uint32_t)0x00000001)) == 0);
+    REG_IP_WR(IP_ISOCNTCNTL_ADDR, (REG_IP_RD(IP_ISOCNTCNTL_ADDR) & ~((uint32_t)0x00000001)) | ((uint32_t)isocorrmode << 0));
+}
+
+/**
+ * @brief ISOCNTSAMP register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00           ISOCNTSAMP   0x0
+ * </pre>
+ */
+#define IP_ISOCNTSAMP_ADDR   0x530001C4
+#define IP_ISOCNTSAMP_OFFSET 0x000001C4
+#define IP_ISOCNTSAMP_INDEX  0x00000071
+#define IP_ISOCNTSAMP_RESET  0x00000000
+
+__INLINE uint32_t ip_isocntsamp_get(void)
+{
+    return REG_IP_RD(IP_ISOCNTSAMP_ADDR);
+}
+
+__INLINE void ip_isocntsamp_set(uint32_t value)
+{
+    REG_IP_WR(IP_ISOCNTSAMP_ADDR, value);
+}
+
+// field definitions
+#define IP_ISOCNTSAMP_MASK   ((uint32_t)0xFFFFFFFF)
+#define IP_ISOCNTSAMP_LSB    0
+#define IP_ISOCNTSAMP_WIDTH  ((uint32_t)0x00000020)
+
+#define IP_ISOCNTSAMP_RST    0x0
+
+__INLINE uint32_t ip_isocntsamp_getf(void)
+{
+    uint32_t localVal = REG_IP_RD(IP_ISOCNTSAMP_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void ip_isocntsamp_setf(uint32_t isocntsamp)
+{
+    ASSERT_ERR((((uint32_t)isocntsamp << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
+    REG_IP_WR(IP_ISOCNTSAMP_ADDR, (uint32_t)isocntsamp << 0);
+}
+
+/**
+ * @brief ISOCNTCORR register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00           ISOCNTCORR   0x0
+ * </pre>
+ */
+#define IP_ISOCNTCORR_ADDR   0x530001C8
+#define IP_ISOCNTCORR_OFFSET 0x000001C8
+#define IP_ISOCNTCORR_INDEX  0x00000072
+#define IP_ISOCNTCORR_RESET  0x00000000
+
+__INLINE uint32_t ip_isocntcorr_get(void)
+{
+    return REG_IP_RD(IP_ISOCNTCORR_ADDR);
+}
+
+__INLINE void ip_isocntcorr_set(uint32_t value)
+{
+    REG_IP_WR(IP_ISOCNTCORR_ADDR, value);
+}
+
+// field definitions
+#define IP_ISOCNTCORR_MASK   ((uint32_t)0xFFFFFFFF)
+#define IP_ISOCNTCORR_LSB    0
+#define IP_ISOCNTCORR_WIDTH  ((uint32_t)0x00000020)
+
+#define IP_ISOCNTCORR_RST    0x0
+
+__INLINE uint32_t ip_isocntcorr_getf(void)
+{
+    uint32_t localVal = REG_IP_RD(IP_ISOCNTCORR_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void ip_isocntcorr_setf(uint32_t isocntcorr)
+{
+    ASSERT_ERR((((uint32_t)isocntcorr << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
+    REG_IP_WR(IP_ISOCNTCORR_ADDR, (uint32_t)isocntcorr << 0);
+}
+
+/**
+ * @brief ISOINTCNTL register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  07:00            ISOINTMSK   0x0
+ * </pre>
+ */
+#define IP_ISOINTCNTL_ADDR   0x530001D0
+#define IP_ISOINTCNTL_OFFSET 0x000001D0
+#define IP_ISOINTCNTL_INDEX  0x00000074
+#define IP_ISOINTCNTL_RESET  0x00000000
+
+__INLINE uint32_t ip_isointcntl_get(void)
+{
+    return REG_IP_RD(IP_ISOINTCNTL_ADDR);
+}
+
+__INLINE void ip_isointcntl_set(uint32_t value)
+{
+    REG_IP_WR(IP_ISOINTCNTL_ADDR, value);
+}
+
+// field definitions
+#define IP_ISOINTMSK_MASK   ((uint32_t)0x000000FF)
+#define IP_ISOINTMSK_LSB    0
+#define IP_ISOINTMSK_WIDTH  ((uint32_t)0x00000008)
+
+#define IP_ISOINTMSK_RST    0x0
+
+__INLINE uint8_t ip_isointcntl_isointmsk_getf(void)
+{
+    uint32_t localVal = REG_IP_RD(IP_ISOINTCNTL_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0x000000FF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void ip_isointcntl_isointmsk_setf(uint8_t isointmsk)
+{
+    ASSERT_ERR((((uint32_t)isointmsk << 0) & ~((uint32_t)0x000000FF)) == 0);
+    REG_IP_WR(IP_ISOINTCNTL_ADDR, (uint32_t)isointmsk << 0);
+}
+
+/**
+ * @brief ISOINTSTAT register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  07:00           ISOINTSTAT   0x0
+ * </pre>
+ */
+#define IP_ISOINTSTAT_ADDR   0x530001D4
+#define IP_ISOINTSTAT_OFFSET 0x000001D4
+#define IP_ISOINTSTAT_INDEX  0x00000075
+#define IP_ISOINTSTAT_RESET  0x00000000
+
+__INLINE uint32_t ip_isointstat_get(void)
+{
+    return REG_IP_RD(IP_ISOINTSTAT_ADDR);
+}
+
+// field definitions
+#define IP_ISOINTSTAT_MASK   ((uint32_t)0x000000FF)
+#define IP_ISOINTSTAT_LSB    0
+#define IP_ISOINTSTAT_WIDTH  ((uint32_t)0x00000008)
+
+#define IP_ISOINTSTAT_RST    0x0
+
+__INLINE uint8_t ip_isointstat_getf(void)
+{
+    uint32_t localVal = REG_IP_RD(IP_ISOINTSTAT_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0x000000FF)) == 0);
+    return (localVal >> 0);
+}
+
+/**
+ * @brief ISOINTACK register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  07:00            ISOINTACK   0x0
+ * </pre>
+ */
+#define IP_ISOINTACK_ADDR   0x530001D8
+#define IP_ISOINTACK_OFFSET 0x000001D8
+#define IP_ISOINTACK_INDEX  0x00000076
+#define IP_ISOINTACK_RESET  0x00000000
+
+__INLINE uint32_t ip_isointack_get(void)
+{
+    return REG_IP_RD(IP_ISOINTACK_ADDR);
+}
+
+__INLINE void ip_isointack_clear(uint32_t value)
+{
+    REG_IP_WR(IP_ISOINTACK_ADDR, value);
+}
+
+// field definitions
+#define IP_ISOINTACK_MASK   ((uint32_t)0x000000FF)
+#define IP_ISOINTACK_LSB    0
+#define IP_ISOINTACK_WIDTH  ((uint32_t)0x00000008)
+
+#define IP_ISOINTACK_RST    0x0
+
+__INLINE uint8_t ip_isointack_getf(void)
+{
+    uint32_t localVal = REG_IP_RD(IP_ISOINTACK_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0x000000FF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void ip_isointack_clearf(uint8_t isointack)
+{
+    ASSERT_ERR((((uint32_t)isointack << 0) & ~((uint32_t)0x000000FF)) == 0);
+    REG_IP_WR(IP_ISOINTACK_ADDR, (uint32_t)isointack << 0);
+}
+
+/**
+ * @brief ISOGPIOCNTL register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     31           ISOGPIOBEH   0
+ *  07:00           ISOGPIOMSK   0x0
+ * </pre>
+ */
+#define IP_ISOGPIOCNTL_ADDR   0x530001E0
+#define IP_ISOGPIOCNTL_OFFSET 0x000001E0
+#define IP_ISOGPIOCNTL_INDEX  0x00000078
+#define IP_ISOGPIOCNTL_RESET  0x00000000
+
+__INLINE uint32_t ip_isogpiocntl_get(void)
+{
+    return REG_IP_RD(IP_ISOGPIOCNTL_ADDR);
+}
+
+__INLINE void ip_isogpiocntl_set(uint32_t value)
+{
+    REG_IP_WR(IP_ISOGPIOCNTL_ADDR, value);
+}
+
+// field definitions
+#define IP_ISOGPIOBEH_BIT    ((uint32_t)0x80000000)
+#define IP_ISOGPIOBEH_POS    31
+#define IP_ISOGPIOMSK_MASK   ((uint32_t)0x000000FF)
+#define IP_ISOGPIOMSK_LSB    0
+#define IP_ISOGPIOMSK_WIDTH  ((uint32_t)0x00000008)
+
+#define IP_ISOGPIOBEH_RST    0x0
+#define IP_ISOGPIOMSK_RST    0x0
+
+__INLINE void ip_isogpiocntl_pack(uint8_t isogpiobeh, uint8_t isogpiomsk)
+{
+    ASSERT_ERR((((uint32_t)isogpiobeh << 31) & ~((uint32_t)0x80000000)) == 0);
+    ASSERT_ERR((((uint32_t)isogpiomsk << 0) & ~((uint32_t)0x000000FF)) == 0);
+    REG_IP_WR(IP_ISOGPIOCNTL_ADDR,  ((uint32_t)isogpiobeh << 31) | ((uint32_t)isogpiomsk << 0));
+}
+
+__INLINE void ip_isogpiocntl_unpack(uint8_t* isogpiobeh, uint8_t* isogpiomsk)
+{
+    uint32_t localVal = REG_IP_RD(IP_ISOGPIOCNTL_ADDR);
+
+    *isogpiobeh = (localVal & ((uint32_t)0x80000000)) >> 31;
+    *isogpiomsk = (localVal & ((uint32_t)0x000000FF)) >> 0;
+}
+
+__INLINE uint8_t ip_isogpiocntl_isogpiobeh_getf(void)
+{
+    uint32_t localVal = REG_IP_RD(IP_ISOGPIOCNTL_ADDR);
+    return ((localVal & ((uint32_t)0x80000000)) >> 31);
+}
+
+__INLINE void ip_isogpiocntl_isogpiobeh_setf(uint8_t isogpiobeh)
+{
+    ASSERT_ERR((((uint32_t)isogpiobeh << 31) & ~((uint32_t)0x80000000)) == 0);
+    REG_IP_WR(IP_ISOGPIOCNTL_ADDR, (REG_IP_RD(IP_ISOGPIOCNTL_ADDR) & ~((uint32_t)0x80000000)) | ((uint32_t)isogpiobeh << 31));
+}
+
+__INLINE uint8_t ip_isogpiocntl_isogpiomsk_getf(void)
+{
+    uint32_t localVal = REG_IP_RD(IP_ISOGPIOCNTL_ADDR);
+    return ((localVal & ((uint32_t)0x000000FF)) >> 0);
+}
+
+__INLINE void ip_isogpiocntl_isogpiomsk_setf(uint8_t isogpiomsk)
+{
+    ASSERT_ERR((((uint32_t)isogpiomsk << 0) & ~((uint32_t)0x000000FF)) == 0);
+    REG_IP_WR(IP_ISOGPIOCNTL_ADDR, (REG_IP_RD(IP_ISOGPIOCNTL_ADDR) & ~((uint32_t)0x000000FF)) | ((uint32_t)isogpiomsk << 0));
+}
+
+/**
+ * @brief ISOTIMERTGT register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00          ISOTIMERTGT   0x0
+ * </pre>
+ */
+#define IP_ISOTIMERTGT_ADDR   0x530001F0
+#define IP_ISOTIMERTGT_OFFSET 0x000001F0
+#define IP_ISOTIMERTGT_INDEX  0x0000007C
+#define IP_ISOTIMERTGT_RESET  0x00000000
+#define IP_ISOTIMERTGT_COUNT  8
+
+__INLINE uint32_t ip_isotimertgt_get(int reg_idx)
+{
+    ASSERT_ERR(reg_idx <= 7);
+    return REG_IP_RD(IP_ISOTIMERTGT_ADDR + reg_idx * 4);
+}
+
+__INLINE void ip_isotimertgt_set(int reg_idx, uint32_t value)
+{
+    ASSERT_ERR(reg_idx <= 7);
+    REG_IP_WR(IP_ISOTIMERTGT_ADDR + reg_idx * 4, value);
+}
+
+// field definitions
+#define IP_ISOTIMERTGT_MASK   ((uint32_t)0xFFFFFFFF)
+#define IP_ISOTIMERTGT_LSB    0
+#define IP_ISOTIMERTGT_WIDTH  ((uint32_t)0x00000020)
+
+#define IP_ISOTIMERTGT_RST    0x0
+
+__INLINE uint32_t ip_isotimertgt_getf(int reg_idx)
+{
+    ASSERT_ERR(reg_idx <= 7);
+    uint32_t localVal = REG_IP_RD(IP_ISOTIMERTGT_ADDR + reg_idx * 4);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void ip_isotimertgt_setf(int reg_idx, uint32_t isotimertgt)
+{
+    ASSERT_ERR(reg_idx <= 7);
+    ASSERT_ERR((((uint32_t)isotimertgt << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
+    REG_IP_WR(IP_ISOTIMERTGT_ADDR + reg_idx * 4, (uint32_t)isotimertgt << 0);
+}
+
+
+#endif // _REG_IPCORE_BTS_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/reg_iqgen.h

@@ -0,0 +1,987 @@
+#ifndef _REG_IQGEN_H_
+#define _REG_IQGEN_H_
+
+#include <stdint.h>
+#include "_reg_iqgen.h"
+#include "compiler.h"
+#include "arch.h"
+#include "reg_access.h"
+
+#define REG_IQGEN_COUNT 6
+
+#define REG_IQGEN_DECODING_MASK 0x0000001F
+
+/**
+ * @brief DFGENCNTL register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     31            DF_SOURCE   0
+ *  25:16       AOD_SWITCH_DLY   0x0
+ *  11:08       IQ_INVALID_DLY   0x0
+ *  06:04           NB_ANTENNA   0x0
+ *     03         PATTERN_MODE   0
+ *     02          TIMING_MODE   0
+ *     01       IQ_SAMPLING_EN   0
+ *     00    ANTENNA_SWITCH_EN   0
+ * </pre>
+ */
+#define IQGEN_DFGENCNTL_ADDR   0x1000A000
+#define IQGEN_DFGENCNTL_OFFSET 0x00000000
+#define IQGEN_DFGENCNTL_INDEX  0x00000000
+#define IQGEN_DFGENCNTL_RESET  0x00000000
+
+__INLINE uint32_t iqgen_dfgencntl_get(void)
+{
+    return REG_PL_RD(IQGEN_DFGENCNTL_ADDR);
+}
+
+__INLINE void iqgen_dfgencntl_set(uint32_t value)
+{
+    REG_PL_WR(IQGEN_DFGENCNTL_ADDR, value);
+}
+
+// field definitions
+#define IQGEN_DF_SOURCE_BIT            ((uint32_t)0x80000000)
+#define IQGEN_DF_SOURCE_POS            31
+#define IQGEN_AOD_SWITCH_DLY_MASK      ((uint32_t)0x03FF0000)
+#define IQGEN_AOD_SWITCH_DLY_LSB       16
+#define IQGEN_AOD_SWITCH_DLY_WIDTH     ((uint32_t)0x0000000A)
+#define IQGEN_IQ_INVALID_DLY_MASK      ((uint32_t)0x00000F00)
+#define IQGEN_IQ_INVALID_DLY_LSB       8
+#define IQGEN_IQ_INVALID_DLY_WIDTH     ((uint32_t)0x00000004)
+#define IQGEN_NB_ANTENNA_MASK          ((uint32_t)0x00000070)
+#define IQGEN_NB_ANTENNA_LSB           4
+#define IQGEN_NB_ANTENNA_WIDTH         ((uint32_t)0x00000003)
+#define IQGEN_PATTERN_MODE_BIT         ((uint32_t)0x00000008)
+#define IQGEN_PATTERN_MODE_POS         3
+#define IQGEN_TIMING_MODE_BIT          ((uint32_t)0x00000004)
+#define IQGEN_TIMING_MODE_POS          2
+#define IQGEN_IQ_SAMPLING_EN_BIT       ((uint32_t)0x00000002)
+#define IQGEN_IQ_SAMPLING_EN_POS       1
+#define IQGEN_ANTENNA_SWITCH_EN_BIT    ((uint32_t)0x00000001)
+#define IQGEN_ANTENNA_SWITCH_EN_POS    0
+
+#define IQGEN_DF_SOURCE_RST            0x0
+#define IQGEN_AOD_SWITCH_DLY_RST       0x0
+#define IQGEN_IQ_INVALID_DLY_RST       0x0
+#define IQGEN_NB_ANTENNA_RST           0x0
+#define IQGEN_PATTERN_MODE_RST         0x0
+#define IQGEN_TIMING_MODE_RST          0x0
+#define IQGEN_IQ_SAMPLING_EN_RST       0x0
+#define IQGEN_ANTENNA_SWITCH_EN_RST    0x0
+
+__INLINE void iqgen_dfgencntl_pack(uint8_t dfsource, uint16_t aodswitchdly, uint8_t iqinvaliddly, uint8_t nbantenna, uint8_t patternmode, uint8_t timingmode, uint8_t iqsamplingen, uint8_t antennaswitchen)
+{
+    ASSERT_ERR((((uint32_t)dfsource << 31) & ~((uint32_t)0x80000000)) == 0);
+    ASSERT_ERR((((uint32_t)aodswitchdly << 16) & ~((uint32_t)0x03FF0000)) == 0);
+    ASSERT_ERR((((uint32_t)iqinvaliddly << 8) & ~((uint32_t)0x00000F00)) == 0);
+    ASSERT_ERR((((uint32_t)nbantenna << 4) & ~((uint32_t)0x00000070)) == 0);
+    ASSERT_ERR((((uint32_t)patternmode << 3) & ~((uint32_t)0x00000008)) == 0);
+    ASSERT_ERR((((uint32_t)timingmode << 2) & ~((uint32_t)0x00000004)) == 0);
+    ASSERT_ERR((((uint32_t)iqsamplingen << 1) & ~((uint32_t)0x00000002)) == 0);
+    ASSERT_ERR((((uint32_t)antennaswitchen << 0) & ~((uint32_t)0x00000001)) == 0);
+    REG_PL_WR(IQGEN_DFGENCNTL_ADDR,  ((uint32_t)dfsource << 31) | ((uint32_t)aodswitchdly << 16) | ((uint32_t)iqinvaliddly << 8) | ((uint32_t)nbantenna << 4) | ((uint32_t)patternmode << 3) | ((uint32_t)timingmode << 2) | ((uint32_t)iqsamplingen << 1) | ((uint32_t)antennaswitchen << 0));
+}
+
+__INLINE void iqgen_dfgencntl_unpack(uint8_t* dfsource, uint16_t* aodswitchdly, uint8_t* iqinvaliddly, uint8_t* nbantenna, uint8_t* patternmode, uint8_t* timingmode, uint8_t* iqsamplingen, uint8_t* antennaswitchen)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_DFGENCNTL_ADDR);
+
+    *dfsource = (localVal & ((uint32_t)0x80000000)) >> 31;
+    *aodswitchdly = (localVal & ((uint32_t)0x03FF0000)) >> 16;
+    *iqinvaliddly = (localVal & ((uint32_t)0x00000F00)) >> 8;
+    *nbantenna = (localVal & ((uint32_t)0x00000070)) >> 4;
+    *patternmode = (localVal & ((uint32_t)0x00000008)) >> 3;
+    *timingmode = (localVal & ((uint32_t)0x00000004)) >> 2;
+    *iqsamplingen = (localVal & ((uint32_t)0x00000002)) >> 1;
+    *antennaswitchen = (localVal & ((uint32_t)0x00000001)) >> 0;
+}
+
+__INLINE uint8_t iqgen_df_source_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_DFGENCNTL_ADDR);
+    return ((localVal & ((uint32_t)0x80000000)) >> 31);
+}
+
+__INLINE void iqgen_df_source_setf(uint8_t dfsource)
+{
+    ASSERT_ERR((((uint32_t)dfsource << 31) & ~((uint32_t)0x80000000)) == 0);
+    REG_PL_WR(IQGEN_DFGENCNTL_ADDR, (REG_PL_RD(IQGEN_DFGENCNTL_ADDR) & ~((uint32_t)0x80000000)) | ((uint32_t)dfsource << 31));
+}
+
+__INLINE uint16_t iqgen_aod_switch_dly_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_DFGENCNTL_ADDR);
+    return ((localVal & ((uint32_t)0x03FF0000)) >> 16);
+}
+
+__INLINE void iqgen_aod_switch_dly_setf(uint16_t aodswitchdly)
+{
+    ASSERT_ERR((((uint32_t)aodswitchdly << 16) & ~((uint32_t)0x03FF0000)) == 0);
+    REG_PL_WR(IQGEN_DFGENCNTL_ADDR, (REG_PL_RD(IQGEN_DFGENCNTL_ADDR) & ~((uint32_t)0x03FF0000)) | ((uint32_t)aodswitchdly << 16));
+}
+
+__INLINE uint8_t iqgen_iq_invalid_dly_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_DFGENCNTL_ADDR);
+    return ((localVal & ((uint32_t)0x00000F00)) >> 8);
+}
+
+__INLINE void iqgen_iq_invalid_dly_setf(uint8_t iqinvaliddly)
+{
+    ASSERT_ERR((((uint32_t)iqinvaliddly << 8) & ~((uint32_t)0x00000F00)) == 0);
+    REG_PL_WR(IQGEN_DFGENCNTL_ADDR, (REG_PL_RD(IQGEN_DFGENCNTL_ADDR) & ~((uint32_t)0x00000F00)) | ((uint32_t)iqinvaliddly << 8));
+}
+
+__INLINE uint8_t iqgen_nb_antenna_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_DFGENCNTL_ADDR);
+    return ((localVal & ((uint32_t)0x00000070)) >> 4);
+}
+
+__INLINE void iqgen_nb_antenna_setf(uint8_t nbantenna)
+{
+    ASSERT_ERR((((uint32_t)nbantenna << 4) & ~((uint32_t)0x00000070)) == 0);
+    REG_PL_WR(IQGEN_DFGENCNTL_ADDR, (REG_PL_RD(IQGEN_DFGENCNTL_ADDR) & ~((uint32_t)0x00000070)) | ((uint32_t)nbantenna << 4));
+}
+
+__INLINE uint8_t iqgen_pattern_mode_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_DFGENCNTL_ADDR);
+    return ((localVal & ((uint32_t)0x00000008)) >> 3);
+}
+
+__INLINE void iqgen_pattern_mode_setf(uint8_t patternmode)
+{
+    ASSERT_ERR((((uint32_t)patternmode << 3) & ~((uint32_t)0x00000008)) == 0);
+    REG_PL_WR(IQGEN_DFGENCNTL_ADDR, (REG_PL_RD(IQGEN_DFGENCNTL_ADDR) & ~((uint32_t)0x00000008)) | ((uint32_t)patternmode << 3));
+}
+
+__INLINE uint8_t iqgen_timing_mode_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_DFGENCNTL_ADDR);
+    return ((localVal & ((uint32_t)0x00000004)) >> 2);
+}
+
+__INLINE void iqgen_timing_mode_setf(uint8_t timingmode)
+{
+    ASSERT_ERR((((uint32_t)timingmode << 2) & ~((uint32_t)0x00000004)) == 0);
+    REG_PL_WR(IQGEN_DFGENCNTL_ADDR, (REG_PL_RD(IQGEN_DFGENCNTL_ADDR) & ~((uint32_t)0x00000004)) | ((uint32_t)timingmode << 2));
+}
+
+__INLINE uint8_t iqgen_iq_sampling_en_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_DFGENCNTL_ADDR);
+    return ((localVal & ((uint32_t)0x00000002)) >> 1);
+}
+
+__INLINE void iqgen_iq_sampling_en_setf(uint8_t iqsamplingen)
+{
+    ASSERT_ERR((((uint32_t)iqsamplingen << 1) & ~((uint32_t)0x00000002)) == 0);
+    REG_PL_WR(IQGEN_DFGENCNTL_ADDR, (REG_PL_RD(IQGEN_DFGENCNTL_ADDR) & ~((uint32_t)0x00000002)) | ((uint32_t)iqsamplingen << 1));
+}
+
+__INLINE uint8_t iqgen_antenna_switch_en_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_DFGENCNTL_ADDR);
+    return ((localVal & ((uint32_t)0x00000001)) >> 0);
+}
+
+__INLINE void iqgen_antenna_switch_en_setf(uint8_t antennaswitchen)
+{
+    ASSERT_ERR((((uint32_t)antennaswitchen << 0) & ~((uint32_t)0x00000001)) == 0);
+    REG_PL_WR(IQGEN_DFGENCNTL_ADDR, (REG_PL_RD(IQGEN_DFGENCNTL_ADDR) & ~((uint32_t)0x00000001)) | ((uint32_t)antennaswitchen << 0));
+}
+
+/**
+ * @brief IQ_SAMPLE_BEH_CNTL register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:30              Q_CNTL7   0x0
+ *  29:28              I_CNTL7   0x0
+ *  27:26              Q_CNTL6   0x0
+ *  25:24              I_CNTL6   0x0
+ *  23:22              Q_CNTL5   0x0
+ *  21:20              I_CNTL5   0x0
+ *  19:18              Q_CNTL4   0x0
+ *  17:16             IQ_CNTL4   0x0
+ *  15:14              Q_CNTL3   0x0
+ *  13:12              I_CNTL3   0x0
+ *  11:10              Q_CNTL2   0x0
+ *  09:08              I_CNTL2   0x0
+ *  07:06              Q_CNTL1   0x0
+ *  05:04              I_CNTL1   0x0
+ *  03:02              Q_CNTL0   0x0
+ *  01:00              I_CNTL0   0x0
+ * </pre>
+ */
+#define IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR   0x1000A004
+#define IQGEN_IQ_SAMPLE_BEH_CNTL_OFFSET 0x00000004
+#define IQGEN_IQ_SAMPLE_BEH_CNTL_INDEX  0x00000001
+#define IQGEN_IQ_SAMPLE_BEH_CNTL_RESET  0x00000000
+
+__INLINE uint32_t iqgen_iq_sample_beh_cntl_get(void)
+{
+    return REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR);
+}
+
+__INLINE void iqgen_iq_sample_beh_cntl_set(uint32_t value)
+{
+    REG_PL_WR(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR, value);
+}
+
+// field definitions
+#define IQGEN_Q_CNTL7_MASK    ((uint32_t)0xC0000000)
+#define IQGEN_Q_CNTL7_LSB     30
+#define IQGEN_Q_CNTL7_WIDTH   ((uint32_t)0x00000002)
+#define IQGEN_I_CNTL7_MASK    ((uint32_t)0x30000000)
+#define IQGEN_I_CNTL7_LSB     28
+#define IQGEN_I_CNTL7_WIDTH   ((uint32_t)0x00000002)
+#define IQGEN_Q_CNTL6_MASK    ((uint32_t)0x0C000000)
+#define IQGEN_Q_CNTL6_LSB     26
+#define IQGEN_Q_CNTL6_WIDTH   ((uint32_t)0x00000002)
+#define IQGEN_I_CNTL6_MASK    ((uint32_t)0x03000000)
+#define IQGEN_I_CNTL6_LSB     24
+#define IQGEN_I_CNTL6_WIDTH   ((uint32_t)0x00000002)
+#define IQGEN_Q_CNTL5_MASK    ((uint32_t)0x00C00000)
+#define IQGEN_Q_CNTL5_LSB     22
+#define IQGEN_Q_CNTL5_WIDTH   ((uint32_t)0x00000002)
+#define IQGEN_I_CNTL5_MASK    ((uint32_t)0x00300000)
+#define IQGEN_I_CNTL5_LSB     20
+#define IQGEN_I_CNTL5_WIDTH   ((uint32_t)0x00000002)
+#define IQGEN_Q_CNTL4_MASK    ((uint32_t)0x000C0000)
+#define IQGEN_Q_CNTL4_LSB     18
+#define IQGEN_Q_CNTL4_WIDTH   ((uint32_t)0x00000002)
+#define IQGEN_IQ_CNTL4_MASK   ((uint32_t)0x00030000)
+#define IQGEN_IQ_CNTL4_LSB    16
+#define IQGEN_IQ_CNTL4_WIDTH  ((uint32_t)0x00000002)
+#define IQGEN_Q_CNTL3_MASK    ((uint32_t)0x0000C000)
+#define IQGEN_Q_CNTL3_LSB     14
+#define IQGEN_Q_CNTL3_WIDTH   ((uint32_t)0x00000002)
+#define IQGEN_I_CNTL3_MASK    ((uint32_t)0x00003000)
+#define IQGEN_I_CNTL3_LSB     12
+#define IQGEN_I_CNTL3_WIDTH   ((uint32_t)0x00000002)
+#define IQGEN_Q_CNTL2_MASK    ((uint32_t)0x00000C00)
+#define IQGEN_Q_CNTL2_LSB     10
+#define IQGEN_Q_CNTL2_WIDTH   ((uint32_t)0x00000002)
+#define IQGEN_I_CNTL2_MASK    ((uint32_t)0x00000300)
+#define IQGEN_I_CNTL2_LSB     8
+#define IQGEN_I_CNTL2_WIDTH   ((uint32_t)0x00000002)
+#define IQGEN_Q_CNTL1_MASK    ((uint32_t)0x000000C0)
+#define IQGEN_Q_CNTL1_LSB     6
+#define IQGEN_Q_CNTL1_WIDTH   ((uint32_t)0x00000002)
+#define IQGEN_I_CNTL1_MASK    ((uint32_t)0x00000030)
+#define IQGEN_I_CNTL1_LSB     4
+#define IQGEN_I_CNTL1_WIDTH   ((uint32_t)0x00000002)
+#define IQGEN_Q_CNTL0_MASK    ((uint32_t)0x0000000C)
+#define IQGEN_Q_CNTL0_LSB     2
+#define IQGEN_Q_CNTL0_WIDTH   ((uint32_t)0x00000002)
+#define IQGEN_I_CNTL0_MASK    ((uint32_t)0x00000003)
+#define IQGEN_I_CNTL0_LSB     0
+#define IQGEN_I_CNTL0_WIDTH   ((uint32_t)0x00000002)
+
+#define IQGEN_Q_CNTL7_RST     0x0
+#define IQGEN_I_CNTL7_RST     0x0
+#define IQGEN_Q_CNTL6_RST     0x0
+#define IQGEN_I_CNTL6_RST     0x0
+#define IQGEN_Q_CNTL5_RST     0x0
+#define IQGEN_I_CNTL5_RST     0x0
+#define IQGEN_Q_CNTL4_RST     0x0
+#define IQGEN_IQ_CNTL4_RST    0x0
+#define IQGEN_Q_CNTL3_RST     0x0
+#define IQGEN_I_CNTL3_RST     0x0
+#define IQGEN_Q_CNTL2_RST     0x0
+#define IQGEN_I_CNTL2_RST     0x0
+#define IQGEN_Q_CNTL1_RST     0x0
+#define IQGEN_I_CNTL1_RST     0x0
+#define IQGEN_Q_CNTL0_RST     0x0
+#define IQGEN_I_CNTL0_RST     0x0
+
+__INLINE void iqgen_iq_sample_beh_cntl_pack(uint8_t qcntl7, uint8_t icntl7, uint8_t qcntl6, uint8_t icntl6, uint8_t qcntl5, uint8_t icntl5, uint8_t qcntl4, uint8_t iqcntl4, uint8_t qcntl3, uint8_t icntl3, uint8_t qcntl2, uint8_t icntl2, uint8_t qcntl1, uint8_t icntl1, uint8_t qcntl0, uint8_t icntl0)
+{
+    ASSERT_ERR((((uint32_t)qcntl7 << 30) & ~((uint32_t)0xC0000000)) == 0);
+    ASSERT_ERR((((uint32_t)icntl7 << 28) & ~((uint32_t)0x30000000)) == 0);
+    ASSERT_ERR((((uint32_t)qcntl6 << 26) & ~((uint32_t)0x0C000000)) == 0);
+    ASSERT_ERR((((uint32_t)icntl6 << 24) & ~((uint32_t)0x03000000)) == 0);
+    ASSERT_ERR((((uint32_t)qcntl5 << 22) & ~((uint32_t)0x00C00000)) == 0);
+    ASSERT_ERR((((uint32_t)icntl5 << 20) & ~((uint32_t)0x00300000)) == 0);
+    ASSERT_ERR((((uint32_t)qcntl4 << 18) & ~((uint32_t)0x000C0000)) == 0);
+    ASSERT_ERR((((uint32_t)iqcntl4 << 16) & ~((uint32_t)0x00030000)) == 0);
+    ASSERT_ERR((((uint32_t)qcntl3 << 14) & ~((uint32_t)0x0000C000)) == 0);
+    ASSERT_ERR((((uint32_t)icntl3 << 12) & ~((uint32_t)0x00003000)) == 0);
+    ASSERT_ERR((((uint32_t)qcntl2 << 10) & ~((uint32_t)0x00000C00)) == 0);
+    ASSERT_ERR((((uint32_t)icntl2 << 8) & ~((uint32_t)0x00000300)) == 0);
+    ASSERT_ERR((((uint32_t)qcntl1 << 6) & ~((uint32_t)0x000000C0)) == 0);
+    ASSERT_ERR((((uint32_t)icntl1 << 4) & ~((uint32_t)0x00000030)) == 0);
+    ASSERT_ERR((((uint32_t)qcntl0 << 2) & ~((uint32_t)0x0000000C)) == 0);
+    ASSERT_ERR((((uint32_t)icntl0 << 0) & ~((uint32_t)0x00000003)) == 0);
+    REG_PL_WR(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR,  ((uint32_t)qcntl7 << 30) | ((uint32_t)icntl7 << 28) | ((uint32_t)qcntl6 << 26) | ((uint32_t)icntl6 << 24) | ((uint32_t)qcntl5 << 22) | ((uint32_t)icntl5 << 20) | ((uint32_t)qcntl4 << 18) | ((uint32_t)iqcntl4 << 16) | ((uint32_t)qcntl3 << 14) | ((uint32_t)icntl3 << 12) | ((uint32_t)qcntl2 << 10) | ((uint32_t)icntl2 << 8) | ((uint32_t)qcntl1 << 6) | ((uint32_t)icntl1 << 4) | ((uint32_t)qcntl0 << 2) | ((uint32_t)icntl0 << 0));
+}
+
+__INLINE void iqgen_iq_sample_beh_cntl_unpack(uint8_t* qcntl7, uint8_t* icntl7, uint8_t* qcntl6, uint8_t* icntl6, uint8_t* qcntl5, uint8_t* icntl5, uint8_t* qcntl4, uint8_t* iqcntl4, uint8_t* qcntl3, uint8_t* icntl3, uint8_t* qcntl2, uint8_t* icntl2, uint8_t* qcntl1, uint8_t* icntl1, uint8_t* qcntl0, uint8_t* icntl0)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR);
+
+    *qcntl7 = (localVal & ((uint32_t)0xC0000000)) >> 30;
+    *icntl7 = (localVal & ((uint32_t)0x30000000)) >> 28;
+    *qcntl6 = (localVal & ((uint32_t)0x0C000000)) >> 26;
+    *icntl6 = (localVal & ((uint32_t)0x03000000)) >> 24;
+    *qcntl5 = (localVal & ((uint32_t)0x00C00000)) >> 22;
+    *icntl5 = (localVal & ((uint32_t)0x00300000)) >> 20;
+    *qcntl4 = (localVal & ((uint32_t)0x000C0000)) >> 18;
+    *iqcntl4 = (localVal & ((uint32_t)0x00030000)) >> 16;
+    *qcntl3 = (localVal & ((uint32_t)0x0000C000)) >> 14;
+    *icntl3 = (localVal & ((uint32_t)0x00003000)) >> 12;
+    *qcntl2 = (localVal & ((uint32_t)0x00000C00)) >> 10;
+    *icntl2 = (localVal & ((uint32_t)0x00000300)) >> 8;
+    *qcntl1 = (localVal & ((uint32_t)0x000000C0)) >> 6;
+    *icntl1 = (localVal & ((uint32_t)0x00000030)) >> 4;
+    *qcntl0 = (localVal & ((uint32_t)0x0000000C)) >> 2;
+    *icntl0 = (localVal & ((uint32_t)0x00000003)) >> 0;
+}
+
+__INLINE uint8_t iqgen_q_cntl7_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR);
+    return ((localVal & ((uint32_t)0xC0000000)) >> 30);
+}
+
+__INLINE void iqgen_q_cntl7_setf(uint8_t qcntl7)
+{
+    ASSERT_ERR((((uint32_t)qcntl7 << 30) & ~((uint32_t)0xC0000000)) == 0);
+    REG_PL_WR(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR, (REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR) & ~((uint32_t)0xC0000000)) | ((uint32_t)qcntl7 << 30));
+}
+
+__INLINE uint8_t iqgen_i_cntl7_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR);
+    return ((localVal & ((uint32_t)0x30000000)) >> 28);
+}
+
+__INLINE void iqgen_i_cntl7_setf(uint8_t icntl7)
+{
+    ASSERT_ERR((((uint32_t)icntl7 << 28) & ~((uint32_t)0x30000000)) == 0);
+    REG_PL_WR(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR, (REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR) & ~((uint32_t)0x30000000)) | ((uint32_t)icntl7 << 28));
+}
+
+__INLINE uint8_t iqgen_q_cntl6_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR);
+    return ((localVal & ((uint32_t)0x0C000000)) >> 26);
+}
+
+__INLINE void iqgen_q_cntl6_setf(uint8_t qcntl6)
+{
+    ASSERT_ERR((((uint32_t)qcntl6 << 26) & ~((uint32_t)0x0C000000)) == 0);
+    REG_PL_WR(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR, (REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR) & ~((uint32_t)0x0C000000)) | ((uint32_t)qcntl6 << 26));
+}
+
+__INLINE uint8_t iqgen_i_cntl6_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR);
+    return ((localVal & ((uint32_t)0x03000000)) >> 24);
+}
+
+__INLINE void iqgen_i_cntl6_setf(uint8_t icntl6)
+{
+    ASSERT_ERR((((uint32_t)icntl6 << 24) & ~((uint32_t)0x03000000)) == 0);
+    REG_PL_WR(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR, (REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR) & ~((uint32_t)0x03000000)) | ((uint32_t)icntl6 << 24));
+}
+
+__INLINE uint8_t iqgen_q_cntl5_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR);
+    return ((localVal & ((uint32_t)0x00C00000)) >> 22);
+}
+
+__INLINE void iqgen_q_cntl5_setf(uint8_t qcntl5)
+{
+    ASSERT_ERR((((uint32_t)qcntl5 << 22) & ~((uint32_t)0x00C00000)) == 0);
+    REG_PL_WR(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR, (REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR) & ~((uint32_t)0x00C00000)) | ((uint32_t)qcntl5 << 22));
+}
+
+__INLINE uint8_t iqgen_i_cntl5_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR);
+    return ((localVal & ((uint32_t)0x00300000)) >> 20);
+}
+
+__INLINE void iqgen_i_cntl5_setf(uint8_t icntl5)
+{
+    ASSERT_ERR((((uint32_t)icntl5 << 20) & ~((uint32_t)0x00300000)) == 0);
+    REG_PL_WR(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR, (REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR) & ~((uint32_t)0x00300000)) | ((uint32_t)icntl5 << 20));
+}
+
+__INLINE uint8_t iqgen_q_cntl4_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR);
+    return ((localVal & ((uint32_t)0x000C0000)) >> 18);
+}
+
+__INLINE void iqgen_q_cntl4_setf(uint8_t qcntl4)
+{
+    ASSERT_ERR((((uint32_t)qcntl4 << 18) & ~((uint32_t)0x000C0000)) == 0);
+    REG_PL_WR(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR, (REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR) & ~((uint32_t)0x000C0000)) | ((uint32_t)qcntl4 << 18));
+}
+
+__INLINE uint8_t iqgen_iq_cntl4_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR);
+    return ((localVal & ((uint32_t)0x00030000)) >> 16);
+}
+
+__INLINE void iqgen_iq_cntl4_setf(uint8_t iqcntl4)
+{
+    ASSERT_ERR((((uint32_t)iqcntl4 << 16) & ~((uint32_t)0x00030000)) == 0);
+    REG_PL_WR(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR, (REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR) & ~((uint32_t)0x00030000)) | ((uint32_t)iqcntl4 << 16));
+}
+
+__INLINE uint8_t iqgen_q_cntl3_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR);
+    return ((localVal & ((uint32_t)0x0000C000)) >> 14);
+}
+
+__INLINE void iqgen_q_cntl3_setf(uint8_t qcntl3)
+{
+    ASSERT_ERR((((uint32_t)qcntl3 << 14) & ~((uint32_t)0x0000C000)) == 0);
+    REG_PL_WR(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR, (REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR) & ~((uint32_t)0x0000C000)) | ((uint32_t)qcntl3 << 14));
+}
+
+__INLINE uint8_t iqgen_i_cntl3_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR);
+    return ((localVal & ((uint32_t)0x00003000)) >> 12);
+}
+
+__INLINE void iqgen_i_cntl3_setf(uint8_t icntl3)
+{
+    ASSERT_ERR((((uint32_t)icntl3 << 12) & ~((uint32_t)0x00003000)) == 0);
+    REG_PL_WR(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR, (REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR) & ~((uint32_t)0x00003000)) | ((uint32_t)icntl3 << 12));
+}
+
+__INLINE uint8_t iqgen_q_cntl2_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR);
+    return ((localVal & ((uint32_t)0x00000C00)) >> 10);
+}
+
+__INLINE void iqgen_q_cntl2_setf(uint8_t qcntl2)
+{
+    ASSERT_ERR((((uint32_t)qcntl2 << 10) & ~((uint32_t)0x00000C00)) == 0);
+    REG_PL_WR(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR, (REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR) & ~((uint32_t)0x00000C00)) | ((uint32_t)qcntl2 << 10));
+}
+
+__INLINE uint8_t iqgen_i_cntl2_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR);
+    return ((localVal & ((uint32_t)0x00000300)) >> 8);
+}
+
+__INLINE void iqgen_i_cntl2_setf(uint8_t icntl2)
+{
+    ASSERT_ERR((((uint32_t)icntl2 << 8) & ~((uint32_t)0x00000300)) == 0);
+    REG_PL_WR(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR, (REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR) & ~((uint32_t)0x00000300)) | ((uint32_t)icntl2 << 8));
+}
+
+__INLINE uint8_t iqgen_q_cntl1_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR);
+    return ((localVal & ((uint32_t)0x000000C0)) >> 6);
+}
+
+__INLINE void iqgen_q_cntl1_setf(uint8_t qcntl1)
+{
+    ASSERT_ERR((((uint32_t)qcntl1 << 6) & ~((uint32_t)0x000000C0)) == 0);
+    REG_PL_WR(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR, (REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR) & ~((uint32_t)0x000000C0)) | ((uint32_t)qcntl1 << 6));
+}
+
+__INLINE uint8_t iqgen_i_cntl1_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR);
+    return ((localVal & ((uint32_t)0x00000030)) >> 4);
+}
+
+__INLINE void iqgen_i_cntl1_setf(uint8_t icntl1)
+{
+    ASSERT_ERR((((uint32_t)icntl1 << 4) & ~((uint32_t)0x00000030)) == 0);
+    REG_PL_WR(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR, (REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR) & ~((uint32_t)0x00000030)) | ((uint32_t)icntl1 << 4));
+}
+
+__INLINE uint8_t iqgen_q_cntl0_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR);
+    return ((localVal & ((uint32_t)0x0000000C)) >> 2);
+}
+
+__INLINE void iqgen_q_cntl0_setf(uint8_t qcntl0)
+{
+    ASSERT_ERR((((uint32_t)qcntl0 << 2) & ~((uint32_t)0x0000000C)) == 0);
+    REG_PL_WR(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR, (REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR) & ~((uint32_t)0x0000000C)) | ((uint32_t)qcntl0 << 2));
+}
+
+__INLINE uint8_t iqgen_i_cntl0_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR);
+    return ((localVal & ((uint32_t)0x00000003)) >> 0);
+}
+
+__INLINE void iqgen_i_cntl0_setf(uint8_t icntl0)
+{
+    ASSERT_ERR((((uint32_t)icntl0 << 0) & ~((uint32_t)0x00000003)) == 0);
+    REG_PL_WR(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR, (REG_PL_RD(IQGEN_IQ_SAMPLE_BEH_CNTL_ADDR) & ~((uint32_t)0x00000003)) | ((uint32_t)icntl0 << 0));
+}
+
+/**
+ * @brief I_SAMPLE_INIT_CNTL0 register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:24            I_OFFSET3   0x0
+ *  23:16            I_OFFSET2   0x0
+ *  15:08            I_OFFSET1   0x0
+ *  07:00            I_OFFSET0   0x0
+ * </pre>
+ */
+#define IQGEN_I_SAMPLE_INIT_CNTL0_ADDR   0x1000A008
+#define IQGEN_I_SAMPLE_INIT_CNTL0_OFFSET 0x00000008
+#define IQGEN_I_SAMPLE_INIT_CNTL0_INDEX  0x00000002
+#define IQGEN_I_SAMPLE_INIT_CNTL0_RESET  0x00000000
+
+__INLINE uint32_t iqgen_i_sample_init_cntl0_get(void)
+{
+    return REG_PL_RD(IQGEN_I_SAMPLE_INIT_CNTL0_ADDR);
+}
+
+__INLINE void iqgen_i_sample_init_cntl0_set(uint32_t value)
+{
+    REG_PL_WR(IQGEN_I_SAMPLE_INIT_CNTL0_ADDR, value);
+}
+
+// field definitions
+#define IQGEN_I_OFFSET3_MASK   ((uint32_t)0xFF000000)
+#define IQGEN_I_OFFSET3_LSB    24
+#define IQGEN_I_OFFSET3_WIDTH  ((uint32_t)0x00000008)
+#define IQGEN_I_OFFSET2_MASK   ((uint32_t)0x00FF0000)
+#define IQGEN_I_OFFSET2_LSB    16
+#define IQGEN_I_OFFSET2_WIDTH  ((uint32_t)0x00000008)
+#define IQGEN_I_OFFSET1_MASK   ((uint32_t)0x0000FF00)
+#define IQGEN_I_OFFSET1_LSB    8
+#define IQGEN_I_OFFSET1_WIDTH  ((uint32_t)0x00000008)
+#define IQGEN_I_OFFSET0_MASK   ((uint32_t)0x000000FF)
+#define IQGEN_I_OFFSET0_LSB    0
+#define IQGEN_I_OFFSET0_WIDTH  ((uint32_t)0x00000008)
+
+#define IQGEN_I_OFFSET3_RST    0x0
+#define IQGEN_I_OFFSET2_RST    0x0
+#define IQGEN_I_OFFSET1_RST    0x0
+#define IQGEN_I_OFFSET0_RST    0x0
+
+__INLINE void iqgen_i_sample_init_cntl0_pack(uint8_t ioffset3, uint8_t ioffset2, uint8_t ioffset1, uint8_t ioffset0)
+{
+    ASSERT_ERR((((uint32_t)ioffset3 << 24) & ~((uint32_t)0xFF000000)) == 0);
+    ASSERT_ERR((((uint32_t)ioffset2 << 16) & ~((uint32_t)0x00FF0000)) == 0);
+    ASSERT_ERR((((uint32_t)ioffset1 << 8) & ~((uint32_t)0x0000FF00)) == 0);
+    ASSERT_ERR((((uint32_t)ioffset0 << 0) & ~((uint32_t)0x000000FF)) == 0);
+    REG_PL_WR(IQGEN_I_SAMPLE_INIT_CNTL0_ADDR,  ((uint32_t)ioffset3 << 24) | ((uint32_t)ioffset2 << 16) | ((uint32_t)ioffset1 << 8) | ((uint32_t)ioffset0 << 0));
+}
+
+__INLINE void iqgen_i_sample_init_cntl0_unpack(uint8_t* ioffset3, uint8_t* ioffset2, uint8_t* ioffset1, uint8_t* ioffset0)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_I_SAMPLE_INIT_CNTL0_ADDR);
+
+    *ioffset3 = (localVal & ((uint32_t)0xFF000000)) >> 24;
+    *ioffset2 = (localVal & ((uint32_t)0x00FF0000)) >> 16;
+    *ioffset1 = (localVal & ((uint32_t)0x0000FF00)) >> 8;
+    *ioffset0 = (localVal & ((uint32_t)0x000000FF)) >> 0;
+}
+
+__INLINE uint8_t iqgen_i_offset3_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_I_SAMPLE_INIT_CNTL0_ADDR);
+    return ((localVal & ((uint32_t)0xFF000000)) >> 24);
+}
+
+__INLINE void iqgen_i_offset3_setf(uint8_t ioffset3)
+{
+    ASSERT_ERR((((uint32_t)ioffset3 << 24) & ~((uint32_t)0xFF000000)) == 0);
+    REG_PL_WR(IQGEN_I_SAMPLE_INIT_CNTL0_ADDR, (REG_PL_RD(IQGEN_I_SAMPLE_INIT_CNTL0_ADDR) & ~((uint32_t)0xFF000000)) | ((uint32_t)ioffset3 << 24));
+}
+
+__INLINE uint8_t iqgen_i_offset2_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_I_SAMPLE_INIT_CNTL0_ADDR);
+    return ((localVal & ((uint32_t)0x00FF0000)) >> 16);
+}
+
+__INLINE void iqgen_i_offset2_setf(uint8_t ioffset2)
+{
+    ASSERT_ERR((((uint32_t)ioffset2 << 16) & ~((uint32_t)0x00FF0000)) == 0);
+    REG_PL_WR(IQGEN_I_SAMPLE_INIT_CNTL0_ADDR, (REG_PL_RD(IQGEN_I_SAMPLE_INIT_CNTL0_ADDR) & ~((uint32_t)0x00FF0000)) | ((uint32_t)ioffset2 << 16));
+}
+
+__INLINE uint8_t iqgen_i_offset1_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_I_SAMPLE_INIT_CNTL0_ADDR);
+    return ((localVal & ((uint32_t)0x0000FF00)) >> 8);
+}
+
+__INLINE void iqgen_i_offset1_setf(uint8_t ioffset1)
+{
+    ASSERT_ERR((((uint32_t)ioffset1 << 8) & ~((uint32_t)0x0000FF00)) == 0);
+    REG_PL_WR(IQGEN_I_SAMPLE_INIT_CNTL0_ADDR, (REG_PL_RD(IQGEN_I_SAMPLE_INIT_CNTL0_ADDR) & ~((uint32_t)0x0000FF00)) | ((uint32_t)ioffset1 << 8));
+}
+
+__INLINE uint8_t iqgen_i_offset0_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_I_SAMPLE_INIT_CNTL0_ADDR);
+    return ((localVal & ((uint32_t)0x000000FF)) >> 0);
+}
+
+__INLINE void iqgen_i_offset0_setf(uint8_t ioffset0)
+{
+    ASSERT_ERR((((uint32_t)ioffset0 << 0) & ~((uint32_t)0x000000FF)) == 0);
+    REG_PL_WR(IQGEN_I_SAMPLE_INIT_CNTL0_ADDR, (REG_PL_RD(IQGEN_I_SAMPLE_INIT_CNTL0_ADDR) & ~((uint32_t)0x000000FF)) | ((uint32_t)ioffset0 << 0));
+}
+
+/**
+ * @brief I_SAMPLE_INIT_CNTL1 register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:24            I_OFFSET7   0x0
+ *  23:16            I_OFFSET6   0x0
+ *  15:08            I_OFFSET5   0x0
+ *  07:00            I_OFFSET4   0x0
+ * </pre>
+ */
+#define IQGEN_I_SAMPLE_INIT_CNTL1_ADDR   0x1000A00C
+#define IQGEN_I_SAMPLE_INIT_CNTL1_OFFSET 0x0000000C
+#define IQGEN_I_SAMPLE_INIT_CNTL1_INDEX  0x00000003
+#define IQGEN_I_SAMPLE_INIT_CNTL1_RESET  0x00000000
+
+__INLINE uint32_t iqgen_i_sample_init_cntl1_get(void)
+{
+    return REG_PL_RD(IQGEN_I_SAMPLE_INIT_CNTL1_ADDR);
+}
+
+__INLINE void iqgen_i_sample_init_cntl1_set(uint32_t value)
+{
+    REG_PL_WR(IQGEN_I_SAMPLE_INIT_CNTL1_ADDR, value);
+}
+
+// field definitions
+#define IQGEN_I_OFFSET7_MASK   ((uint32_t)0xFF000000)
+#define IQGEN_I_OFFSET7_LSB    24
+#define IQGEN_I_OFFSET7_WIDTH  ((uint32_t)0x00000008)
+#define IQGEN_I_OFFSET6_MASK   ((uint32_t)0x00FF0000)
+#define IQGEN_I_OFFSET6_LSB    16
+#define IQGEN_I_OFFSET6_WIDTH  ((uint32_t)0x00000008)
+#define IQGEN_I_OFFSET5_MASK   ((uint32_t)0x0000FF00)
+#define IQGEN_I_OFFSET5_LSB    8
+#define IQGEN_I_OFFSET5_WIDTH  ((uint32_t)0x00000008)
+#define IQGEN_I_OFFSET4_MASK   ((uint32_t)0x000000FF)
+#define IQGEN_I_OFFSET4_LSB    0
+#define IQGEN_I_OFFSET4_WIDTH  ((uint32_t)0x00000008)
+
+#define IQGEN_I_OFFSET7_RST    0x0
+#define IQGEN_I_OFFSET6_RST    0x0
+#define IQGEN_I_OFFSET5_RST    0x0
+#define IQGEN_I_OFFSET4_RST    0x0
+
+__INLINE void iqgen_i_sample_init_cntl1_pack(uint8_t ioffset7, uint8_t ioffset6, uint8_t ioffset5, uint8_t ioffset4)
+{
+    ASSERT_ERR((((uint32_t)ioffset7 << 24) & ~((uint32_t)0xFF000000)) == 0);
+    ASSERT_ERR((((uint32_t)ioffset6 << 16) & ~((uint32_t)0x00FF0000)) == 0);
+    ASSERT_ERR((((uint32_t)ioffset5 << 8) & ~((uint32_t)0x0000FF00)) == 0);
+    ASSERT_ERR((((uint32_t)ioffset4 << 0) & ~((uint32_t)0x000000FF)) == 0);
+    REG_PL_WR(IQGEN_I_SAMPLE_INIT_CNTL1_ADDR,  ((uint32_t)ioffset7 << 24) | ((uint32_t)ioffset6 << 16) | ((uint32_t)ioffset5 << 8) | ((uint32_t)ioffset4 << 0));
+}
+
+__INLINE void iqgen_i_sample_init_cntl1_unpack(uint8_t* ioffset7, uint8_t* ioffset6, uint8_t* ioffset5, uint8_t* ioffset4)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_I_SAMPLE_INIT_CNTL1_ADDR);
+
+    *ioffset7 = (localVal & ((uint32_t)0xFF000000)) >> 24;
+    *ioffset6 = (localVal & ((uint32_t)0x00FF0000)) >> 16;
+    *ioffset5 = (localVal & ((uint32_t)0x0000FF00)) >> 8;
+    *ioffset4 = (localVal & ((uint32_t)0x000000FF)) >> 0;
+}
+
+__INLINE uint8_t iqgen_i_offset7_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_I_SAMPLE_INIT_CNTL1_ADDR);
+    return ((localVal & ((uint32_t)0xFF000000)) >> 24);
+}
+
+__INLINE void iqgen_i_offset7_setf(uint8_t ioffset7)
+{
+    ASSERT_ERR((((uint32_t)ioffset7 << 24) & ~((uint32_t)0xFF000000)) == 0);
+    REG_PL_WR(IQGEN_I_SAMPLE_INIT_CNTL1_ADDR, (REG_PL_RD(IQGEN_I_SAMPLE_INIT_CNTL1_ADDR) & ~((uint32_t)0xFF000000)) | ((uint32_t)ioffset7 << 24));
+}
+
+__INLINE uint8_t iqgen_i_offset6_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_I_SAMPLE_INIT_CNTL1_ADDR);
+    return ((localVal & ((uint32_t)0x00FF0000)) >> 16);
+}
+
+__INLINE void iqgen_i_offset6_setf(uint8_t ioffset6)
+{
+    ASSERT_ERR((((uint32_t)ioffset6 << 16) & ~((uint32_t)0x00FF0000)) == 0);
+    REG_PL_WR(IQGEN_I_SAMPLE_INIT_CNTL1_ADDR, (REG_PL_RD(IQGEN_I_SAMPLE_INIT_CNTL1_ADDR) & ~((uint32_t)0x00FF0000)) | ((uint32_t)ioffset6 << 16));
+}
+
+__INLINE uint8_t iqgen_i_offset5_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_I_SAMPLE_INIT_CNTL1_ADDR);
+    return ((localVal & ((uint32_t)0x0000FF00)) >> 8);
+}
+
+__INLINE void iqgen_i_offset5_setf(uint8_t ioffset5)
+{
+    ASSERT_ERR((((uint32_t)ioffset5 << 8) & ~((uint32_t)0x0000FF00)) == 0);
+    REG_PL_WR(IQGEN_I_SAMPLE_INIT_CNTL1_ADDR, (REG_PL_RD(IQGEN_I_SAMPLE_INIT_CNTL1_ADDR) & ~((uint32_t)0x0000FF00)) | ((uint32_t)ioffset5 << 8));
+}
+
+__INLINE uint8_t iqgen_i_offset4_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_I_SAMPLE_INIT_CNTL1_ADDR);
+    return ((localVal & ((uint32_t)0x000000FF)) >> 0);
+}
+
+__INLINE void iqgen_i_offset4_setf(uint8_t ioffset4)
+{
+    ASSERT_ERR((((uint32_t)ioffset4 << 0) & ~((uint32_t)0x000000FF)) == 0);
+    REG_PL_WR(IQGEN_I_SAMPLE_INIT_CNTL1_ADDR, (REG_PL_RD(IQGEN_I_SAMPLE_INIT_CNTL1_ADDR) & ~((uint32_t)0x000000FF)) | ((uint32_t)ioffset4 << 0));
+}
+
+/**
+ * @brief Q_SAMPLE_INIT_CNTL0 register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:24            Q_OFFSET3   0x0
+ *  23:16            Q_OFFSET2   0x0
+ *  15:08            Q_OFFSET1   0x0
+ *  07:00            Q_OFFSET0   0x0
+ * </pre>
+ */
+#define IQGEN_Q_SAMPLE_INIT_CNTL0_ADDR   0x1000A010
+#define IQGEN_Q_SAMPLE_INIT_CNTL0_OFFSET 0x00000010
+#define IQGEN_Q_SAMPLE_INIT_CNTL0_INDEX  0x00000004
+#define IQGEN_Q_SAMPLE_INIT_CNTL0_RESET  0x00000000
+
+__INLINE uint32_t iqgen_q_sample_init_cntl0_get(void)
+{
+    return REG_PL_RD(IQGEN_Q_SAMPLE_INIT_CNTL0_ADDR);
+}
+
+__INLINE void iqgen_q_sample_init_cntl0_set(uint32_t value)
+{
+    REG_PL_WR(IQGEN_Q_SAMPLE_INIT_CNTL0_ADDR, value);
+}
+
+// field definitions
+#define IQGEN_Q_OFFSET3_MASK   ((uint32_t)0xFF000000)
+#define IQGEN_Q_OFFSET3_LSB    24
+#define IQGEN_Q_OFFSET3_WIDTH  ((uint32_t)0x00000008)
+#define IQGEN_Q_OFFSET2_MASK   ((uint32_t)0x00FF0000)
+#define IQGEN_Q_OFFSET2_LSB    16
+#define IQGEN_Q_OFFSET2_WIDTH  ((uint32_t)0x00000008)
+#define IQGEN_Q_OFFSET1_MASK   ((uint32_t)0x0000FF00)
+#define IQGEN_Q_OFFSET1_LSB    8
+#define IQGEN_Q_OFFSET1_WIDTH  ((uint32_t)0x00000008)
+#define IQGEN_Q_OFFSET0_MASK   ((uint32_t)0x000000FF)
+#define IQGEN_Q_OFFSET0_LSB    0
+#define IQGEN_Q_OFFSET0_WIDTH  ((uint32_t)0x00000008)
+
+#define IQGEN_Q_OFFSET3_RST    0x0
+#define IQGEN_Q_OFFSET2_RST    0x0
+#define IQGEN_Q_OFFSET1_RST    0x0
+#define IQGEN_Q_OFFSET0_RST    0x0
+
+__INLINE void iqgen_q_sample_init_cntl0_pack(uint8_t qoffset3, uint8_t qoffset2, uint8_t qoffset1, uint8_t qoffset0)
+{
+    ASSERT_ERR((((uint32_t)qoffset3 << 24) & ~((uint32_t)0xFF000000)) == 0);
+    ASSERT_ERR((((uint32_t)qoffset2 << 16) & ~((uint32_t)0x00FF0000)) == 0);
+    ASSERT_ERR((((uint32_t)qoffset1 << 8) & ~((uint32_t)0x0000FF00)) == 0);
+    ASSERT_ERR((((uint32_t)qoffset0 << 0) & ~((uint32_t)0x000000FF)) == 0);
+    REG_PL_WR(IQGEN_Q_SAMPLE_INIT_CNTL0_ADDR,  ((uint32_t)qoffset3 << 24) | ((uint32_t)qoffset2 << 16) | ((uint32_t)qoffset1 << 8) | ((uint32_t)qoffset0 << 0));
+}
+
+__INLINE void iqgen_q_sample_init_cntl0_unpack(uint8_t* qoffset3, uint8_t* qoffset2, uint8_t* qoffset1, uint8_t* qoffset0)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_Q_SAMPLE_INIT_CNTL0_ADDR);
+
+    *qoffset3 = (localVal & ((uint32_t)0xFF000000)) >> 24;
+    *qoffset2 = (localVal & ((uint32_t)0x00FF0000)) >> 16;
+    *qoffset1 = (localVal & ((uint32_t)0x0000FF00)) >> 8;
+    *qoffset0 = (localVal & ((uint32_t)0x000000FF)) >> 0;
+}
+
+__INLINE uint8_t iqgen_q_offset3_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_Q_SAMPLE_INIT_CNTL0_ADDR);
+    return ((localVal & ((uint32_t)0xFF000000)) >> 24);
+}
+
+__INLINE void iqgen_q_offset3_setf(uint8_t qoffset3)
+{
+    ASSERT_ERR((((uint32_t)qoffset3 << 24) & ~((uint32_t)0xFF000000)) == 0);
+    REG_PL_WR(IQGEN_Q_SAMPLE_INIT_CNTL0_ADDR, (REG_PL_RD(IQGEN_Q_SAMPLE_INIT_CNTL0_ADDR) & ~((uint32_t)0xFF000000)) | ((uint32_t)qoffset3 << 24));
+}
+
+__INLINE uint8_t iqgen_q_offset2_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_Q_SAMPLE_INIT_CNTL0_ADDR);
+    return ((localVal & ((uint32_t)0x00FF0000)) >> 16);
+}
+
+__INLINE void iqgen_q_offset2_setf(uint8_t qoffset2)
+{
+    ASSERT_ERR((((uint32_t)qoffset2 << 16) & ~((uint32_t)0x00FF0000)) == 0);
+    REG_PL_WR(IQGEN_Q_SAMPLE_INIT_CNTL0_ADDR, (REG_PL_RD(IQGEN_Q_SAMPLE_INIT_CNTL0_ADDR) & ~((uint32_t)0x00FF0000)) | ((uint32_t)qoffset2 << 16));
+}
+
+__INLINE uint8_t iqgen_q_offset1_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_Q_SAMPLE_INIT_CNTL0_ADDR);
+    return ((localVal & ((uint32_t)0x0000FF00)) >> 8);
+}
+
+__INLINE void iqgen_q_offset1_setf(uint8_t qoffset1)
+{
+    ASSERT_ERR((((uint32_t)qoffset1 << 8) & ~((uint32_t)0x0000FF00)) == 0);
+    REG_PL_WR(IQGEN_Q_SAMPLE_INIT_CNTL0_ADDR, (REG_PL_RD(IQGEN_Q_SAMPLE_INIT_CNTL0_ADDR) & ~((uint32_t)0x0000FF00)) | ((uint32_t)qoffset1 << 8));
+}
+
+__INLINE uint8_t iqgen_q_offset0_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_Q_SAMPLE_INIT_CNTL0_ADDR);
+    return ((localVal & ((uint32_t)0x000000FF)) >> 0);
+}
+
+__INLINE void iqgen_q_offset0_setf(uint8_t qoffset0)
+{
+    ASSERT_ERR((((uint32_t)qoffset0 << 0) & ~((uint32_t)0x000000FF)) == 0);
+    REG_PL_WR(IQGEN_Q_SAMPLE_INIT_CNTL0_ADDR, (REG_PL_RD(IQGEN_Q_SAMPLE_INIT_CNTL0_ADDR) & ~((uint32_t)0x000000FF)) | ((uint32_t)qoffset0 << 0));
+}
+
+/**
+ * @brief Q_SAMPLE_INIT_CNTL1 register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:24            Q_OFFSET7   0x0
+ *  23:16            Q_OFFSET6   0x0
+ *  15:08            Q_OFFSET5   0x0
+ *  07:00            Q_OFFSET4   0x0
+ * </pre>
+ */
+#define IQGEN_Q_SAMPLE_INIT_CNTL1_ADDR   0x1000A014
+#define IQGEN_Q_SAMPLE_INIT_CNTL1_OFFSET 0x00000014
+#define IQGEN_Q_SAMPLE_INIT_CNTL1_INDEX  0x00000005
+#define IQGEN_Q_SAMPLE_INIT_CNTL1_RESET  0x00000000
+
+__INLINE uint32_t iqgen_q_sample_init_cntl1_get(void)
+{
+    return REG_PL_RD(IQGEN_Q_SAMPLE_INIT_CNTL1_ADDR);
+}
+
+__INLINE void iqgen_q_sample_init_cntl1_set(uint32_t value)
+{
+    REG_PL_WR(IQGEN_Q_SAMPLE_INIT_CNTL1_ADDR, value);
+}
+
+// field definitions
+#define IQGEN_Q_OFFSET7_MASK   ((uint32_t)0xFF000000)
+#define IQGEN_Q_OFFSET7_LSB    24
+#define IQGEN_Q_OFFSET7_WIDTH  ((uint32_t)0x00000008)
+#define IQGEN_Q_OFFSET6_MASK   ((uint32_t)0x00FF0000)
+#define IQGEN_Q_OFFSET6_LSB    16
+#define IQGEN_Q_OFFSET6_WIDTH  ((uint32_t)0x00000008)
+#define IQGEN_Q_OFFSET5_MASK   ((uint32_t)0x0000FF00)
+#define IQGEN_Q_OFFSET5_LSB    8
+#define IQGEN_Q_OFFSET5_WIDTH  ((uint32_t)0x00000008)
+#define IQGEN_Q_OFFSET4_MASK   ((uint32_t)0x000000FF)
+#define IQGEN_Q_OFFSET4_LSB    0
+#define IQGEN_Q_OFFSET4_WIDTH  ((uint32_t)0x00000008)
+
+#define IQGEN_Q_OFFSET7_RST    0x0
+#define IQGEN_Q_OFFSET6_RST    0x0
+#define IQGEN_Q_OFFSET5_RST    0x0
+#define IQGEN_Q_OFFSET4_RST    0x0
+
+__INLINE void iqgen_q_sample_init_cntl1_pack(uint8_t qoffset7, uint8_t qoffset6, uint8_t qoffset5, uint8_t qoffset4)
+{
+    ASSERT_ERR((((uint32_t)qoffset7 << 24) & ~((uint32_t)0xFF000000)) == 0);
+    ASSERT_ERR((((uint32_t)qoffset6 << 16) & ~((uint32_t)0x00FF0000)) == 0);
+    ASSERT_ERR((((uint32_t)qoffset5 << 8) & ~((uint32_t)0x0000FF00)) == 0);
+    ASSERT_ERR((((uint32_t)qoffset4 << 0) & ~((uint32_t)0x000000FF)) == 0);
+    REG_PL_WR(IQGEN_Q_SAMPLE_INIT_CNTL1_ADDR,  ((uint32_t)qoffset7 << 24) | ((uint32_t)qoffset6 << 16) | ((uint32_t)qoffset5 << 8) | ((uint32_t)qoffset4 << 0));
+}
+
+__INLINE void iqgen_q_sample_init_cntl1_unpack(uint8_t* qoffset7, uint8_t* qoffset6, uint8_t* qoffset5, uint8_t* qoffset4)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_Q_SAMPLE_INIT_CNTL1_ADDR);
+
+    *qoffset7 = (localVal & ((uint32_t)0xFF000000)) >> 24;
+    *qoffset6 = (localVal & ((uint32_t)0x00FF0000)) >> 16;
+    *qoffset5 = (localVal & ((uint32_t)0x0000FF00)) >> 8;
+    *qoffset4 = (localVal & ((uint32_t)0x000000FF)) >> 0;
+}
+
+__INLINE uint8_t iqgen_q_offset7_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_Q_SAMPLE_INIT_CNTL1_ADDR);
+    return ((localVal & ((uint32_t)0xFF000000)) >> 24);
+}
+
+__INLINE void iqgen_q_offset7_setf(uint8_t qoffset7)
+{
+    ASSERT_ERR((((uint32_t)qoffset7 << 24) & ~((uint32_t)0xFF000000)) == 0);
+    REG_PL_WR(IQGEN_Q_SAMPLE_INIT_CNTL1_ADDR, (REG_PL_RD(IQGEN_Q_SAMPLE_INIT_CNTL1_ADDR) & ~((uint32_t)0xFF000000)) | ((uint32_t)qoffset7 << 24));
+}
+
+__INLINE uint8_t iqgen_q_offset6_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_Q_SAMPLE_INIT_CNTL1_ADDR);
+    return ((localVal & ((uint32_t)0x00FF0000)) >> 16);
+}
+
+__INLINE void iqgen_q_offset6_setf(uint8_t qoffset6)
+{
+    ASSERT_ERR((((uint32_t)qoffset6 << 16) & ~((uint32_t)0x00FF0000)) == 0);
+    REG_PL_WR(IQGEN_Q_SAMPLE_INIT_CNTL1_ADDR, (REG_PL_RD(IQGEN_Q_SAMPLE_INIT_CNTL1_ADDR) & ~((uint32_t)0x00FF0000)) | ((uint32_t)qoffset6 << 16));
+}
+
+__INLINE uint8_t iqgen_q_offset5_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_Q_SAMPLE_INIT_CNTL1_ADDR);
+    return ((localVal & ((uint32_t)0x0000FF00)) >> 8);
+}
+
+__INLINE void iqgen_q_offset5_setf(uint8_t qoffset5)
+{
+    ASSERT_ERR((((uint32_t)qoffset5 << 8) & ~((uint32_t)0x0000FF00)) == 0);
+    REG_PL_WR(IQGEN_Q_SAMPLE_INIT_CNTL1_ADDR, (REG_PL_RD(IQGEN_Q_SAMPLE_INIT_CNTL1_ADDR) & ~((uint32_t)0x0000FF00)) | ((uint32_t)qoffset5 << 8));
+}
+
+__INLINE uint8_t iqgen_q_offset4_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(IQGEN_Q_SAMPLE_INIT_CNTL1_ADDR);
+    return ((localVal & ((uint32_t)0x000000FF)) >> 0);
+}
+
+__INLINE void iqgen_q_offset4_setf(uint8_t qoffset4)
+{
+    ASSERT_ERR((((uint32_t)qoffset4 << 0) & ~((uint32_t)0x000000FF)) == 0);
+    REG_PL_WR(IQGEN_Q_SAMPLE_INIT_CNTL1_ADDR, (REG_PL_RD(IQGEN_Q_SAMPLE_INIT_CNTL1_ADDR) & ~((uint32_t)0x000000FF)) | ((uint32_t)qoffset4 << 0));
+}
+
+
+#endif // _REG_IQGEN_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/reg_sw_profiling.h

@@ -0,0 +1,602 @@
+#ifndef _REG_SW_PROFILING_H_
+#define _REG_SW_PROFILING_H_
+
+#include <stdint.h>
+#include "_reg_sw_profiling.h"
+#include "compiler.h"
+#include "arch.h"
+#include "reg_access.h"
+
+#define REG_SW_PROFILING_COUNT 10
+
+#define REG_SW_PROFILING_DECODING_MASK 0x0000003F
+
+/**
+ * @brief CFG register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  01:00            DATA_SIZE   0x0
+ * </pre>
+ */
+#define SW_PROF_CFG_ADDR   0x1000D100
+#define SW_PROF_CFG_OFFSET 0x00000000
+#define SW_PROF_CFG_INDEX  0x00000000
+#define SW_PROF_CFG_RESET  0x00000000
+
+__INLINE uint32_t sw_prof_cfg_get(void)
+{
+    return REG_PL_RD(SW_PROF_CFG_ADDR);
+}
+
+__INLINE void sw_prof_cfg_set(uint32_t value)
+{
+    REG_PL_WR(SW_PROF_CFG_ADDR, value);
+}
+
+// field definitions
+#define SW_PROF_DATA_SIZE_MASK   ((uint32_t)0x00000003)
+#define SW_PROF_DATA_SIZE_LSB    0
+#define SW_PROF_DATA_SIZE_WIDTH  ((uint32_t)0x00000002)
+
+#define SW_PROF_DATA_SIZE_RST    0x0
+
+__INLINE uint8_t sw_prof_data_size_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(SW_PROF_CFG_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0x00000003)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void sw_prof_data_size_setf(uint8_t datasize)
+{
+    ASSERT_ERR((((uint32_t)datasize << 0) & ~((uint32_t)0x00000003)) == 0);
+    REG_PL_WR(SW_PROF_CFG_ADDR, (uint32_t)datasize << 0);
+}
+
+/**
+ * @brief FUNC_IN_PTR register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00          FUNC_IN_PTR   0x0
+ * </pre>
+ */
+#define SW_PROF_FUNC_IN_PTR_ADDR   0x1000D104
+#define SW_PROF_FUNC_IN_PTR_OFFSET 0x00000004
+#define SW_PROF_FUNC_IN_PTR_INDEX  0x00000001
+#define SW_PROF_FUNC_IN_PTR_RESET  0x00000000
+
+__INLINE uint32_t sw_prof_func_in_ptr_get(void)
+{
+    return REG_PL_RD(SW_PROF_FUNC_IN_PTR_ADDR);
+}
+
+__INLINE void sw_prof_func_in_ptr_set(uint32_t value)
+{
+    REG_PL_WR(SW_PROF_FUNC_IN_PTR_ADDR, value);
+}
+
+// field definitions
+#define SW_PROF_FUNC_IN_PTR_MASK   ((uint32_t)0xFFFFFFFF)
+#define SW_PROF_FUNC_IN_PTR_LSB    0
+#define SW_PROF_FUNC_IN_PTR_WIDTH  ((uint32_t)0x00000020)
+
+#define SW_PROF_FUNC_IN_PTR_RST    0x0
+
+__INLINE uint32_t sw_prof_func_in_ptr_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(SW_PROF_FUNC_IN_PTR_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void sw_prof_func_in_ptr_setf(uint32_t funcinptr)
+{
+    ASSERT_ERR((((uint32_t)funcinptr << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
+    REG_PL_WR(SW_PROF_FUNC_IN_PTR_ADDR, (uint32_t)funcinptr << 0);
+}
+
+/**
+ * @brief FUNC_OUT_PTR register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00         FUNC_OUT_PTR   0x0
+ * </pre>
+ */
+#define SW_PROF_FUNC_OUT_PTR_ADDR   0x1000D108
+#define SW_PROF_FUNC_OUT_PTR_OFFSET 0x00000008
+#define SW_PROF_FUNC_OUT_PTR_INDEX  0x00000002
+#define SW_PROF_FUNC_OUT_PTR_RESET  0x00000000
+
+__INLINE uint32_t sw_prof_func_out_ptr_get(void)
+{
+    return REG_PL_RD(SW_PROF_FUNC_OUT_PTR_ADDR);
+}
+
+__INLINE void sw_prof_func_out_ptr_set(uint32_t value)
+{
+    REG_PL_WR(SW_PROF_FUNC_OUT_PTR_ADDR, value);
+}
+
+// field definitions
+#define SW_PROF_FUNC_OUT_PTR_MASK   ((uint32_t)0xFFFFFFFF)
+#define SW_PROF_FUNC_OUT_PTR_LSB    0
+#define SW_PROF_FUNC_OUT_PTR_WIDTH  ((uint32_t)0x00000020)
+
+#define SW_PROF_FUNC_OUT_PTR_RST    0x0
+
+__INLINE uint32_t sw_prof_func_out_ptr_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(SW_PROF_FUNC_OUT_PTR_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void sw_prof_func_out_ptr_setf(uint32_t funcoutptr)
+{
+    ASSERT_ERR((((uint32_t)funcoutptr << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
+    REG_PL_WR(SW_PROF_FUNC_OUT_PTR_ADDR, (uint32_t)funcoutptr << 0);
+}
+
+/**
+ * @brief FUNC_NAME_PTR register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00        FUNC_NAME_PTR   0x0
+ * </pre>
+ */
+#define SW_PROF_FUNC_NAME_PTR_ADDR   0x1000D10C
+#define SW_PROF_FUNC_NAME_PTR_OFFSET 0x0000000C
+#define SW_PROF_FUNC_NAME_PTR_INDEX  0x00000003
+#define SW_PROF_FUNC_NAME_PTR_RESET  0x00000000
+
+__INLINE uint32_t sw_prof_func_name_ptr_get(void)
+{
+    return REG_PL_RD(SW_PROF_FUNC_NAME_PTR_ADDR);
+}
+
+__INLINE void sw_prof_func_name_ptr_set(uint32_t value)
+{
+    REG_PL_WR(SW_PROF_FUNC_NAME_PTR_ADDR, value);
+}
+
+// field definitions
+#define SW_PROF_FUNC_NAME_PTR_MASK   ((uint32_t)0xFFFFFFFF)
+#define SW_PROF_FUNC_NAME_PTR_LSB    0
+#define SW_PROF_FUNC_NAME_PTR_WIDTH  ((uint32_t)0x00000020)
+
+#define SW_PROF_FUNC_NAME_PTR_RST    0x0
+
+__INLINE uint32_t sw_prof_func_name_ptr_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(SW_PROF_FUNC_NAME_PTR_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void sw_prof_func_name_ptr_setf(uint32_t funcnameptr)
+{
+    ASSERT_ERR((((uint32_t)funcnameptr << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
+    REG_PL_WR(SW_PROF_FUNC_NAME_PTR_ADDR, (uint32_t)funcnameptr << 0);
+}
+
+/**
+ * @brief DATA_PTR_IN register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00          DATA_IN_PTR   0x0
+ * </pre>
+ */
+#define SW_PROF_DATA_PTR_IN_ADDR   0x1000D110
+#define SW_PROF_DATA_PTR_IN_OFFSET 0x00000010
+#define SW_PROF_DATA_PTR_IN_INDEX  0x00000004
+#define SW_PROF_DATA_PTR_IN_RESET  0x00000000
+
+__INLINE uint32_t sw_prof_data_ptr_in_get(void)
+{
+    return REG_PL_RD(SW_PROF_DATA_PTR_IN_ADDR);
+}
+
+__INLINE void sw_prof_data_ptr_in_set(uint32_t value)
+{
+    REG_PL_WR(SW_PROF_DATA_PTR_IN_ADDR, value);
+}
+
+// field definitions
+#define SW_PROF_DATA_IN_PTR_MASK   ((uint32_t)0xFFFFFFFF)
+#define SW_PROF_DATA_IN_PTR_LSB    0
+#define SW_PROF_DATA_IN_PTR_WIDTH  ((uint32_t)0x00000020)
+
+#define SW_PROF_DATA_IN_PTR_RST    0x0
+
+__INLINE uint32_t sw_prof_data_in_ptr_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(SW_PROF_DATA_PTR_IN_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void sw_prof_data_in_ptr_setf(uint32_t datainptr)
+{
+    ASSERT_ERR((((uint32_t)datainptr << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
+    REG_PL_WR(SW_PROF_DATA_PTR_IN_ADDR, (uint32_t)datainptr << 0);
+}
+
+/**
+ * @brief DATA_PTR_OUT register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00         DATA_PTR_OUT   0x0
+ * </pre>
+ */
+#define SW_PROF_DATA_PTR_OUT_ADDR   0x1000D114
+#define SW_PROF_DATA_PTR_OUT_OFFSET 0x00000014
+#define SW_PROF_DATA_PTR_OUT_INDEX  0x00000005
+#define SW_PROF_DATA_PTR_OUT_RESET  0x00000000
+
+__INLINE uint32_t sw_prof_data_ptr_out_get(void)
+{
+    return REG_PL_RD(SW_PROF_DATA_PTR_OUT_ADDR);
+}
+
+__INLINE void sw_prof_data_ptr_out_set(uint32_t value)
+{
+    REG_PL_WR(SW_PROF_DATA_PTR_OUT_ADDR, value);
+}
+
+// field definitions
+#define SW_PROF_DATA_PTR_OUT_MASK   ((uint32_t)0xFFFFFFFF)
+#define SW_PROF_DATA_PTR_OUT_LSB    0
+#define SW_PROF_DATA_PTR_OUT_WIDTH  ((uint32_t)0x00000020)
+
+#define SW_PROF_DATA_PTR_OUT_RST    0x0
+
+__INLINE uint32_t sw_prof_data_ptr_out_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(SW_PROF_DATA_PTR_OUT_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void sw_prof_data_ptr_out_setf(uint32_t dataptrout)
+{
+    ASSERT_ERR((((uint32_t)dataptrout << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
+    REG_PL_WR(SW_PROF_DATA_PTR_OUT_ADDR, (uint32_t)dataptrout << 0);
+}
+
+/**
+ * @brief DATA_PTR_NAME register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00        DATA_PTR_NAME   0x0
+ * </pre>
+ */
+#define SW_PROF_DATA_PTR_NAME_ADDR   0x1000D118
+#define SW_PROF_DATA_PTR_NAME_OFFSET 0x00000018
+#define SW_PROF_DATA_PTR_NAME_INDEX  0x00000006
+#define SW_PROF_DATA_PTR_NAME_RESET  0x00000000
+
+__INLINE uint32_t sw_prof_data_ptr_name_get(void)
+{
+    return REG_PL_RD(SW_PROF_DATA_PTR_NAME_ADDR);
+}
+
+__INLINE void sw_prof_data_ptr_name_set(uint32_t value)
+{
+    REG_PL_WR(SW_PROF_DATA_PTR_NAME_ADDR, value);
+}
+
+// field definitions
+#define SW_PROF_DATA_PTR_NAME_MASK   ((uint32_t)0xFFFFFFFF)
+#define SW_PROF_DATA_PTR_NAME_LSB    0
+#define SW_PROF_DATA_PTR_NAME_WIDTH  ((uint32_t)0x00000020)
+
+#define SW_PROF_DATA_PTR_NAME_RST    0x0
+
+__INLINE uint32_t sw_prof_data_ptr_name_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(SW_PROF_DATA_PTR_NAME_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void sw_prof_data_ptr_name_setf(uint32_t dataptrname)
+{
+    ASSERT_ERR((((uint32_t)dataptrname << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
+    REG_PL_WR(SW_PROF_DATA_PTR_NAME_ADDR, (uint32_t)dataptrname << 0);
+}
+
+/**
+ * @brief DATA_PTR_TRACE register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00       DATA_PTR_TRACE   0x0
+ * </pre>
+ */
+#define SW_PROF_DATA_PTR_TRACE_ADDR   0x1000D11C
+#define SW_PROF_DATA_PTR_TRACE_OFFSET 0x0000001C
+#define SW_PROF_DATA_PTR_TRACE_INDEX  0x00000007
+#define SW_PROF_DATA_PTR_TRACE_RESET  0x00000000
+
+__INLINE uint32_t sw_prof_data_ptr_trace_get(void)
+{
+    return REG_PL_RD(SW_PROF_DATA_PTR_TRACE_ADDR);
+}
+
+__INLINE void sw_prof_data_ptr_trace_set(uint32_t value)
+{
+    REG_PL_WR(SW_PROF_DATA_PTR_TRACE_ADDR, value);
+}
+
+// field definitions
+#define SW_PROF_DATA_PTR_TRACE_MASK   ((uint32_t)0xFFFFFFFF)
+#define SW_PROF_DATA_PTR_TRACE_LSB    0
+#define SW_PROF_DATA_PTR_TRACE_WIDTH  ((uint32_t)0x00000020)
+
+#define SW_PROF_DATA_PTR_TRACE_RST    0x0
+
+__INLINE uint32_t sw_prof_data_ptr_trace_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(SW_PROF_DATA_PTR_TRACE_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void sw_prof_data_ptr_trace_setf(uint32_t dataptrtrace)
+{
+    ASSERT_ERR((((uint32_t)dataptrtrace << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
+    REG_PL_WR(SW_PROF_DATA_PTR_TRACE_ADDR, (uint32_t)dataptrtrace << 0);
+}
+
+/**
+ * @brief MEM_PROTECT_CTRL register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:16     MEM_PROTECT_SIZE   0x0
+ *     14   MEM_INIT_CLR_ACCESS   0
+ *     13      MEM_READ_ACCESS   0
+ *     12     MEM_WRITE_ACCESS   0
+ *     08     MEM_GRANT_ACCESS   0
+ *     03     MEM_INIT_CLR_SET   0
+ *     02         MEM_READ_SET   0
+ *     01        MEM_WRITE_SET   0
+ *     00        MEM_GRANT_SET   0
+ * </pre>
+ */
+#define SW_PROF_MEM_PROTECT_CTRL_ADDR   0x1000D120
+#define SW_PROF_MEM_PROTECT_CTRL_OFFSET 0x00000020
+#define SW_PROF_MEM_PROTECT_CTRL_INDEX  0x00000008
+#define SW_PROF_MEM_PROTECT_CTRL_RESET  0x00000000
+
+__INLINE uint32_t sw_prof_mem_protect_ctrl_get(void)
+{
+    return REG_PL_RD(SW_PROF_MEM_PROTECT_CTRL_ADDR);
+}
+
+__INLINE void sw_prof_mem_protect_ctrl_set(uint32_t value)
+{
+    REG_PL_WR(SW_PROF_MEM_PROTECT_CTRL_ADDR, value);
+}
+
+// field definitions
+#define SW_PROF_MEM_PROTECT_SIZE_MASK      ((uint32_t)0xFFFF0000)
+#define SW_PROF_MEM_PROTECT_SIZE_LSB       16
+#define SW_PROF_MEM_PROTECT_SIZE_WIDTH     ((uint32_t)0x00000010)
+#define SW_PROF_MEM_INIT_CLR_ACCESS_BIT    ((uint32_t)0x00004000)
+#define SW_PROF_MEM_INIT_CLR_ACCESS_POS    14
+#define SW_PROF_MEM_READ_ACCESS_BIT        ((uint32_t)0x00002000)
+#define SW_PROF_MEM_READ_ACCESS_POS        13
+#define SW_PROF_MEM_WRITE_ACCESS_BIT       ((uint32_t)0x00001000)
+#define SW_PROF_MEM_WRITE_ACCESS_POS       12
+#define SW_PROF_MEM_GRANT_ACCESS_BIT       ((uint32_t)0x00000100)
+#define SW_PROF_MEM_GRANT_ACCESS_POS       8
+#define SW_PROF_MEM_INIT_CLR_SET_BIT       ((uint32_t)0x00000008)
+#define SW_PROF_MEM_INIT_CLR_SET_POS       3
+#define SW_PROF_MEM_READ_SET_BIT           ((uint32_t)0x00000004)
+#define SW_PROF_MEM_READ_SET_POS           2
+#define SW_PROF_MEM_WRITE_SET_BIT          ((uint32_t)0x00000002)
+#define SW_PROF_MEM_WRITE_SET_POS          1
+#define SW_PROF_MEM_GRANT_SET_BIT          ((uint32_t)0x00000001)
+#define SW_PROF_MEM_GRANT_SET_POS          0
+
+#define SW_PROF_MEM_PROTECT_SIZE_RST       0x0
+#define SW_PROF_MEM_INIT_CLR_ACCESS_RST    0x0
+#define SW_PROF_MEM_READ_ACCESS_RST        0x0
+#define SW_PROF_MEM_WRITE_ACCESS_RST       0x0
+#define SW_PROF_MEM_GRANT_ACCESS_RST       0x0
+#define SW_PROF_MEM_INIT_CLR_SET_RST       0x0
+#define SW_PROF_MEM_READ_SET_RST           0x0
+#define SW_PROF_MEM_WRITE_SET_RST          0x0
+#define SW_PROF_MEM_GRANT_SET_RST          0x0
+
+__INLINE void sw_prof_mem_protect_ctrl_pack(uint16_t memprotectsize, uint8_t meminitclraccess, uint8_t memreadaccess, uint8_t memwriteaccess, uint8_t memgrantaccess, uint8_t meminitclrset, uint8_t memreadset, uint8_t memwriteset, uint8_t memgrantset)
+{
+    ASSERT_ERR((((uint32_t)memprotectsize << 16) & ~((uint32_t)0xFFFF0000)) == 0);
+    ASSERT_ERR((((uint32_t)meminitclraccess << 14) & ~((uint32_t)0x00004000)) == 0);
+    ASSERT_ERR((((uint32_t)memreadaccess << 13) & ~((uint32_t)0x00002000)) == 0);
+    ASSERT_ERR((((uint32_t)memwriteaccess << 12) & ~((uint32_t)0x00001000)) == 0);
+    ASSERT_ERR((((uint32_t)memgrantaccess << 8) & ~((uint32_t)0x00000100)) == 0);
+    ASSERT_ERR((((uint32_t)meminitclrset << 3) & ~((uint32_t)0x00000008)) == 0);
+    ASSERT_ERR((((uint32_t)memreadset << 2) & ~((uint32_t)0x00000004)) == 0);
+    ASSERT_ERR((((uint32_t)memwriteset << 1) & ~((uint32_t)0x00000002)) == 0);
+    ASSERT_ERR((((uint32_t)memgrantset << 0) & ~((uint32_t)0x00000001)) == 0);
+    REG_PL_WR(SW_PROF_MEM_PROTECT_CTRL_ADDR,  ((uint32_t)memprotectsize << 16) | ((uint32_t)meminitclraccess << 14) | ((uint32_t)memreadaccess << 13) | ((uint32_t)memwriteaccess << 12) | ((uint32_t)memgrantaccess << 8) | ((uint32_t)meminitclrset << 3) | ((uint32_t)memreadset << 2) | ((uint32_t)memwriteset << 1) | ((uint32_t)memgrantset << 0));
+}
+
+__INLINE void sw_prof_mem_protect_ctrl_unpack(uint16_t* memprotectsize, uint8_t* meminitclraccess, uint8_t* memreadaccess, uint8_t* memwriteaccess, uint8_t* memgrantaccess, uint8_t* meminitclrset, uint8_t* memreadset, uint8_t* memwriteset, uint8_t* memgrantset)
+{
+    uint32_t localVal = REG_PL_RD(SW_PROF_MEM_PROTECT_CTRL_ADDR);
+
+    *memprotectsize = (localVal & ((uint32_t)0xFFFF0000)) >> 16;
+    *meminitclraccess = (localVal & ((uint32_t)0x00004000)) >> 14;
+    *memreadaccess = (localVal & ((uint32_t)0x00002000)) >> 13;
+    *memwriteaccess = (localVal & ((uint32_t)0x00001000)) >> 12;
+    *memgrantaccess = (localVal & ((uint32_t)0x00000100)) >> 8;
+    *meminitclrset = (localVal & ((uint32_t)0x00000008)) >> 3;
+    *memreadset = (localVal & ((uint32_t)0x00000004)) >> 2;
+    *memwriteset = (localVal & ((uint32_t)0x00000002)) >> 1;
+    *memgrantset = (localVal & ((uint32_t)0x00000001)) >> 0;
+}
+
+__INLINE uint16_t sw_prof_mem_protect_size_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(SW_PROF_MEM_PROTECT_CTRL_ADDR);
+    return ((localVal & ((uint32_t)0xFFFF0000)) >> 16);
+}
+
+__INLINE void sw_prof_mem_protect_size_setf(uint16_t memprotectsize)
+{
+    ASSERT_ERR((((uint32_t)memprotectsize << 16) & ~((uint32_t)0xFFFF0000)) == 0);
+    REG_PL_WR(SW_PROF_MEM_PROTECT_CTRL_ADDR, (REG_PL_RD(SW_PROF_MEM_PROTECT_CTRL_ADDR) & ~((uint32_t)0xFFFF0000)) | ((uint32_t)memprotectsize << 16));
+}
+
+__INLINE uint8_t sw_prof_mem_init_clr_access_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(SW_PROF_MEM_PROTECT_CTRL_ADDR);
+    return ((localVal & ((uint32_t)0x00004000)) >> 14);
+}
+
+__INLINE void sw_prof_mem_init_clr_access_setf(uint8_t meminitclraccess)
+{
+    ASSERT_ERR((((uint32_t)meminitclraccess << 14) & ~((uint32_t)0x00004000)) == 0);
+    REG_PL_WR(SW_PROF_MEM_PROTECT_CTRL_ADDR, (REG_PL_RD(SW_PROF_MEM_PROTECT_CTRL_ADDR) & ~((uint32_t)0x00004000)) | ((uint32_t)meminitclraccess << 14));
+}
+
+__INLINE uint8_t sw_prof_mem_read_access_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(SW_PROF_MEM_PROTECT_CTRL_ADDR);
+    return ((localVal & ((uint32_t)0x00002000)) >> 13);
+}
+
+__INLINE void sw_prof_mem_read_access_setf(uint8_t memreadaccess)
+{
+    ASSERT_ERR((((uint32_t)memreadaccess << 13) & ~((uint32_t)0x00002000)) == 0);
+    REG_PL_WR(SW_PROF_MEM_PROTECT_CTRL_ADDR, (REG_PL_RD(SW_PROF_MEM_PROTECT_CTRL_ADDR) & ~((uint32_t)0x00002000)) | ((uint32_t)memreadaccess << 13));
+}
+
+__INLINE uint8_t sw_prof_mem_write_access_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(SW_PROF_MEM_PROTECT_CTRL_ADDR);
+    return ((localVal & ((uint32_t)0x00001000)) >> 12);
+}
+
+__INLINE void sw_prof_mem_write_access_setf(uint8_t memwriteaccess)
+{
+    ASSERT_ERR((((uint32_t)memwriteaccess << 12) & ~((uint32_t)0x00001000)) == 0);
+    REG_PL_WR(SW_PROF_MEM_PROTECT_CTRL_ADDR, (REG_PL_RD(SW_PROF_MEM_PROTECT_CTRL_ADDR) & ~((uint32_t)0x00001000)) | ((uint32_t)memwriteaccess << 12));
+}
+
+__INLINE uint8_t sw_prof_mem_grant_access_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(SW_PROF_MEM_PROTECT_CTRL_ADDR);
+    return ((localVal & ((uint32_t)0x00000100)) >> 8);
+}
+
+__INLINE void sw_prof_mem_grant_access_setf(uint8_t memgrantaccess)
+{
+    ASSERT_ERR((((uint32_t)memgrantaccess << 8) & ~((uint32_t)0x00000100)) == 0);
+    REG_PL_WR(SW_PROF_MEM_PROTECT_CTRL_ADDR, (REG_PL_RD(SW_PROF_MEM_PROTECT_CTRL_ADDR) & ~((uint32_t)0x00000100)) | ((uint32_t)memgrantaccess << 8));
+}
+
+__INLINE uint8_t sw_prof_mem_init_clr_set_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(SW_PROF_MEM_PROTECT_CTRL_ADDR);
+    return ((localVal & ((uint32_t)0x00000008)) >> 3);
+}
+
+__INLINE void sw_prof_mem_init_clr_set_setf(uint8_t meminitclrset)
+{
+    ASSERT_ERR((((uint32_t)meminitclrset << 3) & ~((uint32_t)0x00000008)) == 0);
+    REG_PL_WR(SW_PROF_MEM_PROTECT_CTRL_ADDR, (REG_PL_RD(SW_PROF_MEM_PROTECT_CTRL_ADDR) & ~((uint32_t)0x00000008)) | ((uint32_t)meminitclrset << 3));
+}
+
+__INLINE uint8_t sw_prof_mem_read_set_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(SW_PROF_MEM_PROTECT_CTRL_ADDR);
+    return ((localVal & ((uint32_t)0x00000004)) >> 2);
+}
+
+__INLINE void sw_prof_mem_read_set_setf(uint8_t memreadset)
+{
+    ASSERT_ERR((((uint32_t)memreadset << 2) & ~((uint32_t)0x00000004)) == 0);
+    REG_PL_WR(SW_PROF_MEM_PROTECT_CTRL_ADDR, (REG_PL_RD(SW_PROF_MEM_PROTECT_CTRL_ADDR) & ~((uint32_t)0x00000004)) | ((uint32_t)memreadset << 2));
+}
+
+__INLINE uint8_t sw_prof_mem_write_set_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(SW_PROF_MEM_PROTECT_CTRL_ADDR);
+    return ((localVal & ((uint32_t)0x00000002)) >> 1);
+}
+
+__INLINE void sw_prof_mem_write_set_setf(uint8_t memwriteset)
+{
+    ASSERT_ERR((((uint32_t)memwriteset << 1) & ~((uint32_t)0x00000002)) == 0);
+    REG_PL_WR(SW_PROF_MEM_PROTECT_CTRL_ADDR, (REG_PL_RD(SW_PROF_MEM_PROTECT_CTRL_ADDR) & ~((uint32_t)0x00000002)) | ((uint32_t)memwriteset << 1));
+}
+
+__INLINE uint8_t sw_prof_mem_grant_set_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(SW_PROF_MEM_PROTECT_CTRL_ADDR);
+    return ((localVal & ((uint32_t)0x00000001)) >> 0);
+}
+
+__INLINE void sw_prof_mem_grant_set_setf(uint8_t memgrantset)
+{
+    ASSERT_ERR((((uint32_t)memgrantset << 0) & ~((uint32_t)0x00000001)) == 0);
+    REG_PL_WR(SW_PROF_MEM_PROTECT_CTRL_ADDR, (REG_PL_RD(SW_PROF_MEM_PROTECT_CTRL_ADDR) & ~((uint32_t)0x00000001)) | ((uint32_t)memgrantset << 0));
+}
+
+/**
+ * @brief MEM_PROTECT_ADDR register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00     MEM_PROTECT_ADDR   0x0
+ * </pre>
+ */
+#define SW_PROF_MEM_PROTECT_ADDR_ADDR   0x1000D124
+#define SW_PROF_MEM_PROTECT_ADDR_OFFSET 0x00000024
+#define SW_PROF_MEM_PROTECT_ADDR_INDEX  0x00000009
+#define SW_PROF_MEM_PROTECT_ADDR_RESET  0x00000000
+
+__INLINE uint32_t sw_prof_mem_protect_addr_get(void)
+{
+    return REG_PL_RD(SW_PROF_MEM_PROTECT_ADDR_ADDR);
+}
+
+__INLINE void sw_prof_mem_protect_addr_set(uint32_t value)
+{
+    REG_PL_WR(SW_PROF_MEM_PROTECT_ADDR_ADDR, value);
+}
+
+// field definitions
+#define SW_PROF_MEM_PROTECT_ADDR_MASK   ((uint32_t)0xFFFFFFFF)
+#define SW_PROF_MEM_PROTECT_ADDR_LSB    0
+#define SW_PROF_MEM_PROTECT_ADDR_WIDTH  ((uint32_t)0x00000020)
+
+#define SW_PROF_MEM_PROTECT_ADDR_RST    0x0
+
+__INLINE uint32_t sw_prof_mem_protect_addr_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(SW_PROF_MEM_PROTECT_ADDR_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void sw_prof_mem_protect_addr_setf(uint32_t memprotectaddr)
+{
+    ASSERT_ERR((((uint32_t)memprotectaddr << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
+    REG_PL_WR(SW_PROF_MEM_PROTECT_ADDR_ADDR, (uint32_t)memprotectaddr << 0);
+}
+
+
+#endif // _REG_SW_PROFILING_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/reg_timer.h

@@ -0,0 +1,410 @@
+#ifndef _REG_TIMER_H_
+#define _REG_TIMER_H_
+
+#include <stdint.h>
+#include "_reg_timer.h"
+#include "compiler.h"
+#include "arch.h"
+#include "reg_access.h"
+
+#define REG_TIMER_COUNT 7
+
+#define REG_TIMER_DECODING_MASK 0x0000001F
+
+/**
+ * @brief TIMER_CTRL register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     31               enable   0
+ *     30                reset   0
+ *  27:00           unit_in_us   0x3E8
+ * </pre>
+ */
+#define TMR_TIMER_CTRL_ADDR   0x1000E000
+#define TMR_TIMER_CTRL_OFFSET 0x00000000
+#define TMR_TIMER_CTRL_INDEX  0x00000000
+#define TMR_TIMER_CTRL_RESET  0x000003E8
+
+__INLINE uint32_t tmr_timer_ctrl_get(void)
+{
+    return REG_PL_RD(TMR_TIMER_CTRL_ADDR);
+}
+
+__INLINE void tmr_timer_ctrl_set(uint32_t value)
+{
+    REG_PL_WR(TMR_TIMER_CTRL_ADDR, value);
+}
+
+// field definitions
+#define TMR_ENABLE_BIT        ((uint32_t)0x80000000)
+#define TMR_ENABLE_POS        31
+#define TMR_RESET_BIT         ((uint32_t)0x40000000)
+#define TMR_RESET_POS         30
+#define TMR_UNIT_IN_US_MASK   ((uint32_t)0x0FFFFFFF)
+#define TMR_UNIT_IN_US_LSB    0
+#define TMR_UNIT_IN_US_WIDTH  ((uint32_t)0x0000001C)
+
+#define TMR_ENABLE_RST        0x0
+#define TMR_RESET_RST         0x0
+#define TMR_UNIT_IN_US_RST    0x3E8
+
+__INLINE void tmr_timer_ctrl_pack(uint8_t enable, uint8_t reset, uint32_t unitinus)
+{
+    ASSERT_ERR((((uint32_t)enable << 31) & ~((uint32_t)0x80000000)) == 0);
+    ASSERT_ERR((((uint32_t)reset << 30) & ~((uint32_t)0x40000000)) == 0);
+    ASSERT_ERR((((uint32_t)unitinus << 0) & ~((uint32_t)0x0FFFFFFF)) == 0);
+    REG_PL_WR(TMR_TIMER_CTRL_ADDR,  ((uint32_t)enable << 31) | ((uint32_t)reset << 30) | ((uint32_t)unitinus << 0));
+}
+
+__INLINE void tmr_timer_ctrl_unpack(uint8_t* enable, uint8_t* reset, uint32_t* unitinus)
+{
+    uint32_t localVal = REG_PL_RD(TMR_TIMER_CTRL_ADDR);
+
+    *enable = (localVal & ((uint32_t)0x80000000)) >> 31;
+    *reset = (localVal & ((uint32_t)0x40000000)) >> 30;
+    *unitinus = (localVal & ((uint32_t)0x0FFFFFFF)) >> 0;
+}
+
+__INLINE uint8_t tmr_enable_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(TMR_TIMER_CTRL_ADDR);
+    return ((localVal & ((uint32_t)0x80000000)) >> 31);
+}
+
+__INLINE void tmr_enable_setf(uint8_t enable)
+{
+    ASSERT_ERR((((uint32_t)enable << 31) & ~((uint32_t)0x80000000)) == 0);
+    REG_PL_WR(TMR_TIMER_CTRL_ADDR, (REG_PL_RD(TMR_TIMER_CTRL_ADDR) & ~((uint32_t)0x80000000)) | ((uint32_t)enable << 31));
+}
+
+__INLINE uint8_t tmr_reset_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(TMR_TIMER_CTRL_ADDR);
+    return ((localVal & ((uint32_t)0x40000000)) >> 30);
+}
+
+__INLINE void tmr_reset_setf(uint8_t reset)
+{
+    ASSERT_ERR((((uint32_t)reset << 30) & ~((uint32_t)0x40000000)) == 0);
+    REG_PL_WR(TMR_TIMER_CTRL_ADDR, (REG_PL_RD(TMR_TIMER_CTRL_ADDR) & ~((uint32_t)0x40000000)) | ((uint32_t)reset << 30));
+}
+
+__INLINE uint32_t tmr_unit_in_us_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(TMR_TIMER_CTRL_ADDR);
+    return ((localVal & ((uint32_t)0x0FFFFFFF)) >> 0);
+}
+
+__INLINE void tmr_unit_in_us_setf(uint32_t unitinus)
+{
+    ASSERT_ERR((((uint32_t)unitinus << 0) & ~((uint32_t)0x0FFFFFFF)) == 0);
+    REG_PL_WR(TMR_TIMER_CTRL_ADDR, (REG_PL_RD(TMR_TIMER_CTRL_ADDR) & ~((uint32_t)0x0FFFFFFF)) | ((uint32_t)unitinus << 0));
+}
+
+/**
+ * @brief CURRENT_TIME register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  27:00                 time   0x0
+ * </pre>
+ */
+#define TMR_CURRENT_TIME_ADDR   0x1000E004
+#define TMR_CURRENT_TIME_OFFSET 0x00000004
+#define TMR_CURRENT_TIME_INDEX  0x00000001
+#define TMR_CURRENT_TIME_RESET  0x00000000
+
+__INLINE uint32_t tmr_current_time_get(void)
+{
+    return REG_PL_RD(TMR_CURRENT_TIME_ADDR);
+}
+
+__INLINE void tmr_current_time_set(uint32_t value)
+{
+    REG_PL_WR(TMR_CURRENT_TIME_ADDR, value);
+}
+
+// field definitions
+#define TMR_TIME_MASK   ((uint32_t)0x0FFFFFFF)
+#define TMR_TIME_LSB    0
+#define TMR_TIME_WIDTH  ((uint32_t)0x0000001C)
+
+#define TMR_TIME_RST    0x0
+
+__INLINE uint32_t tmr_time_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(TMR_CURRENT_TIME_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0x0FFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+/**
+ * @brief END_TIME register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  27:00             end_time   0x0
+ * </pre>
+ */
+#define TMR_END_TIME_ADDR   0x1000E008
+#define TMR_END_TIME_OFFSET 0x00000008
+#define TMR_END_TIME_INDEX  0x00000002
+#define TMR_END_TIME_RESET  0x00000000
+
+__INLINE uint32_t tmr_end_time_get(void)
+{
+    return REG_PL_RD(TMR_END_TIME_ADDR);
+}
+
+__INLINE void tmr_end_time_set(uint32_t value)
+{
+    REG_PL_WR(TMR_END_TIME_ADDR, value);
+}
+
+// field definitions
+#define TMR_END_TIME_MASK   ((uint32_t)0x0FFFFFFF)
+#define TMR_END_TIME_LSB    0
+#define TMR_END_TIME_WIDTH  ((uint32_t)0x0000001C)
+
+#define TMR_END_TIME_RST    0x0
+
+__INLINE uint32_t tmr_end_time_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(TMR_END_TIME_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0x0FFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void tmr_end_time_setf(uint32_t endtime)
+{
+    ASSERT_ERR((((uint32_t)endtime << 0) & ~((uint32_t)0x0FFFFFFF)) == 0);
+    REG_PL_WR(TMR_END_TIME_ADDR, (uint32_t)endtime << 0);
+}
+
+/**
+ * @brief PERIODIC_TIME register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  27:00               period   0x0
+ * </pre>
+ */
+#define TMR_PERIODIC_TIME_ADDR   0x1000E00C
+#define TMR_PERIODIC_TIME_OFFSET 0x0000000C
+#define TMR_PERIODIC_TIME_INDEX  0x00000003
+#define TMR_PERIODIC_TIME_RESET  0x00000000
+
+__INLINE uint32_t tmr_periodic_time_get(void)
+{
+    return REG_PL_RD(TMR_PERIODIC_TIME_ADDR);
+}
+
+__INLINE void tmr_periodic_time_set(uint32_t value)
+{
+    REG_PL_WR(TMR_PERIODIC_TIME_ADDR, value);
+}
+
+// field definitions
+#define TMR_PERIOD_MASK   ((uint32_t)0x0FFFFFFF)
+#define TMR_PERIOD_LSB    0
+#define TMR_PERIOD_WIDTH  ((uint32_t)0x0000001C)
+
+#define TMR_PERIOD_RST    0x0
+
+__INLINE uint32_t tmr_period_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(TMR_PERIODIC_TIME_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0x0FFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void tmr_period_setf(uint32_t period)
+{
+    ASSERT_ERR((((uint32_t)period << 0) & ~((uint32_t)0x0FFFFFFF)) == 0);
+    REG_PL_WR(TMR_PERIODIC_TIME_ADDR, (uint32_t)period << 0);
+}
+
+/**
+ * @brief ISR_STATUS register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     01        periodic_stat   0
+ *     00        end_time_stat   0
+ * </pre>
+ */
+#define TMR_ISR_STATUS_ADDR   0x1000E010
+#define TMR_ISR_STATUS_OFFSET 0x00000010
+#define TMR_ISR_STATUS_INDEX  0x00000004
+#define TMR_ISR_STATUS_RESET  0x00000000
+
+__INLINE uint32_t tmr_isr_status_get(void)
+{
+    return REG_PL_RD(TMR_ISR_STATUS_ADDR);
+}
+
+// field definitions
+#define TMR_PERIODIC_STAT_BIT    ((uint32_t)0x00000002)
+#define TMR_PERIODIC_STAT_POS    1
+#define TMR_END_TIME_STAT_BIT    ((uint32_t)0x00000001)
+#define TMR_END_TIME_STAT_POS    0
+
+#define TMR_PERIODIC_STAT_RST    0x0
+#define TMR_END_TIME_STAT_RST    0x0
+
+__INLINE void tmr_isr_status_unpack(uint8_t* periodicstat, uint8_t* endtimestat)
+{
+    uint32_t localVal = REG_PL_RD(TMR_ISR_STATUS_ADDR);
+
+    *periodicstat = (localVal & ((uint32_t)0x00000002)) >> 1;
+    *endtimestat = (localVal & ((uint32_t)0x00000001)) >> 0;
+}
+
+__INLINE uint8_t tmr_periodic_stat_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(TMR_ISR_STATUS_ADDR);
+    return ((localVal & ((uint32_t)0x00000002)) >> 1);
+}
+
+__INLINE uint8_t tmr_end_time_stat_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(TMR_ISR_STATUS_ADDR);
+    return ((localVal & ((uint32_t)0x00000001)) >> 0);
+}
+
+/**
+ * @brief ISR_EN register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     01          periodic_en   0
+ *     00          end_time_en   0
+ * </pre>
+ */
+#define TMR_ISR_EN_ADDR   0x1000E014
+#define TMR_ISR_EN_OFFSET 0x00000014
+#define TMR_ISR_EN_INDEX  0x00000005
+#define TMR_ISR_EN_RESET  0x00000000
+
+__INLINE uint32_t tmr_isr_en_get(void)
+{
+    return REG_PL_RD(TMR_ISR_EN_ADDR);
+}
+
+__INLINE void tmr_isr_en_set(uint32_t value)
+{
+    REG_PL_WR(TMR_ISR_EN_ADDR, value);
+}
+
+// field definitions
+#define TMR_PERIODIC_EN_BIT    ((uint32_t)0x00000002)
+#define TMR_PERIODIC_EN_POS    1
+#define TMR_END_TIME_EN_BIT    ((uint32_t)0x00000001)
+#define TMR_END_TIME_EN_POS    0
+
+#define TMR_PERIODIC_EN_RST    0x0
+#define TMR_END_TIME_EN_RST    0x0
+
+__INLINE void tmr_isr_en_pack(uint8_t periodicen, uint8_t endtimeen)
+{
+    ASSERT_ERR((((uint32_t)periodicen << 1) & ~((uint32_t)0x00000002)) == 0);
+    ASSERT_ERR((((uint32_t)endtimeen << 0) & ~((uint32_t)0x00000001)) == 0);
+    REG_PL_WR(TMR_ISR_EN_ADDR,  ((uint32_t)periodicen << 1) | ((uint32_t)endtimeen << 0));
+}
+
+__INLINE void tmr_isr_en_unpack(uint8_t* periodicen, uint8_t* endtimeen)
+{
+    uint32_t localVal = REG_PL_RD(TMR_ISR_EN_ADDR);
+
+    *periodicen = (localVal & ((uint32_t)0x00000002)) >> 1;
+    *endtimeen = (localVal & ((uint32_t)0x00000001)) >> 0;
+}
+
+__INLINE uint8_t tmr_periodic_en_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(TMR_ISR_EN_ADDR);
+    return ((localVal & ((uint32_t)0x00000002)) >> 1);
+}
+
+__INLINE void tmr_periodic_en_setf(uint8_t periodicen)
+{
+    ASSERT_ERR((((uint32_t)periodicen << 1) & ~((uint32_t)0x00000002)) == 0);
+    REG_PL_WR(TMR_ISR_EN_ADDR, (REG_PL_RD(TMR_ISR_EN_ADDR) & ~((uint32_t)0x00000002)) | ((uint32_t)periodicen << 1));
+}
+
+__INLINE uint8_t tmr_end_time_en_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(TMR_ISR_EN_ADDR);
+    return ((localVal & ((uint32_t)0x00000001)) >> 0);
+}
+
+__INLINE void tmr_end_time_en_setf(uint8_t endtimeen)
+{
+    ASSERT_ERR((((uint32_t)endtimeen << 0) & ~((uint32_t)0x00000001)) == 0);
+    REG_PL_WR(TMR_ISR_EN_ADDR, (REG_PL_RD(TMR_ISR_EN_ADDR) & ~((uint32_t)0x00000001)) | ((uint32_t)endtimeen << 0));
+}
+
+/**
+ * @brief ISR_CLR register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     01         periodic_clr   0
+ *     00         end_time_clr   0
+ * </pre>
+ */
+#define TMR_ISR_CLR_ADDR   0x1000E018
+#define TMR_ISR_CLR_OFFSET 0x00000018
+#define TMR_ISR_CLR_INDEX  0x00000006
+#define TMR_ISR_CLR_RESET  0x00000000
+
+__INLINE uint32_t tmr_isr_clr_get(void)
+{
+    return REG_PL_RD(TMR_ISR_CLR_ADDR);
+}
+
+__INLINE void tmr_isr_clr_set(uint32_t value)
+{
+    REG_PL_WR(TMR_ISR_CLR_ADDR, value);
+}
+
+// field definitions
+#define TMR_PERIODIC_CLR_BIT    ((uint32_t)0x00000002)
+#define TMR_PERIODIC_CLR_POS    1
+#define TMR_END_TIME_CLR_BIT    ((uint32_t)0x00000001)
+#define TMR_END_TIME_CLR_POS    0
+
+#define TMR_PERIODIC_CLR_RST    0x0
+#define TMR_END_TIME_CLR_RST    0x0
+
+__INLINE void tmr_isr_clr_pack(uint8_t periodicclr, uint8_t endtimeclr)
+{
+    ASSERT_ERR((((uint32_t)periodicclr << 1) & ~((uint32_t)0x00000002)) == 0);
+    ASSERT_ERR((((uint32_t)endtimeclr << 0) & ~((uint32_t)0x00000001)) == 0);
+    REG_PL_WR(TMR_ISR_CLR_ADDR,  ((uint32_t)periodicclr << 1) | ((uint32_t)endtimeclr << 0));
+}
+
+__INLINE void tmr_isr_clr_unpack(uint8_t* periodicclr, uint8_t* endtimeclr)
+{
+    uint32_t localVal = REG_PL_RD(TMR_ISR_CLR_ADDR);
+
+    *periodicclr = (localVal & ((uint32_t)0x00000002)) >> 1;
+    *endtimeclr = (localVal & ((uint32_t)0x00000001)) >> 0;
+}
+
+__INLINE void tmr_periodic_clr_setf(uint8_t periodicclr)
+{
+    ASSERT_ERR((((uint32_t)periodicclr << 1) & ~((uint32_t)0x00000002)) == 0);
+    REG_PL_WR(TMR_ISR_CLR_ADDR, (REG_PL_RD(TMR_ISR_CLR_ADDR) & ~((uint32_t)0x00000002)) | ((uint32_t)periodicclr << 1));
+}
+
+__INLINE void tmr_end_time_clr_setf(uint8_t endtimeclr)
+{
+    ASSERT_ERR((((uint32_t)endtimeclr << 0) & ~((uint32_t)0x00000001)) == 0);
+    REG_PL_WR(TMR_ISR_CLR_ADDR, (REG_PL_RD(TMR_ISR_CLR_ADDR) & ~((uint32_t)0x00000001)) | ((uint32_t)endtimeclr << 0));
+}
+
+
+#endif // _REG_TIMER_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/reg_uart.h

@@ -0,0 +1,774 @@
+#ifndef _REG_UART_H_
+#define _REG_UART_H_
+
+#include <stdint.h>
+#include "_reg_uart.h"
+#include "compiler.h"
+#include "arch.h"
+#include "reg_access.h"
+
+#define REG_UART_COUNT 9
+
+#define REG_UART_DECODING_MASK 0x0000003F
+
+/**
+ * @brief CTRL register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:24        CLK_DIV_FRACP   0x0
+ *  23:16         CLK_DIV_INTP   0x0
+ *  15:08              CNT_VAL   0x0
+ *     04            CNT_START   0
+ *     01        EXT_WAKEUP_EN   0
+ *     00            FORCE_RTS   0
+ * </pre>
+ */
+#define UART_CTRL_ADDR   0x10007000
+#define UART_CTRL_OFFSET 0x00000000
+#define UART_CTRL_INDEX  0x00000000
+#define UART_CTRL_RESET  0x00000000
+
+__INLINE uint32_t uart_ctrl_get(void)
+{
+    return REG_PL_RD(UART_CTRL_ADDR);
+}
+
+__INLINE void uart_ctrl_set(uint32_t value)
+{
+    REG_PL_WR(UART_CTRL_ADDR, value);
+}
+
+// field definitions
+#define UART_CLK_DIV_FRACP_MASK   ((uint32_t)0xFF000000)
+#define UART_CLK_DIV_FRACP_LSB    24
+#define UART_CLK_DIV_FRACP_WIDTH  ((uint32_t)0x00000008)
+#define UART_CLK_DIV_INTP_MASK    ((uint32_t)0x00FF0000)
+#define UART_CLK_DIV_INTP_LSB     16
+#define UART_CLK_DIV_INTP_WIDTH   ((uint32_t)0x00000008)
+#define UART_CNT_VAL_MASK         ((uint32_t)0x0000FF00)
+#define UART_CNT_VAL_LSB          8
+#define UART_CNT_VAL_WIDTH        ((uint32_t)0x00000008)
+#define UART_CNT_START_BIT        ((uint32_t)0x00000010)
+#define UART_CNT_START_POS        4
+#define UART_EXT_WAKEUP_EN_BIT    ((uint32_t)0x00000002)
+#define UART_EXT_WAKEUP_EN_POS    1
+#define UART_FORCE_RTS_BIT        ((uint32_t)0x00000001)
+#define UART_FORCE_RTS_POS        0
+
+#define UART_CLK_DIV_FRACP_RST    0x0
+#define UART_CLK_DIV_INTP_RST     0x0
+#define UART_CNT_VAL_RST          0x0
+#define UART_CNT_START_RST        0x0
+#define UART_EXT_WAKEUP_EN_RST    0x0
+#define UART_FORCE_RTS_RST        0x0
+
+__INLINE void uart_ctrl_pack(uint8_t clkdivfracp, uint8_t clkdivintp, uint8_t cntval, uint8_t cntstart, uint8_t extwakeupen, uint8_t forcerts)
+{
+    ASSERT_ERR((((uint32_t)clkdivfracp << 24) & ~((uint32_t)0xFF000000)) == 0);
+    ASSERT_ERR((((uint32_t)clkdivintp << 16) & ~((uint32_t)0x00FF0000)) == 0);
+    ASSERT_ERR((((uint32_t)cntval << 8) & ~((uint32_t)0x0000FF00)) == 0);
+    ASSERT_ERR((((uint32_t)cntstart << 4) & ~((uint32_t)0x00000010)) == 0);
+    ASSERT_ERR((((uint32_t)extwakeupen << 1) & ~((uint32_t)0x00000002)) == 0);
+    ASSERT_ERR((((uint32_t)forcerts << 0) & ~((uint32_t)0x00000001)) == 0);
+    REG_PL_WR(UART_CTRL_ADDR,  ((uint32_t)clkdivfracp << 24) | ((uint32_t)clkdivintp << 16) | ((uint32_t)cntval << 8) | ((uint32_t)cntstart << 4) | ((uint32_t)extwakeupen << 1) | ((uint32_t)forcerts << 0));
+}
+
+__INLINE void uart_ctrl_unpack(uint8_t* clkdivfracp, uint8_t* clkdivintp, uint8_t* cntval, uint8_t* cntstart, uint8_t* extwakeupen, uint8_t* forcerts)
+{
+    uint32_t localVal = REG_PL_RD(UART_CTRL_ADDR);
+
+    *clkdivfracp = (localVal & ((uint32_t)0xFF000000)) >> 24;
+    *clkdivintp = (localVal & ((uint32_t)0x00FF0000)) >> 16;
+    *cntval = (localVal & ((uint32_t)0x0000FF00)) >> 8;
+    *cntstart = (localVal & ((uint32_t)0x00000010)) >> 4;
+    *extwakeupen = (localVal & ((uint32_t)0x00000002)) >> 1;
+    *forcerts = (localVal & ((uint32_t)0x00000001)) >> 0;
+}
+
+__INLINE uint8_t uart_clk_div_fracp_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART_CTRL_ADDR);
+    return ((localVal & ((uint32_t)0xFF000000)) >> 24);
+}
+
+__INLINE void uart_clk_div_fracp_setf(uint8_t clkdivfracp)
+{
+    ASSERT_ERR((((uint32_t)clkdivfracp << 24) & ~((uint32_t)0xFF000000)) == 0);
+    REG_PL_WR(UART_CTRL_ADDR, (REG_PL_RD(UART_CTRL_ADDR) & ~((uint32_t)0xFF000000)) | ((uint32_t)clkdivfracp << 24));
+}
+
+__INLINE uint8_t uart_clk_div_intp_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART_CTRL_ADDR);
+    return ((localVal & ((uint32_t)0x00FF0000)) >> 16);
+}
+
+__INLINE void uart_clk_div_intp_setf(uint8_t clkdivintp)
+{
+    ASSERT_ERR((((uint32_t)clkdivintp << 16) & ~((uint32_t)0x00FF0000)) == 0);
+    REG_PL_WR(UART_CTRL_ADDR, (REG_PL_RD(UART_CTRL_ADDR) & ~((uint32_t)0x00FF0000)) | ((uint32_t)clkdivintp << 16));
+}
+
+__INLINE uint8_t uart_cnt_val_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART_CTRL_ADDR);
+    return ((localVal & ((uint32_t)0x0000FF00)) >> 8);
+}
+
+__INLINE void uart_cnt_val_setf(uint8_t cntval)
+{
+    ASSERT_ERR((((uint32_t)cntval << 8) & ~((uint32_t)0x0000FF00)) == 0);
+    REG_PL_WR(UART_CTRL_ADDR, (REG_PL_RD(UART_CTRL_ADDR) & ~((uint32_t)0x0000FF00)) | ((uint32_t)cntval << 8));
+}
+
+__INLINE void uart_cnt_start_setf(uint8_t cntstart)
+{
+    ASSERT_ERR((((uint32_t)cntstart << 4) & ~((uint32_t)0x00000010)) == 0);
+    REG_PL_WR(UART_CTRL_ADDR, (REG_PL_RD(UART_CTRL_ADDR) & ~((uint32_t)0x00000010)) | ((uint32_t)cntstart << 4));
+}
+
+__INLINE uint8_t uart_ext_wakeup_en_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART_CTRL_ADDR);
+    return ((localVal & ((uint32_t)0x00000002)) >> 1);
+}
+
+__INLINE void uart_ext_wakeup_en_setf(uint8_t extwakeupen)
+{
+    ASSERT_ERR((((uint32_t)extwakeupen << 1) & ~((uint32_t)0x00000002)) == 0);
+    REG_PL_WR(UART_CTRL_ADDR, (REG_PL_RD(UART_CTRL_ADDR) & ~((uint32_t)0x00000002)) | ((uint32_t)extwakeupen << 1));
+}
+
+__INLINE uint8_t uart_force_rts_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART_CTRL_ADDR);
+    return ((localVal & ((uint32_t)0x00000001)) >> 0);
+}
+
+__INLINE void uart_force_rts_setf(uint8_t forcerts)
+{
+    ASSERT_ERR((((uint32_t)forcerts << 0) & ~((uint32_t)0x00000001)) == 0);
+    REG_PL_WR(UART_CTRL_ADDR, (REG_PL_RD(UART_CTRL_ADDR) & ~((uint32_t)0x00000001)) | ((uint32_t)forcerts << 0));
+}
+
+/**
+ * @brief STAT register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     09       TX_DMA_STARTED   0
+ *     08       RX_DMA_STARTED   0
+ *     05           EXT_WAKEUP   0
+ *     04              CNT_END   0
+ *     03        TX_FIFO_EMPTY   0
+ *     02    RX_FIFO_NOT_EMPTY   0
+ *     01                  CTS   0
+ *     00                  RTS   0
+ * </pre>
+ */
+#define UART_STAT_ADDR   0x10007004
+#define UART_STAT_OFFSET 0x00000004
+#define UART_STAT_INDEX  0x00000001
+#define UART_STAT_RESET  0x00000000
+
+__INLINE uint32_t uart_stat_get(void)
+{
+    return REG_PL_RD(UART_STAT_ADDR);
+}
+
+// field definitions
+#define UART_TX_DMA_STARTED_BIT       ((uint32_t)0x00000200)
+#define UART_TX_DMA_STARTED_POS       9
+#define UART_RX_DMA_STARTED_BIT       ((uint32_t)0x00000100)
+#define UART_RX_DMA_STARTED_POS       8
+#define UART_EXT_WAKEUP_BIT           ((uint32_t)0x00000020)
+#define UART_EXT_WAKEUP_POS           5
+#define UART_CNT_END_BIT              ((uint32_t)0x00000010)
+#define UART_CNT_END_POS              4
+#define UART_TX_FIFO_EMPTY_BIT        ((uint32_t)0x00000008)
+#define UART_TX_FIFO_EMPTY_POS        3
+#define UART_RX_FIFO_NOT_EMPTY_BIT    ((uint32_t)0x00000004)
+#define UART_RX_FIFO_NOT_EMPTY_POS    2
+#define UART_CTS_BIT                  ((uint32_t)0x00000002)
+#define UART_CTS_POS                  1
+#define UART_RTS_BIT                  ((uint32_t)0x00000001)
+#define UART_RTS_POS                  0
+
+#define UART_TX_DMA_STARTED_RST       0x0
+#define UART_RX_DMA_STARTED_RST       0x0
+#define UART_EXT_WAKEUP_RST           0x0
+#define UART_CNT_END_RST              0x0
+#define UART_TX_FIFO_EMPTY_RST        0x0
+#define UART_RX_FIFO_NOT_EMPTY_RST    0x0
+#define UART_CTS_RST                  0x0
+#define UART_RTS_RST                  0x0
+
+__INLINE void uart_stat_unpack(uint8_t* txdmastarted, uint8_t* rxdmastarted, uint8_t* extwakeup, uint8_t* cntend, uint8_t* txfifoempty, uint8_t* rxfifonotempty, uint8_t* cts, uint8_t* rts)
+{
+    uint32_t localVal = REG_PL_RD(UART_STAT_ADDR);
+
+    *txdmastarted = (localVal & ((uint32_t)0x00000200)) >> 9;
+    *rxdmastarted = (localVal & ((uint32_t)0x00000100)) >> 8;
+    *extwakeup = (localVal & ((uint32_t)0x00000020)) >> 5;
+    *cntend = (localVal & ((uint32_t)0x00000010)) >> 4;
+    *txfifoempty = (localVal & ((uint32_t)0x00000008)) >> 3;
+    *rxfifonotempty = (localVal & ((uint32_t)0x00000004)) >> 2;
+    *cts = (localVal & ((uint32_t)0x00000002)) >> 1;
+    *rts = (localVal & ((uint32_t)0x00000001)) >> 0;
+}
+
+__INLINE uint8_t uart_tx_dma_started_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART_STAT_ADDR);
+    return ((localVal & ((uint32_t)0x00000200)) >> 9);
+}
+
+__INLINE uint8_t uart_rx_dma_started_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART_STAT_ADDR);
+    return ((localVal & ((uint32_t)0x00000100)) >> 8);
+}
+
+__INLINE uint8_t uart_ext_wakeup_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART_STAT_ADDR);
+    return ((localVal & ((uint32_t)0x00000020)) >> 5);
+}
+
+__INLINE uint8_t uart_cnt_end_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART_STAT_ADDR);
+    return ((localVal & ((uint32_t)0x00000010)) >> 4);
+}
+
+__INLINE uint8_t uart_tx_fifo_empty_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART_STAT_ADDR);
+    return ((localVal & ((uint32_t)0x00000008)) >> 3);
+}
+
+__INLINE uint8_t uart_rx_fifo_not_empty_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART_STAT_ADDR);
+    return ((localVal & ((uint32_t)0x00000004)) >> 2);
+}
+
+__INLINE uint8_t uart_cts_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART_STAT_ADDR);
+    return ((localVal & ((uint32_t)0x00000002)) >> 1);
+}
+
+__INLINE uint8_t uart_rts_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART_STAT_ADDR);
+    return ((localVal & ((uint32_t)0x00000001)) >> 0);
+}
+
+/**
+ * @brief CLK register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00                 FREQ   0x0
+ * </pre>
+ */
+#define UART_CLK_ADDR   0x10007008
+#define UART_CLK_OFFSET 0x00000008
+#define UART_CLK_INDEX  0x00000002
+#define UART_CLK_RESET  0x00000000
+
+__INLINE uint32_t uart_clk_get(void)
+{
+    return REG_PL_RD(UART_CLK_ADDR);
+}
+
+// field definitions
+#define UART_FREQ_MASK   ((uint32_t)0xFFFFFFFF)
+#define UART_FREQ_LSB    0
+#define UART_FREQ_WIDTH  ((uint32_t)0x00000020)
+
+#define UART_FREQ_RST    0x0
+
+__INLINE uint32_t uart_freq_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART_CLK_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+/**
+ * @brief ISR_STAT register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     06          TX_DMA_DONE   0
+ *     05          RX_DMA_DONE   0
+ *     04            BREAK_ISR   0
+ *     01    TX_FIFO_EMPTY_ISR   0
+ *     00   RX_FIFO_NOT_EMPTY_ISR   0
+ * </pre>
+ */
+#define UART_ISR_STAT_ADDR   0x1000700C
+#define UART_ISR_STAT_OFFSET 0x0000000C
+#define UART_ISR_STAT_INDEX  0x00000003
+#define UART_ISR_STAT_RESET  0x00000000
+
+__INLINE uint32_t uart_isr_stat_get(void)
+{
+    return REG_PL_RD(UART_ISR_STAT_ADDR);
+}
+
+// field definitions
+#define UART_TX_DMA_DONE_BIT              ((uint32_t)0x00000040)
+#define UART_TX_DMA_DONE_POS              6
+#define UART_RX_DMA_DONE_BIT              ((uint32_t)0x00000020)
+#define UART_RX_DMA_DONE_POS              5
+#define UART_BREAK_ISR_BIT                ((uint32_t)0x00000010)
+#define UART_BREAK_ISR_POS                4
+#define UART_TX_FIFO_EMPTY_ISR_BIT        ((uint32_t)0x00000002)
+#define UART_TX_FIFO_EMPTY_ISR_POS        1
+#define UART_RX_FIFO_NOT_EMPTY_ISR_BIT    ((uint32_t)0x00000001)
+#define UART_RX_FIFO_NOT_EMPTY_ISR_POS    0
+
+#define UART_TX_DMA_DONE_RST              0x0
+#define UART_RX_DMA_DONE_RST              0x0
+#define UART_BREAK_ISR_RST                0x0
+#define UART_TX_FIFO_EMPTY_ISR_RST        0x0
+#define UART_RX_FIFO_NOT_EMPTY_ISR_RST    0x0
+
+__INLINE void uart_isr_stat_unpack(uint8_t* txdmadone, uint8_t* rxdmadone, uint8_t* breakisr, uint8_t* txfifoemptyisr, uint8_t* rxfifonotemptyisr)
+{
+    uint32_t localVal = REG_PL_RD(UART_ISR_STAT_ADDR);
+
+    *txdmadone = (localVal & ((uint32_t)0x00000040)) >> 6;
+    *rxdmadone = (localVal & ((uint32_t)0x00000020)) >> 5;
+    *breakisr = (localVal & ((uint32_t)0x00000010)) >> 4;
+    *txfifoemptyisr = (localVal & ((uint32_t)0x00000002)) >> 1;
+    *rxfifonotemptyisr = (localVal & ((uint32_t)0x00000001)) >> 0;
+}
+
+__INLINE uint8_t uart_tx_dma_done_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART_ISR_STAT_ADDR);
+    return ((localVal & ((uint32_t)0x00000040)) >> 6);
+}
+
+__INLINE uint8_t uart_rx_dma_done_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART_ISR_STAT_ADDR);
+    return ((localVal & ((uint32_t)0x00000020)) >> 5);
+}
+
+__INLINE uint8_t uart_break_isr_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART_ISR_STAT_ADDR);
+    return ((localVal & ((uint32_t)0x00000010)) >> 4);
+}
+
+__INLINE uint8_t uart_tx_fifo_empty_isr_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART_ISR_STAT_ADDR);
+    return ((localVal & ((uint32_t)0x00000002)) >> 1);
+}
+
+__INLINE uint8_t uart_rx_fifo_not_empty_isr_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART_ISR_STAT_ADDR);
+    return ((localVal & ((uint32_t)0x00000001)) >> 0);
+}
+
+/**
+ * @brief ISR_EN register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     06       TX_DMA_DONE_EN   0
+ *     05       RX_DMA_DONE_EN   0
+ *     04             BREAK_EN   0
+ *     01     TX_FIFO_EMPTY_EN   0
+ *     00   RX_FIFO_NOT_EMPTY_EN   0
+ * </pre>
+ */
+#define UART_ISR_EN_ADDR   0x10007010
+#define UART_ISR_EN_OFFSET 0x00000010
+#define UART_ISR_EN_INDEX  0x00000004
+#define UART_ISR_EN_RESET  0x00000000
+
+__INLINE uint32_t uart_isr_en_get(void)
+{
+    return REG_PL_RD(UART_ISR_EN_ADDR);
+}
+
+__INLINE void uart_isr_en_set(uint32_t value)
+{
+    REG_PL_WR(UART_ISR_EN_ADDR, value);
+}
+
+// field definitions
+#define UART_TX_DMA_DONE_EN_BIT          ((uint32_t)0x00000040)
+#define UART_TX_DMA_DONE_EN_POS          6
+#define UART_RX_DMA_DONE_EN_BIT          ((uint32_t)0x00000020)
+#define UART_RX_DMA_DONE_EN_POS          5
+#define UART_BREAK_EN_BIT                ((uint32_t)0x00000010)
+#define UART_BREAK_EN_POS                4
+#define UART_TX_FIFO_EMPTY_EN_BIT        ((uint32_t)0x00000002)
+#define UART_TX_FIFO_EMPTY_EN_POS        1
+#define UART_RX_FIFO_NOT_EMPTY_EN_BIT    ((uint32_t)0x00000001)
+#define UART_RX_FIFO_NOT_EMPTY_EN_POS    0
+
+#define UART_TX_DMA_DONE_EN_RST          0x0
+#define UART_RX_DMA_DONE_EN_RST          0x0
+#define UART_BREAK_EN_RST                0x0
+#define UART_TX_FIFO_EMPTY_EN_RST        0x0
+#define UART_RX_FIFO_NOT_EMPTY_EN_RST    0x0
+
+__INLINE void uart_isr_en_pack(uint8_t txdmadoneen, uint8_t rxdmadoneen, uint8_t breaken, uint8_t txfifoemptyen, uint8_t rxfifonotemptyen)
+{
+    ASSERT_ERR((((uint32_t)txdmadoneen << 6) & ~((uint32_t)0x00000040)) == 0);
+    ASSERT_ERR((((uint32_t)rxdmadoneen << 5) & ~((uint32_t)0x00000020)) == 0);
+    ASSERT_ERR((((uint32_t)breaken << 4) & ~((uint32_t)0x00000010)) == 0);
+    ASSERT_ERR((((uint32_t)txfifoemptyen << 1) & ~((uint32_t)0x00000002)) == 0);
+    ASSERT_ERR((((uint32_t)rxfifonotemptyen << 0) & ~((uint32_t)0x00000001)) == 0);
+    REG_PL_WR(UART_ISR_EN_ADDR,  ((uint32_t)txdmadoneen << 6) | ((uint32_t)rxdmadoneen << 5) | ((uint32_t)breaken << 4) | ((uint32_t)txfifoemptyen << 1) | ((uint32_t)rxfifonotemptyen << 0));
+}
+
+__INLINE void uart_isr_en_unpack(uint8_t* txdmadoneen, uint8_t* rxdmadoneen, uint8_t* breaken, uint8_t* txfifoemptyen, uint8_t* rxfifonotemptyen)
+{
+    uint32_t localVal = REG_PL_RD(UART_ISR_EN_ADDR);
+
+    *txdmadoneen = (localVal & ((uint32_t)0x00000040)) >> 6;
+    *rxdmadoneen = (localVal & ((uint32_t)0x00000020)) >> 5;
+    *breaken = (localVal & ((uint32_t)0x00000010)) >> 4;
+    *txfifoemptyen = (localVal & ((uint32_t)0x00000002)) >> 1;
+    *rxfifonotemptyen = (localVal & ((uint32_t)0x00000001)) >> 0;
+}
+
+__INLINE uint8_t uart_tx_dma_done_en_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART_ISR_EN_ADDR);
+    return ((localVal & ((uint32_t)0x00000040)) >> 6);
+}
+
+__INLINE void uart_tx_dma_done_en_setf(uint8_t txdmadoneen)
+{
+    ASSERT_ERR((((uint32_t)txdmadoneen << 6) & ~((uint32_t)0x00000040)) == 0);
+    REG_PL_WR(UART_ISR_EN_ADDR, (REG_PL_RD(UART_ISR_EN_ADDR) & ~((uint32_t)0x00000040)) | ((uint32_t)txdmadoneen << 6));
+}
+
+__INLINE uint8_t uart_rx_dma_done_en_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART_ISR_EN_ADDR);
+    return ((localVal & ((uint32_t)0x00000020)) >> 5);
+}
+
+__INLINE void uart_rx_dma_done_en_setf(uint8_t rxdmadoneen)
+{
+    ASSERT_ERR((((uint32_t)rxdmadoneen << 5) & ~((uint32_t)0x00000020)) == 0);
+    REG_PL_WR(UART_ISR_EN_ADDR, (REG_PL_RD(UART_ISR_EN_ADDR) & ~((uint32_t)0x00000020)) | ((uint32_t)rxdmadoneen << 5));
+}
+
+__INLINE uint8_t uart_break_en_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART_ISR_EN_ADDR);
+    return ((localVal & ((uint32_t)0x00000010)) >> 4);
+}
+
+__INLINE void uart_break_en_setf(uint8_t breaken)
+{
+    ASSERT_ERR((((uint32_t)breaken << 4) & ~((uint32_t)0x00000010)) == 0);
+    REG_PL_WR(UART_ISR_EN_ADDR, (REG_PL_RD(UART_ISR_EN_ADDR) & ~((uint32_t)0x00000010)) | ((uint32_t)breaken << 4));
+}
+
+__INLINE uint8_t uart_tx_fifo_empty_en_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART_ISR_EN_ADDR);
+    return ((localVal & ((uint32_t)0x00000002)) >> 1);
+}
+
+__INLINE void uart_tx_fifo_empty_en_setf(uint8_t txfifoemptyen)
+{
+    ASSERT_ERR((((uint32_t)txfifoemptyen << 1) & ~((uint32_t)0x00000002)) == 0);
+    REG_PL_WR(UART_ISR_EN_ADDR, (REG_PL_RD(UART_ISR_EN_ADDR) & ~((uint32_t)0x00000002)) | ((uint32_t)txfifoemptyen << 1));
+}
+
+__INLINE uint8_t uart_rx_fifo_not_empty_en_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART_ISR_EN_ADDR);
+    return ((localVal & ((uint32_t)0x00000001)) >> 0);
+}
+
+__INLINE void uart_rx_fifo_not_empty_en_setf(uint8_t rxfifonotemptyen)
+{
+    ASSERT_ERR((((uint32_t)rxfifonotemptyen << 0) & ~((uint32_t)0x00000001)) == 0);
+    REG_PL_WR(UART_ISR_EN_ADDR, (REG_PL_RD(UART_ISR_EN_ADDR) & ~((uint32_t)0x00000001)) | ((uint32_t)rxfifonotemptyen << 0));
+}
+
+/**
+ * @brief ISR_CLR register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     06      TX_DMA_DONE_CLR   0
+ *     05      RX_DMA_DONE_CLR   0
+ *     04            BREAK_CLR   0
+ *     01    TX_FIFO_EMPTY_CLR   0
+ *     00   RX_FIFO_NOT_EMPTY_CLR   0
+ * </pre>
+ */
+#define UART_ISR_CLR_ADDR   0x10007014
+#define UART_ISR_CLR_OFFSET 0x00000014
+#define UART_ISR_CLR_INDEX  0x00000005
+#define UART_ISR_CLR_RESET  0x00000000
+
+__INLINE void uart_isr_clr_set(uint32_t value)
+{
+    REG_PL_WR(UART_ISR_CLR_ADDR, value);
+}
+
+// field definitions
+#define UART_TX_DMA_DONE_CLR_BIT          ((uint32_t)0x00000040)
+#define UART_TX_DMA_DONE_CLR_POS          6
+#define UART_RX_DMA_DONE_CLR_BIT          ((uint32_t)0x00000020)
+#define UART_RX_DMA_DONE_CLR_POS          5
+#define UART_BREAK_CLR_BIT                ((uint32_t)0x00000010)
+#define UART_BREAK_CLR_POS                4
+#define UART_TX_FIFO_EMPTY_CLR_BIT        ((uint32_t)0x00000002)
+#define UART_TX_FIFO_EMPTY_CLR_POS        1
+#define UART_RX_FIFO_NOT_EMPTY_CLR_BIT    ((uint32_t)0x00000001)
+#define UART_RX_FIFO_NOT_EMPTY_CLR_POS    0
+
+#define UART_TX_DMA_DONE_CLR_RST          0x0
+#define UART_RX_DMA_DONE_CLR_RST          0x0
+#define UART_BREAK_CLR_RST                0x0
+#define UART_TX_FIFO_EMPTY_CLR_RST        0x0
+#define UART_RX_FIFO_NOT_EMPTY_CLR_RST    0x0
+
+__INLINE void uart_isr_clr_pack(uint8_t txdmadoneclr, uint8_t rxdmadoneclr, uint8_t breakclr, uint8_t txfifoemptyclr, uint8_t rxfifonotemptyclr)
+{
+    ASSERT_ERR((((uint32_t)txdmadoneclr << 6) & ~((uint32_t)0x00000040)) == 0);
+    ASSERT_ERR((((uint32_t)rxdmadoneclr << 5) & ~((uint32_t)0x00000020)) == 0);
+    ASSERT_ERR((((uint32_t)breakclr << 4) & ~((uint32_t)0x00000010)) == 0);
+    ASSERT_ERR((((uint32_t)txfifoemptyclr << 1) & ~((uint32_t)0x00000002)) == 0);
+    ASSERT_ERR((((uint32_t)rxfifonotemptyclr << 0) & ~((uint32_t)0x00000001)) == 0);
+    REG_PL_WR(UART_ISR_CLR_ADDR,  ((uint32_t)txdmadoneclr << 6) | ((uint32_t)rxdmadoneclr << 5) | ((uint32_t)breakclr << 4) | ((uint32_t)txfifoemptyclr << 1) | ((uint32_t)rxfifonotemptyclr << 0));
+}
+
+__INLINE void uart_tx_dma_done_clr_setf(uint8_t txdmadoneclr)
+{
+    ASSERT_ERR((((uint32_t)txdmadoneclr << 6) & ~((uint32_t)0x00000040)) == 0);
+    REG_PL_WR(UART_ISR_CLR_ADDR, (REG_PL_RD(UART_ISR_CLR_ADDR) & ~((uint32_t)0x00000040)) | ((uint32_t)txdmadoneclr << 6));
+}
+
+__INLINE void uart_rx_dma_done_clr_setf(uint8_t rxdmadoneclr)
+{
+    ASSERT_ERR((((uint32_t)rxdmadoneclr << 5) & ~((uint32_t)0x00000020)) == 0);
+    REG_PL_WR(UART_ISR_CLR_ADDR, (REG_PL_RD(UART_ISR_CLR_ADDR) & ~((uint32_t)0x00000020)) | ((uint32_t)rxdmadoneclr << 5));
+}
+
+__INLINE void uart_break_clr_setf(uint8_t breakclr)
+{
+    ASSERT_ERR((((uint32_t)breakclr << 4) & ~((uint32_t)0x00000010)) == 0);
+    REG_PL_WR(UART_ISR_CLR_ADDR, (REG_PL_RD(UART_ISR_CLR_ADDR) & ~((uint32_t)0x00000010)) | ((uint32_t)breakclr << 4));
+}
+
+__INLINE void uart_tx_fifo_empty_clr_setf(uint8_t txfifoemptyclr)
+{
+    ASSERT_ERR((((uint32_t)txfifoemptyclr << 1) & ~((uint32_t)0x00000002)) == 0);
+    REG_PL_WR(UART_ISR_CLR_ADDR, (REG_PL_RD(UART_ISR_CLR_ADDR) & ~((uint32_t)0x00000002)) | ((uint32_t)txfifoemptyclr << 1));
+}
+
+__INLINE void uart_rx_fifo_not_empty_clr_setf(uint8_t rxfifonotemptyclr)
+{
+    ASSERT_ERR((((uint32_t)rxfifonotemptyclr << 0) & ~((uint32_t)0x00000001)) == 0);
+    REG_PL_WR(UART_ISR_CLR_ADDR, (REG_PL_RD(UART_ISR_CLR_ADDR) & ~((uint32_t)0x00000001)) | ((uint32_t)rxfifonotemptyclr << 0));
+}
+
+/**
+ * @brief RX_DMA register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00               RX_PTR   0x0
+ * </pre>
+ */
+#define UART_RX_DMA_ADDR   0x10007018
+#define UART_RX_DMA_OFFSET 0x00000018
+#define UART_RX_DMA_INDEX  0x00000006
+#define UART_RX_DMA_RESET  0x00000000
+
+__INLINE uint32_t uart_rx_dma_get(void)
+{
+    return REG_PL_RD(UART_RX_DMA_ADDR);
+}
+
+__INLINE void uart_rx_dma_set(uint32_t value)
+{
+    REG_PL_WR(UART_RX_DMA_ADDR, value);
+}
+
+// field definitions
+#define UART_RX_PTR_MASK   ((uint32_t)0xFFFFFFFF)
+#define UART_RX_PTR_LSB    0
+#define UART_RX_PTR_WIDTH  ((uint32_t)0x00000020)
+
+#define UART_RX_PTR_RST    0x0
+
+__INLINE uint32_t uart_rx_ptr_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART_RX_DMA_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void uart_rx_ptr_setf(uint32_t rxptr)
+{
+    ASSERT_ERR((((uint32_t)rxptr << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
+    REG_PL_WR(UART_RX_DMA_ADDR, (uint32_t)rxptr << 0);
+}
+
+/**
+ * @brief TX_DMA register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00               TX_PTR   0x0
+ * </pre>
+ */
+#define UART_TX_DMA_ADDR   0x1000701C
+#define UART_TX_DMA_OFFSET 0x0000001C
+#define UART_TX_DMA_INDEX  0x00000007
+#define UART_TX_DMA_RESET  0x00000000
+
+__INLINE uint32_t uart_tx_dma_get(void)
+{
+    return REG_PL_RD(UART_TX_DMA_ADDR);
+}
+
+__INLINE void uart_tx_dma_set(uint32_t value)
+{
+    REG_PL_WR(UART_TX_DMA_ADDR, value);
+}
+
+// field definitions
+#define UART_TX_PTR_MASK   ((uint32_t)0xFFFFFFFF)
+#define UART_TX_PTR_LSB    0
+#define UART_TX_PTR_WIDTH  ((uint32_t)0x00000020)
+
+#define UART_TX_PTR_RST    0x0
+
+__INLINE uint32_t uart_tx_ptr_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART_TX_DMA_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void uart_tx_ptr_setf(uint32_t txptr)
+{
+    ASSERT_ERR((((uint32_t)txptr << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
+    REG_PL_WR(UART_TX_DMA_ADDR, (uint32_t)txptr << 0);
+}
+
+/**
+ * @brief DMA_CTRL register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     31             TX_START   0
+ *  28:16              TX_SIZE   0x0
+ *     15             RX_START   0
+ *  12:00              RX_SIZE   0x0
+ * </pre>
+ */
+#define UART_DMA_CTRL_ADDR   0x10007020
+#define UART_DMA_CTRL_OFFSET 0x00000020
+#define UART_DMA_CTRL_INDEX  0x00000008
+#define UART_DMA_CTRL_RESET  0x00000000
+
+__INLINE uint32_t uart_dma_ctrl_get(void)
+{
+    return REG_PL_RD(UART_DMA_CTRL_ADDR);
+}
+
+__INLINE void uart_dma_ctrl_set(uint32_t value)
+{
+    REG_PL_WR(UART_DMA_CTRL_ADDR, value);
+}
+
+// field definitions
+#define UART_TX_START_BIT    ((uint32_t)0x80000000)
+#define UART_TX_START_POS    31
+#define UART_TX_SIZE_MASK    ((uint32_t)0x1FFF0000)
+#define UART_TX_SIZE_LSB     16
+#define UART_TX_SIZE_WIDTH   ((uint32_t)0x0000000D)
+#define UART_RX_START_BIT    ((uint32_t)0x00008000)
+#define UART_RX_START_POS    15
+#define UART_RX_SIZE_MASK    ((uint32_t)0x00001FFF)
+#define UART_RX_SIZE_LSB     0
+#define UART_RX_SIZE_WIDTH   ((uint32_t)0x0000000D)
+
+#define UART_TX_START_RST    0x0
+#define UART_TX_SIZE_RST     0x0
+#define UART_RX_START_RST    0x0
+#define UART_RX_SIZE_RST     0x0
+
+__INLINE void uart_dma_ctrl_pack(uint8_t txstart, uint16_t txsize, uint8_t rxstart, uint16_t rxsize)
+{
+    ASSERT_ERR((((uint32_t)txstart << 31) & ~((uint32_t)0x80000000)) == 0);
+    ASSERT_ERR((((uint32_t)txsize << 16) & ~((uint32_t)0x1FFF0000)) == 0);
+    ASSERT_ERR((((uint32_t)rxstart << 15) & ~((uint32_t)0x00008000)) == 0);
+    ASSERT_ERR((((uint32_t)rxsize << 0) & ~((uint32_t)0x00001FFF)) == 0);
+    REG_PL_WR(UART_DMA_CTRL_ADDR,  ((uint32_t)txstart << 31) | ((uint32_t)txsize << 16) | ((uint32_t)rxstart << 15) | ((uint32_t)rxsize << 0));
+}
+
+__INLINE void uart_dma_ctrl_unpack(uint8_t* txstart, uint16_t* txsize, uint8_t* rxstart, uint16_t* rxsize)
+{
+    uint32_t localVal = REG_PL_RD(UART_DMA_CTRL_ADDR);
+
+    *txstart = (localVal & ((uint32_t)0x80000000)) >> 31;
+    *txsize = (localVal & ((uint32_t)0x1FFF0000)) >> 16;
+    *rxstart = (localVal & ((uint32_t)0x00008000)) >> 15;
+    *rxsize = (localVal & ((uint32_t)0x00001FFF)) >> 0;
+}
+
+__INLINE void uart_tx_start_setf(uint8_t txstart)
+{
+    ASSERT_ERR((((uint32_t)txstart << 31) & ~((uint32_t)0x80000000)) == 0);
+    REG_PL_WR(UART_DMA_CTRL_ADDR, (REG_PL_RD(UART_DMA_CTRL_ADDR) & ~((uint32_t)0x80000000)) | ((uint32_t)txstart << 31));
+}
+
+__INLINE uint16_t uart_tx_size_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART_DMA_CTRL_ADDR);
+    return ((localVal & ((uint32_t)0x1FFF0000)) >> 16);
+}
+
+__INLINE void uart_tx_size_setf(uint16_t txsize)
+{
+    ASSERT_ERR((((uint32_t)txsize << 16) & ~((uint32_t)0x1FFF0000)) == 0);
+    REG_PL_WR(UART_DMA_CTRL_ADDR, (REG_PL_RD(UART_DMA_CTRL_ADDR) & ~((uint32_t)0x1FFF0000)) | ((uint32_t)txsize << 16));
+}
+
+__INLINE void uart_rx_start_setf(uint8_t rxstart)
+{
+    ASSERT_ERR((((uint32_t)rxstart << 15) & ~((uint32_t)0x00008000)) == 0);
+    REG_PL_WR(UART_DMA_CTRL_ADDR, (REG_PL_RD(UART_DMA_CTRL_ADDR) & ~((uint32_t)0x00008000)) | ((uint32_t)rxstart << 15));
+}
+
+__INLINE uint16_t uart_rx_size_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART_DMA_CTRL_ADDR);
+    return ((localVal & ((uint32_t)0x00001FFF)) >> 0);
+}
+
+__INLINE void uart_rx_size_setf(uint16_t rxsize)
+{
+    ASSERT_ERR((((uint32_t)rxsize << 0) & ~((uint32_t)0x00001FFF)) == 0);
+    REG_PL_WR(UART_DMA_CTRL_ADDR, (REG_PL_RD(UART_DMA_CTRL_ADDR) & ~((uint32_t)0x00001FFF)) | ((uint32_t)rxsize << 0));
+}
+
+
+#endif // _REG_UART_H_
+

component/ble/plf/refip/src/build/ble-full/reg/fw/reg_uart2.h

@@ -0,0 +1,774 @@
+#ifndef _REG_UART2_H_
+#define _REG_UART2_H_
+
+#include <stdint.h>
+#include "_reg_uart2.h"
+#include "compiler.h"
+#include "arch.h"
+#include "reg_access.h"
+
+#define REG_UART2_COUNT 9
+
+#define REG_UART2_DECODING_MASK 0x0000003F
+
+/**
+ * @brief CTRL register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:24        CLK_DIV_FRACP   0x0
+ *  23:16         CLK_DIV_INTP   0x0
+ *  15:08              CNT_VAL   0x0
+ *     04            CNT_START   0
+ *     01        EXT_WAKEUP_EN   0
+ *     00            FORCE_RTS   0
+ * </pre>
+ */
+#define UART2_CTRL_ADDR   0x10008000
+#define UART2_CTRL_OFFSET 0x00000000
+#define UART2_CTRL_INDEX  0x00000000
+#define UART2_CTRL_RESET  0x00000000
+
+__INLINE uint32_t uart2_ctrl_get(void)
+{
+    return REG_PL_RD(UART2_CTRL_ADDR);
+}
+
+__INLINE void uart2_ctrl_set(uint32_t value)
+{
+    REG_PL_WR(UART2_CTRL_ADDR, value);
+}
+
+// field definitions
+#define UART2_CLK_DIV_FRACP_MASK   ((uint32_t)0xFF000000)
+#define UART2_CLK_DIV_FRACP_LSB    24
+#define UART2_CLK_DIV_FRACP_WIDTH  ((uint32_t)0x00000008)
+#define UART2_CLK_DIV_INTP_MASK    ((uint32_t)0x00FF0000)
+#define UART2_CLK_DIV_INTP_LSB     16
+#define UART2_CLK_DIV_INTP_WIDTH   ((uint32_t)0x00000008)
+#define UART2_CNT_VAL_MASK         ((uint32_t)0x0000FF00)
+#define UART2_CNT_VAL_LSB          8
+#define UART2_CNT_VAL_WIDTH        ((uint32_t)0x00000008)
+#define UART2_CNT_START_BIT        ((uint32_t)0x00000010)
+#define UART2_CNT_START_POS        4
+#define UART2_EXT_WAKEUP_EN_BIT    ((uint32_t)0x00000002)
+#define UART2_EXT_WAKEUP_EN_POS    1
+#define UART2_FORCE_RTS_BIT        ((uint32_t)0x00000001)
+#define UART2_FORCE_RTS_POS        0
+
+#define UART2_CLK_DIV_FRACP_RST    0x0
+#define UART2_CLK_DIV_INTP_RST     0x0
+#define UART2_CNT_VAL_RST          0x0
+#define UART2_CNT_START_RST        0x0
+#define UART2_EXT_WAKEUP_EN_RST    0x0
+#define UART2_FORCE_RTS_RST        0x0
+
+__INLINE void uart2_ctrl_pack(uint8_t clkdivfracp, uint8_t clkdivintp, uint8_t cntval, uint8_t cntstart, uint8_t extwakeupen, uint8_t forcerts)
+{
+    ASSERT_ERR((((uint32_t)clkdivfracp << 24) & ~((uint32_t)0xFF000000)) == 0);
+    ASSERT_ERR((((uint32_t)clkdivintp << 16) & ~((uint32_t)0x00FF0000)) == 0);
+    ASSERT_ERR((((uint32_t)cntval << 8) & ~((uint32_t)0x0000FF00)) == 0);
+    ASSERT_ERR((((uint32_t)cntstart << 4) & ~((uint32_t)0x00000010)) == 0);
+    ASSERT_ERR((((uint32_t)extwakeupen << 1) & ~((uint32_t)0x00000002)) == 0);
+    ASSERT_ERR((((uint32_t)forcerts << 0) & ~((uint32_t)0x00000001)) == 0);
+    REG_PL_WR(UART2_CTRL_ADDR,  ((uint32_t)clkdivfracp << 24) | ((uint32_t)clkdivintp << 16) | ((uint32_t)cntval << 8) | ((uint32_t)cntstart << 4) | ((uint32_t)extwakeupen << 1) | ((uint32_t)forcerts << 0));
+}
+
+__INLINE void uart2_ctrl_unpack(uint8_t* clkdivfracp, uint8_t* clkdivintp, uint8_t* cntval, uint8_t* cntstart, uint8_t* extwakeupen, uint8_t* forcerts)
+{
+    uint32_t localVal = REG_PL_RD(UART2_CTRL_ADDR);
+
+    *clkdivfracp = (localVal & ((uint32_t)0xFF000000)) >> 24;
+    *clkdivintp = (localVal & ((uint32_t)0x00FF0000)) >> 16;
+    *cntval = (localVal & ((uint32_t)0x0000FF00)) >> 8;
+    *cntstart = (localVal & ((uint32_t)0x00000010)) >> 4;
+    *extwakeupen = (localVal & ((uint32_t)0x00000002)) >> 1;
+    *forcerts = (localVal & ((uint32_t)0x00000001)) >> 0;
+}
+
+__INLINE uint8_t uart2_clk_div_fracp_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART2_CTRL_ADDR);
+    return ((localVal & ((uint32_t)0xFF000000)) >> 24);
+}
+
+__INLINE void uart2_clk_div_fracp_setf(uint8_t clkdivfracp)
+{
+    ASSERT_ERR((((uint32_t)clkdivfracp << 24) & ~((uint32_t)0xFF000000)) == 0);
+    REG_PL_WR(UART2_CTRL_ADDR, (REG_PL_RD(UART2_CTRL_ADDR) & ~((uint32_t)0xFF000000)) | ((uint32_t)clkdivfracp << 24));
+}
+
+__INLINE uint8_t uart2_clk_div_intp_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART2_CTRL_ADDR);
+    return ((localVal & ((uint32_t)0x00FF0000)) >> 16);
+}
+
+__INLINE void uart2_clk_div_intp_setf(uint8_t clkdivintp)
+{
+    ASSERT_ERR((((uint32_t)clkdivintp << 16) & ~((uint32_t)0x00FF0000)) == 0);
+    REG_PL_WR(UART2_CTRL_ADDR, (REG_PL_RD(UART2_CTRL_ADDR) & ~((uint32_t)0x00FF0000)) | ((uint32_t)clkdivintp << 16));
+}
+
+__INLINE uint8_t uart2_cnt_val_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART2_CTRL_ADDR);
+    return ((localVal & ((uint32_t)0x0000FF00)) >> 8);
+}
+
+__INLINE void uart2_cnt_val_setf(uint8_t cntval)
+{
+    ASSERT_ERR((((uint32_t)cntval << 8) & ~((uint32_t)0x0000FF00)) == 0);
+    REG_PL_WR(UART2_CTRL_ADDR, (REG_PL_RD(UART2_CTRL_ADDR) & ~((uint32_t)0x0000FF00)) | ((uint32_t)cntval << 8));
+}
+
+__INLINE void uart2_cnt_start_setf(uint8_t cntstart)
+{
+    ASSERT_ERR((((uint32_t)cntstart << 4) & ~((uint32_t)0x00000010)) == 0);
+    REG_PL_WR(UART2_CTRL_ADDR, (REG_PL_RD(UART2_CTRL_ADDR) & ~((uint32_t)0x00000010)) | ((uint32_t)cntstart << 4));
+}
+
+__INLINE uint8_t uart2_ext_wakeup_en_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART2_CTRL_ADDR);
+    return ((localVal & ((uint32_t)0x00000002)) >> 1);
+}
+
+__INLINE void uart2_ext_wakeup_en_setf(uint8_t extwakeupen)
+{
+    ASSERT_ERR((((uint32_t)extwakeupen << 1) & ~((uint32_t)0x00000002)) == 0);
+    REG_PL_WR(UART2_CTRL_ADDR, (REG_PL_RD(UART2_CTRL_ADDR) & ~((uint32_t)0x00000002)) | ((uint32_t)extwakeupen << 1));
+}
+
+__INLINE uint8_t uart2_force_rts_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART2_CTRL_ADDR);
+    return ((localVal & ((uint32_t)0x00000001)) >> 0);
+}
+
+__INLINE void uart2_force_rts_setf(uint8_t forcerts)
+{
+    ASSERT_ERR((((uint32_t)forcerts << 0) & ~((uint32_t)0x00000001)) == 0);
+    REG_PL_WR(UART2_CTRL_ADDR, (REG_PL_RD(UART2_CTRL_ADDR) & ~((uint32_t)0x00000001)) | ((uint32_t)forcerts << 0));
+}
+
+/**
+ * @brief STAT register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     09       TX_DMA_STARTED   0
+ *     08       RX_DMA_STARTED   0
+ *     05           EXT_WAKEUP   0
+ *     04              CNT_END   0
+ *     03        TX_FIFO_EMPTY   0
+ *     02    RX_FIFO_NOT_EMPTY   0
+ *     01                  CTS   0
+ *     00                  RTS   0
+ * </pre>
+ */
+#define UART2_STAT_ADDR   0x10008004
+#define UART2_STAT_OFFSET 0x00000004
+#define UART2_STAT_INDEX  0x00000001
+#define UART2_STAT_RESET  0x00000000
+
+__INLINE uint32_t uart2_stat_get(void)
+{
+    return REG_PL_RD(UART2_STAT_ADDR);
+}
+
+// field definitions
+#define UART2_TX_DMA_STARTED_BIT       ((uint32_t)0x00000200)
+#define UART2_TX_DMA_STARTED_POS       9
+#define UART2_RX_DMA_STARTED_BIT       ((uint32_t)0x00000100)
+#define UART2_RX_DMA_STARTED_POS       8
+#define UART2_EXT_WAKEUP_BIT           ((uint32_t)0x00000020)
+#define UART2_EXT_WAKEUP_POS           5
+#define UART2_CNT_END_BIT              ((uint32_t)0x00000010)
+#define UART2_CNT_END_POS              4
+#define UART2_TX_FIFO_EMPTY_BIT        ((uint32_t)0x00000008)
+#define UART2_TX_FIFO_EMPTY_POS        3
+#define UART2_RX_FIFO_NOT_EMPTY_BIT    ((uint32_t)0x00000004)
+#define UART2_RX_FIFO_NOT_EMPTY_POS    2
+#define UART2_CTS_BIT                  ((uint32_t)0x00000002)
+#define UART2_CTS_POS                  1
+#define UART2_RTS_BIT                  ((uint32_t)0x00000001)
+#define UART2_RTS_POS                  0
+
+#define UART2_TX_DMA_STARTED_RST       0x0
+#define UART2_RX_DMA_STARTED_RST       0x0
+#define UART2_EXT_WAKEUP_RST           0x0
+#define UART2_CNT_END_RST              0x0
+#define UART2_TX_FIFO_EMPTY_RST        0x0
+#define UART2_RX_FIFO_NOT_EMPTY_RST    0x0
+#define UART2_CTS_RST                  0x0
+#define UART2_RTS_RST                  0x0
+
+__INLINE void uart2_stat_unpack(uint8_t* txdmastarted, uint8_t* rxdmastarted, uint8_t* extwakeup, uint8_t* cntend, uint8_t* txfifoempty, uint8_t* rxfifonotempty, uint8_t* cts, uint8_t* rts)
+{
+    uint32_t localVal = REG_PL_RD(UART2_STAT_ADDR);
+
+    *txdmastarted = (localVal & ((uint32_t)0x00000200)) >> 9;
+    *rxdmastarted = (localVal & ((uint32_t)0x00000100)) >> 8;
+    *extwakeup = (localVal & ((uint32_t)0x00000020)) >> 5;
+    *cntend = (localVal & ((uint32_t)0x00000010)) >> 4;
+    *txfifoempty = (localVal & ((uint32_t)0x00000008)) >> 3;
+    *rxfifonotempty = (localVal & ((uint32_t)0x00000004)) >> 2;
+    *cts = (localVal & ((uint32_t)0x00000002)) >> 1;
+    *rts = (localVal & ((uint32_t)0x00000001)) >> 0;
+}
+
+__INLINE uint8_t uart2_tx_dma_started_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART2_STAT_ADDR);
+    return ((localVal & ((uint32_t)0x00000200)) >> 9);
+}
+
+__INLINE uint8_t uart2_rx_dma_started_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART2_STAT_ADDR);
+    return ((localVal & ((uint32_t)0x00000100)) >> 8);
+}
+
+__INLINE uint8_t uart2_ext_wakeup_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART2_STAT_ADDR);
+    return ((localVal & ((uint32_t)0x00000020)) >> 5);
+}
+
+__INLINE uint8_t uart2_cnt_end_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART2_STAT_ADDR);
+    return ((localVal & ((uint32_t)0x00000010)) >> 4);
+}
+
+__INLINE uint8_t uart2_tx_fifo_empty_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART2_STAT_ADDR);
+    return ((localVal & ((uint32_t)0x00000008)) >> 3);
+}
+
+__INLINE uint8_t uart2_rx_fifo_not_empty_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART2_STAT_ADDR);
+    return ((localVal & ((uint32_t)0x00000004)) >> 2);
+}
+
+__INLINE uint8_t uart2_cts_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART2_STAT_ADDR);
+    return ((localVal & ((uint32_t)0x00000002)) >> 1);
+}
+
+__INLINE uint8_t uart2_rts_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART2_STAT_ADDR);
+    return ((localVal & ((uint32_t)0x00000001)) >> 0);
+}
+
+/**
+ * @brief CLK register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00                 FREQ   0x0
+ * </pre>
+ */
+#define UART2_CLK_ADDR   0x10008008
+#define UART2_CLK_OFFSET 0x00000008
+#define UART2_CLK_INDEX  0x00000002
+#define UART2_CLK_RESET  0x00000000
+
+__INLINE uint32_t uart2_clk_get(void)
+{
+    return REG_PL_RD(UART2_CLK_ADDR);
+}
+
+// field definitions
+#define UART2_FREQ_MASK   ((uint32_t)0xFFFFFFFF)
+#define UART2_FREQ_LSB    0
+#define UART2_FREQ_WIDTH  ((uint32_t)0x00000020)
+
+#define UART2_FREQ_RST    0x0
+
+__INLINE uint32_t uart2_freq_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART2_CLK_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+/**
+ * @brief ISR_STAT register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     06          TX_DMA_DONE   0
+ *     05          RX_DMA_DONE   0
+ *     04            BREAK_ISR   0
+ *     01    TX_FIFO_EMPTY_ISR   0
+ *     00   RX_FIFO_NOT_EMPTY_ISR   0
+ * </pre>
+ */
+#define UART2_ISR_STAT_ADDR   0x1000800C
+#define UART2_ISR_STAT_OFFSET 0x0000000C
+#define UART2_ISR_STAT_INDEX  0x00000003
+#define UART2_ISR_STAT_RESET  0x00000000
+
+__INLINE uint32_t uart2_isr_stat_get(void)
+{
+    return REG_PL_RD(UART2_ISR_STAT_ADDR);
+}
+
+// field definitions
+#define UART2_TX_DMA_DONE_BIT              ((uint32_t)0x00000040)
+#define UART2_TX_DMA_DONE_POS              6
+#define UART2_RX_DMA_DONE_BIT              ((uint32_t)0x00000020)
+#define UART2_RX_DMA_DONE_POS              5
+#define UART2_BREAK_ISR_BIT                ((uint32_t)0x00000010)
+#define UART2_BREAK_ISR_POS                4
+#define UART2_TX_FIFO_EMPTY_ISR_BIT        ((uint32_t)0x00000002)
+#define UART2_TX_FIFO_EMPTY_ISR_POS        1
+#define UART2_RX_FIFO_NOT_EMPTY_ISR_BIT    ((uint32_t)0x00000001)
+#define UART2_RX_FIFO_NOT_EMPTY_ISR_POS    0
+
+#define UART2_TX_DMA_DONE_RST              0x0
+#define UART2_RX_DMA_DONE_RST              0x0
+#define UART2_BREAK_ISR_RST                0x0
+#define UART2_TX_FIFO_EMPTY_ISR_RST        0x0
+#define UART2_RX_FIFO_NOT_EMPTY_ISR_RST    0x0
+
+__INLINE void uart2_isr_stat_unpack(uint8_t* txdmadone, uint8_t* rxdmadone, uint8_t* breakisr, uint8_t* txfifoemptyisr, uint8_t* rxfifonotemptyisr)
+{
+    uint32_t localVal = REG_PL_RD(UART2_ISR_STAT_ADDR);
+
+    *txdmadone = (localVal & ((uint32_t)0x00000040)) >> 6;
+    *rxdmadone = (localVal & ((uint32_t)0x00000020)) >> 5;
+    *breakisr = (localVal & ((uint32_t)0x00000010)) >> 4;
+    *txfifoemptyisr = (localVal & ((uint32_t)0x00000002)) >> 1;
+    *rxfifonotemptyisr = (localVal & ((uint32_t)0x00000001)) >> 0;
+}
+
+__INLINE uint8_t uart2_tx_dma_done_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART2_ISR_STAT_ADDR);
+    return ((localVal & ((uint32_t)0x00000040)) >> 6);
+}
+
+__INLINE uint8_t uart2_rx_dma_done_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART2_ISR_STAT_ADDR);
+    return ((localVal & ((uint32_t)0x00000020)) >> 5);
+}
+
+__INLINE uint8_t uart2_break_isr_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART2_ISR_STAT_ADDR);
+    return ((localVal & ((uint32_t)0x00000010)) >> 4);
+}
+
+__INLINE uint8_t uart2_tx_fifo_empty_isr_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART2_ISR_STAT_ADDR);
+    return ((localVal & ((uint32_t)0x00000002)) >> 1);
+}
+
+__INLINE uint8_t uart2_rx_fifo_not_empty_isr_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART2_ISR_STAT_ADDR);
+    return ((localVal & ((uint32_t)0x00000001)) >> 0);
+}
+
+/**
+ * @brief ISR_EN register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     06       TX_DMA_DONE_EN   0
+ *     05       RX_DMA_DONE_EN   0
+ *     04             BREAK_EN   0
+ *     01     TX_FIFO_EMPTY_EN   0
+ *     00   RX_FIFO_NOT_EMPTY_EN   0
+ * </pre>
+ */
+#define UART2_ISR_EN_ADDR   0x10008010
+#define UART2_ISR_EN_OFFSET 0x00000010
+#define UART2_ISR_EN_INDEX  0x00000004
+#define UART2_ISR_EN_RESET  0x00000000
+
+__INLINE uint32_t uart2_isr_en_get(void)
+{
+    return REG_PL_RD(UART2_ISR_EN_ADDR);
+}
+
+__INLINE void uart2_isr_en_set(uint32_t value)
+{
+    REG_PL_WR(UART2_ISR_EN_ADDR, value);
+}
+
+// field definitions
+#define UART2_TX_DMA_DONE_EN_BIT          ((uint32_t)0x00000040)
+#define UART2_TX_DMA_DONE_EN_POS          6
+#define UART2_RX_DMA_DONE_EN_BIT          ((uint32_t)0x00000020)
+#define UART2_RX_DMA_DONE_EN_POS          5
+#define UART2_BREAK_EN_BIT                ((uint32_t)0x00000010)
+#define UART2_BREAK_EN_POS                4
+#define UART2_TX_FIFO_EMPTY_EN_BIT        ((uint32_t)0x00000002)
+#define UART2_TX_FIFO_EMPTY_EN_POS        1
+#define UART2_RX_FIFO_NOT_EMPTY_EN_BIT    ((uint32_t)0x00000001)
+#define UART2_RX_FIFO_NOT_EMPTY_EN_POS    0
+
+#define UART2_TX_DMA_DONE_EN_RST          0x0
+#define UART2_RX_DMA_DONE_EN_RST          0x0
+#define UART2_BREAK_EN_RST                0x0
+#define UART2_TX_FIFO_EMPTY_EN_RST        0x0
+#define UART2_RX_FIFO_NOT_EMPTY_EN_RST    0x0
+
+__INLINE void uart2_isr_en_pack(uint8_t txdmadoneen, uint8_t rxdmadoneen, uint8_t breaken, uint8_t txfifoemptyen, uint8_t rxfifonotemptyen)
+{
+    ASSERT_ERR((((uint32_t)txdmadoneen << 6) & ~((uint32_t)0x00000040)) == 0);
+    ASSERT_ERR((((uint32_t)rxdmadoneen << 5) & ~((uint32_t)0x00000020)) == 0);
+    ASSERT_ERR((((uint32_t)breaken << 4) & ~((uint32_t)0x00000010)) == 0);
+    ASSERT_ERR((((uint32_t)txfifoemptyen << 1) & ~((uint32_t)0x00000002)) == 0);
+    ASSERT_ERR((((uint32_t)rxfifonotemptyen << 0) & ~((uint32_t)0x00000001)) == 0);
+    REG_PL_WR(UART2_ISR_EN_ADDR,  ((uint32_t)txdmadoneen << 6) | ((uint32_t)rxdmadoneen << 5) | ((uint32_t)breaken << 4) | ((uint32_t)txfifoemptyen << 1) | ((uint32_t)rxfifonotemptyen << 0));
+}
+
+__INLINE void uart2_isr_en_unpack(uint8_t* txdmadoneen, uint8_t* rxdmadoneen, uint8_t* breaken, uint8_t* txfifoemptyen, uint8_t* rxfifonotemptyen)
+{
+    uint32_t localVal = REG_PL_RD(UART2_ISR_EN_ADDR);
+
+    *txdmadoneen = (localVal & ((uint32_t)0x00000040)) >> 6;
+    *rxdmadoneen = (localVal & ((uint32_t)0x00000020)) >> 5;
+    *breaken = (localVal & ((uint32_t)0x00000010)) >> 4;
+    *txfifoemptyen = (localVal & ((uint32_t)0x00000002)) >> 1;
+    *rxfifonotemptyen = (localVal & ((uint32_t)0x00000001)) >> 0;
+}
+
+__INLINE uint8_t uart2_tx_dma_done_en_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART2_ISR_EN_ADDR);
+    return ((localVal & ((uint32_t)0x00000040)) >> 6);
+}
+
+__INLINE void uart2_tx_dma_done_en_setf(uint8_t txdmadoneen)
+{
+    ASSERT_ERR((((uint32_t)txdmadoneen << 6) & ~((uint32_t)0x00000040)) == 0);
+    REG_PL_WR(UART2_ISR_EN_ADDR, (REG_PL_RD(UART2_ISR_EN_ADDR) & ~((uint32_t)0x00000040)) | ((uint32_t)txdmadoneen << 6));
+}
+
+__INLINE uint8_t uart2_rx_dma_done_en_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART2_ISR_EN_ADDR);
+    return ((localVal & ((uint32_t)0x00000020)) >> 5);
+}
+
+__INLINE void uart2_rx_dma_done_en_setf(uint8_t rxdmadoneen)
+{
+    ASSERT_ERR((((uint32_t)rxdmadoneen << 5) & ~((uint32_t)0x00000020)) == 0);
+    REG_PL_WR(UART2_ISR_EN_ADDR, (REG_PL_RD(UART2_ISR_EN_ADDR) & ~((uint32_t)0x00000020)) | ((uint32_t)rxdmadoneen << 5));
+}
+
+__INLINE uint8_t uart2_break_en_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART2_ISR_EN_ADDR);
+    return ((localVal & ((uint32_t)0x00000010)) >> 4);
+}
+
+__INLINE void uart2_break_en_setf(uint8_t breaken)
+{
+    ASSERT_ERR((((uint32_t)breaken << 4) & ~((uint32_t)0x00000010)) == 0);
+    REG_PL_WR(UART2_ISR_EN_ADDR, (REG_PL_RD(UART2_ISR_EN_ADDR) & ~((uint32_t)0x00000010)) | ((uint32_t)breaken << 4));
+}
+
+__INLINE uint8_t uart2_tx_fifo_empty_en_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART2_ISR_EN_ADDR);
+    return ((localVal & ((uint32_t)0x00000002)) >> 1);
+}
+
+__INLINE void uart2_tx_fifo_empty_en_setf(uint8_t txfifoemptyen)
+{
+    ASSERT_ERR((((uint32_t)txfifoemptyen << 1) & ~((uint32_t)0x00000002)) == 0);
+    REG_PL_WR(UART2_ISR_EN_ADDR, (REG_PL_RD(UART2_ISR_EN_ADDR) & ~((uint32_t)0x00000002)) | ((uint32_t)txfifoemptyen << 1));
+}
+
+__INLINE uint8_t uart2_rx_fifo_not_empty_en_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART2_ISR_EN_ADDR);
+    return ((localVal & ((uint32_t)0x00000001)) >> 0);
+}
+
+__INLINE void uart2_rx_fifo_not_empty_en_setf(uint8_t rxfifonotemptyen)
+{
+    ASSERT_ERR((((uint32_t)rxfifonotemptyen << 0) & ~((uint32_t)0x00000001)) == 0);
+    REG_PL_WR(UART2_ISR_EN_ADDR, (REG_PL_RD(UART2_ISR_EN_ADDR) & ~((uint32_t)0x00000001)) | ((uint32_t)rxfifonotemptyen << 0));
+}
+
+/**
+ * @brief ISR_CLR register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     06      TX_DMA_DONE_CLR   0
+ *     05      RX_DMA_DONE_CLR   0
+ *     04            BREAK_CLR   0
+ *     01    TX_FIFO_EMPTY_CLR   0
+ *     00   RX_FIFO_NOT_EMPTY_CLR   0
+ * </pre>
+ */
+#define UART2_ISR_CLR_ADDR   0x10008014
+#define UART2_ISR_CLR_OFFSET 0x00000014
+#define UART2_ISR_CLR_INDEX  0x00000005
+#define UART2_ISR_CLR_RESET  0x00000000
+
+__INLINE void uart2_isr_clr_set(uint32_t value)
+{
+    REG_PL_WR(UART2_ISR_CLR_ADDR, value);
+}
+
+// field definitions
+#define UART2_TX_DMA_DONE_CLR_BIT          ((uint32_t)0x00000040)
+#define UART2_TX_DMA_DONE_CLR_POS          6
+#define UART2_RX_DMA_DONE_CLR_BIT          ((uint32_t)0x00000020)
+#define UART2_RX_DMA_DONE_CLR_POS          5
+#define UART2_BREAK_CLR_BIT                ((uint32_t)0x00000010)
+#define UART2_BREAK_CLR_POS                4
+#define UART2_TX_FIFO_EMPTY_CLR_BIT        ((uint32_t)0x00000002)
+#define UART2_TX_FIFO_EMPTY_CLR_POS        1
+#define UART2_RX_FIFO_NOT_EMPTY_CLR_BIT    ((uint32_t)0x00000001)
+#define UART2_RX_FIFO_NOT_EMPTY_CLR_POS    0
+
+#define UART2_TX_DMA_DONE_CLR_RST          0x0
+#define UART2_RX_DMA_DONE_CLR_RST          0x0
+#define UART2_BREAK_CLR_RST                0x0
+#define UART2_TX_FIFO_EMPTY_CLR_RST        0x0
+#define UART2_RX_FIFO_NOT_EMPTY_CLR_RST    0x0
+
+__INLINE void uart2_isr_clr_pack(uint8_t txdmadoneclr, uint8_t rxdmadoneclr, uint8_t breakclr, uint8_t txfifoemptyclr, uint8_t rxfifonotemptyclr)
+{
+    ASSERT_ERR((((uint32_t)txdmadoneclr << 6) & ~((uint32_t)0x00000040)) == 0);
+    ASSERT_ERR((((uint32_t)rxdmadoneclr << 5) & ~((uint32_t)0x00000020)) == 0);
+    ASSERT_ERR((((uint32_t)breakclr << 4) & ~((uint32_t)0x00000010)) == 0);
+    ASSERT_ERR((((uint32_t)txfifoemptyclr << 1) & ~((uint32_t)0x00000002)) == 0);
+    ASSERT_ERR((((uint32_t)rxfifonotemptyclr << 0) & ~((uint32_t)0x00000001)) == 0);
+    REG_PL_WR(UART2_ISR_CLR_ADDR,  ((uint32_t)txdmadoneclr << 6) | ((uint32_t)rxdmadoneclr << 5) | ((uint32_t)breakclr << 4) | ((uint32_t)txfifoemptyclr << 1) | ((uint32_t)rxfifonotemptyclr << 0));
+}
+
+__INLINE void uart2_tx_dma_done_clr_setf(uint8_t txdmadoneclr)
+{
+    ASSERT_ERR((((uint32_t)txdmadoneclr << 6) & ~((uint32_t)0x00000040)) == 0);
+    REG_PL_WR(UART2_ISR_CLR_ADDR, (REG_PL_RD(UART2_ISR_CLR_ADDR) & ~((uint32_t)0x00000040)) | ((uint32_t)txdmadoneclr << 6));
+}
+
+__INLINE void uart2_rx_dma_done_clr_setf(uint8_t rxdmadoneclr)
+{
+    ASSERT_ERR((((uint32_t)rxdmadoneclr << 5) & ~((uint32_t)0x00000020)) == 0);
+    REG_PL_WR(UART2_ISR_CLR_ADDR, (REG_PL_RD(UART2_ISR_CLR_ADDR) & ~((uint32_t)0x00000020)) | ((uint32_t)rxdmadoneclr << 5));
+}
+
+__INLINE void uart2_break_clr_setf(uint8_t breakclr)
+{
+    ASSERT_ERR((((uint32_t)breakclr << 4) & ~((uint32_t)0x00000010)) == 0);
+    REG_PL_WR(UART2_ISR_CLR_ADDR, (REG_PL_RD(UART2_ISR_CLR_ADDR) & ~((uint32_t)0x00000010)) | ((uint32_t)breakclr << 4));
+}
+
+__INLINE void uart2_tx_fifo_empty_clr_setf(uint8_t txfifoemptyclr)
+{
+    ASSERT_ERR((((uint32_t)txfifoemptyclr << 1) & ~((uint32_t)0x00000002)) == 0);
+    REG_PL_WR(UART2_ISR_CLR_ADDR, (REG_PL_RD(UART2_ISR_CLR_ADDR) & ~((uint32_t)0x00000002)) | ((uint32_t)txfifoemptyclr << 1));
+}
+
+__INLINE void uart2_rx_fifo_not_empty_clr_setf(uint8_t rxfifonotemptyclr)
+{
+    ASSERT_ERR((((uint32_t)rxfifonotemptyclr << 0) & ~((uint32_t)0x00000001)) == 0);
+    REG_PL_WR(UART2_ISR_CLR_ADDR, (REG_PL_RD(UART2_ISR_CLR_ADDR) & ~((uint32_t)0x00000001)) | ((uint32_t)rxfifonotemptyclr << 0));
+}
+
+/**
+ * @brief RX_DMA register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00               RX_PTR   0x0
+ * </pre>
+ */
+#define UART2_RX_DMA_ADDR   0x10008018
+#define UART2_RX_DMA_OFFSET 0x00000018
+#define UART2_RX_DMA_INDEX  0x00000006
+#define UART2_RX_DMA_RESET  0x00000000
+
+__INLINE uint32_t uart2_rx_dma_get(void)
+{
+    return REG_PL_RD(UART2_RX_DMA_ADDR);
+}
+
+__INLINE void uart2_rx_dma_set(uint32_t value)
+{
+    REG_PL_WR(UART2_RX_DMA_ADDR, value);
+}
+
+// field definitions
+#define UART2_RX_PTR_MASK   ((uint32_t)0xFFFFFFFF)
+#define UART2_RX_PTR_LSB    0
+#define UART2_RX_PTR_WIDTH  ((uint32_t)0x00000020)
+
+#define UART2_RX_PTR_RST    0x0
+
+__INLINE uint32_t uart2_rx_ptr_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART2_RX_DMA_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void uart2_rx_ptr_setf(uint32_t rxptr)
+{
+    ASSERT_ERR((((uint32_t)rxptr << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
+    REG_PL_WR(UART2_RX_DMA_ADDR, (uint32_t)rxptr << 0);
+}
+
+/**
+ * @brief TX_DMA register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *  31:00               TX_PTR   0x0
+ * </pre>
+ */
+#define UART2_TX_DMA_ADDR   0x1000801C
+#define UART2_TX_DMA_OFFSET 0x0000001C
+#define UART2_TX_DMA_INDEX  0x00000007
+#define UART2_TX_DMA_RESET  0x00000000
+
+__INLINE uint32_t uart2_tx_dma_get(void)
+{
+    return REG_PL_RD(UART2_TX_DMA_ADDR);
+}
+
+__INLINE void uart2_tx_dma_set(uint32_t value)
+{
+    REG_PL_WR(UART2_TX_DMA_ADDR, value);
+}
+
+// field definitions
+#define UART2_TX_PTR_MASK   ((uint32_t)0xFFFFFFFF)
+#define UART2_TX_PTR_LSB    0
+#define UART2_TX_PTR_WIDTH  ((uint32_t)0x00000020)
+
+#define UART2_TX_PTR_RST    0x0
+
+__INLINE uint32_t uart2_tx_ptr_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART2_TX_DMA_ADDR);
+    ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
+    return (localVal >> 0);
+}
+
+__INLINE void uart2_tx_ptr_setf(uint32_t txptr)
+{
+    ASSERT_ERR((((uint32_t)txptr << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
+    REG_PL_WR(UART2_TX_DMA_ADDR, (uint32_t)txptr << 0);
+}
+
+/**
+ * @brief DMA_CTRL register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *     31             TX_START   0
+ *  28:16              TX_SIZE   0x0
+ *     15             RX_START   0
+ *  12:00              RX_SIZE   0x0
+ * </pre>
+ */
+#define UART2_DMA_CTRL_ADDR   0x10008020
+#define UART2_DMA_CTRL_OFFSET 0x00000020
+#define UART2_DMA_CTRL_INDEX  0x00000008
+#define UART2_DMA_CTRL_RESET  0x00000000
+
+__INLINE uint32_t uart2_dma_ctrl_get(void)
+{
+    return REG_PL_RD(UART2_DMA_CTRL_ADDR);
+}
+
+__INLINE void uart2_dma_ctrl_set(uint32_t value)
+{
+    REG_PL_WR(UART2_DMA_CTRL_ADDR, value);
+}
+
+// field definitions
+#define UART2_TX_START_BIT    ((uint32_t)0x80000000)
+#define UART2_TX_START_POS    31
+#define UART2_TX_SIZE_MASK    ((uint32_t)0x1FFF0000)
+#define UART2_TX_SIZE_LSB     16
+#define UART2_TX_SIZE_WIDTH   ((uint32_t)0x0000000D)
+#define UART2_RX_START_BIT    ((uint32_t)0x00008000)
+#define UART2_RX_START_POS    15
+#define UART2_RX_SIZE_MASK    ((uint32_t)0x00001FFF)
+#define UART2_RX_SIZE_LSB     0
+#define UART2_RX_SIZE_WIDTH   ((uint32_t)0x0000000D)
+
+#define UART2_TX_START_RST    0x0
+#define UART2_TX_SIZE_RST     0x0
+#define UART2_RX_START_RST    0x0
+#define UART2_RX_SIZE_RST     0x0
+
+__INLINE void uart2_dma_ctrl_pack(uint8_t txstart, uint16_t txsize, uint8_t rxstart, uint16_t rxsize)
+{
+    ASSERT_ERR((((uint32_t)txstart << 31) & ~((uint32_t)0x80000000)) == 0);
+    ASSERT_ERR((((uint32_t)txsize << 16) & ~((uint32_t)0x1FFF0000)) == 0);
+    ASSERT_ERR((((uint32_t)rxstart << 15) & ~((uint32_t)0x00008000)) == 0);
+    ASSERT_ERR((((uint32_t)rxsize << 0) & ~((uint32_t)0x00001FFF)) == 0);
+    REG_PL_WR(UART2_DMA_CTRL_ADDR,  ((uint32_t)txstart << 31) | ((uint32_t)txsize << 16) | ((uint32_t)rxstart << 15) | ((uint32_t)rxsize << 0));
+}
+
+__INLINE void uart2_dma_ctrl_unpack(uint8_t* txstart, uint16_t* txsize, uint8_t* rxstart, uint16_t* rxsize)
+{
+    uint32_t localVal = REG_PL_RD(UART2_DMA_CTRL_ADDR);
+
+    *txstart = (localVal & ((uint32_t)0x80000000)) >> 31;
+    *txsize = (localVal & ((uint32_t)0x1FFF0000)) >> 16;
+    *rxstart = (localVal & ((uint32_t)0x00008000)) >> 15;
+    *rxsize = (localVal & ((uint32_t)0x00001FFF)) >> 0;
+}
+
+__INLINE void uart2_tx_start_setf(uint8_t txstart)
+{
+    ASSERT_ERR((((uint32_t)txstart << 31) & ~((uint32_t)0x80000000)) == 0);
+    REG_PL_WR(UART2_DMA_CTRL_ADDR, (REG_PL_RD(UART2_DMA_CTRL_ADDR) & ~((uint32_t)0x80000000)) | ((uint32_t)txstart << 31));
+}
+
+__INLINE uint16_t uart2_tx_size_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART2_DMA_CTRL_ADDR);
+    return ((localVal & ((uint32_t)0x1FFF0000)) >> 16);
+}
+
+__INLINE void uart2_tx_size_setf(uint16_t txsize)
+{
+    ASSERT_ERR((((uint32_t)txsize << 16) & ~((uint32_t)0x1FFF0000)) == 0);
+    REG_PL_WR(UART2_DMA_CTRL_ADDR, (REG_PL_RD(UART2_DMA_CTRL_ADDR) & ~((uint32_t)0x1FFF0000)) | ((uint32_t)txsize << 16));
+}
+
+__INLINE void uart2_rx_start_setf(uint8_t rxstart)
+{
+    ASSERT_ERR((((uint32_t)rxstart << 15) & ~((uint32_t)0x00008000)) == 0);
+    REG_PL_WR(UART2_DMA_CTRL_ADDR, (REG_PL_RD(UART2_DMA_CTRL_ADDR) & ~((uint32_t)0x00008000)) | ((uint32_t)rxstart << 15));
+}
+
+__INLINE uint16_t uart2_rx_size_getf(void)
+{
+    uint32_t localVal = REG_PL_RD(UART2_DMA_CTRL_ADDR);
+    return ((localVal & ((uint32_t)0x00001FFF)) >> 0);
+}
+
+__INLINE void uart2_rx_size_setf(uint16_t rxsize)
+{
+    ASSERT_ERR((((uint32_t)rxsize << 0) & ~((uint32_t)0x00001FFF)) == 0);
+    REG_PL_WR(UART2_DMA_CTRL_ADDR, (REG_PL_RD(UART2_DMA_CTRL_ADDR) & ~((uint32_t)0x00001FFF)) | ((uint32_t)rxsize << 0));
+}
+
+
+#endif // _REG_UART2_H_
+

component/ble/plf/refip/src/data_path/plf_data_path.h

@@ -0,0 +1,95 @@
+/**
+ ****************************************************************************************
+ *
+ * @file dplf_ata_path.h
+ *
+ * @brief Main API file for the Link Layer platform specific Data path manager
+ *
+ * Copyright (C) RivieraWaves 2009-2019
+ *
+ ****************************************************************************************
+ */
+
+#ifndef PLF_DATA_PATH_H_
+#define PLF_DATA_PATH_H_
+
+/**
+ ****************************************************************************************
+ * @defgroup PLF_DATA_PATH Link Layer platform specific ISO data path
+ * @ingroup ROOT
+ * @brief Link Layer platform specific ISO data path
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+
+#include "rwip_config.h"
+#if (BLE_ISO_PRESENT)
+
+#include <stdbool.h>        // boolean definition
+#include <stdint.h>         // integer definition
+
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/// Isochronous Channel data path selection
+enum plf_dp_type
+{
+    // -------- VENDOR SPECIFIC --------- //
+
+    // Add vendor specific data-path number here
+
+    ISO_DP_NEW                          = 0xF1,
+};
+
+
+/*
+ * TYPE DEFINITIONS
+ ****************************************************************************************
+ */
+
+
+/*
+ * GLOBAL VARIABLE DEFINITION
+ *****************************************************************************************
+ */
+
+
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief Initialization of the BLE Data Path driver
+ *
+ * @param[in] init_type  Type of initialization (@see enum rwip_init_type)
+ ****************************************************************************************
+ */
+void plf_data_path_init(uint8_t init_type);
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve the data path interface according to the direction
+ *
+ * @param[in]  type      Type of data path interface (@see enum iso_dp_type)
+ * @param[in]  direction Data Path direction (@see enum iso_rx_tx_select)
+ *
+ * @return Pointer to the interface of the data path driver, NULL if no driver found
+ ****************************************************************************************
+ */
+const struct data_path_itf* plf_data_path_itf_get(uint8_t type, uint8_t direction);
+
+#endif // (BLE_ISO_PRESENT)
+/// @} PLF_DATA_PATH
+
+#endif // PLF_DATA_PATH_H_

component/ble/plf/refip/src/driver/flash/flash.h

@@ -0,0 +1,127 @@
+/**
+ ****************************************************************************************
+ *
+ * @file flash.h
+ *
+ * @brief Flash driver interface
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef FLASH_H_
+#define FLASH_H_
+
+#include <stdint.h>               // standard integer functions
+
+/**
+ ****************************************************************************************
+ * @addtogroup FLASH
+ * @ingroup DRIVERS
+ *
+ * @brief Flash memory driver
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+///Flash type code used to select the correct erasing and programming algorithm
+#define FLASH_TYPE_UNKNOWN             0
+#define FLASH_TYPE_INTEL_28F320C3      1
+#define FLASH_TYPE_INTEL_28F800C3      2
+#define FLASH_TYPE_NUMONYX_M25P128     3
+
+///Base address of Flash on system bus
+#define FLASH_BASE_ADDR          0x03000000
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief Initialize flash driver.
+ ****************************************************************************************
+ */
+void flash_init(void);
+
+/**
+ ****************************************************************************************
+ * @brief   Identify the flash device.
+ *
+ * This function is used to read the flash device ID.
+ * 
+ * Note: callback parameter is not used
+ *
+ * @param[out]   id          Pointer to id location
+ * @param[in]    callback    Callback for end of identification
+ * @return       status      0 if operation can start successfully
+ ****************************************************************************************
+ */
+uint8_t flash_identify(uint8_t* id, void (*callback)(void));
+
+/**
+ ****************************************************************************************
+ * @brief   Erase a flash section.
+ *
+ * This function is used to erase a part of the flash memory.
+ * 
+ * Note: callback parameter is not used
+ *
+ * @param[in]    flash_type  Flash type
+ * @param[in]    offset      Starting offset from the beginning of the flash device
+ * @param[in]    size        Size of the portion of flash to erase
+ * @param[in]    callback    Callback for end of erase
+ * @return       status      0 if operation can start successfully
+ ****************************************************************************************
+ */
+uint8_t flash_erase(uint8_t flash_type, uint32_t offset, uint32_t size, void (*callback)(void));
+
+/**
+ ****************************************************************************************
+ * @brief   Write a flash section.
+ *
+ * This function is used to write a part of the flash memory.
+ * 
+ * Note: callback parameter is not used
+ *
+ * @param[in]    flash_type  Flash type
+ * @param[in]    offset      Starting offset from the beginning of the flash device
+ * @param[in]    length      Size of the portion of flash to write
+ * @param[in]    buffer      Pointer on data to write
+ * @param[in]    callback    Callback for end of write
+ * @return       status      0 if operation can start successfully
+ ****************************************************************************************
+ */
+uint8_t flash_write(uint8_t flash_type, uint32_t offset, uint32_t length, uint8_t *buffer, void (*callback)(void));
+
+/**
+ ****************************************************************************************
+ * @brief   Read a flash section.
+ *
+ * This function is used to read a part of the flash memory.
+ * 
+ * Note: callback parameter is not used
+ *
+ * @param[in]    flash_type  Flash type
+ * @param[in]    offset      Starting offset from the beginning of the flash device
+ * @param[in]    length      Size of the portion of flash to read
+ * @param[out]   buffer      Pointer on data to read
+ * @param[in]    callback    Callback for end of read
+ * @return       status      0 if operation can start successfully
+ ****************************************************************************************
+ */
+uint8_t flash_read(uint8_t flash_type, uint32_t offset, uint32_t length, uint8_t *buffer, void (*callback)(void));
+
+
+/// @} FLASH
+
+#endif // FLASH_H_

component/ble/plf/refip/src/driver/reg/reg_access.h

@@ -0,0 +1,166 @@
+/**
+ ****************************************************************************************
+ *
+ * @file reg_access.h
+ *
+ * @brief File implementing the basic primitives for register accesses
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef REG_ACCESS_H_
+#define REG_ACCESS_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup REG REG_ACCESS
+ * @ingroup DRIVERS
+ *
+ * @brief Basic primitives for register access
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include <string.h>            // string functions
+
+#if defined(CFG_EMB)
+#include "co_utils.h"
+#include "em_map.h"       // EM Map
+#endif // defined(CFG_EMB)
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/*
+ * MACROS
+ ****************************************************************************************
+ */
+/// Macro to read a platform register
+#define REG_PL_RD(addr)              (*(volatile uint32_t *)(addr))
+
+/// Macro to write a platform register
+#define REG_PL_WR(addr, value)       (*(volatile uint32_t *)(addr)) = (value)
+
+/// Macro to read a common ip register
+#define REG_IP_RD(addr)              (*(volatile uint32_t *)(addr))
+
+/// Macro to write a common ip register
+#define REG_IP_WR(addr, value)       (*(volatile uint32_t *)(addr)) = (value)
+
+/// Macro to read a BLE register
+#define REG_BLE_RD(addr)             (*(volatile uint32_t *)(addr))
+
+/// Macro to write a BLE register
+#define REG_BLE_WR(addr, value)      (*(volatile uint32_t *)(addr)) = (value)
+
+/// Macro to read a BLE control structure field (16-bit wide)
+#define EM_BLE_RD(addr)              (*(volatile uint16_t *)(addr))
+
+/// Macro to write a BLE control structure field (16-bit wide)
+#define EM_BLE_WR(addr, value)       (*(volatile uint16_t *)(addr)) = (value)
+
+/// Macro to read a BT register
+#define REG_BT_RD(addr)              (*(volatile uint32_t *)(addr))
+
+/// Macro to write a BT register
+#define REG_BT_WR(addr, value)       (*(volatile uint32_t *)(addr)) = (value)
+
+/// Macro to read a BT control structure field (16-bit wide)
+#define EM_BT_RD(addr)               (*(volatile uint16_t *)(addr))
+
+/// Macro to write a BT control structure field (16-bit wide)
+#define EM_BT_WR(addr, value)        (*(volatile uint16_t *)(addr)) = (value)
+
+/// Macro to read a EM field (16-bit wide)
+#define EM_RD(addr)               (*(volatile uint16_t *)(addr))
+
+/// Macro to write a EM field (16-bit wide)
+#define EM_WR(addr, value)        (*(volatile uint16_t *)(addr)) = (value)
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+#if (defined(CFG_BT) || (defined(CFG_BLE) && defined(CFG_EMB)))
+/// Read bytes from EM
+__INLINE void em_rd(void *sys_addr, uint16_t em_addr, uint16_t len)
+{
+    memcpy(sys_addr, (void *)(em_addr + EM_BASE_ADDR), len);
+}
+/// Write bytes to EM
+__INLINE void em_wr(void const *sys_addr, uint16_t em_addr, uint16_t len)
+{
+    memcpy((void *)(em_addr + EM_BASE_ADDR), sys_addr, len);
+}
+
+// copy two exchange memory area
+__INLINE void em_cpy(uint16_t dst_em_addr, uint16_t src_em_addr, uint16_t len)
+{
+    memcpy((void *)(dst_em_addr + EM_BASE_ADDR), (void *)(src_em_addr + EM_BASE_ADDR), len);
+}
+
+/// Fill an EM space with the same value
+__INLINE void em_set(int value, uint16_t em_addr, uint16_t len)
+{
+    memset((void *)(em_addr + EM_BASE_ADDR), value, len);
+}
+
+/// Read 32-bits value from EM
+__INLINE uint32_t em_rd32p(uint16_t em_addr)
+{
+    return co_read32p((void *)(em_addr + EM_BASE_ADDR));
+}
+/// Write 32-bits value to EM
+__INLINE void em_wr32p(uint16_t em_addr, uint32_t value)
+{
+    co_write32p((void *)(em_addr + EM_BASE_ADDR), value);
+}
+
+/// Read 24-bits value from EM
+__INLINE uint32_t em_rd24p(uint16_t em_addr)
+{
+    return co_read24p((void *)(em_addr + EM_BASE_ADDR));
+}
+/// Write 24-bits value to EM
+__INLINE void em_wr24p(uint16_t em_addr, uint32_t value)
+{
+    co_write24p((void *)(em_addr + EM_BASE_ADDR), value);
+}
+
+/// Read 16-bits value from EM
+__INLINE uint16_t em_rd16p(uint16_t em_addr)
+{
+    return co_read16p((void *)(em_addr + EM_BASE_ADDR));
+}
+/// Write 16-bits value to EM
+__INLINE void em_wr16p(uint16_t em_addr, uint16_t value)
+{
+    co_write16p((void *)(em_addr + EM_BASE_ADDR), value);
+}
+
+/// Read 8-bits value from EM
+__INLINE uint8_t em_rd8p(uint16_t em_addr)
+{
+    return *((uint8_t *)(em_addr + EM_BASE_ADDR));
+}
+/// Write 8-bits value to EM
+__INLINE void em_wr8p(uint16_t em_addr, uint8_t value)
+{
+    *(uint8_t *)(em_addr + EM_BASE_ADDR) = value;
+}
+#endif // (defined(CFG_BT) || (defined(CFG_BLE) && defined(CFG_EMB)))
+
+/// @} REG
+
+#endif // REG_ACCESS_H_

component/ble/plf/refip/src/driver/uart/uart.c

@@ -0,0 +1,534 @@
+/**
+ ****************************************************************************************
+ *
+ * @file uart.c
+ *
+ * @brief UART driver
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @addtogroup UART
+ * @{
+ ****************************************************************************************
+ */
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "arch.h"
+#include "compiler.h"
+#include <stddef.h> // standard definition
+#include <stdint.h>
+// #include "xinc_reg.h"
+#include "reg_access.h"
+// #include "bsp_gpio.h"
+// #include "bsp_uart.h"
+#include "uart.h"
+#include "xc_drv_uart.h"
+
+#ifndef CFG_ROM
+#include "rwip.h" // SW interface
+#if (PLF_NVDS)
+#include "nvds.h" // NVDS
+#endif            // (PLF_NVDS)
+#endif            // CFG_ROM
+
+#include "dbg.h"
+#include <stdio.h>
+#if (BLE_TEST_MODE_SUPPORT)
+/*
+ * DEFINES
+ *****************************************************************************************
+ */
+
+// /// Max baudrate supported by this UART (in bps)
+// #define UART_BAUD_MAX      3500000
+// /// Min baudrate supported by this UART (in bps)
+// #define UART_BAUD_MIN      9600
+
+// /// Duration of 1 byte transfer over UART (10 bits) in us (for 921600 default
+// baudrate) #define UART_CHAR_DURATION        11
+
+/*
+ * ENUMERATION DEFINITIONS
+ *****************************************************************************************
+ */
+
+/*
+ * STRUCT DEFINITIONS
+ *****************************************************************************************
+ */
+
+/*
+ * GLOBAL VARIABLE DEFINITIONS
+ ****************************************************************************************
+ */
+/// uart environment structure
+volatile static struct uart_env_tag uart_env;
+volatile static uint8_t uart_rx_done   = 0;
+volatile static uint16_t uart_rx_index = 0;
+
+uint8_t uart_tx_buf[UART_FIFO_MAX_COUNT];
+uint8_t uart_rx_buf[UART_FIFO_MAX_COUNT];
+/*
+ * LOCAL FUNCTION DEFINITIONS
+ ****************************************************************************************
+ */
+
+/*
+ * EXPORTED FUNCTION DEFINITIONS
+ ****************************************************************************************
+ */
+
+uint8_t uart_handle     = UART1_IDX;
+UART_InitCfg_t uart_cfg = {0};
+
+void uart_init(void)
+{
+    uart_rx_done            = 0;
+    uart_rx_index           = 0;
+    // Initialize RX and TX transfer callbacks
+    uart_env.rx.callback    = NULL;
+    uart_env.tx.callback    = NULL;
+
+    uart_env.uart_tx_buf    = NULL;
+    uart_env.uart_rx_buf    = NULL;
+
+    uart_env.uart_tx_length = 0;
+    uart_env.uart_rx_length = 0;
+
+    uart_env.uart_tx_enable = 0;
+    uart_env.uart_rx_enable = 0;
+
+    GPIO_InitCfg_t gpio_cfg = {0};
+
+    gpio_cfg.Mux            = GPIO_Mux0;
+    gpio_cfg.Pull           = GPIO_PULLUP;
+    gpio_cfg.Int            = NOT_INT;
+
+    gpio_cfg.Pin            = GPIO_16; // GPIO_16;
+    gpio_cfg.Dir            = GPIO_DIR_OUTPUT;
+    gpio_cfg.FunSel         = UART1_TX;
+    xc_gpio_init(&gpio_cfg);
+
+    gpio_cfg.Pin    = GPIO_15; // GPIO_15;
+    gpio_cfg.Dir    = GPIO_DIR_INPUT;
+    gpio_cfg.FunSel = UART1_RX;
+    xc_gpio_init(&gpio_cfg);
+
+    uart_cfg.Parity              = UART_PARITY_DISABLE;
+    uart_cfg.StopBits            = UART_TCR_STOP_1BITS;
+    uart_cfg.WordLength          = UART_DATA_8_BITS;
+    uart_cfg.BaudRate            = UART_BAUDRATE_115200;
+    uart_cfg.HardwareFlowControl = UART_HWFC_DISABLE;
+    xc_uart_init(uart_handle, &uart_cfg);
+
+    xc_uart_enable_rx_it(uart_handle);
+
+    if (uart_handle == UART0_IDX) {
+        NVIC_EnableIRQ(UART0_IRQn);
+    } else if (uart_handle == UART1_IDX) {
+        NVIC_EnableIRQ(UART1_IRQn);
+    }
+
+#if (VIRTUAL_UART_H4TL == 1)
+#if (BLE_APP_PRESENT)
+    if (0)
+#endif
+    {
+        hci_data_init(HCI_DATA_TYPE_CMD | HCI_DATA_TYPE_EVENT);
+        host_get_event_cbReg(uart_send);
+    }
+#endif
+}
+
+void uart_send(void *buff, uint16_t len)
+{
+    xc_uart_send_data(uart_handle, buff, len);
+}
+
+void uart_flow_on(void)
+{
+    // Configure modem (HW flow control enable)
+}
+
+bool uart_flow_off(void)
+{
+    bool flow_off = true;
+
+    GLOBAL_INT_DISABLE();
+
+    do {
+
+        // Force RTS to 'flow off' via GPIO
+        // uart_force_rts_setf(1);
+
+    } while (0);
+
+    GLOBAL_INT_RESTORE();
+
+    return flow_off;
+}
+
+void uart_finish_transfers(void)
+{
+
+    // Wait TX FIFO empty
+    //  while(!uart_tx_fifo_empty_getf());
+}
+
+void uart_read(uint8_t *bufptr, uint32_t size,
+               void (*callback)(void *, uint8_t), void *dummy)
+{
+    // Sanity check
+    ASSERT_ERR(bufptr != NULL);
+    ASSERT_ERR(size != 0);
+    ASSERT_ERR(callback != NULL);
+    uart_env.rx.callback    = callback;
+    uart_env.rx.dummy       = dummy;
+
+    uart_env.uart_rx_buf    = bufptr;
+    uart_env.uart_rx_length = size;
+    uart_env.uart_rx_enable = 1;
+
+    //    DEBUG("uart_env.rx.callback:%x\r\n",uart_env.rx.callback);
+    //    DEBUG("uart_read
+    //    len:%d,data:%02x,%02x,%02x\r\n",uart_env.uart_rx_length,uart_env.uart_rx_buf[0],uart_env.uart_rx_buf[1],uart_env.uart_rx_buf[2]);
+}
+
+void uart_write(uint8_t *bufptr, uint32_t size,
+                void (*callback)(void *, uint8_t), void *dummy)
+{
+    DEBUG("HCI  RSP: ");
+    // Sanity check
+    ASSERT_ERR(bufptr != NULL);
+    ASSERT_ERR(size != 0);
+    ASSERT_ERR(callback != NULL);
+    uart_env.tx.callback    = callback;
+    uart_env.tx.dummy       = dummy;
+
+    uart_env.uart_tx_buf    = bufptr;
+    uart_env.uart_tx_length = size;
+    uart_env.uart_tx_enable = 1;
+
+    for (int i = 0; i < size; i++) {
+        DEBUG("%02x ", *bufptr++);
+    }
+    DEBUG("\r\n");
+}
+
+void uart_isr(void) {}
+#define UART1_BASE 0x40011000
+#include "Platform.h"
+#define __write_hw_reg32(reg, val) ((*reg) = (val))
+#define __read_hw_reg32(reg, val)  ((val) = (*reg))
+#define UART1_RBR                  ((volatile unsigned *)(UART1_BASE + 0x00))
+#define UART1_THR                  ((volatile unsigned *)(UART1_BASE + 0x00))
+#define UART1_DLL                  ((volatile unsigned *)(UART1_BASE + 0x00))
+#define UART1_IER                  ((volatile unsigned *)(UART1_BASE + 0x04))
+#define UART1_DLH                  ((volatile unsigned *)(UART1_BASE + 0x04))
+#define UART1_IIR                  ((volatile unsigned *)(UART1_BASE + 0x08))
+#define UART1_FCR                  ((volatile unsigned *)(UART1_BASE + 0x08))
+#define UART1_TCR                  ((volatile unsigned *)(UART1_BASE + 0x0c))
+#define UART1_MCR                  ((volatile unsigned *)(UART1_BASE + 0x10))
+#define UART1_TSR                  ((volatile unsigned *)(UART1_BASE + 0x14))
+#define UART1_MSR                  ((volatile unsigned *)(UART1_BASE + 0x18))
+#define UART1_USR                  ((volatile unsigned *)(UART1_BASE + 0x7c))
+
+void uart_hci_handler(void)
+{
+    // DEBUG("UART1_Handler\r\n");
+    uint32_t iir = 0;
+    uint32_t tsr;
+    uint8_t data = 0;
+
+    __read_hw_reg32(UART1_IIR, iir);
+
+    // DEBUG("iWK:%x\r\n",iWK);
+    iir &= 0x0F;
+
+    if ((iir != 0x04) && (iir != 0x0c))
+        return;
+
+    if ((iir & 0x04) == 0x04) {
+        __read_hw_reg32(UART1_TSR, tsr);
+        while ((tsr & 0x01) == 0x01) {
+
+            __read_hw_reg32(UART1_RBR, data);
+            uart_rx_buf[uart_rx_index++] = data;
+            if (uart_rx_index == UART_FIFO_MAX_COUNT) {
+                uart_rx_index = 0;
+            }
+
+            __read_hw_reg32(UART1_TSR, tsr);
+        }
+    }
+
+    if ((iir & 0x0c) == 0x0c) {
+        __read_hw_reg32(UART1_TSR, tsr);
+        while ((tsr & 0x01) == 0x01) {
+
+            __read_hw_reg32(UART1_RBR, data);
+            uart_rx_buf[uart_rx_index++] = data;
+            if (uart_rx_index == UART_FIFO_MAX_COUNT) {
+                uart_rx_index = 0;
+            }
+
+            __read_hw_reg32(UART1_TSR, tsr);
+        }
+        host_send_cmd(uart_rx_buf, uart_rx_index);
+        uart_rx_index = 0;
+    }
+}
+
+void timeout_check()
+{
+    static uint16_t count = 0;
+    if (uart_rx_index != 0) {
+        if (count++ > 3000) {
+            host_send_cmd(uart_rx_buf, uart_rx_index);
+            uart_rx_index = 0;
+            count         = 0;
+        }
+    }
+}
+void uart_rx_cmd_respone(uint8_t *buff, uint8_t len)
+{
+    uint8_t rsp_buff[32];
+
+    rsp_buff[0] = 0x04;
+    rsp_buff[1] = 0x0e;
+    rsp_buff[2] = 0x04 + len;
+    rsp_buff[3] = 0x01;
+    rsp_buff[4] = 0xe0;
+    rsp_buff[5] = 0xfc;
+    rsp_buff[6] = len;
+
+    memcpy(&rsp_buff[7], buff, len);
+
+    uart_send(rsp_buff, 7 + len);
+}
+
+void uart_rx_cmd_handler(uint8_t *buff, uint8_t len) {}
+
+void uart_rx_handler(uint8_t value)
+{
+    static uint8_t cmd_status = UART_CMD_STATE_HEAD;
+    static uint16_t index     = 0;
+    static uint16_t length;
+    static uint8_t uart_cmd[32];
+
+    switch (cmd_status) {
+    case UART_CMD_STATE_HEAD: {
+        if (value == 0x01) {
+            cmd_status = UART_CMD_STATE_OPCODE_ONE;
+        } else {
+            cmd_status = UART_CMD_STATE_HEAD;
+        }
+    } break;
+
+    case UART_CMD_STATE_OPCODE_ONE: {
+        if (value == 0xe0) {
+            cmd_status = UART_CMD_STATE_OPCODE_TWO;
+        } else {
+            cmd_status = UART_CMD_STATE_HEAD;
+        }
+    } break;
+
+    case UART_CMD_STATE_OPCODE_TWO: {
+        if (value == 0xfc) {
+            cmd_status = UART_CMD_STATE_LENGTH;
+        } else {
+            cmd_status = UART_CMD_STATE_HEAD;
+        }
+    } break;
+
+    case UART_CMD_STATE_LENGTH: {
+        length = value;
+        if (length > 0) {
+            cmd_status = UART_CMD_STATE_CMD;
+            index      = 0;
+        } else {
+            cmd_status = UART_CMD_STATE_HEAD;
+        }
+    } break;
+
+    case UART_CMD_STATE_CMD: {
+        uart_cmd[index++] = value;
+
+        if (index == length) {
+            uart_rx_cmd_handler(uart_cmd, length);
+            cmd_status = UART_CMD_STATE_HEAD;
+        }
+    } break;
+    }
+}
+
+#if (VIRTUAL_UART_H4TL == 1)
+
+volatile struct hci_cmd_event_data host_cmd_data;
+volatile struct hci_cmd_event_data host_event_data;
+
+void hci_data_init(uint8_t type)
+{
+    //    DEBUG("hci_data_init:%x\r\n",type);
+    if (type & HCI_DATA_TYPE_CMD) {
+        host_cmd_data.callback = NULL;
+        memset((void *)&host_cmd_data.data_buff[0], 0, HCI_DATA_BUF_SIZE);
+        host_cmd_data.data_len = 0;
+    }
+
+    if (type & HCI_DATA_TYPE_EVENT) {
+        // host_event_data.callback = NULL;
+        memset((void *)&host_event_data.data_buff[0], 0, HCI_DATA_BUF_SIZE);
+        host_event_data.data_len = 0;
+    }
+}
+
+void host_send_cmd(uint8_t *bufptr, uint16_t length)
+{
+    host_cmd_data.callback = NULL; // Test Only
+    memcpy((void *)&host_cmd_data.data_buff[0], bufptr, length);
+    host_cmd_data.data_len = length;
+
+    DEBUG("HCI SEND: ");
+    for (int i = 0; i < length; i++) {
+
+        DEBUG("%02x ", host_cmd_data.data_buff[i]);
+    }
+    DEBUG("\r\n");
+}
+
+void host_get_event(void)
+{
+    if (host_event_data.callback != NULL) {
+        host_event_data.callback((void *)host_event_data.data_buff,
+                                 host_event_data.data_len);
+    }
+    hci_data_init(HCI_DATA_TYPE_EVENT);
+}
+
+void host_get_event_cbReg(void (*callback)(void *, uint16_t))
+{
+    host_event_data.callback = callback;
+}
+
+void uart_h4tl_data_switch(void)
+{
+    void (*callback)(void *, uint8_t) = NULL;
+    void *data                        = NULL;
+    uint16_t data_len                 = 0;
+
+    if (uart_env.uart_tx_enable || uart_env.uart_rx_enable) {
+        //   DEBUG("uart_h4tl_data_switch:%d,%d\r\n",uart_env.uart_tx_enable,uart_env.uart_rx_enable);
+    }
+
+    while (uart_env.uart_tx_enable == 1) {
+        callback                = uart_env.tx.callback;
+        data                    = uart_env.tx.dummy;
+
+        uart_env.uart_tx_enable = 0;
+        memcpy((void *)&host_event_data.data_buff[data_len],
+               uart_env.uart_tx_buf, uart_env.uart_tx_length);
+        data_len                 += uart_env.uart_tx_length;
+        host_event_data.data_len += uart_env.uart_tx_length;
+        if (callback != NULL) {
+            uart_env.tx.callback = NULL;
+            uart_env.tx.dummy    = NULL;
+
+            callback(data, RWIP_EIF_STATUS_OK);
+        } else {
+        }
+    }
+
+    if (host_event_data.data_len != 0) {
+        host_get_event();
+    }
+
+    data_len = 0;
+
+    if (host_cmd_data.data_len > 0) {
+        while (uart_env.uart_rx_enable == 1) {
+            callback                = uart_env.rx.callback;
+            data                    = uart_env.rx.dummy;
+            uart_env.uart_rx_enable = 0;
+
+            memcpy((void *)uart_env.uart_rx_buf,
+                   (void *)&host_cmd_data.data_buff[data_len],
+                   uart_env.uart_rx_length);
+
+            data_len += uart_env.uart_rx_length;
+
+            //            DEBUG("data_len:%d,uart_rx_length:%d\r\n",data_len,uart_env.uart_rx_length);
+
+            //            DEBUG("callback:%x\r\n",callback);
+            if (callback != NULL) {
+                uart_env.rx.callback = NULL;
+                uart_env.rx.dummy    = NULL;
+
+                callback(data, RWIP_EIF_STATUS_OK);
+            } else {
+            }
+            //            DEBUG("data_len:%d,host_cmd_data.data_len:%d\r\n",data_len,host_cmd_data.data_len);
+            if (data_len >= host_cmd_data.data_len) {
+                // hci_data_init(HCI_DATA_TYPE_CMD);
+                break;
+            }
+        }
+        hci_data_init(HCI_DATA_TYPE_CMD);
+    }
+}
+#endif
+
+// Creation of uart external interface api
+const struct rwip_eif_api uart_api = {
+    uart_read,
+    uart_write,
+    uart_flow_on,
+    uart_flow_off,
+};
+
+// static bool test_mode = false;
+static bool test_mode = true;
+
+bool get_test_mode(void) { return test_mode; }
+
+void enter_test_mode(void)
+{
+    DEBUG("enter_test_mode \n");
+    /// rf_test_pin_init();
+    uart_init();
+    NVIC_SetPriority((IRQn_Type)UART1_IRQn, 2);
+    h4tl_init(0, rwip_eif_get(0));
+    while (1) {
+        // schedule all pending events
+        rwip_schedule();
+#if (VIRTUAL_UART_H4TL == 1)
+        uart_h4tl_data_switch();
+        timeout_check();
+#endif
+    }
+}
+
+const struct rwip_eif_api *rwip_eif_get(uint8_t idx)
+{
+    const struct rwip_eif_api *ret = NULL;
+    switch (idx) {
+    case 0: {
+        ret = &uart_api;
+    } break;
+    default: {
+        ASSERT_INFO(0, idx, 0);
+    } break;
+    }
+    return ret;
+}
+#endif // (BLE_TEST_MODE_SUPPORT)
+
+/// @} UART

component/ble/plf/refip/src/driver/uart/uart.h

@@ -0,0 +1,207 @@
+/**
+ ****************************************************************************************
+ *
+ * @file uart.h
+ *
+ * @brief UART Driver for HCI over UART operation.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef _UART_H_
+#define _UART_H_
+
+/**
+ ****************************************************************************************
+ * @defgroup UART UART
+ * @ingroup DRIVERS
+ * @brief UART driver
+ *
+ * @{
+ *
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include <stdbool.h>          // standard boolean definitions
+#include <stdint.h>           // standard integer functions
+
+
+#define VIRTUAL_UART_H4TL  1
+
+#define UART_FIFO_MAX_COUNT 300
+/*
+ * ENUMERATION DEFINITIONS
+ *****************************************************************************************
+ */
+typedef enum _UART_CMD_STATE
+{
+    UART_CMD_STATE_HEAD,
+    UART_CMD_STATE_OPCODE_ONE,
+    UART_CMD_STATE_OPCODE_TWO,
+    UART_CMD_STATE_LENGTH,
+    UART_CMD_STATE_CMD,
+    UART_CMD_STATE_CMD_FLASH,
+    UART_CMD_STATE_LENGTH_FLASH_LEN0,
+    UART_CMD_STATE_LENGTH_FLASH_LEN1,
+    UART_CMD_STATE_LENGTH_FLASH_SCMD,
+    UART_CMD_STATE_PAYLOAD,
+    UART_CMD_STATE_ERROR_ONE,  
+    UART_CMD_STATE_ERROR_TWO,
+    UART_CMD_STATE_ERROR_THREE,
+    UART_CMD_STATE_ERROR_FOUR,
+    UART_CMD_STATE_PACKET,
+    
+}UART_CMD_STATE;
+
+#if (VIRTUAL_UART_H4TL == 1)
+
+#define HCI_DATA_BUF_SIZE   300
+#define HCI_DATA_TYPE_CMD   0x01
+#define HCI_DATA_TYPE_EVENT 0x02
+
+struct hci_cmd_event_data
+{
+    // call back function pointer
+    void (*callback)(void*,uint16_t);
+    //Dumy data pointer
+    uint8_t data_buff[HCI_DATA_BUF_SIZE];
+    uint32_t data_len;
+};
+
+#endif
+
+
+/* TX and RX channel class holding data used for asynchronous read and write data
+ * transactions
+ */
+
+/// UART TX RX Channel
+struct uart_txrxchannel
+{
+    uint32_t size;
+    uint8_t *bufptr;
+    /// call back function pointer
+    void (*callback) (void*, uint8_t);
+    /// Dummy data pointer returned to callback when operation is over.
+    void* dummy;
+};
+
+/// UART environment structure
+struct uart_env_tag
+{
+    /// tx channel
+    struct uart_txrxchannel tx;
+    /// rx channel
+    struct uart_txrxchannel rx;
+    /// error detect
+    uint8_t errordetect;
+    /// external wakeup
+    bool ext_wakeup;
+    
+    uint8_t *uart_tx_buf;   
+    uint8_t *uart_rx_buf;
+    uint32_t uart_tx_length;
+    uint32_t uart_rx_length;
+    uint8_t uart_tx_enable;   
+    uint8_t uart_rx_enable;
+};
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+#if (BLE_TEST_MODE_SUPPORT)
+/**
+ ****************************************************************************************
+ * @brief Initializes the UART to default values.
+ *****************************************************************************************
+ */
+void uart_init(void);
+#endif // (BLE_TEST_MODE_SUPPORT)
+
+#ifndef CFG_ROM
+/**
+ ****************************************************************************************
+ * @brief Enable UART flow.
+ *****************************************************************************************
+ */
+void uart_flow_on(void);
+
+/**
+ ****************************************************************************************
+ * @brief Disable UART flow.
+ *****************************************************************************************
+ */
+bool uart_flow_off(void);
+#endif //CFG_ROM
+
+/**
+ ****************************************************************************************
+ * @brief Finish current UART transfers
+ *****************************************************************************************
+ */
+void uart_finish_transfers(void);
+
+/**
+ ****************************************************************************************
+ * @brief Starts a data reception.
+ *
+ * @param[out] bufptr   Pointer to the RX buffer
+ * @param[in]  size     Size of the expected reception
+ * @param[in]  callback Pointer to the function called back when transfer finished
+ * @param[in]  dummy    Dummy data pointer returned to callback when reception is finished
+ *****************************************************************************************
+ */
+void uart_read(uint8_t *bufptr, uint32_t size, void (*callback) (void*, uint8_t), void* dummy);
+
+/**
+ ****************************************************************************************
+ * @brief Starts a data transmission.
+ *
+ * @param[in] bufptr   Pointer to the TX buffer
+ * @param[in] size     Size of the transmission
+ * @param[in] callback Pointer to the function called back when transfer finished
+ * @param[in] dummy    Dummy data pointer returned to callback when transmission is finished
+ *****************************************************************************************
+ */
+void uart_write(uint8_t *bufptr, uint32_t size, void (*callback) (void*, uint8_t), void* dummy);
+
+#if defined(CFG_ROM)
+/**
+ ****************************************************************************************
+ * @brief Poll UART on reception and transmission.
+ *
+ * This function is used to poll UART for reception and transmission.
+ * It is used when IRQ are not used to detect incoming bytes.
+ *****************************************************************************************
+ */
+void uart_poll(void);
+#endif //CFG_ROM
+
+/**
+ ****************************************************************************************
+ * @brief Serves the data transfer interrupt requests.
+ *
+ * It clears the requests and executes the appropriate callback function.
+ *****************************************************************************************
+ */
+void uart_isr(void);
+
+void hci_data_init(uint8_t type);
+void host_get_event_cbReg(void(*callback)(void*,uint16_t));
+void host_send_cmd(uint8_t *bufptr,uint16_t length);
+void uart_h4tl_data_switch(void);
+void uart_send(void *buff,uint16_t len);
+
+
+
+
+/// @} UART
+#endif /* _UART_H_ */