/*! * \file xc60xx.h * * \brief The header of xc60xx chip * * \copyright Revised BSD License, see section \ref LICENSE. * * \code * * _ __ _ ________ _ * | |/ /(_)___ / ____/ /_ (_)___ * | // / __ \/ / / __ \/ / __ \ * / |/ / / / / /___/ / / / / /_/ / * /_/|_/_/_/ /_/\____/_/ /_/_/ .___/ * /_/ * (C) 2022-2025 XinChip * * \endcode * * \author ( XinChip ) Alex-J * * \author ( XinChip ) */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __XC60XX_H__ #define __XC60XX_H__ #ifdef __cplusplus extern "C" { #endif /*----------------------------------------------------------------------------------- INCLUDE HEADE FILES ------------------------------------------------------------------------------------*/ #include #include #include #include /*------------------------------------------------------------------------------------ Macros -------------------------------------------------------------------------------------*/ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ #define __RAM_CODE __attribute__((section("ram_code"))) #define __WEAK __attribute__((weak)) #ifndef __PACKED #define __PACKED __attribute__((packed)) #endif #ifndef __UNALIGNED_UINT32_WRITE #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) #endif #define __STATIC_INLINE static __inline /* * ========================================================================== * ---------- Interrupt Number Definition ----------------------------------- * ========================================================================== */ typedef enum IRQn { /****** Cortex-M# Processor Exceptions Numbers ***************************************************/ /* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M4 device */ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Hard Fault Interrupt */ SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */ /****** Device Specific Interrupt Numbers ********************************************************/ /* ToDo: add here your device specific external interrupt numbers according the interrupt handlers defined in startup_Device.s eg.: Interrupt for Timer#1 TIM1_IRQHandler -> TIM1_IRQn */ BLE_IRQn = 0, /*!< Device Interrupt */ DMA_IRQn = 1, CPR_IRQn = 2, GPIO_IRQn = 3, RTC_IRQn = 4, TIMER0_IRQn = 5, TIMER1_IRQn = 6, TIMER2_IRQn = 7, TIMER3_IRQn = 8, WDT_IRQn = 9, I2C_IRQn = 10, UART0_IRQn = 11, UART1_IRQn = 12, SPI0_IRQn = 13, SPI1_IRQn = 14, KBS_IRQn = 15, QDEC_IRQn = 16, GADC_IRQn = 17, PWM_IRQn = 18, AES_IRQn = 19, USB_IRQn = 20, AUDIO_IRQn = 21, RF24G_IRQn = 22, SPI2_IRQn = 23, MPU_IRQn = 24, UART2_IRQn = 25, I2S_IRQn = 26, TIMER_AO0_IRQn = 27, TIMER_AO1_IRQn = 28, CMP_IRQn = 29, FMC_IRQn = 30, CAN_IRQn = 31 } IRQn_Type; /* * ========================================================================== * ----------- Processor and Core Peripheral Section ------------------------ * ========================================================================== */ /* Configuration of the Cortex-M# Processor and Core Peripherals */ /* ToDo: set the defines according your Device */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ #if defined ( __CC_ARM ) #if defined (__TARGET_FPU_VFP) #define __FPU_PRESENT 1 /*!< FPU present or not */ #else #define __FPU_PRESENT 0 /*!< FPU present or not */ #endif #else #define __FPU_PRESENT 0 /*!< FPU present or not */ #endif /*@}*/ /* end of group _CMSIS */ #include "core_cm0.h" /* Cortex-M4 processor and core peripherals */ //#include "cmsis_armcc.h" /* =========================================================================================================================== */ /* ================ DMAC ================ */ /* =========================================================================================================================== */ /** * @brief 精简直接存储器存取控制器(DMAC) */ //typedef struct { /*!< (@ 0x50001000) DMAS Structure */ // /* Channel registers // * offset = (channel_num * 0x058) + channel_0 offset // */ // struct { // __IOM uint32_t SAR; /*!< (@ 0x50001000) Source Address Reg */ // __IM uint32_t RESERVED0; /*!< (@ 0x50001004) Reserved */ // __IOM uint32_t DAR; /*!< (@ 0x50001008) Destination Address Reg */ // __IM uint32_t RESERVED1[3]; /*!< (@ 0x5000100C)-->(@ 0x50001014) Reserved */ // __IOM uint32_t CTL_L; /*!< (@ 0x50001018) Control Reg low */ // __IOM uint32_t CTL_H; /*!< (@ 0x5000101C) Control Reg high */ // __IM uint32_t RESERVED2[8]; /*!< (@ 0x50001020)-->(@ 0x5000103C) Reserved */ // __IOM uint32_t CFG_L; /*!< (@ 0x50001040) Configuration Reg low */ // __IOM uint32_t CFG_H; /*!< (@ 0x50001044) Configuration Reg high */ // __IM uint32_t RESERVED3[4]; /*!< (@ 0x50001048)-->(@ 0x50001054) Reserved */ // } Ch[8]; // /* Interrupt Raw Status Registers */ // __IOM uint32_t RAW_TRF; /*!< (@ 0x500012C0) Raw Status for IntTfr */ // __IM uint32_t RESERVED4; /*!< (@ 0x500012C4) Reserved */ // __IOM uint32_t RAW_BLOCK; /*!< (@ 0x500012C8) Raw Status for IntBlock */ // __IM uint32_t RESERVED5; /*!< (@ 0x500012CC) Reserved */ // __IOM uint32_t RAW_SRC_TRAN; /*!< (@ 0x500012D0) Raw Status IntSrcTran */ // __IM uint32_t RESERVED6; /*!< (@ 0x500012D4) Reserved */ // __IOM uint32_t RAW_DST_TRAN; /*!< (@ 0x500012D8) Raw Status IntDstTran */ // __IM uint32_t RESERVED7; /*!< (@ 0x500012DC) Reserved */ // __IOM uint32_t RAW_ERR; /*!< (@ 0x500012E0) Raw Status for IntErr */ // __IM uint32_t RESERVED8; /*!< (@ 0x500012E4) Reserved */ // /* Interrupt Status Registers */ // __IM uint32_t STATUS_TRF; /*!< (@ 0x500012E8) Status for IntTfr */ // __IM uint32_t RESERVED9; /*!< (@ 0x500012EC) Reserved */ // __IM uint32_t STATUS_BLOCK; /*!< (@ 0x500012F0) Status for IntBlock */ // __IM uint32_t RESERVED10; /*!< (@ 0x500012F4) Reserved */ // __IM uint32_t STATUS_SRC_TRAN; /*!< (@ 0x500012F8) Status for IntSrcTran */ // __IM uint32_t RESERVED11; /*!< (@ 0x500012FC) Reserved */ // __IM uint32_t STATUS_DST_TRAN; /*!< (@ 0x50001300) Status for IntDstTran */ // __IM uint32_t RESERVED12; /*!< (@ 0x50001304) Reserved */ // __IM uint32_t STATUS_ERR; /*!< (@ 0x50001308) Status for IntErr */ // __IM uint32_t RESERVED13; /*!< (@ 0x5000130C) Reserved */ // /* Interrupt Mask Registers */ // __IOM uint32_t MASK_TRF; /*!< (@ 0x50001310) Mask for IntTfr */ // __IM uint32_t RESERVED14; /*!< (@ 0x50001314) Reserved */ // __IOM uint32_t MASK_BLOCK; /*!< (@ 0x50001318) Mask for IntBlock */ // __IM uint32_t RESERVED15; /*!< (@ 0x5000131C) Reserved */ // __IOM uint32_t MASK_SRC_TRAN; /*!< (@ 0x50001320) Mask for IntSrcTran */ // __IM uint32_t RESERVED16; /*!< (@ 0x50001324) Reserved */ // __IOM uint32_t MASK_DST_TRAN; /*!< (@ 0x50001328) Mask for IntDstTran */ // __IM uint32_t RESERVED17; /*!< (@ 0x5000132C) Reserved */ // __IOM uint32_t MASK_ERR; /*!< (@ 0x50001330) Mask for IntErr */ // __IM uint32_t RESERVED18; /*!< (@ 0x50001334) Reserved */ // /* Interrupt Clear Registers */ // __OM uint32_t CLEAR_TRF; /*!< (@ 0x50001338) Clear for IntTfr */ // __OM uint32_t RESERVED19; /*!< (@ 0x5000133C) Reserved */ // __OM uint32_t CLEAR_BLOCK; /*!< (@ 0x50001340) Clear for IntBlock */ // __OM uint32_t RESERVED20; /*!< (@ 0x50001344) Reserved */ // __OM uint32_t CLEAR_SRC_TRAN; /*!< (@ 0x50001348) Clear for IntSrcTran */ // __OM uint32_t RESERVED21; /*!< (@ 0x5000134C) Reserved */ // __OM uint32_t CLEAR_DST_TRAN; /*!< (@ 0x50001350) Clear for IntDstTran */ // __OM uint32_t RESERVED22; /*!< (@ 0x50001354) Reserved */ // __OM uint32_t CLEAR_ERR; /*!< (@ 0x50001358) Clear for IntErr */ // __OM uint32_t RESERVED23; /*!< (@ 0x5000135C) Reserved */ // __IM uint32_t STATUS_INT; /*!< (@ 0x50001360) Combined Intr Status */ // __IM uint32_t RESERVED24; /*!< (@ 0x50001364) Reserved */ // /* Software Handshaking Registers */ // __IOM uint32_t REQ_SRC_REG; /*!< (@ 0x50001368) Src Sw Transaction Req */ // __IM uint32_t RESERVED25; /*!< (@ 0x5000136C) Reserved */ // __IOM uint32_t REQ_DST_REG; /*!< (@ 0x50001370) Dest Sw Transaction Req */ // __IM uint32_t RESERVED26; /*!< (@ 0x50001374) Reserved */ // __IOM uint32_t SGL_RQ_SRC_REG; /*!< (@ 0x50001378) Sgl Src Transac Req */ // __IM uint32_t RESERVED27; /*!< (@ 0x5000137C) Reserved */ // __IOM uint32_t SGL_RQ_DST_REG; /*!< (@ 0x50001380) Sgl Dest Transac Req */ // __IM uint32_t RESERVED28; /*!< (@ 0x50001384) Reserved */ // __IOM uint32_t LST_SRC_REG; /*!< (@ 0x50001388) Last Src Transac Req */ // __IM uint32_t RESERVED29; /*!< (@ 0x5000138C) Reserved */ // __IOM uint32_t LST_DST_REG; /*!< (@ 0x50001390) Last Dest Transac Req */ // __IM uint32_t RESERVED30; /*!< (@ 0x50001394) Reserved */ // /* Misc Registers */ // __IOM uint32_t DMA_CFG_REG; /*!< (@ 0x50001398) Configuration Register */ // __IM uint32_t RESERVED31; /*!< (@ 0x5000139C) Reserved */ // __IOM uint32_t CH_EN_REG; /*!< (@ 0x500013A0) Channel Enable Register */ // __IM uint32_t RESERVED32; /*!< (@ 0x500013A4) Reserved */ // __IOM uint32_t DMA_ID_REG; /*!< (@ 0x500013A8) ID Register */ // __IM uint32_t RESERVED33; /*!< (@ 0x500013AC) Reserved */ // __IOM uint32_t DMA_TEST_REG; /*!< (@ 0x500013B0) Test Register */ // __IM uint32_t RESERVED34; /*!< (@ 0x500013B4) Reserved */ // __IOM uint32_t OLD_VER_ID_REG; /*!< (@ 0x500013B8) legacy support */ // __IM uint32_t RESERVED35[3]; /*!< (@ 0x500013BC)-->(@ 0x500013C4) Reserved */ // __IM uint32_t DMA_COMP_PARAM_6_L; /*!< (@ 0x500013C8) hardware params low 32bits */ // __IM uint32_t DMA_COMP_PARAM_6_H; /*!< (@ 0x500013CC) hardware params high 32bits */ // __IM uint32_t DMA_COMP_PARAM_5_L; /*!< (@ 0x500013D0) hardware params low 32bits */ // __IM uint32_t DMA_COMP_PARAM_5_H; /*!< (@ 0x500013D4) hardware params high 32bits */ // __IM uint32_t DMA_COMP_PARAM_4_L; /*!< (@ 0x500013D8) hardware params low 32bits */ // __IM uint32_t DMA_COMP_PARAM_4_H; /*!< (@ 0x500013DC) hardware params high 32bits */ // __IM uint32_t DMA_COMP_PARAM_3_L; /*!< (@ 0x500013E0) hardware params low 32bits */ // __IM uint32_t DMA_COMP_PARAM_3_H; /*!< (@ 0x500013E4) hardware params high 32bits */ // __IM uint32_t DMA_COMP_PARAM_2_L; /*!< (@ 0x500013E8) hardware params low 32bits */ // __IM uint32_t DMA_COMP_PARAM_2_H; /*!< (@ 0x500013EC) hardware params high 32bits */ // __IM uint32_t DMA_COMP_PARAM_1_L; /*!< (@ 0x500013F0) hardware params low 32bits */ // __IM uint32_t DMA_COMP_PARAM_1_H; /*!< (@ 0x500013F4) hardware params high 32bits */ // __IM uint32_t DMA_VER_ID_L; /*!< (@ 0x500013F8) DMA Component Type Number */ // __IM uint32_t DMA_VER_ID_H; /*!< (@ 0x500013FC) DMA Component Version */ // //} DMAC_TypeDef; /*!< Size = 4096 (0x1000) */ /* ========================================================================================================================= */ /* ================ FMC ================ */ /* ========================================================================================================================= */ //typedef struct { /*!< (@ 0x51000000) FMC Structure */ // __IOM uint32_t CTRL0; /*!< (@ 0x00000000) */ // __IOM uint32_t CTRL1; /*!< (@ 0x00000004) */ // __IOM uint32_t EN; /*!< (@ 0x00000008) */ // __IM uint32_t RESERVED0[1]; /*!< (@ 0x0000000C) */ // __IOM uint32_t SE; /*!< (@ 0x00000010) */ // // __IOM uint32_t BAUD; /*!< (@ 0x00000014) */ // __IOM uint32_t TXFTL; /*!< (@ 0x00000018) */ // __IOM uint32_t RXFTL; /*!< (@ 0x0000001C) */ // __IOM uint32_t TXFL; /*!< (@ 0x00000020) */ // __IOM uint32_t RXFL; /*!< (@ 0x00000024) */ // __IOM uint32_t STS; /*!< (@ 0x00000028) */ // __IOM uint32_t IE; /*!< (@ 0x0000002C) */ // __IOM uint32_t IS; /*!< (@ 0x00000030) */ // __IOM uint32_t RIS; /*!< (@ 0x00000034) */ // __IOM uint32_t TXOIC; /*!< (@ 0x00000038) */ // __IOM uint32_t RXOIC; /*!< (@ 0x0000003C) */ // __IOM uint32_t RXUIC; /*!< (@ 0x00000040) */ // __IM uint32_t RESERVED1[1]; /*!< (@ 0x00000044) */ // __IOM uint32_t IC; /*!< (@ 0x00000048) */ // __IOM uint32_t DMAC; /*!< (@ 0x0000004C) */ // __IOM uint32_t DMATDL; /*!< (@ 0x00000050) */ // __IOM uint32_t DMARDL; /*!< (@ 0x00000054) */ // __IM uint32_t RESERVED2[2]; /*!< (@ 0x00000058) */ // // __IOM uint32_t DATA; /*!< (@ 0x00000060) */ // // __IM uint32_t RESERVED3[36]; /*!< (@ 0x00000064) */ // __IOM uint32_t SPI_CTRLR0; /*!< (@ 0x000000F4) */ // // __IM uint32_t RESERVED4[3]; // __IOM uint32_t XIP_INCR_INST; /*!< (@ 0x00000100) */ // __IOM uint32_t XIP_WRAP_INST; /*!< (@ 0x00000104) */ // __IOM uint32_t XIP_CTRL; /*!< (@ 0x00000108) */ // __IOM uint32_t XIP_SER; /*!< (@ 0x0000010C) */ // __IOM uint32_t XRXOICR; /*!< (@ 0x00000110) */ // __IOM uint32_t XIP_CNT_TIME_OUT; /*!< (@ 0x00000114) */ // //} FMC_TypeDef; //typedef struct { /*!< (@ 0x51000000) FMC CACHE Structure */ // // __IOM uint32_t CCR; /*!< (@ 0x00000000) */ // __IM uint32_t SR; /*!< (@ 0x00000004) */ // __IOM uint32_t IRQMASK; /*!< (@ 0x00000008) */ // __IOM uint32_t IRQSTAT; /*!< (@ 0x0000000C) */ // __IOM uint32_t HWPARAMS; /*!< (@ 0x00000010) */ // __IOM uint32_t CSHR; /*!< (@ 0x00000014) */ // __IOM uint32_t CSMR; /*!< (@ 0x00000018) */ //} FMC_CACHE_TypeDef; /* ======================================================================================================================== */ /* ================ BT/BLE COMMON ================ */ /* ======================================================================================================================== */ //typedef struct { /*!< (@ 0x53022000) BT/BLE Common Structure */ // __IOM uint32_t AGC_REG_IN0; /*!< (@ 0x00000000) */ // __IOM uint32_t AGC_REG_IN1; /*!< (@ 0x00000004) */ // __IOM uint32_t AGC_REG_IN2; /*!< (@ 0x00000008) */ // __IOM uint32_t AGC_REG_IN3; /*!< (@ 0x0000000C) */ // __IOM uint32_t AGC_REG_IN4; /*!< (@ 0x00000010) */ // __IOM uint32_t AGC_REG_IN5; /*!< (@ 0x00000014) */ // __IOM uint32_t AGC_REG_IN6; /*!< (@ 0x00000018) */ // __IOM uint32_t AGC_REG_IN7; /*!< (@ 0x0000001C) */ // __IOM uint32_t AGC_REG_IN8; /*!< (@ 0x00000020) */ // __IOM uint32_t AGC_REG_IN9; /*!< (@ 0x00000024) */ // __IM uint32_t AGC_REG_OUT0; /*!< (@ 0x00000028) */ // __IM uint32_t AGC_REG_OUT1; /*!< (@ 0x0000002C) */ // __IM uint32_t AGC_REG_OUT2; /*!< (@ 0x00000030) */ // __IM uint32_t AGC_REG_OUT3; /*!< (@ 0x00000034) */ // __IM uint32_t AGC_REG_OUT4; /*!< (@ 0x00000038) */ // __IOM uint32_t COSSIN_CTRL; /*!< (@ 0x0000003C) */ // __IOM uint32_t RF24G_CTRL; /*!< (@ 0x00000040) */ // __IOM uint32_t BLE_COMMON_CTRL; /*!< (@ 0x00000044) */ // __IOM uint32_t MODEM_DELAY_CTRL; /*!< (@ 0x00000048) */ // __IOM uint32_t RF_DELAY_CTRL; /*!< (@ 0x0000004C) */ // __IOM uint32_t RF_AUTO_CHAN; /*!< (@ 0x00000050) */ // __IOM uint32_t BLEMISC_INT; /*!< (@ 0x00000054) */ // __IM uint32_t BLEMISC_INT_RAW; /*!< (@ 0x00000058) */ // __IOM uint32_t BLEMISC_INT_EN; /*!< (@ 0x0000005C) */ // //} BLE_COMN_TypeDef; /* ======================================================================================================================== */ /* ================ CPR ================ */ /* ======================================================================================================================== */ //typedef struct { /*!< (@ 0x40000000) CPR PD 域寄存器地址映射 Structure */ // __IOM uint32_t SLP_SRC_MASK; /*!< (@ 0x40000000) 睡眠源屏蔽寄存器 */ // __IM uint32_t RESERVED[3]; // __IOM uint32_t SLP_CNT_LIMIT; /*!< (@ 0x40000010) 睡眠进入阈值寄存器 */ // __IOM uint32_t SLP_ST; /*!< (@ 0x40000014) 睡眠启动寄存器 */ // __IOM uint32_t SLP_FSM_STATE; /*!< (@ 0x40000018) 睡眠状态机状态寄存器 */ // __IM uint32_t RESERVED01[1]; // __IOM uint32_t M0_FCLK_CTL; /*!< (@ 0x40000020) M0 fclk 时钟控制寄存器 */ // __IOM uint32_t CTL_PCLK_GRCTL; /*!< (@ 0x00000024) CTL_PCLK 时钟控制寄存器 GR */ // __IOM uint32_t SIM_CLK_GRCTL; /*!< (@ 0x00000028) SIM_CLK时钟GR控制寄存器 */ // __IOM uint32_t SIM_CLK_CTLL; /*!< (@ 0x0000002C) SIM_CLK 时钟控制寄存器 */ // __IOM uint32_t UART0_CLK_GRCTL; /*!< (@ 0x00000030) UART0 CLK GR */ // __IOM uint32_t UART0_CLK_CTL; /*!< (@ 0x00000034) UART0 CLK CTL */ // __IOM uint32_t UART1_CLK_GRCTL; /*!< (@ 0x00000038) UART1 CLK GR */ // __IOM uint32_t UART1_CLK_CTL; /*!< (@ 0x0000003C) UART1 CLK CTL */ // // __IOM uint32_t BT_CLK_CTL; /*!< (@ 0x00000040) BT_CLK 时钟控制寄存器 */ // __IM uint32_t RESERVED02; // __IOM uint32_t BT_MODEM_CTL; /*!< (@ 0x00000048) BT_MODEM_CLK时钟控制寄存器 */ // __IOM uint32_t QDEC_CLK_CTL; /*!< (@ 0x0000004C) QDEC 时钟控制寄存器 */ // __IOM uint32_t SSI0_MCLK_CTL; /*!< (@ 0x00000050) SSI0_MCLK CTL */ // __IOM uint32_t SSI1_MCLK_CTL; /*!< (@ 0x00000054) SSI1_MCLK CTL */ // __IOM uint32_t TIMER0_CLK_CTL; /*!< (@ 0x00000058) TIMER0 CLK CTL */ // __IOM uint32_t TIMER1_CLK_CTL; /*!< (@ 0x0000005C) TIMER1 CLK CTL */ // // __IOM uint32_t TIMER2_CLK_CTL; /*!< (@ 0x00000060) TIMER2 CLK CTL */ // __IOM uint32_t TIMER3_CLK_CTL; /*!< (@ 0x00000064) TIMER2 CLK CTL */ // __IOM uint32_t PWM_CLK_CTL; /*!< (@ 0x00000068) PWM CLK CTL */ // __IOM uint32_t AHBCLKEN_GRCTL; /*!< (@ 0x0000006C) AHBCLKEN_GRCTL */ // // __IOM uint32_t CTLAPBCLKEN_GRCTL; /*!< (@ 0x00000070) CTLAPBCLKEN_GRCTL */ // __IOM uint32_t OTHERCLKEN_GRCTL; /*!< (@ 0x00000074) OTHERCLKEN_GRCTL */ // __IOM uint32_t I2C_CLK_CTL; /*!< (@ 0x00000078) I2C_CLK_CTL */ // __IM uint32_t RESERVED03[9]; // __IOM uint32_t INT; /*!< (@ 0x000000A0) M0 的 CPR 中断状态寄存器 */ // __IOM uint32_t INT_EN; /*!< (@ 0x000000A4) M0 的 CPR 中断状态寄存器 */ // __IOM uint32_t INT_RAW; /*!< (@ 0x000000A8) M0 的 CPR 中断状态寄存器 */ // __IM uint32_t RESERVED04[5]; // __IOM uint32_t GPIO_FUN_SELx[8]; /*!< (@ 0x000000C0) gpio_fun_sel0..7 */ // // __IM uint32_t RESERVED05[8]; // // __IOM uint32_t RSTCTL_CTLAPB_SW; /*!< (@ 0x00000100) CTLAPB 模块软复位寄存器 */ // __IOM uint32_t RSTCTL_SUBRST_SW; /*!< (@ 0x00000104) SUB 模块软复位寄存器 */ // __IOM uint32_t RSTCTL_M0RST_SW; /*!< (@ 0x00000108) M0 相关软复位寄存器 */ // __IOM uint32_t RSTCTL_M0RST_MASK; /*!< (@ 0x0000010C) M0 复位屏蔽寄存器 */ // // __IOM uint32_t RSTCTL_LOCKUP_STATE; /*!< (@ 0x00000110) M0 死锁状态指示寄存器 */ // __IOM uint32_t RSTCTL_WDTRST_MASK; /*!< (@ 0x00000114) WDT 复位屏蔽寄存 */ // __IOM uint32_t LP_CTL; /*!< (@ 0x00000118) 低功耗控制寄存器 */ // __IM uint32_t RESERVED06[1]; // __IOM uint32_t CTL_SHRAM_ICM_PRIORITY; /*!< (@ 0x00000120) SHRAM 的 ICM 优先级配置寄存器 */ // __IOM uint32_t CTL_CTLAPB_ICM_PRIORITY; /*!< (@ 0x00000124) CTL_APB 桥的 ICM优先级配置寄存器 */ // __IOM uint32_t CTL_MUXCTL1_2[2]; /*!< (@ 0x00000128) MUXPIN 控制寄存器1 2 */ // __IOM uint32_t RF_REG3; /*!< (@ 0x00000130) CRP 通用寄存器3 */ // __IOM uint32_t RF_REG4; /*!< (@ 0x00000134) CRP 通用寄存器4 */ // __IM uint32_t RESERVED07[1]; // __IOM uint32_t REMAP_CTRL; /*!< (@ 0x0000013C) REMAP 控制寄存器 */ // __IOM uint32_t CTL_BOOTCTL; /*!< (@ 0x00000140) BOOTCTL 指示寄存器 */ // __IOM uint32_t CTL_M0_STCALIB; /*!< (@ 0x00000144) M0 配置寄存器 */ // __IOM uint32_t CTL_M0_IRQLATENCY; /*!< (@ 0x00000148) M0 IRQ 延迟寄存器 */ // __IM uint32_t RESERVED08[5]; // // SSI 控制寄存器 // __IOM uint32_t SSI_CTRL; /*!< (@ 0x00000160) SSI 控制寄存器 */ // __IM uint32_t RESERVED09[3]; // __IOM uint32_t TESTCTRL0; /*!< (@ 0x00000170) 测试控制寄存器 0 */ // __IOM uint32_t TESTCTRL1; /*!< (@ 0x00000174) 测试控制寄存器 1 */ // __IOM uint32_t TESTCTRL2; /*!< (@ 0x00000178) 测试控制寄存器 2 */ // __IOM uint32_t TESTCTRL3; /*!< (@ 0x0000017C) 测试控制寄存器 3 */ // __IOM uint32_t TESTCTRL4; /*!< (@ 0x00000180) 测试控制寄存器 4 */ // __IOM uint32_t TESTCTRL5; /*!< (@ 0x00000184) 测试控制寄存器 5 */ // __IOM uint32_t TESTCTRL6; /*!< (@ 0x00000188) 测试控制寄存器 6 */ // __IOM uint32_t TESTCTRL7; /*!< (@ 0x0000018C) 测试控制寄存器 7 */ // __IOM uint32_t TESTCTRL8; /*!< (@ 0x00000190) 测试控制寄存器 8 */ // __IOM uint32_t TESTCTRL9; /*!< (@ 0x00000194) 测试控制寄存器 9 */ // __IM uint32_t RESERVED10[1]; // __IOM uint32_t CTL_MUXCTL3[1]; /*!< (@ 0x0000019C) MUXPIN 控制寄存器 3 */ // __IOM uint32_t RF_REG5; /*!< (@ 0x000001A0) 管脚上下拉配置寄存 3 */ // __IM uint32_t RESERVED11[3]; // __IOM uint32_t RF_REG0; /*!< (@ 0x000001b0) CRP 通用寄存器 */ // __IOM uint32_t RF_REG1; /*!< (@ 0x000001b4) USB、2.4G、ADUDIO_ADC控制寄存器 */ // __IOM uint32_t RF_REG2; /*!< (@ 0x000001b8) ADUDIO_ADC控制寄存器 2 */ // __IOM uint32_t OPA_CTRL_REG; /*!< (@ 0x000001bc) OPA 控制寄存器 */ // __IM uint32_t RESERVED13[36]; //0x000001c0 - 0x0000024C // __IOM uint32_t UART2_CLK_GRCTL; /*!< (@ 0x00000250) UART2 CLK GR */ // __IOM uint32_t UART2_CLK_CTL; /*!< (@ 0x00000254) UART2 CLK CTL */ // __IOM uint32_t I2S_CLK_CTL; /*!< (@ 0x00000258) I2S CLK CTL */ // __IOM uint32_t CAN_CLK_CTL; /*!< (@ 0x0000025C) CAN CLK CTL */ // __IOM uint32_t CMP_CTL; /*!< (@ 0x00000260) CMP CTL */ // __IOM uint32_t CMP_INT; /*!< (@ 0x00000264) CMP INT */ // __IOM uint32_t CMP_INT_RAW; /*!< (@ 0x00000268) CMP INT RAW */ // __IOM uint32_t CMP_INT_EN; /*!< (@ 0x0000026C) CMP INT EN */ // __IOM uint32_t FMC_CTL; /*!< (@ 0x00000270) FMC_CTL */ // __IOM uint32_t OTP_CTL; /*!< (@ 0x00000274) CMP EM */ //}CPR_CTL_TypeDef; //typedef struct { /*!< (@ 0x40002400) CPR AO Structure */ // __IM uint32_t RESERVED00; // __IOM uint32_t SLP_CTL; /*!< (@ 0x00000004) 睡眠控制寄存器 */ // __IOM uint32_t SLPCTL_INT_MASK; /*!< (@ 0x00000008) 睡眠唤醒 M0 中断屏蔽寄存器 */ // __IOM uint32_t SLP_PD_MASK; /*!< (@ 0x0000000C) 睡眠断电屏蔽寄存器 */ // __IOM uint32_t MCLK_DIV_CLK_CTL; /*!< (@ 0x00000010) MCLK_DIV_CLK(32K)分频控制寄存器 */ // __IOM uint32_t RFPMU_SPI_CTL; /*!< (@ 0x00000014) SPI 控制寄存器 */ // __IM uint32_t RESERVED01; // __IOM uint32_t SYS_TIME; /*!< (@ 0x0000001C) SPI 控制寄存器 */ // __IOM uint32_t BBLDO_ADJ; /*!< (@ 0x00000020) */ // __IM uint32_t RESERVED02[3]; /*!< (@ 0x00000024) */ // __IOM uint32_t RF_AON_REG; /*!< (@ 0x00000030) */ // __IOM uint32_t PE_CTRLx[2]; /*!< (@ 0x00000034) CPR AO GPIO PE Ctrl1..2 */ // __IOM uint32_t PU_CTRLx[1]; /*!< (@ 0x0000003C) CPR AO GPIO PU Ctrl1 */ // __IOM uint32_t AON_VDD_SWITCH_EN; /*!< (@ 0x00000040) */ // __IOM uint32_t AON_VDD_ISO_EN; /*!< (@ 0x00000044) */ // // __IOM uint32_t LPOLDO_ADJ; /*!< (@ 0x00000048) */ // __IM uint32_t RESERVED05[1]; /*!< (@ 0x0000004C) */ // __IOM uint32_t AON_CORERFLDO_EN; /*!< (@ 0x00000050) */ // __IOM uint32_t DCDC_CTRL[2]; /*!< (@ 0x00000054) CPR AO DCDC CTRL */ // __IOM uint32_t RESERVED04[1];/*!< (@ 0x0000005C) */ // __IM uint32_t RESERVED06[7]; /*!< (@ 0x00000060) */ // __IOM uint32_t AOCLKEN_GRCTL; /*!< (@ 0x0000007C) AO 域时钟使能寄存器 */ // __IM uint32_t RESERVED07[51]; // __IOM uint32_t CTL_CLK32K; /*!< (@ 0x0000014C) 32K 时钟配置寄存器 */ // __IM uint32_t RESERVED08[1]; // __IOM uint32_t ALWAYS_ON_REG0; /*!< (@ 0x00000154) AO 通用器 0 */ // __IOM uint32_t ALWAYS_ON_REG1; /*!< (@ 0x00000158) AO 通用器 1 */ // __IOM uint32_t AO_CTRL; /*!< (@ 0x0000015C) AO 控制寄存器 */ // __IOM uint32_t ALWAYS_ON_REG2; /*!< (@ 0x00000160) AO 通用器 2 */ // __IM uint32_t RESERVED09[2]; // __IOM uint32_t ALWAYS_ON_REG3; /*!< (@ 0x0000016C) AO 通用器 3 */ // __IOM uint32_t AON_BOR_CTRL; /*!< (@ 0x00000170) BOR控制器 */ // __IOM uint32_t ALWAYS_ON_REG4; /*!< (@ 0x00000174) AO 通用器 4 */ // //}CPR_AO_CTL_TypeDef; /* =========================================================================================================================== */ /* ================ TIMER0 ================ */ /* =========================================================================================================================== */ /** * @brief Timer/Counter 0 (TIMER0) */ //typedef struct { /*!< (@ 0x40003000) TIMER0 Structure */ // __IOM uint32_t TLC; /*!< (@ 0x00000000) Load count value into register */ // __IOM uint32_t TCV; /*!< (@ 0x00000004) current count value register */ // __IOM uint32_t TCR; /*!< (@ 0x00000008) control register */ // __IOM uint32_t TIC; /*!< (@ 0x0000000C) interrupt clear register */ // __IOM uint32_t TIS; /*!< (@ 0x00000010) Interrupt Status Register */ //}TIMER_TypeDef; //typedef struct { /*!< (@ 0x40003000) TIMER0 Structure */ // __IOM uint32_t GLOBAL_TIS; /*!< (@ 0x000000A0) Global Interrupt Status Register */ // __IOM uint32_t GLOBAL_TIC; /*!< (@ 0x000000A4) Global interrupt clear register */ // __IOM uint32_t GLOBAL_RTIS; /*!< (@ 0x000000A8) Global Raw Interrupt Status register */ // //}TIMER_GLOBAL_TypeDef; /* =========================================================================================================================== */ /* ================ RTC0 ================ */ /* =========================================================================================================================== */ /** * @brief Real time counter 0 (RTC0) */ //typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ // __IM uint32_t CCVR; /*!< (@ 0x00000000) current count value register */ // __IOM uint32_t CLR; /*!< (@ 0x00000004) Counter initial value setting register */ // __IOM uint32_t CMR_ONE; /*!< (@ 0x00000008) Timing Match Register 1 */ // __IOM uint32_t CMR_TWO; /*!< (@ 0x0000000C) Timing Match Register 2 */ // __IOM uint32_t CMR_THREE; /*!< (@ 0x00000010) Timing Match Register 3 */ // __IOM uint32_t ICR; /*!< (@ 0x00000014) Interrupt Control Register */ // __IOM uint32_t ISR_EOI; /*!< (@ 0x00000018) The interrupt status register and the interrupt clear register share one */ // __IM uint32_t WVR; /*!< (@ 0x0000001C) Current Week Counter Value Register */ // __IOM uint32_t WLR; /*!< (@ 0x00000020) Week counter initial value setting register */ // __IOM uint32_t RAW_LIMIT; /*!< (@ 0x00000024) Counting frequency setting register */ // __IOM uint32_t SECOND_LIMIT; /*!< (@ 0x00000028) Second count upper limit control register */ // __IOM uint32_t MINUTE_LIMIT; /*!< (@ 0x0000002C) Minute count upper limit control register */ // __IOM uint32_t HOUR_LIMIT; /*!< (@ 0x00000030) hour count upper limit control register */ // __IM uint32_t ISR_RAW; /*!< (@ 0x00000034) interrupt raw status register */ // __IM uint32_t RVR; /*!< (@ 0x00000038) Current second count value register */ // __IOM uint32_t RESERVED0; // __IOM uint32_t AO_TIMER_CTL; /*!< (@ 0x00000040) 16-bit Counter Control Register */ // __IOM uint32_t AO_GPIO_MODE; /*!< (@ 0x00000044) GPIO Mode Configuration Register */ // __IOM uint32_t AO_GPIO_CTL; /*!< (@ 0x00000048) GPIO Control Register */ // __IOM uint32_t ALL_INTR_AO; /*!< (@ 0x0000004C) AO Interrupt Register */ // __IM uint32_t FREQ_32K_TIMER_VAL; /*!< (@ 0x00000050) FREQ_TIMER value register */ // __IOM uint32_t RTC_CALI_CONFIG; /*!< (@ 0x00000054) */ // __IOM uint32_t RTC_CALI_RESULT; /*!< (@ 0x00000058) */ // __IOM uint32_t PWRKEY_CTRL0; /*!< (@ 0x0000005C) */ // __IOM uint32_t PWRKEY_CTRL1; /*!< (@ 0x00000060) */ // __IOM uint32_t PWRKEY_CTRL2; /*!< (@ 0x00000064) */ // __IOM uint32_t PWRKEY_SOFT_CTRL0; /*!< (@ 0x00000068) */ // __IOM uint32_t PWRKEY_SOFT_CTRL1; /*!< (@ 0x0000006C) */ // __IOM uint32_t RCCAL_EN; /*!< (@ 0x00000070) */ // __IOM uint32_t RCCAL_LFCFG; /*!< (@ 0x00000074) */ // __IOM uint32_t RCCAL_HFCFG; /*!< (@ 0x00000078) */ // __IOM uint32_t RCCAL_LIM1; /*!< (@ 0x0000007C) */ // __IOM uint32_t RCCAL_LIM2; /*!< (@ 0x00000080) */ // __IOM uint32_t RCCAL_ADJ_CFG; /*!< (@ 0x00000084) */ // __IOM uint32_t RCCAL_ADJ_STEP; /*!< (@ 0x00000088) */ // __IOM uint32_t RCCAL_HFCNT_VAL; /*!< (@ 0x0000008C) */ // __IOM uint32_t RCCAL_ADJ_VAL; /*!< (@ 0x00000090) */ // __IOM uint32_t RCCAL_STATUS; /*!< (@ 0x00000094) */ // __IOM uint32_t RCCAL_INTEN; /*!< (@ 0x00000098) */ // __IOM uint32_t RCCAL_INTSTA; /*!< (@ 0x0000009C) */ // __IOM uint32_t RCCAL_INTRAW; /*!< (@ 0x000000A0) */ // __IOM uint32_t PWRKEY_CTRL3; /*!< (@ 0x000000A4) */ // //}RTC_TypeDef; /* =========================================================================================================================== */ /* ================ Device Specific Peripheral Address Map ================ */ /* =========================================================================================================================== */ /** * @brief GPIO Port 1 (P0) */ //typedef struct { /*!< (@ 0x40001000) P0 Structure */ // __IOM uint32_t PORT_DR[2]; /*!< (@ 0x40001000) GPIO_PORT_DRx */ // __IM uint32_t RESERVED[6]; // __IOM uint32_t PORT_DDR[2]; /*!< (@ 0x40001020) GPIO_PORT_DATA DRx */ // __IM uint32_t RESERVED1[6]; // __IOM uint32_t EXT_PORT[2]; /*!< (@ 0x40001040) Read GPIO port */ // __IM uint32_t RESERVED2[46]; // __IOM uint32_t INTR_CTRL[8]; /*!< (@ 0x40001100) Intr ctr GPIO port */ // __IM uint32_t RESERVED3[24]; // __IOM uint32_t DEBOUNCE[2]; /*!< (@ 0x40001180) Set individual bits in GPIO port */ // __IM uint32_t RESERVED4[6]; // __IM uint32_t INTR_RAW[1]; /*!< (@ 0x400011A0) Intr RAW */ // __IM uint32_t RESERVED5[3]; // __IOM uint32_t INTR_CLR[2]; /*!< (@ 0x400011B0) Intr Clear */ // __IM uint32_t RESERVED6[18]; // __IOM uint32_t INTR_MASK_C0[2]; /*!< (@ 0x40001200) DIR set register */ // __IM uint32_t RESERVED7[6]; // __IM uint32_t INTR_STATUS_C0[1]; /*!< (@ 0x40001220) 中断状态寄存器 */ // //}GPIO_TypeDef; /*!< Size = 548 (0x224) */ //typedef union //{ // __IM uint32_t RBR; // __OM uint32_t THR; // __IOM uint32_t DLL; //} REG0; // //typedef union //{ // __IOM uint32_t IER; // __IOM uint32_t DLH; //} REG1; //typedef union //{ // __IM uint32_t IIR; // __OM uint32_t FCR; //} REG2; //typedef struct { /*!< (@ 0x40011000) UART1 Structure */ // REG0 RBR_THR_DLL; // REG1 IER_DLH; // REG2 IIR_FCR; // __IOM uint32_t TCR; // __IOM uint32_t MCR; // __IM uint32_t TSR; // __IM uint32_t MSR; // __IM uint32_t RESERVED4[24]; // __IM uint32_t USR; //}UART_TypeDef; /* =========================================================================================================================== */ /* ================ SPIM0_NS ================ */ /* =========================================================================================================================== */ /** * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0_NS) */ //typedef struct { /*!< (@ 0x40014000) SPIM1_NS Structure */ // __IOM uint32_t CTRL0; /*!< (@ 0x00000000) */ // __IOM uint32_t CTRL1; /*!< (@ 0x00000004) */ // __IOM uint32_t EN; /*!< (@ 0x00000008) */ // __IM uint32_t RESERVED0; // __IOM uint32_t SE; /*!< (@ 0x00000010) */ // __IOM uint32_t BAUD; /*!< (@ 0x00000014) */ // __IOM uint32_t TXFTL; /*!< (@ 0x00000018) */ // __IOM uint32_t RXFTL; /*!< (@ 0x0000001C) */ // __IM uint32_t TXFL; /*!< (@ 0x00000020) */ // __IM uint32_t RXFL; /*!< (@ 0x00000024) */ // __IM uint32_t STS; /*!< (@ 0x00000028) */ // __IOM uint32_t IE; /*!< (@ 0x0000002C) */ // __IM uint32_t IS; /*!< (@ 0x00000030) */ // __IM uint32_t RIS; /*!< (@ 0x00000034) */ // __IM uint32_t TXOIC; /*!< (@ 0x00000038) */ // __IM uint32_t RXOIC; /*!< (@ 0x0000003C) */ // __IM uint32_t RXUIC; /*!< (@ 0x00000040) */ // __IM uint32_t RESERVED1; // __IM uint32_t IC; /*!< (@ 0x00000048) */ // __IOM uint32_t DMAS; /*!< (@ 0x0000004C) */ // __IOM uint32_t DMATDL; /*!< (@ 0x00000050) */ // __IOM uint32_t DMARDL; /*!< (@ 0x00000054) */ // __IM uint32_t RESERVED2[2]; // __IOM uint32_t DATA; /*!< (@ 0x00000060) */ // __IM uint32_t RESERVED3[36]; // __IOM uint32_t SSI2_SPI_CTRLR0; /*!< (@ 0x000000F4) */ //} SPI_TypeDef; /* =========================================================================================================================== */ /* ================ I2C ================ */ /* =========================================================================================================================== */ /** * @brief I2C compatible Two-Wire Interface 0 (I2C0) */ //typedef struct { /*!< (@ 0x40006000) I2C Structure */ // __IOM uint32_t I2C_CON; /*!< (@ 0x00000000) */ // __IOM uint32_t I2C_TAR; /*!< (@ 0x00000004) */ // __IOM uint32_t I2C_SAR; /*!< (@ 0x00000008) */ // __IM uint32_t RESERVED0; // __IOM uint32_t I2C_DATA_CMD; /*!< (@ 0x00000010) */ // __IOM uint32_t I2C_SS_SCL_HCNT; /*!< (@ 0x00000014) */ // __IOM uint32_t I2C_SS_SCL_LCNT; /*!< (@ 0x00000018) */ // __IOM uint32_t I2C_FS_SCL_HCNT; /*!< (@ 0x0000001c) */ // __IOM uint32_t I2C_FS_SCL_LCNT; /*!< (@ 0x00000020) */ // __IM uint32_t RESERVED1[2]; // __IOM uint32_t I2C_INTR_STAT; /*!< (@ 0x0000002C) */ // __IOM uint32_t I2C_INTR_EN; /*!< (@ 0x00000030) */ // __IOM uint32_t I2C_RAW_INTR_STAT; /*!< (@ 0x00000034) */ // __IOM uint32_t I2C_RX_TL; /*!< (@ 0x00000038) */ // __IOM uint32_t I2C_TX_TL; /*!< (@ 0x0000003c) */ // // __IM uint32_t I2C_CLR_INTR; /*!< (@ 0x00000040) */ // __IM uint32_t I2C_CLR_RX_UNDER; /*!< (@ 0x00000044) */ // __IM uint32_t I2C_CLR_RX_OVER; /*!< (@ 0x00000048) */ // __IM uint32_t I2C_CLR_TX_OVER; /*!< (@ 0x0000004c) */ // // __IM uint32_t I2C_CLR_RD_REQ; /*!< (@ 0x00000050) */ // __IM uint32_t I2C_CLR_TX_ABRT; /*!< (@ 0x00000054) */ // __IM uint32_t I2C_CLR_RX_DONE; /*!< (@ 0x00000058) */ // __IM uint32_t I2C_CLR_ACTIVITY; /*!< (@ 0x0000005c) */ // // __IM uint32_t I2C_CLR_STOP_DET; /*!< (@ 0x00000060) */ // __IM uint32_t I2C_CLR_START_DET; /*!< (@ 0x00000064) */ // __IM uint32_t I2C_CLR_GEN_CALL; /*!< (@ 0x00000068) */ // __IOM uint32_t I2C_ENABLE; /*!< (@ 0x0000006c) */ // __IM uint32_t I2C_STATUS; /*!< (@ 0x00000070) */ // __IM uint32_t I2C_TXFLR; /*!< (@ 0x00000074) */ // __IM uint32_t I2C_RXFLR; /*!< (@ 0x00000078) */ // __IOM uint32_t I2C_SDA_HOLD; /*!< (@ 0x0000007c) */ // __IOM uint32_t I2C_TX_ABRT_SOURCE; /*!< (@ 0x00000080) */ // //} I2C_TypeDef; /* =========================================================================================================================== */ /* ================ WDT ================ */ /* =========================================================================================================================== */ /** * @brief Watchdog Timer (WDT) */ //typedef struct { /*!< (@ 0x40010000) WDT Structure */ // __IOM uint32_t CR; /*!< (@ 0x00000000) control register */ // __IOM uint32_t TORR; /*!< (@ 0x00000004) Timeout Range Register */ // __IOM uint32_t CCVR; /*!< (@ 0x00000008) current count value register */ // __OM uint32_t CRR; /*!< (@ 0x0000000c) Counter restart register */ // __IM uint32_t STAT; /*!< (@ 0x00000010) Interrupt Status Register */ // __IM uint32_t ICR; /*!< (@ 0x00000014) interrupt clear register */ // //} WDT_TypeDef; /* =========================================================================================================================== */ /* ================ GPADC ================ */ /* =========================================================================================================================== */ /** * @brief Successive approximation register (SAR) analog-to-digital converter (SAADC) */ //typedef struct { /*!< (@ 0x40018000) SAADC Structure */ // __IOM uint32_t MAIN_CTL; /*!< (@ 0x00000000) */ // __IOM uint32_t CHAN_CTL; /*!< (@ 0x00000004) */ // __IOM uint32_t FIFO_CTL; /*!< (@ 0x00000008) */ // __IOM uint32_t TIMER0; /*!< (@ 0x0000000C) */ // __IOM uint32_t TIMER1 ; /*!< (@ 0x00000010) */ // __IOM uint32_t INT ; /*!< (@ 0x00000014) */ // __IM uint32_t INT_RAW; /*!< (@ 0x00000018) */ // __IOM uint32_t INT_EN; /*!< (@ 0x0000001C) */ // __IM uint32_t FIFO; /*!< (@ 0x00000020) */ // __IOM uint32_t RF_CTL; /*!< (@ 0x00000024) */ //} ADC_TypeDef; /* =========================================================================================================================== */ /* ================ QDEC ================ */ /* =========================================================================================================================== */ /** * @brief Quadrature Decoder (QDEC) */ // typedef struct { /*!< (@ 0x40016000UL) QDEC Structure */ // __IOM uint32_t QDEC_CTL; /*!< (@ 0x00000000) QDEC Control Register */ // __IOM uint32_t SAMP_CTL; /*!< (@ 0x00000004) QDEC Sample Control Register */ // __IM uint32_t SAMPLE; /*!< (@ 0x00000008) QDEC Sample State Register */ // __IM uint32_t ACC; /*!< (@ 0x0000000C) QDEC Acc Counter Now Register */ // __IM uint32_t ACC_R; /*!< (@ 0x00000010) QDEC Acc Counter Record Register */ // __IM uint32_t DB; /*!< (@ 0x00000014) QDEC Double Bounce Counter Now Register */ // __IM uint32_t DB_R; /*!< (@ 0x00000018) QDEC Double Bounce Counter Record Register */ // __IOM uint32_t INT; /*!< (@ 0x0000001C) QDEC Interrupt Register */ // __IOM uint32_t INT_MSK; /*!< (@ 0x00000020) QDEC Interrupt Mask Register */ // __IM uint32_t QDEC_STAT; /*!< (@ 0x00000024) QDEC Counter Busy State Register */ // } QDEC_TypeDef; /* =========================================================================================================================== */ /* ================ PWM ================ */ /* =========================================================================================================================== */ /** * @brief Pulse width modulation unit (PWM) */ //typedef struct { /*!< (@ 0x40017000UL) PWM Structure */ // __IOM uint32_t EN; /*!< (@ 0x00000000) PWM EN Register */ // __IOM uint32_t UP; /*!< (@ 0x00000004) PWM UPDATE Register */ // __IOM uint32_t RST; /*!< (@ 0x00000008) PWM RST Register */ // __IOM uint32_t PERIOD; /*!< (@ 0x0000000c) PWM Period Register */ // __IOM uint32_t OCPY; /*!< (@ 0x00000010) PWM OCPY Register */ // __IOM uint32_t PWMCOMPEN; /*!< (@ 0x00000014) PWM COMP EN Register */ // __IOM uint32_t PWMCOMPTIME; /*!< (@ 0x00000018) PWM COMP TIME Register */ // __IM uint32_t RESERVED[1]; // __IOM uint32_t PWM_BREAK_CTL; /*!< (@ 0x00000020)PWM_BREAK_CTL Register */ //} PWM_TypeDef; //typedef struct { /*!< (@ 0x40017000UL) PWM Structure */ // __IOM uint32_t EN; /*!< (@ 0x00000000) PWM EN Register */ // __IOM uint32_t UP; /*!< (@ 0x00000004) PWM UPDATE Register */ // __IOM uint32_t RST; /*!< (@ 0x00000008) PWM RST Register */ // __IOM uint32_t PERIOD; /*!< (@ 0x0000000c) PWM Period Register */ // __IOM uint32_t OCPY; /*!< (@ 0x00000010) PWM OCPY Register */ // __IM uint32_t RESERVED[2]; // __IOM uint32_t PWMCOMPEN; /*!< (@ 0x0000001C) PWM COMP EN Register */ // __IOM uint32_t PWMCOMPTIME; /*!< (@ 0x00000020) PWM OCPYCOMP TIME Register */ //} PWM_TypeDef; /** * @brief Pulse width modulation unit (PWM_COMMON) */ //typedef struct { /*!< (@ 0x40017C00UL) PWM Structure */ // __IM uint32_t CAP_TIM0_VAL; /*!< (@ 0x00000000) */ // __IM uint32_t CAP_TIM1_VAL; /*!< (@ 0x00000004) */ // __IM uint32_t CAP_TIM2_VAL; /*!< (@ 0x00000008) */ // __IOM uint32_t CAP_TIM_INT; /*!< (@ 0x0000000C) */ // __IOM uint32_t CAP_TIM_INT_EN; /*!< (@ 0x00000010) */ // __IM uint32_t CAP_TIM_INT_RAW; /*!< (@ 0x00000014) */ // __IOM uint32_t CAP_TIM0_CTL; /*!< (@ 0x00000018) */ // __IOM uint32_t CAP_TIM1_CTL; /*!< (@ 0x0000001C) */ // __IOM uint32_t CAP_TIM2_CTL; /*!< (@ 0x00000020) */ //}PWM_COMMON_TypeDef; /* =========================================================================================================================== */ /* ================ PWM Timer ================ */ /* =========================================================================================================================== */ /** * @brief APB Timer N register */ //typedef struct { // /* data */ // __IOM uint32_t TLC; /*!< (@ 0x00000000) TimerN Load Count Register */ // __IM uint32_t TCV; /*!< (@ 0x00000004) TimerN Current Count Value Register */ // __IOM uint32_t TCR; /*!< (@ 0x00000008) TimerN Control Register */ // __IM uint32_t TEOI; /*!< (@ 0x0000000C) TimerN End-of-Interrupt Register */ // __IM uint32_t TIS; /*!< (@ 0x00000010) TimerN Interrupt Status Register */ //} APB_TIMERn_TypeDef; /** * @brief PWM Timer register */ //typedef struct { // /* data */ // APB_TIMERn_TypeDef TimerN[6]; // __IM uint32_t RESERVED0[10]; /*!< (@ 0x00000078)-->(@ 0x0000009C) Reserved */ // __IM uint32_t A_TIS; /*!< (@ 0x000000A0) All Timers Interrupt Status Register */ // __IM uint32_t A_TEOI; /*!< (@ 0x000000A4) All Timers End-of-Interrupt Register */ // __IM uint32_t A_TRIS; /*!< (@ 0x000000A8) All Timers Raw Interrupt Status Register */ // __IM uint32_t TCOMP; /*!< (@ 0x000000AC) Timers Component Version */ // __IOM uint16_t T1_LC2; /*!< (@ 0x000000B0) Timer1 Load Count2 Register */ // __IM uint16_t RESERVED1; // __IOM uint16_t T2_LC2; /*!< (@ 0x000000B4) Timer2 Load Count2 Register */ // __IM uint16_t RESERVED2; // __IOM uint16_t T3_LC2; /*!< (@ 0x000000B8) Timer3 Load Count2 Register */ // __IM uint16_t RESERVED3; // __IOM uint16_t T4_LC2; /*!< (@ 0x000000BC) Timer4 Load Count2 Register */ // __IM uint16_t RESERVED4; // __IOM uint16_t T5_LC2; /*!< (@ 0x000000C0) Timer5 Load Count2 Register */ // __IM uint16_t RESERVED5; // __IOM uint16_t T6_LC2; /*!< (@ 0x000000C4) Timer4 Load Count2 Register */ // __IM uint16_t RESERVED6; //} PWM_TIMER_TypeDef; /* =========================================================================================================================== */ /* ================ CAN ================ */ /* =========================================================================================================================== */ //typedef struct { // // __IOM uint32_t Frame_Information; // __IOM uint32_t ID[2]; // __IOM uint32_t DATA[8]; // //} CAN_SFF_TypeDef; //typedef struct { // // __IOM uint32_t Frame_Information; // __IOM uint32_t ID[4]; // __IOM uint32_t DATA[8]; // //} CAN_EFF_TypeDef; //typedef struct { // // __IOM uint32_t ACR[4]; // __IOM uint32_t AMR[4]; // //} CAN_Filter_TypeDef; //typedef union //{ // CAN_SFF_TypeDef CAN_SFF; // CAN_EFF_TypeDef CAN_EFF; // CAN_Filter_TypeDef CAN_Filter; //} CAN_FRAME_TypeDef; //typedef struct { // // __IOM uint32_t MOD; /*!< (@ 0x00000000) */ // __IOM uint32_t CMR; /*!< (@ 0x00000004) */ // __IOM uint32_t SR; /*!< (@ 0x00000008) */ // __IOM uint32_t IR; /*!< (@ 0x0000000C) */ // __IOM uint32_t IER; /*!< (@ 0x00000010) */ // __IM uint32_t RESERVED0[1]; /*!< (@ 0x00000014) */ // __IOM uint32_t BTR0; /*!< (@ 0x00000018) */ // __IOM uint32_t BTR1; /*!< (@ 0x0000001C) */ // __IOM uint32_t OCR ; /*!< (@ 0x00000020) */ // __IM uint32_t RESERVED1[2]; /*!< (@ 0x00000024) */ // __IOM uint32_t ALC; /*!< (@ 0x0000002C) */ // __IOM uint32_t ECC; /*!< (@ 0x00000030) */ // __IOM uint32_t EWLR; /*!< (@ 0x00000034) */ // __IOM uint32_t RXERR; /*!< (@ 0x00000038) */ // __IOM uint32_t TXERR; /*!< (@ 0x0000003C) */ // CAN_FRAME_TypeDef CAN_FRAME; /*!< (@ 0x00000040) */ // __IOM uint32_t RMC; /*!< (@ 0x00000074) */ // __IOM uint32_t RBSA; /*!< (@ 0x00000078) */ // __IOM uint32_t CDR; /*!< (@ 0x0000007C) */ //} CAN_TypeDef; /* =========================================================================================================================== */ /* ================ BT RF ================ */ /* =========================================================================================================================== */ /* BT RF Register Typedef */ //typedef struct { // __IOM uint16_t ana0_reg_l; /* RF analog0 Reg (0x000) */ // __IOM uint16_t ana0_reg_h; // __IOM uint16_t ana1_reg_l; /* RF analog1 Reg (0x004) */ // __IOM uint16_t ana1_reg_h; // __IOM uint16_t ana2_reg_l; /* RF analog2 Reg (0x008) */ // __IOM uint16_t ana2_reg_h; // __IOM uint16_t ana3_reg_l; /* RF analog3 Reg (0x00C) */ // __IOM uint16_t ana3_reg_h; // __IOM uint16_t ana4_reg_l; /* RF analog4 Reg (0x010) */ // __IOM uint16_t ana4_reg_h; // __IOM uint16_t ana5_reg_l; /* RF analog5 Reg (0x014) */ // __IOM uint16_t ana5_reg_h; // __IOM uint16_t ana6_reg_l; /* RF analog6 Reg (0x018) */ // __IOM uint16_t ana6_reg_h; // __IOM uint16_t ana7_reg_l; /* RF analog7 Reg (0x01C) */ // __IOM uint16_t ana7_reg_h; // __IOM uint16_t ana8_reg_l; /* RF analog8 Reg (0x020) */ // __IOM uint16_t ana8_reg_h; // __IOM uint16_t ana9_reg_l; /* RF analog9 Reg (0x024) */ // __IOM uint16_t ana9_reg_h; // __IOM uint16_t ana10_reg_l; /* RF analog10 Reg (0x028) */ // __IOM uint16_t ana10_reg_h; // __IOM uint16_t ana11_reg_l; /* RF analog11 Reg (0x02C) */ // __IOM uint16_t ana11_reg_h; // __IOM uint16_t ana12_reg_l; /* RF analog12 Reg (0x030) */ // __IOM uint16_t ana12_reg_h; // __IOM uint16_t ana13_reg_l; /* RF analog13 Reg (0x034) */ // __IOM uint16_t ana13_reg_h; // __IOM uint16_t ana14_reg_l; /* RF analog14 Reg (0x038) */ // __IOM uint16_t ana14_reg_h; // __IOM uint16_t ana15_reg_l; /* RF analog15 Reg (0x03C) */ // __IOM uint16_t ana15_reg_h; // __IOM uint16_t ana16_reg_l; /* RF analog16 Reg (0x040) */ // __IOM uint16_t ana16_reg_h; // __IOM uint16_t ana17_reg_l; /* RF analog17 Reg (0x044) */ // __IOM uint16_t ana17_reg_h; // __IOM uint16_t ana18_reg_l; /* RF analog18 Reg (0x048) */ // __IOM uint16_t ana18_reg_h; // __IOM uint16_t ana19_reg_l; /* RF analog19 Reg (0x04C) */ // __IOM uint16_t ana19_reg_h; // __IOM uint16_t ana20_reg_l; /* RF analog20 Reg (0x050) */ // __IOM uint16_t ana20_reg_h; // __IOM uint16_t ana21_reg_l; /* RF analog21 Reg (0x054) */ // __IOM uint16_t ana21_reg_h; // __IOM uint32_t reserved1[2]; /* Reserved (0x058) - (0x05c) */ // __IOM uint16_t ana24_reg_l; /* RF analog24 Reg (0x060) */ // __IOM uint16_t ana24_reg_h; // __IOM uint16_t ana25_reg_l; /* RF analog25 Reg (0x064) */ // __IOM uint16_t ana25_reg_h; // __IOM uint16_t ana26_reg_l; /* RF analog26 Reg (0x068) */ // __IOM uint16_t ana26_reg_h; // __IOM uint16_t ana27_reg_l; /* RF analog27 Reg (0x06C) */ // __IOM uint16_t ana27_reg_h; // __IOM uint16_t ana28_reg_l; /* RF analog28 Reg (0x070) */ // __IOM uint16_t ana28_reg_h; // __IOM uint16_t ana29_reg_l; /* RF analog29 Reg (0x074) */ // __IOM uint16_t ana29_reg_h; // __IOM uint16_t ana30_reg_l; /* RF analog30 Reg (0x078) */ // __IOM uint16_t ana30_reg_h; // __IOM uint16_t ana31_reg_l; /* RF analog31 Reg (0x07C) */ // __IOM uint16_t ana31_reg_h; // __IOM uint16_t rccal_reg_l; /* RF rccal Reg (0x080) */ // __IOM uint16_t rccal_reg_h; // __IOM uint16_t rccal_rslt_l; /* RF rccal result Reg (0x084) */ // __IOM uint16_t rccal_rslt_h; // struct { // __IOM uint16_t rx_lna_map0_l; /* BT rx lna map0 Reg (0x088) */ // __IOM uint16_t rx_lna_map0_h; // __IOM uint16_t rx_lna_map1_l; /* BT rx lna map1 Reg (0x08C) */ // __IOM uint16_t rx_lna_map1_h; // __IOM uint16_t rx_vga_map0_l; /* BT rx vga map0 Reg (0x090) */ // __IOM uint16_t rx_vga_map0_h; // __IOM uint16_t rx_vga_map1_l; /* BT rx vga map1 Reg (0x094) */ // __IOM uint16_t rx_vga_map1_h; // __IOM uint16_t rx_vga_map2_l; /* BT rx vga map2 Reg (0x098) */ // __IOM uint16_t rx_vga_map2_h; // __IOM uint16_t rx_vga_map3_l; /* BT rx vga map3 Reg (0x09C) */ // __IOM uint16_t rx_vga_map3_h; // __IOM uint16_t rx_vga_map4_l; /* BT rx vga map4 Reg (0x0A0) */ // __IOM uint16_t rx_vga_map4_h; // __IOM uint16_t rx_vga_map5_l; /* BT rx vga map5 Reg (0x0A4) */ // __IOM uint16_t rx_vga_map5_h; // __IOM uint16_t rx_vga_map6_l; /* BT rx vga map6 Reg (0x0A8) */ // __IOM uint16_t rx_vga_map6_h; // __IOM uint16_t rx_vga_map7_l; /* BT rx vga map7 Reg (0x0AC) */ // __IOM uint16_t rx_vga_map7_h; // __IOM uint16_t rx_pm_reg_l; /* BT rx pm Reg (0x0B0) */ // __IOM uint16_t rx_pm_reg_h; // __IOM uint16_t rx_chan_reg_l; /* BT rx chan Reg (0x0B4) */ // __IOM uint16_t rx_chan_reg_h; // __IOM uint16_t rx_ctrl_sel_l; /* BT rx control select Reg (0x0B8) */ // __IOM uint16_t rx_ctrl_sel_h; // } BT; //} BT_RF_TypeDef; /* =========================================================================================================================== */ /* ================ 2.4G ================ */ /* =========================================================================================================================== */ /* RF 2.4G Module Register Typedef */ // typedef struct { // __IOM uint32_t CFG_TOP; /*!< Top-level configuration (0x000) */ // __IOM uint32_t EN_AA; /*!< Auto-acknowledgement settings (0x004) */ // __IOM uint32_t EN_RXADDR; /*!< Enable RX addresses (0x008) */ // __IOM uint32_t SETUP_AW; /*!< Address width & timing stup (0x00C) */ // __IOM uint32_t SETUP_RETR; /*!< Automatic retransmission setup (0x010) */ // __IOM uint32_t RF_CH; /*!< RF channel (0x014) */ // __IOM uint32_t SETUP_RF; /*!< RF settings (0x018) */ // __IOM uint32_t STATUS; /*!< Status, SDO output may be adjusted (0x01C) */ // __IOM uint32_t OBSERVE_TX; /*!< Transmission observation (0x020) */ // __IOM uint32_t RSSI; /*!< TSSI and RSSI indicator/control (0x024) */ // __IOM uint32_t RX_ADDR_P0_L; /*!< RX address low 32bit for data pipe 0 (0x028) */ // __IOM uint32_t RX_ADDR_P0_H; /*!< RX address high 8bit for data pipe 0 (0x02C) */ // __IOM uint32_t RX_ADDR_P1_L; /*!< RX address low 32bit for data pipe 1 (0x030) */ // __IOM uint32_t RX_ADDR_P1_H; /*!< RX address high 8bit for data pipe 1 (0x034) */ // __IOM uint32_t RX_ADDR_P2TOP5; /*!< Only LSB are set, MSB use RX_ADDR_P1 (0x038) */ // __IOM uint32_t BER_RECV_CNT; /*!< Receive total Bit Counter for BER Test (0x03C) */ // __IOM uint32_t BER_ERR_CNT; /*!< Receive error Bit Counter for BER Test (0x040) */ // __IOM uint32_t AGC_SETTING; /*!< AGC setting (0x044) */ // __IOM uint32_t PGA_SETTING; /*!< PGA setting (0x048) */ // __IOM uint32_t TX_ADDR_L; /*!< TX address low 32bit (0x04C) */ // __IOM uint32_t TX_ADDR_H; /*!< TX address high 8bit (0x050) */ // __IOM uint32_t RX_PW_Px_L; /*!< Number of bytes in data pipe0~3 (0x054) */ // __IOM uint32_t RX_PW_Px_H; /*!< Number of bytes in data pipe4~5 (0x058) */ // __IOM uint32_t ANALOG_CFG0_L; /*!< Analog register 0 low 32bit (0x05C) */ // __IOM uint32_t ANALOG_CFG0_H; /*!< Analog register 0 high 32bit (0x060) */ // __IOM uint32_t ANALOG_CFG1_L; /*!< Analog register 1 low 32bit (0x064) */ // __IOM uint32_t ANALOG_CFG1_H; /*!< Analog register 1 high 32bit (0x068) */ // __IOM uint32_t ANALOG_CFG2_L; /*!< Analog register 2 low 32bit (0x06C) */ // __IOM uint32_t ANALOG_CFG2_H; /*!< Analog register 2 high 32bit (0x070) */ // __IOM uint32_t ANALOG_CFG3_L; /*!< Analog register 3 low 32bit (0x074) */ // __IOM uint32_t ANALOG_CFG3_H; /*!< Analog register 3 high 32bit (0x078) */ // __IM uint32_t Reserved1; /*!< Reserved1 (0x07C) */ // __IOM uint32_t STATUS_FIFO; /*!< FIFO status (0x080) */ // __IOM uint32_t RSSIREC; /*!< RSSI recorder feature (0x084) */ // __IOM uint32_t TXPROC_CFG; /*!< TX Process configuration (0x088) */ // __IOM uint32_t RXPROC_CFG_L; /*!< RX Process configuration (0x08C) */ // __IM uint32_t Reserved2; /*!< Reserved2 (0x090) */ // __IOM uint32_t DYNPD; /*!< Dynamic payload length (0x094) */ // __IOM uint32_t FEATURE; /*!< Features (0x098) */ // __IM uint32_t Reserved3[3]; /*!< Reserved3 (0x09C - 0x0A4) */ // __IOM uint32_t RXPROC_CFG_H; /*!< PA Ramp Configuration (0x0A8) */ // __IM uint32_t Reserved4[5]; /*!< Reserved4 (0x0AC - 0x0BC) */ // __IOM uint32_t CMD_CFG; /*!< Command Configuration (0x0C0) */ // __IOM uint32_t TX_FIFO_DATA; /*!< Tx Fifo Data (0x0C4) */ // __IOM uint32_t RX_FIFO_DATA; /*!< Rx Fifo Data (0x0C8) */ // __IOM uint32_t RX_FIFO_LEN; /*!< Tx Fifo Data Len (0x0CC) */ // } RF_2_4G_TypeDef; /* =========================================================================================================================== */ /* ================ USB ================ */ /* =========================================================================================================================== */ ///** // * @brief USB_OTG_Core_Registers // */ //typedef struct //{ // __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ // __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ // __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ // __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ // __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ // __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ // __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ // __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ // __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ // __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ // __IO uint32_t GNPTXFSIZ; /*!< Non Periodic Tx FIFO Size Register 028h */ // __IO uint32_t GNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ //// uint32_t Reserved30[57]; /*!< Reserved 0x30-0x110 */ //} USB_OTG_GlobalTypeDef; ///** // * @brief USB_OTG_device_Registers // */ //typedef struct //{ // __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ // __IO uint32_t DCTL; /*!< dev Control Register 804h */ // __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ // __I uint32_t Reserved0C; /*!< Reserved 80Ch */ // __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ // __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ // __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ // __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ // __I uint32_t DTKNQR1; /*!< dev IN Token Seq Reg 1 820h */ // __I uint32_t DTKNQR2; /*!< dev IN Token Seq Reg 2 824h */ // __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ // __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ // __I uint32_t DTKNQR3; /*!< dev IN Token Seq Reg 3 830h */ // __I uint32_t DTKNQR4; /*!< dev IN Token Seq Reg 4 834h */ //} USB_OTG_DeviceTypeDef; ///** // * @brief USB_OTG_IN_Endpoint-Specific_Register // */ //typedef struct //{ // __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ // uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ // __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ // uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ // __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ // uint32_t Reserved14; /*!< Reserved 900h + (ep_num * 20h) + 14h */ // __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ // uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ //} USB_OTG_INEndpointTypeDef; /** * @brief USB_OTG_OUT_Endpoint-Specific_Registers */ /** * @brief USB_OTG_OUT_Endpoint-Specific_Registers */ //typedef struct //{ // __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ // uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ // __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ // uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ // __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ // uint32_t Reserved14[5]; /*!< Reserved B00h + (ep_num * 20h) + 14h - B00h + (ep_num * 20h) + 1Ch */ //} USB_OTG_OUTEndpointTypeDef; /** @addtogroup Device_Peripheral_peripheralAddr * @{ */ //#define XC_CPR_BASE 0x40000000UL //#define XC_GPIO_BASE 0x40001000UL //#define XC_RTC_BASE 0x40002000UL //#define XC_CPR_AO_BASE 0x40002400UL //#define XC_AOTIMER0_BASE 0x40002800UL //#define XC_AOTIMER1_BASE 0x40002814UL //#define XC_TIMER0_BASE 0x40003000UL //#define XC_TIMER1_BASE 0x40003014UL //#define XC_TIMER2_BASE 0x40003028UL //#define XC_TIMER3_BASE 0x4000303CUL //#define XC_WDT_BASE 0x40004000UL //#define XC_I2C_BASE 0x40006000UL //#define XC_UART0_BASE 0x40010000UL //#define XC_UART1_BASE 0x40011000UL //#define XC_UART2_BASE 0x40011400UL //#define XC_I2S_BASE 0x40011800UL //#define XC_CAN_BASE 0x40011C00UL //#define XC_SPI0_BASE 0x40013000UL //#define XC_SPI1_BASE 0x40014000UL //#define XC_SPI2_BASE 0x40014800UL //#define XC_QDEC_BASE 0x40016000UL //#define XC_PWM0_BASE 0x40017000UL //#define XC_PWM1_BASE 0x40017040UL //#define XC_PWM2_BASE 0x40017400UL //#define XC_PWM3_BASE 0x40017440UL //#define XC_PWM4_BASE 0x40017800UL //#define XC_PWM5_BASE 0x40017840UL //#define XC_PWM_COMMON_BASE 0x40017C00UL //#define XC_PWM_TIMER_BASE 0x40017D00UL //#define XC_ADC_BASE 0x40018000UL //#define XC_DMA_BASE 0x50001000UL //#define XC_FMC_BASE 0x51000000UL //#define XC_FMC_CACHE_BASE 0x52000000UL //#define XC_BLE_COMMON_BASE 0x53022000UL //#define XC_BT_RF_BASE 0x53021000UL //#define XC_RF_2_4G_BASE 0x53023000UL //#define XC_USB_FS_PERIPH_BASE 0x50010000UL /* =========================================================================================================================== */ /* ================ Peripheral declaration ================ */ /* =========================================================================================================================== */ /** @addtogroup Device_Peripheral_declaration * @{ */ //#define XC_CPR ((CPR_CTL_TypeDef*) XC_CPR_BASE) //#define XC_GPIO ((GPIO_TypeDef*) XC_GPIO_BASE) //#define XC_RTC ((RTC_TypeDef*) XC_RTC_BASE) //#define XC_CPR_AO ((CPR_AO_CTL_TypeDef*) XC_CPR_AO_BASE) //#define XC_AOTIMER0 ((TIMER_TypeDef*) XC_AOTIMER0_BASE) //#define XC_AOTIMER1 ((TIMER_TypeDef*) XC_AOTIMER1_BASE) //#define XC_TIMER0 ((TIMER_TypeDef*) XC_TIMER0_BASE) //#define XC_TIMER1 ((TIMER_TypeDef*) XC_TIMER1_BASE) //#define XC_TIMER2 ((TIMER_TypeDef*) XC_TIMER2_BASE) //#define XC_TIMER3 ((TIMER_TypeDef*) XC_TIMER3_BASE) //#define XC_WDT ((WDT_TypeDef*) XC_WDT_BASE) //#define XC_I2C ((I2C_TypeDef*) XC_I2C_BASE) //#define XC_UART0 ((UART_TypeDef*) XC_UART0_BASE) //#define XC_UART1 ((UART_TypeDef*) XC_UART1_BASE) //#define XC_UART2 ((UART_TypeDef*) XC_UART2_BASE) //#define XC_I2S ((I2C_TypeDef*) XC_I2S_BASE) //#define XC_CAN ((CAN_TypeDef*) XC_CAN_BASE) //#define XC_SPI0 ((SPI_TypeDef*) XC_SPI0_BASE) //#define XC_SPI1 ((SPI_TypeDef*) XC_SPI1_BASE) //#define XC_SPI2 ((SPI_TypeDef*) XC_SPI2_BASE) //#define XC_QDEC ((QDEC_TypeDef*) XC_QDEC_BASE) //#define XC_PWM0 ((PWM_TypeDef*) XC_PWM0_BASE) //#define XC_PWM1 ((PWM_TypeDef*) XC_PWM1_BASE) //#define XC_PWM2 ((PWM_TypeDef*) XC_PWM2_BASE) //#define XC_PWM3 ((PWM_TypeDef*) XC_PWM3_BASE) //#define XC_PWM4 ((PWM_TypeDef*) XC_PWM4_BASE) //#define XC_PWM5 ((PWM_TypeDef*) XC_PWM5_BASE) //#define XC_PWM_COMMON ((PWM_COMMON_TypeDef*) XC_PWM_COMMON_BASE) //#define XC_PWM_TIMER ((PWM_TIMER_TypeDef*) XC_PWM_TIMER_BASE) //#define XC_ADC ((ADC_TypeDef*) XC_ADC_BASE) //#define XC_DMA ((DMAC_TypeDef*) XC_DMA_BASE) //#define XC_FMC ((FMC_TypeDef*) XC_FMC_BASE) //#define XC_FMC_CACHE ((FMC_CACHE_TypeDef*) XC_FMC_CACHE_BASE) //#define XC_BLE_COMN ((BLE_COMN_TypeDef*) XC_BLE_COMMON_BASE) //#define XC_BT_RF ((BT_RF_TypeDef *) XC_BT_RF_BASE) //#define XC_RF_2_4G ((RF_2_4G_TypeDef *) XC_RF_2_4G_BASE) //#define XC_USB_OTG_FS ((USB_OTG_GlobalTypeDef *) XC_USB_FS_PERIPH_BASE) /** @addtogroup Driver_Bitfields_Included * @{ */ //#include "xc6xxx_cpr_bitfields.h" //#include "xc6xxx_cpr_ao_bitfields.h" //#include "xc6xxx_gpio_bitfields.h" //#include "xc6xxx_timer_bitfields.h" //#include "xc6xxx_rtc_bitfields.h" //#include "xc6xxx_spi_bitfields.h" //#include "xc6xxx_fmc_spi_bitfields.h" //#include "xc6xxx_i2c_bitfields.h" //#include "xc6xxx_uart_bitfields.h" //#include "xc6xxx_qdec_bitfields.h" //#include "xc6xxx_wdt_bitfields.h" //#include "xc6xxx_adc_bitfields.h" //#include "xc6xxx_pwm_bitfields.h" //#include "xc6xxx_can_bitfields.h" //#include "xc6xxx_dmac_bitfields.h" /** * @} */ #ifdef __cplusplus } #endif #endif /* __XC60XX_H__ */