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hpw422移植新的sdk

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xushaoxiang
2026-07-03 18:08:25 +08:00
commit 945a5a5b0b
2583 changed files with 713209 additions and 0 deletions
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc20xx.h
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc26xx.h
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc60xx.h
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc62xx.h
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/*!
* \file xc62xx.h
*
* \brief The header of xc62xx chip
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __XC62XX_H__
#define __XC62XX_H__
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include <stdio.h>
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
#define __RAM_CODE __attribute__((section("ram_code")))
#define __WEAK __attribute__((weak))
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#define __STATIC_INLINE static __inline
#define FMC_SPI_DMA_OFF
#define SPI_OFF
#define SPI_DMA_OFF
#define UART_DMA_OFF
#define QDEC_USE_P12_P13
#define HFCLK_SRC_XTAL_IS_32M
#define XC62XX_CLOCK_CONFIG
#define XC62XX_ROM_DRIVER_ADDR
#define XC62XX_ADC_CALI_PARA
#define XC62XX_ADC_CHANNEL
#define BOR_VERSION_IS_V2
#define NO_SUPPORT_UART2
#define NO_SUPPORT_HFCLK_RC_16M
#define NO_SUPPORT_HFCLK_BBPLL_96M
#define NO_SUPPORT_HFCLK_BBPLL_128M
#define NO_SUPPORT_LFCLK_XTAL_32768
#define NO_SUPPORT_PWM_CAPTURE
#define NO_SUPPORT_PWM_ADC
#define NO_SUPPORT_PWM_BRAKE
#define NO_SUPPORT_PWM_LOWPOWER
#define NO_SUPPORT_DMA
#define NO_SUPPORT_DMA_LINKLIST
#define NO_SUPPORT_QUAD_SPI
#define NO_SUPPORT_M4FPU_FUNTION
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
typedef enum IRQn
{
/****** Cortex-M# Processor Exceptions Numbers ***************************************************/
/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M4 device */
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Hard Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
/****** Device Specific Interrupt Numbers ********************************************************/
/* ToDo: add here your device specific external interrupt numbers
according the interrupt handlers defined in startup_Device.s
eg.: Interrupt for Timer#1 TIM1_IRQHandler -> TIM1_IRQn */
BLE_IRQn = 0, /*!< Device Interrupt */
CPR_IRQn = 2,
GPIO_IRQn = 3,
RTC_IRQn = 4,
TIMER0_IRQn = 5,
TIMER1_IRQn = 6,
TIMER2_IRQn = 7,
TIMER3_IRQn = 8,
WDT_IRQn = 9,
I2C_IRQn = 10,
UART0_IRQn = 11,
UART1_IRQn = 12,
SPI0_IRQn = 13,
KBS_IRQn = 15,
QDEC_IRQn = 16,
GADC_IRQn = 17,
PWM_IRQn = 18,
AES_IRQn = 19,
USB_IRQn = 20,
AUDIO_IRQn = 21,
RF24G_IRQn = 22,
MPU_IRQn = 24,
I2S_IRQn = 26,
TIMER_AO0_IRQn = 27,
TIMER_AO1_IRQn = 28,
CMP_IRQn = 29,
FMC_IRQn = 30,
CAN_IRQn = 31
} IRQn_Type;
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/* Configuration of the Cortex-M# Processor and Core Peripherals */
/* ToDo: set the defines according your Device */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#if defined ( __CC_ARM )
#if defined (__TARGET_FPU_VFP)
#define __FPU_PRESENT 1 /*!< FPU present or not */
#else
#define __FPU_PRESENT 0 /*!< FPU present or not */
#endif
#else
#define __FPU_PRESENT 0 /*!< FPU present or not */
#endif
/*@}*/ /* end of group <Device>_CMSIS */
#include "core_cm0.h" /* Cortex-M4 processor and core peripherals */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __XC62XX_H__ */
component/xc6xx_drivers/Drivers/CMSIS/Device/xc65xx.h
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/*!
* \file xc65xx.h
*
* \brief The header of xc65xx chip
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __XC65XX_H__
#define __XC65XX_H__
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include <stdio.h>
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
#define __RAM_CODE __attribute__((section("ram_code")))
#define __WEAK __attribute__((weak))
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#define __STATIC_INLINE static __inline
#define QDEC_USE_P20_P21
#define HFCLK_SRC_XTAL_IS_32M
#define NO_SUPPORT_ROM_FMC_SPI
#define NO_SUPPORT_DMA_LINKLIST
#define NO_SUPPORT_QUAD_SPI
#define NO_SUPPORT_M4FPU_FUNTION
#define NO_SUPPORT_HFCLK_BBPLL_128M
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
typedef enum IRQn
{
/****** Cortex-M# Processor Exceptions Numbers ***************************************************/
/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M4 device */
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Hard Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
/****** Device Specific Interrupt Numbers ********************************************************/
/* ToDo: add here your device specific external interrupt numbers
according the interrupt handlers defined in startup_Device.s
eg.: Interrupt for Timer#1 TIM1_IRQHandler -> TIM1_IRQn */
BLE_IRQn = 0, /*!< Device Interrupt */
DMA_IRQn = 1,
CPR_IRQn = 2,
GPIO_IRQn = 3,
RTC_IRQn = 4,
TIMER0_IRQn = 5,
TIMER1_IRQn = 6,
TIMER2_IRQn = 7,
TIMER3_IRQn = 8,
WDT_IRQn = 9,
I2C_IRQn = 10,
UART0_IRQn = 11,
UART1_IRQn = 12,
SPI0_IRQn = 13,
SPI1_IRQn = 14,
KBS_IRQn = 15,
QDEC_IRQn = 16,
GADC_IRQn = 17,
PWM_IRQn = 18,
AES_IRQn = 19,
USB_IRQn = 20,
AUDIO_IRQn = 21,
RF24G_IRQn = 22,
SPI2_IRQn = 23,
MPU_IRQn = 24,
UART2_IRQn = 25,
I2S_IRQn = 26,
TIMER_AO0_IRQn = 27,
TIMER_AO1_IRQn = 28,
CMP_IRQn = 29,
FMC_IRQn = 30,
CAN_IRQn = 31
} IRQn_Type;
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/* Configuration of the Cortex-M# Processor and Core Peripherals */
/* ToDo: set the defines according your Device */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#if defined ( __CC_ARM )
#if defined (__TARGET_FPU_VFP)
#define __FPU_PRESENT 1 /*!< FPU present or not */
#else
#define __FPU_PRESENT 0 /*!< FPU present or not */
#endif
#else
#define __FPU_PRESENT 0 /*!< FPU present or not */
#endif
/*@}*/ /* end of group <Device>_CMSIS */
#include "core_cm0.h" /* Cortex-M4 processor and core peripherals */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __XC65XX_H__ */
component/xc6xx_drivers/Drivers/CMSIS/Device/xc6axx.h
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/*!
* \file xc6axx.h
*
* \brief The header of xc6axx chip
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __XC6AXX_H__
#define __XC6AXX_H__
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include <stdio.h>
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
#define __RAM_CODE __attribute__((section("ram_code")))
#define __WEAK __attribute__((weak))
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#define __STATIC_INLINE static __inline
#define QDEC_USE_P20_P21
#define HFCLK_SRC_XTAL_IS_24M
#define XC6AXX_TEST_CODE
#define NEW_BLE_COMMON_BASE
#define XC6AXX_ROM_DRIVER_ADDR
#define NO_SUPPORT_ROM_FMC_SPI
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
typedef enum IRQn
{
/* ------------------- Processor Exceptions Numbers ----------------------------- */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */
MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
SVCall_IRQn = -5, /* 11 SV Call Interrupt */
DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */
/* ------------------- Processor Interrupt Numbers ------------------------------ */
BLE_IRQn = 0, /*!< Device Interrupt */
DMA_IRQn = 1,
CPR_IRQn = 2,
GPIO_IRQn = 3,
RTC_IRQn = 4,
TIMER0_IRQn = 5,
TIMER1_IRQn = 6,
TIMER2_IRQn = 7,
TIMER3_IRQn = 8,
WDT_IRQn = 9,
I2C_IRQn = 10,
UART0_IRQn = 11,
UART1_IRQn = 12,
SPI0_IRQn = 13,
SPI1_IRQn = 14,
KBS_IRQn = 15,
QDEC_IRQn = 16,
GADC_IRQn = 17,
PWM_IRQn = 18,
AES_IRQn = 19,
USB_IRQn = 20,
CDC_IRQn = 21,
RF24G_IRQn = 22,
SPI2_IRQn = 23,
FPU_IRQn = 24,
UART2_IRQn = 25,
I2S_IRQn = 26,
TIMER_AO0_IRQn = 27,
TIMER_AO1_IRQn = 28,
CMP_IRQn = 29,
FMC_IRQn = 30,
CAN_IRQn = 31,
BT_IRQn = 32,
BT_DM_IRQn = 33,
BT_DBM_IRQn = 34,
UNUSED_IRQn
/* Interrupts 46 .. 63 are left out */
} IRQn_Type;
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/* Configuration of the Cortex-M# Processor and Core Peripherals */
/* ToDo: set the defines according your Device */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#if defined ( __CC_ARM )
#if defined (__TARGET_FPU_VFP)
#define __FPU_PRESENT 1 /*!< FPU present or not */
#else
#define __FPU_PRESENT 0 /*!< FPU present or not */
#endif
#else
#define __FPU_PRESENT 0 /*!< FPU present or not */
#endif
/*@}*/ /* end of group <Device>_CMSIS */
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
#include "compiler.h"
/* =========================================================================================================================== */
/* ================ QDEC ================ */
/* =========================================================================================================================== */
/**
* @brief Quadrature Decoder (QDEC)
*/
typedef struct { /*!< (@ 0x40016000UL) QDEC Structure */
__IOM uint32_t QDEC_CTL; /*!< (@ 0x00000000) QDEC Control Register */
__IOM uint32_t SAMP_CTL; /*!< (@ 0x00000004) QDEC Sample Control Register */
__IM uint32_t SAMPLE; /*!< (@ 0x00000008) QDEC Sample State Register */
__IM uint32_t ACC; /*!< (@ 0x0000000C) QDEC Acc Counter Now Register */
__IM uint32_t ACC_R; /*!< (@ 0x00000010) QDEC Acc Counter Record Register */
__IM uint32_t DB; /*!< (@ 0x00000014) QDEC Double Bounce Counter Now Register */
__IM uint32_t DB_R; /*!< (@ 0x00000018) QDEC Double Bounce Counter Record Register */
__IOM uint32_t INT; /*!< (@ 0x0000001C) QDEC Interrupt Register */
__IOM uint32_t INT_MSK; /*!< (@ 0x00000020) QDEC Interrupt Mask Register */
__IM uint32_t QDEC_STAT; /*!< (@ 0x00000024) QDEC Counter Busy State Register */
} QDEC_TypeDef;
/* =========================================================================================================================== */
/* ================ 2.4G ================ */
/* =========================================================================================================================== */
/* RF 2.4G Module Register Typedef */
typedef struct {
__IOM uint32_t CFG_TOP; /*!< Top-level configuration (0x000) */
__IOM uint32_t EN_AA; /*!< Auto-acknowledgement settings (0x004) */
__IOM uint32_t EN_RXADDR; /*!< Enable RX addresses (0x008) */
__IOM uint32_t SETUP_AW; /*!< Address width & timing stup (0x00C) */
__IOM uint32_t SETUP_RETR; /*!< Automatic retransmission setup (0x010) */
__IOM uint32_t RF_CH; /*!< RF channel (0x014) */
__IOM uint32_t SETUP_RF; /*!< RF settings (0x018) */
__IOM uint32_t STATUS; /*!< Status, SDO output may be adjusted (0x01C) */
__IOM uint32_t OBSERVE_TX; /*!< Transmission observation (0x020) */
__IOM uint32_t RSSI; /*!< TSSI and RSSI indicator/control (0x024) */
__IOM uint32_t RX_ADDR_P0_L; /*!< RX address low 32bit for data pipe 0 (0x028) */
__IOM uint32_t RX_ADDR_P0_H; /*!< RX address high 8bit for data pipe 0 (0x02C) */
__IOM uint32_t RX_ADDR_P1_L; /*!< RX address low 32bit for data pipe 1 (0x030) */
__IOM uint32_t RX_ADDR_P1_H; /*!< RX address high 8bit for data pipe 1 (0x034) */
__IOM uint32_t RX_ADDR_P2TOP5; /*!< Only LSB are set, MSB use RX_ADDR_P1 (0x038) */
__IOM uint32_t BER_RECV_CNT; /*!< Receive total Bit Counter for BER Test (0x03C) */
__IOM uint32_t BER_ERR_CNT; /*!< Receive error Bit Counter for BER Test (0x040) */
__IOM uint32_t AGC_SETTING; /*!< AGC setting (0x044) */
__IOM uint32_t PGA_SETTING; /*!< PGA setting (0x048) */
__IOM uint32_t TX_ADDR_L; /*!< TX address low 32bit (0x04C) */
__IOM uint32_t TX_ADDR_H; /*!< TX address high 8bit (0x050) */
__IOM uint32_t RX_PW_Px_L; /*!< Number of bytes in data pipe0~3 (0x054) */
__IOM uint32_t RX_PW_Px_H; /*!< Number of bytes in data pipe4~5 (0x058) */
__IOM uint32_t ANALOG_CFG0_L; /*!< Analog register 0 low 32bit (0x05C) */
__IOM uint32_t ANALOG_CFG0_H; /*!< Analog register 0 high 32bit (0x060) */
__IOM uint32_t ANALOG_CFG1_L; /*!< Analog register 1 low 32bit (0x064) */
__IOM uint32_t ANALOG_CFG1_H; /*!< Analog register 1 high 32bit (0x068) */
__IOM uint32_t ANALOG_CFG2_L; /*!< Analog register 2 low 32bit (0x06C) */
__IOM uint32_t ANALOG_CFG2_H; /*!< Analog register 2 high 32bit (0x070) */
__IOM uint32_t ANALOG_CFG3_L; /*!< Analog register 3 low 32bit (0x074) */
__IOM uint32_t ANALOG_CFG3_H; /*!< Analog register 3 high 32bit (0x078) */
__IM uint32_t Reserved1; /*!< Reserved1 (0x07C) */
__IOM uint32_t STATUS_FIFO; /*!< FIFO status (0x080) */
__IOM uint32_t RSSIREC; /*!< RSSI recorder feature (0x084) */
__IOM uint32_t TXPROC_CFG; /*!< TX Process configuration (0x088) */
__IOM uint32_t RXPROC_CFG_L; /*!< RX Process configuration (0x08C) */
__IM uint32_t Reserved2; /*!< Reserved2 (0x090) */
__IOM uint32_t DYNPD; /*!< Dynamic payload length (0x094) */
__IOM uint32_t FEATURE; /*!< Features (0x098) */
__IM uint32_t Reserved3[3]; /*!< Reserved3 (0x09C - 0x0A4) */
__IOM uint32_t RXPROC_CFG_H; /*!< PA Ramp Configuration (0x0A8) */
__IM uint32_t Reserved4[5]; /*!< Reserved4 (0x0AC - 0x0BC) */
__IOM uint32_t CMD_CFG; /*!< Command Configuration (0x0C0) */
__IOM uint32_t TX_FIFO_DATA; /*!< Tx Fifo Data (0x0C4) */
__IOM uint32_t RX_FIFO_DATA; /*!< Rx Fifo Data (0x0C8) */
__IOM uint32_t RX_FIFO_LEN; /*!< Tx Fifo Data Len (0x0CC) */
} RF_2_4G_TypeDef;
#ifdef __cplusplus
}
#endif
#endif /* __XC6AXX_H__ */
component/xc6xx_drivers/Drivers/CMSIS/Device/xc6xxx.h
+288
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@@ -0,0 +1,288 @@
/*!
* \file xc6xxx.h
*
* \brief CMSIS xc6xxx Device Peripheral Access Layer Header File.
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __XC6xxx_H
#define __XC6xxx_H
#ifdef __cplusplus
extern "C"
{
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
/** @addtogroup Device_Included
* @{
*/
#if defined(XC65XX)
#include "xc65xx.h"
#elif defined(XC62XX)
#include "xc62xx.h"
#elif defined(XC6AXX)
#include "xc6axx.h"
#elif defined(XC20XX)
#include "xc20xx.h"
#elif defined(XC26XX)
#include "xc26xx.h"
#elif defined(XC_LORA_XX)
#include "xc_lora_xx.h"
#else
#error "Please select first the target XC6xxx device used in your application (in xc6xxx.h file)"
#endif
#include "sdk_config.h"
/**
* @}
*/
/*------------------------------------------------------------------------------------
TypeDef
-------------------------------------------------------------------------------------*/
/** @addtogroup Exported_types
* @{
*/
typedef enum
{
RESET = 0,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
{
XR_OK = 0,
XR_ERROR,
XR_TIMEOUT,
XR_UNKNOWN = 0xFF,
} eXC_RESULT;
/**
* @}
*/
extern __RAM_CODE int sendchar(int c);
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
/** @addtogroup Exported_macro
* @{
*/
#define XC_CHECK(module_enabled) (module_enabled)
#define GD_FlASH_RDID 0x1364c8
#define BIT(n) ((1UL << (n)))
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) \
WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define REG_BIT_VAL_GET(REG, MSK, POS) ((REG & MSK) >> POS)
#define BIT_BUILD(VAL, POS, MSK) ((uint32_t)(((VAL) << POS) & MSK))
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#define MAX(a, b) ((a) < (b) ? (b) : (a))
// power of 2 macro
#define POW2(pow) (1 << (pow))
// Is A greater than or equal to B macro ?
#define A_MAXEQ_B(a, b) ((a) >= (b))
#define ALIGN_DOWN_ADDR(a, size) (a & (~(size - 1)))
#define ALIGN_UP_ADDR(a, size) ((a + size - 1) & (~(size - 1)))
#if ((defined(DEBUG_ENABLE) && (DEBUG_ENABLE != 1)) || (!defined(DEBUG_ENABLE)))
#define DEBUG_ENABLE 0
#else
#define DEBUG_ENABLE 1
#endif
#if (DEBUG_ENABLE == 1)
#define DEBUG(fmt, ...) printf(fmt, ##__VA_ARGS__)
#define PRINT(fmt, ...) printf(fmt, ##__VA_ARGS__)
#define RAM_DEBUG(str) \
{ \
const char* s = (str); \
while (*s) { \
sendchar(*s++); \
} \
}
#else
#define DEBUG(fmt, ...)
#define PRINT(fmt, ...)
#define RAM_DEBUG(str)
#endif
#define RSTN_VALID (0UL)
#define RSTN_INVALID (1UL)
#ifndef ENABLE
#define ENABLE 0x01
#endif
#ifndef DISABLE
#define DISABLE 0x00
#endif
#ifndef RSTCTL_ENABLE
#define RSTCTL_ENABLE 0x00
#endif
#ifndef RSTCTL_DISABLE
#define RSTCTL_DISABLE 0x01
#endif
#ifndef ASSERT_ERR
#define ASSERT_ERR(cond) \
{ \
}
#endif
/** @brief Enable interrupts globally in the system.
* This macro must be used when the initialization phase is over and the interrupts
* can start being handled by the system.
*/
#define GLOBAL_INT_START() ; \
do { \
__enable_irq(); \
} while(0);
#define GLOBAL_INT_STOP() ; \
do { \
__disable_irq(); \
} while(0);
#define GLOBAL_INT_DISABLE() ; \
do { \
uint32_t irq_temp; \
irq_temp = __disable_irq();
#define GLOBAL_INT_RESTORE() ; \
if(!irq_temp) \
{ \
__enable_irq(); \
} \
} while(0);
/**
* @}
*/
#include "xc_drv_conf.h"
/**
* @brief HAL Status structures definition
*/
typedef enum
{
HAL_OK = 0x00U,
HAL_ERROR = 0x01U,
HAL_BUSY = 0x02U,
HAL_TIMEOUT = 0x03U
} HAL_StatusTypeDef;
/**
* @brief HAL Lock structures definition
*/
typedef enum
{
HAL_UNLOCKED = 0x00U,
HAL_LOCKED = 0x01U
} HAL_LockTypeDef;
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
#define HAL_Delay delay_ms
void HAL_Delay(unsigned int Delay);
void Error_Handler(void);
#define __HAL_LOCK(__HANDLE__) \
do { \
if ((__HANDLE__)->Lock == HAL_LOCKED) { \
return HAL_BUSY; \
} else { \
(__HANDLE__)->Lock = HAL_LOCKED; \
} \
} while (0U)
#define __HAL_UNLOCK(__HANDLE__) \
do { \
(__HANDLE__)->Lock = HAL_UNLOCKED; \
} while (0U)
#if ((__ARMCC_VERSION % 1000) != 960)
#error "Compiler build number mismatch. Required: build 960."
#endif
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive
* "#pragma data_alignment=4" must be used instead */
#if defined(__ARMCC_VERSION) && \
(__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__((aligned(4)))
#endif
#elif defined(__GNUC__) && !defined(__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__((aligned(4)))
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#else
#ifndef __ALIGN_END
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#if defined(__CC_ARM) /* ARM Compiler V5*/
#define __ALIGN_BEGIN __align(4)
#elif defined(__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
#ifdef __cplusplus
}
#endif
#endif /* __XCxxxx_H */
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_lora_xx.h
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_adc.h
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_aotimer.h
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#ifndef _XC_REG_AOTIMER_H_
#define _XC_REG_AOTIMER_H_
#include <stdint.h>
#include "xc6xxx.h"
#define XC_REG_AOTIMER_BASE_ADDR 0x40002800
#define XC_REG_AOTIMER_DECODING_MASK 0x0000001F
/**
* @brief AOTIMER_TLC register definition
*/
#define AOTIMER_TLC_REG(i) (*(volatile uint32_t *)(0x40002800 + aotimer_offset[i]))
#define AOTIMER_TLC_ADDR(i) (0x40002800 + aotimer_offset[i])
#define AOTIMER_TLC_OFFSET 0x00000000
__INLINE uint32_t aotimer_tlc_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return AOTIMER_TLC_REG(reg_idx);
}
__INLINE void aotimer_tlc_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 1);
AOTIMER_TLC_REG(reg_idx) = value;
}
/**
* @brief AOTIMER_TCV register definition
*/
#define AOTIMER_TCV_REG(i) (*(volatile uint32_t *)(0x40002804 + aotimer_offset[i]))
#define AOTIMER_TCV_ADDR(i) (0x40002804 + aotimer_offset[i])
#define AOTIMER_TCV_OFFSET 0x00000004
__INLINE uint32_t aotimer_tcv_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return AOTIMER_TCV_REG(reg_idx);
}
/**
* @brief AOTIMER_TCR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 02 TIM 0
* 01 TMS 0
* 00 TES 0
* </pre>
*/
#define AOTIMER_TCR_REG(i) (*(volatile uint32_t *)(0x40002808 + aotimer_offset[i]))
#define AOTIMER_TCR_ADDR(i) (0x40002808 + aotimer_offset[i])
#define AOTIMER_TCR_OFFSET 0x00000008
__INLINE uint32_t aotimer_tcr_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return AOTIMER_TCR_REG(reg_idx);
}
__INLINE void aotimer_tcr_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 1);
AOTIMER_TCR_REG(reg_idx) = value;
}
// field definitions
#define TIM_BIT 0x00000004
#define TIM_POS 2
#define TMS_BIT 0x00000002
#define TMS_POS 1
#define TES_BIT 0x00000001
#define TES_POS 0
#define TIM_RST 0x0
#define TMS_RST 0x0
#define TES_RST 0x0
__INLINE void aotimer_tcr_pack(uint32_t reg_idx, uint8_t tim, uint8_t tms, uint8_t tes)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((tim << 2) & ~0x00000004) == 0);
ASSERT_ERR(((tms << 1) & ~0x00000002) == 0);
ASSERT_ERR(((tes << 0) & ~0x00000001) == 0);
AOTIMER_TCR_REG(reg_idx) = (tim << 2) | (tms << 1) | (tes << 0);
}
__INLINE void aotimer_tcr_unpack(uint32_t reg_idx, uint8_t* tim, uint8_t* tms, uint8_t* tes)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = AOTIMER_TCR_REG(reg_idx);
*tim = (localVal & 0x00000004) >> 2;
*tms = (localVal & 0x00000002) >> 1;
*tes = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t aotimer_tcr__tim__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = AOTIMER_TCR_REG(reg_idx);
return ((localVal & 0x00000004) >> 2);
}
__INLINE void aotimer_tcr__tim__setf(uint32_t reg_idx, uint8_t tim)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((tim << 2) & ~0x00000004) == 0);
AOTIMER_TCR_REG(reg_idx) = (AOTIMER_TCR_REG(reg_idx) & ~0x00000004) | (tim << 2);
}
__INLINE uint8_t aotimer_tcr__tms__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = AOTIMER_TCR_REG(reg_idx);
return ((localVal & 0x00000002) >> 1);
}
__INLINE void aotimer_tcr__tms__setf(uint32_t reg_idx, uint8_t tms)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((tms << 1) & ~0x00000002) == 0);
AOTIMER_TCR_REG(reg_idx) = (AOTIMER_TCR_REG(reg_idx) & ~0x00000002) | (tms << 1);
}
__INLINE uint8_t aotimer_tcr__tes__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = AOTIMER_TCR_REG(reg_idx);
return ((localVal & 0x00000001) >> 0);
}
__INLINE void aotimer_tcr__tes__setf(uint32_t reg_idx, uint8_t tes)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((tes << 0) & ~0x00000001) == 0);
AOTIMER_TCR_REG(reg_idx) = (AOTIMER_TCR_REG(reg_idx) & ~0x00000001) | (tes << 0);
}
/**
* @brief AOTIMER_TIC register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 TIC 0
* </pre>
*/
#define AOTIMER_TIC_REG(i) (*(volatile uint32_t *)(0x4000280C + aotimer_offset[i]))
#define AOTIMER_TIC_ADDR(i) (0x4000280C + aotimer_offset[i])
#define AOTIMER_TIC_OFFSET 0x0000000C
__INLINE uint32_t aotimer_tic_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return AOTIMER_TIC_REG(reg_idx);
}
// field definitions
#define TIC_BIT 0x00000001
#define TIC_POS 0
#define TIC_RST 0x0
__INLINE uint8_t aotimer_tic__tic__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = AOTIMER_TIC_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
/**
* @brief AOTIMER_TIS register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 TIS 0
* </pre>
*/
#define AOTIMER_TIS_REG(i) (*(volatile uint32_t *)(0x40002810 + aotimer_offset[i]))
#define AOTIMER_TIS_ADDR(i) (0x40002810 + aotimer_offset[i])
#define AOTIMER_TIS_OFFSET 0x00000010
__INLINE uint32_t aotimer_tis_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return AOTIMER_TIS_REG(reg_idx);
}
// field definitions
#define TIS_BIT 0x00000001
#define TIS_POS 0
#define TIS_RST 0x0
__INLINE uint8_t aotimer_tis__tis__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = AOTIMER_TIS_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
#endif // _XC_REG_AOTIMER_H_
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_cdc.h
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_cprao.h
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_dma.h
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_fmc.h
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_fmc_cache.h
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#ifndef _XC_REG_FMC_CACHE_H_
#define _XC_REG_FMC_CACHE_H_
#include <stdint.h>
#define XC_REG_FMC_CACHE_BASE_ADDR 0x52000000
#define XC_REG_FMC_CACHE_DECODING_MASK 0x0000001F
/**
* @brief FMC_CACHE_CCR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 06 STATISTIC_EN 0
* 05 SET_PREFETCH 0
* 04 SET_MAN_INV 0
* 03 SET_MAN_POW 0
* 02 POW_REQ 0
* 01 INV_REQ 0
* 00 EN 0
* </pre>
*/
#define FMC_CACHE_CCR_REG (*(volatile uint32_t *)(0x52000000))
#define FMC_CACHE_CCR_ADDR 0x52000000
#define FMC_CACHE_CCR_OFFSET 0x00000000
__INLINE uint32_t fmc_cache_ccr_get(void)
{
return FMC_CACHE_CCR_REG;
}
__INLINE void fmc_cache_ccr_set(uint32_t value)
{
FMC_CACHE_CCR_REG = value;
}
// field definitions
#define STATISTIC_EN_BIT 0x00000040
#define STATISTIC_EN_POS 6
#define SET_PREFETCH_BIT 0x00000020
#define SET_PREFETCH_POS 5
#define SET_MAN_INV_BIT 0x00000010
#define SET_MAN_INV_POS 4
#define SET_MAN_POW_BIT 0x00000008
#define SET_MAN_POW_POS 3
#define POW_REQ_BIT 0x00000004
#define POW_REQ_POS 2
#define INV_REQ_BIT 0x00000002
#define INV_REQ_POS 1
#define EN_BIT 0x00000001
#define EN_POS 0
#define STATISTIC_EN_RST 0x0
#define SET_PREFETCH_RST 0x0
#define SET_MAN_INV_RST 0x0
#define SET_MAN_POW_RST 0x0
#define POW_REQ_RST 0x0
#define INV_REQ_RST 0x0
#define EN_RST 0x0
__INLINE void fmc_cache_ccr_pack(uint8_t statistic_en, uint8_t set_prefetch, uint8_t set_man_inv, uint8_t set_man_pow, uint8_t pow_req, uint8_t inv_req, uint8_t en)
{
ASSERT_ERR(((statistic_en << 6) & ~0x00000040) == 0);
ASSERT_ERR(((set_prefetch << 5) & ~0x00000020) == 0);
ASSERT_ERR(((set_man_inv << 4) & ~0x00000010) == 0);
ASSERT_ERR(((set_man_pow << 3) & ~0x00000008) == 0);
ASSERT_ERR(((pow_req << 2) & ~0x00000004) == 0);
ASSERT_ERR(((inv_req << 1) & ~0x00000002) == 0);
ASSERT_ERR(((en << 0) & ~0x00000001) == 0);
FMC_CACHE_CCR_REG = (statistic_en << 6) | (set_prefetch << 5) | (set_man_inv << 4) | (set_man_pow << 3) | (pow_req << 2) | (inv_req << 1) | (en << 0);
}
__INLINE void fmc_cache_ccr_unpack(uint8_t* statistic_en, uint8_t* set_prefetch, uint8_t* set_man_inv, uint8_t* set_man_pow, uint8_t* pow_req, uint8_t* inv_req, uint8_t* en)
{
uint32_t localVal = FMC_CACHE_CCR_REG;
*statistic_en = (localVal & 0x00000040) >> 6;
*set_prefetch = (localVal & 0x00000020) >> 5;
*set_man_inv = (localVal & 0x00000010) >> 4;
*set_man_pow = (localVal & 0x00000008) >> 3;
*pow_req = (localVal & 0x00000004) >> 2;
*inv_req = (localVal & 0x00000002) >> 1;
*en = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t fmc_cache_ccr__statistic_en__getf(void)
{
uint32_t localVal = FMC_CACHE_CCR_REG;
return ((localVal & 0x00000040) >> 6);
}
__INLINE void fmc_cache_ccr__statistic_en__setf(uint8_t statistic_en)
{
ASSERT_ERR(((statistic_en << 6) & ~0x00000040) == 0);
FMC_CACHE_CCR_REG = (FMC_CACHE_CCR_REG & ~0x00000040) | (statistic_en << 6);
}
__INLINE uint8_t fmc_cache_ccr__set_prefetch__getf(void)
{
uint32_t localVal = FMC_CACHE_CCR_REG;
return ((localVal & 0x00000020) >> 5);
}
__INLINE void fmc_cache_ccr__set_prefetch__setf(uint8_t set_prefetch)
{
ASSERT_ERR(((set_prefetch << 5) & ~0x00000020) == 0);
FMC_CACHE_CCR_REG = (FMC_CACHE_CCR_REG & ~0x00000020) | (set_prefetch << 5);
}
__INLINE uint8_t fmc_cache_ccr__set_man_inv__getf(void)
{
uint32_t localVal = FMC_CACHE_CCR_REG;
return ((localVal & 0x00000010) >> 4);
}
__INLINE void fmc_cache_ccr__set_man_inv__setf(uint8_t set_man_inv)
{
ASSERT_ERR(((set_man_inv << 4) & ~0x00000010) == 0);
FMC_CACHE_CCR_REG = (FMC_CACHE_CCR_REG & ~0x00000010) | (set_man_inv << 4);
}
__INLINE uint8_t fmc_cache_ccr__set_man_pow__getf(void)
{
uint32_t localVal = FMC_CACHE_CCR_REG;
return ((localVal & 0x00000008) >> 3);
}
__INLINE void fmc_cache_ccr__set_man_pow__setf(uint8_t set_man_pow)
{
ASSERT_ERR(((set_man_pow << 3) & ~0x00000008) == 0);
FMC_CACHE_CCR_REG = (FMC_CACHE_CCR_REG & ~0x00000008) | (set_man_pow << 3);
}
__INLINE uint8_t fmc_cache_ccr__pow_req__getf(void)
{
uint32_t localVal = FMC_CACHE_CCR_REG;
return ((localVal & 0x00000004) >> 2);
}
__INLINE void fmc_cache_ccr__pow_req__setf(uint8_t pow_req)
{
ASSERT_ERR(((pow_req << 2) & ~0x00000004) == 0);
FMC_CACHE_CCR_REG = (FMC_CACHE_CCR_REG & ~0x00000004) | (pow_req << 2);
}
__INLINE uint8_t fmc_cache_ccr__inv_req__getf(void)
{
uint32_t localVal = FMC_CACHE_CCR_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE void fmc_cache_ccr__inv_req__setf(uint8_t inv_req)
{
ASSERT_ERR(((inv_req << 1) & ~0x00000002) == 0);
FMC_CACHE_CCR_REG = (FMC_CACHE_CCR_REG & ~0x00000002) | (inv_req << 1);
}
__INLINE uint8_t fmc_cache_ccr__en__getf(void)
{
uint32_t localVal = FMC_CACHE_CCR_REG;
return ((localVal & 0x00000001) >> 0);
}
__INLINE void fmc_cache_ccr__en__setf(uint8_t en)
{
ASSERT_ERR(((en << 0) & ~0x00000001) == 0);
FMC_CACHE_CCR_REG = (FMC_CACHE_CCR_REG & ~0x00000001) | (en << 0);
}
/**
* @brief FMC_CACHE_SR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 04 POW_STAT 0
* 02 INV_STAT 0
* 01:00 CS 0x0
* </pre>
*/
#define FMC_CACHE_SR_REG (*(volatile uint32_t *)(0x52000004))
#define FMC_CACHE_SR_ADDR 0x52000004
#define FMC_CACHE_SR_OFFSET 0x00000004
__INLINE uint32_t fmc_cache_sr_get(void)
{
return FMC_CACHE_SR_REG;
}
// field definitions
#define POW_STAT_BIT 0x00000010
#define POW_STAT_POS 4
#define INV_STAT_BIT 0x00000004
#define INV_STAT_POS 2
#define CS_MASK 0x00000003
#define CS_LSB 0
#define CS_WIDTH 0x00000002
#define POW_STAT_RST 0x0
#define INV_STAT_RST 0x0
#define CS_RST 0x0
__INLINE void fmc_cache_sr_unpack(uint8_t* pow_stat, uint8_t* inv_stat, uint8_t* cs)
{
uint32_t localVal = FMC_CACHE_SR_REG;
*pow_stat = (localVal & 0x00000010) >> 4;
*inv_stat = (localVal & 0x00000004) >> 2;
*cs = (localVal & 0x00000003) >> 0;
}
__INLINE uint8_t fmc_cache_sr__pow_stat__getf(void)
{
uint32_t localVal = FMC_CACHE_SR_REG;
return ((localVal & 0x00000010) >> 4);
}
__INLINE uint8_t fmc_cache_sr__inv_stat__getf(void)
{
uint32_t localVal = FMC_CACHE_SR_REG;
return ((localVal & 0x00000004) >> 2);
}
__INLINE uint8_t fmc_cache_sr__cs__getf(void)
{
uint32_t localVal = FMC_CACHE_SR_REG;
return ((localVal & 0x00000003) >> 0);
}
/**
* @brief FMC_CACHE_IRQMASK register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 01 MAN_INV_ERR0 0
* 00 POW_ERR0 0
* </pre>
*/
#define FMC_CACHE_IRQMASK_REG (*(volatile uint32_t *)(0x52000008))
#define FMC_CACHE_IRQMASK_ADDR 0x52000008
#define FMC_CACHE_IRQMASK_OFFSET 0x00000008
__INLINE uint32_t fmc_cache_irqmask_get(void)
{
return FMC_CACHE_IRQMASK_REG;
}
__INLINE void fmc_cache_irqmask_set(uint32_t value)
{
FMC_CACHE_IRQMASK_REG = value;
}
// field definitions
#define MAN_INV_ERR0_BIT 0x00000002
#define MAN_INV_ERR0_POS 1
#define POW_ERR0_BIT 0x00000001
#define POW_ERR0_POS 0
#define MAN_INV_ERR0_RST 0x0
#define POW_ERR0_RST 0x0
__INLINE void fmc_cache_irqmask_pack(uint8_t man_inv_err0, uint8_t pow_err0)
{
ASSERT_ERR(((man_inv_err0 << 1) & ~0x00000002) == 0);
ASSERT_ERR(((pow_err0 << 0) & ~0x00000001) == 0);
FMC_CACHE_IRQMASK_REG = (man_inv_err0 << 1) | (pow_err0 << 0);
}
__INLINE void fmc_cache_irqmask_unpack(uint8_t* man_inv_err0, uint8_t* pow_err0)
{
uint32_t localVal = FMC_CACHE_IRQMASK_REG;
*man_inv_err0 = (localVal & 0x00000002) >> 1;
*pow_err0 = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t fmc_cache_irqmask__man_inv_err0__getf(void)
{
uint32_t localVal = FMC_CACHE_IRQMASK_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE void fmc_cache_irqmask__man_inv_err0__setf(uint8_t man_inv_err0)
{
ASSERT_ERR(((man_inv_err0 << 1) & ~0x00000002) == 0);
FMC_CACHE_IRQMASK_REG = (FMC_CACHE_IRQMASK_REG & ~0x00000002) | (man_inv_err0 << 1);
}
__INLINE uint8_t fmc_cache_irqmask__pow_err0__getf(void)
{
uint32_t localVal = FMC_CACHE_IRQMASK_REG;
return ((localVal & 0x00000001) >> 0);
}
__INLINE void fmc_cache_irqmask__pow_err0__setf(uint8_t pow_err0)
{
ASSERT_ERR(((pow_err0 << 0) & ~0x00000001) == 0);
FMC_CACHE_IRQMASK_REG = (FMC_CACHE_IRQMASK_REG & ~0x00000001) | (pow_err0 << 0);
}
/**
* @brief FMC_CACHE_IRQSTAT register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 01 MAN_INV_ERR1 0
* 00 POW_ERR1 0
* </pre>
*/
#define FMC_CACHE_IRQSTAT_REG (*(volatile uint32_t *)(0x5200000C))
#define FMC_CACHE_IRQSTAT_ADDR 0x5200000C
#define FMC_CACHE_IRQSTAT_OFFSET 0x0000000C
__INLINE uint32_t fmc_cache_irqstat_get(void)
{
return FMC_CACHE_IRQSTAT_REG;
}
__INLINE void fmc_cache_irqstat_set(uint32_t value)
{
FMC_CACHE_IRQSTAT_REG = value;
}
// field definitions
#define MAN_INV_ERR1_BIT 0x00000002
#define MAN_INV_ERR1_POS 1
#define POW_ERR1_BIT 0x00000001
#define POW_ERR1_POS 0
#define MAN_INV_ERR1_RST 0x0
#define POW_ERR1_RST 0x0
__INLINE void fmc_cache_irqstat_pack(uint8_t man_inv_err1, uint8_t pow_err1)
{
ASSERT_ERR(((man_inv_err1 << 1) & ~0x00000002) == 0);
ASSERT_ERR(((pow_err1 << 0) & ~0x00000001) == 0);
FMC_CACHE_IRQSTAT_REG = (man_inv_err1 << 1) | (pow_err1 << 0);
}
__INLINE void fmc_cache_irqstat_unpack(uint8_t* man_inv_err1, uint8_t* pow_err1)
{
uint32_t localVal = FMC_CACHE_IRQSTAT_REG;
*man_inv_err1 = (localVal & 0x00000002) >> 1;
*pow_err1 = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t fmc_cache_irqstat__man_inv_err1__getf(void)
{
uint32_t localVal = FMC_CACHE_IRQSTAT_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE void fmc_cache_irqstat__man_inv_err1__setf(uint8_t man_inv_err1)
{
ASSERT_ERR(((man_inv_err1 << 1) & ~0x00000002) == 0);
FMC_CACHE_IRQSTAT_REG = (FMC_CACHE_IRQSTAT_REG & ~0x00000002) | (man_inv_err1 << 1);
}
__INLINE uint8_t fmc_cache_irqstat__pow_err1__getf(void)
{
uint32_t localVal = FMC_CACHE_IRQSTAT_REG;
return ((localVal & 0x00000001) >> 0);
}
__INLINE void fmc_cache_irqstat__pow_err1__setf(uint8_t pow_err1)
{
ASSERT_ERR(((pow_err1 << 0) & ~0x00000001) == 0);
FMC_CACHE_IRQSTAT_REG = (FMC_CACHE_IRQSTAT_REG & ~0x00000001) | (pow_err1 << 0);
}
/**
* @brief FMC_CACHE_HWPARAMS register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 13 GEN_STAT_LOGIC 0
* 12 RESET_ALL_REGS 0
* 11:10 CACHE_WAY 0x0
* 09:05 CW 0x0
* 04:00 AW 0x0
* </pre>
*/
#define FMC_CACHE_HWPARAMS_REG (*(volatile uint32_t *)(0x52000010))
#define FMC_CACHE_HWPARAMS_ADDR 0x52000010
#define FMC_CACHE_HWPARAMS_OFFSET 0x00000010
__INLINE uint32_t fmc_cache_hwparams_get(void)
{
return FMC_CACHE_HWPARAMS_REG;
}
// field definitions
#define GEN_STAT_LOGIC_BIT 0x00002000
#define GEN_STAT_LOGIC_POS 13
#define RESET_ALL_REGS_BIT 0x00001000
#define RESET_ALL_REGS_POS 12
#define CACHE_WAY_MASK 0x00000C00
#define CACHE_WAY_LSB 10
#define CACHE_WAY_WIDTH 0x00000002
#define CW_MASK 0x000003E0
#define CW_LSB 5
#define CW_WIDTH 0x00000005
#define AW_MASK 0x0000001F
#define AW_LSB 0
#define AW_WIDTH 0x00000005
#define GEN_STAT_LOGIC_RST 0x0
#define RESET_ALL_REGS_RST 0x0
#define CACHE_WAY_RST 0x0
#define CW_RST 0x0
#define AW_RST 0x0
__INLINE void fmc_cache_hwparams_unpack(uint8_t* gen_stat_logic, uint8_t* reset_all_regs, uint8_t* cache_way, uint8_t* cw, uint8_t* aw)
{
uint32_t localVal = FMC_CACHE_HWPARAMS_REG;
*gen_stat_logic = (localVal & 0x00002000) >> 13;
*reset_all_regs = (localVal & 0x00001000) >> 12;
*cache_way = (localVal & 0x00000C00) >> 10;
*cw = (localVal & 0x000003E0) >> 5;
*aw = (localVal & 0x0000001F) >> 0;
}
__INLINE uint8_t fmc_cache_hwparams__gen_stat_logic__getf(void)
{
uint32_t localVal = FMC_CACHE_HWPARAMS_REG;
return ((localVal & 0x00002000) >> 13);
}
__INLINE uint8_t fmc_cache_hwparams__reset_all_regs__getf(void)
{
uint32_t localVal = FMC_CACHE_HWPARAMS_REG;
return ((localVal & 0x00001000) >> 12);
}
__INLINE uint8_t fmc_cache_hwparams__cache_way__getf(void)
{
uint32_t localVal = FMC_CACHE_HWPARAMS_REG;
return ((localVal & 0x00000C00) >> 10);
}
__INLINE uint8_t fmc_cache_hwparams__cw__getf(void)
{
uint32_t localVal = FMC_CACHE_HWPARAMS_REG;
return ((localVal & 0x000003E0) >> 5);
}
__INLINE uint8_t fmc_cache_hwparams__aw__getf(void)
{
uint32_t localVal = FMC_CACHE_HWPARAMS_REG;
return ((localVal & 0x0000001F) >> 0);
}
/**
* @brief FMC_CACHE_CSHR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 CSHR 0x0
* </pre>
*/
#define FMC_CACHE_CSHR_REG (*(volatile uint32_t *)(0x52000014))
#define FMC_CACHE_CSHR_ADDR 0x52000014
#define FMC_CACHE_CSHR_OFFSET 0x00000014
__INLINE uint32_t fmc_cache_cshr_get(void)
{
return FMC_CACHE_CSHR_REG;
}
__INLINE void fmc_cache_cshr_set(uint32_t value)
{
FMC_CACHE_CSHR_REG = value;
}
// field definitions
#define CSHR_MASK 0xFFFFFFFF
#define CSHR_LSB 0
#define CSHR_WIDTH 0x00000020
#define CSHR_RST 0x0
__INLINE uint32_t fmc_cache_cshr__cshr__getf(void)
{
uint32_t localVal = FMC_CACHE_CSHR_REG;
ASSERT_ERR((localVal & ~0xFFFFFFFF) == 0);
return (localVal >> 0);
}
__INLINE void fmc_cache_cshr__cshr__setf(uint32_t cshr)
{
ASSERT_ERR(((cshr << 0) & ~0xFFFFFFFF) == 0);
FMC_CACHE_CSHR_REG = cshr << 0;
}
/**
* @brief FMC_CACHE_CSMR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 CSMR 0x0
* </pre>
*/
#define FMC_CACHE_CSMR_REG (*(volatile uint32_t *)(0x52000018))
#define FMC_CACHE_CSMR_ADDR 0x52000018
#define FMC_CACHE_CSMR_OFFSET 0x00000018
__INLINE uint32_t fmc_cache_csmr_get(void)
{
return FMC_CACHE_CSMR_REG;
}
__INLINE void fmc_cache_csmr_set(uint32_t value)
{
FMC_CACHE_CSMR_REG = value;
}
// field definitions
#define CSMR_MASK 0xFFFFFFFF
#define CSMR_LSB 0
#define CSMR_WIDTH 0x00000020
#define CSMR_RST 0x0
__INLINE uint32_t fmc_cache_csmr__csmr__getf(void)
{
uint32_t localVal = FMC_CACHE_CSMR_REG;
ASSERT_ERR((localVal & ~0xFFFFFFFF) == 0);
return (localVal >> 0);
}
__INLINE void fmc_cache_csmr__csmr__setf(uint32_t csmr)
{
ASSERT_ERR(((csmr << 0) & ~0xFFFFFFFF) == 0);
FMC_CACHE_CSMR_REG = csmr << 0;
}
#endif // _XC_REG_FMC_CACHE_H_
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_gpio.h
+655
View File
@@ -0,0 +1,655 @@
#ifndef _XC_REG_GPIO_H_
#define _XC_REG_GPIO_H_
#include <stdint.h>
#define XC_REG_GPIO_BASE_ADDR 0x40001000
#define XC_REG_GPIO_DECODING_MASK 0x000003FF
#define GPIO_REG_SIZE 0x04
/**
* @brief GPIO_PORT_DR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:16 DR_WE 0x0
* 15:00 DR 0x0
* </pre>
*/
#define GPIO_PORT_DR_REG(i) (*(volatile uint32_t *)(0x40001000 + i*GPIO_REG_SIZE))
#define GPIO_PORT_DR_ADDR(i) (0x40001000 + i*GPIO_REG_SIZE)
#define GPIO_PORT_DR_OFFSET 0x00000000
__INLINE uint32_t gpio_port_dr_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return GPIO_PORT_DR_REG(reg_idx);
}
__INLINE void gpio_port_dr_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 1);
GPIO_PORT_DR_REG(reg_idx) = value;
}
// field definitions
#define DR_WE_MASK 0xFFFF0000
#define DR_WE_LSB 16
#define DR_WE_WIDTH 0x00000010
#define DR_MASK 0x0000FFFF
#define DR_LSB 0
#define DR_WIDTH 0x00000010
#define DR_WE_RST 0x0
#define DR_RST 0x0
__INLINE void gpio_port_dr_pack(uint32_t reg_idx, uint16_t drwe, uint16_t dr)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((drwe << 16) & ~0xFFFF0000) == 0);
ASSERT_ERR(((dr << 0) & ~0x0000FFFF) == 0);
GPIO_PORT_DR_REG(reg_idx) = (drwe << 16) | (dr << 0);
}
__INLINE void gpio_port_dr_unpack(uint32_t reg_idx, uint16_t* drwe, uint16_t* dr)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = GPIO_PORT_DR_REG(reg_idx);
*drwe = (localVal & 0xFFFF0000) >> 16;
*dr = (localVal & 0x0000FFFF) >> 0;
}
__INLINE void gpio_port_dr__dr_we__setf(uint32_t reg_idx, uint16_t drwe)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((drwe << 16) & ~0xFFFF0000) == 0);
GPIO_PORT_DR_REG(reg_idx) = (GPIO_PORT_DR_REG(reg_idx) & ~0xFFFF0000) | (drwe << 16);
}
__INLINE uint16_t gpio_port_dr__dr__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = GPIO_PORT_DR_REG(reg_idx);
return ((localVal & 0x0000FFFF) >> 0);
}
__INLINE void gpio_port_dr__dr__setf(uint32_t reg_idx, uint16_t dr)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((dr << 0) & ~0x0000FFFF) == 0);
GPIO_PORT_DR_REG(reg_idx) = (GPIO_PORT_DR_REG(reg_idx) & ~0x0000FFFF) | (dr << 0);
}
/**
* @brief GPIO_PORT_DDR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:16 DDR_WE 0x0
* 15:00 DDR 0x0
* </pre>
*/
#define GPIO_PORT_DDR_REG(i) (*(volatile uint32_t *)(0x40001020 + i*GPIO_REG_SIZE))
#define GPIO_PORT_DDR_ADDR(i) (0x40001020 + i*GPIO_REG_SIZE)
#define GPIO_PORT_DDR_OFFSET 0x00000020
__INLINE uint32_t gpio_port_ddr_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return GPIO_PORT_DDR_REG(reg_idx);
}
__INLINE void gpio_port_ddr_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 1);
GPIO_PORT_DDR_REG(reg_idx) = value;
}
// field definitions
#define DDR_WE_MASK 0xFFFF0000
#define DDR_WE_LSB 16
#define DDR_WE_WIDTH 0x00000010
#define DDR_MASK 0x0000FFFF
#define DDR_LSB 0
#define DDR_WIDTH 0x00000010
#define DDR_WE_RST 0x0
#define DDR_RST 0x0
__INLINE void gpio_port_ddr_pack(uint32_t reg_idx, uint16_t ddrwe, uint16_t ddr)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((ddrwe << 16) & ~0xFFFF0000) == 0);
ASSERT_ERR(((ddr << 0) & ~0x0000FFFF) == 0);
GPIO_PORT_DDR_REG(reg_idx) = (ddrwe << 16) | (ddr << 0);
}
__INLINE void gpio_port_ddr_unpack(uint32_t reg_idx, uint16_t* ddrwe, uint16_t* ddr)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = GPIO_PORT_DDR_REG(reg_idx);
*ddrwe = (localVal & 0xFFFF0000) >> 16;
*ddr = (localVal & 0x0000FFFF) >> 0;
}
__INLINE void gpio_port_ddr__ddr_we__setf(uint32_t reg_idx, uint16_t ddrwe)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((ddrwe << 16) & ~0xFFFF0000) == 0);
GPIO_PORT_DDR_REG(reg_idx) = (GPIO_PORT_DDR_REG(reg_idx) & ~0xFFFF0000) | (ddrwe << 16);
}
__INLINE uint16_t gpio_port_ddr__ddr__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = GPIO_PORT_DDR_REG(reg_idx);
return ((localVal & 0x0000FFFF) >> 0);
}
__INLINE void gpio_port_ddr__ddr__setf(uint32_t reg_idx, uint16_t ddr)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((ddr << 0) & ~0x0000FFFF) == 0);
GPIO_PORT_DDR_REG(reg_idx) = (GPIO_PORT_DDR_REG(reg_idx) & ~0x0000FFFF) | (ddr << 0);
}
/**
* @brief GPIO_EXT_PORT register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 DIN 0x0
* </pre>
*/
#define GPIO_EXT_PORT_REG(i) (*(volatile uint32_t *)(0x40001040 + i*GPIO_REG_SIZE))
#define GPIO_EXT_PORT_ADDR(i) (0x40001040 + i*GPIO_REG_SIZE)
#define GPIO_EXT_PORT_OFFSET 0x00000040
__INLINE uint32_t gpio_ext_port_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return GPIO_EXT_PORT_REG(reg_idx);
}
// field definitions
#define DIN_MASK 0xFFFFFFFF
#define DIN_LSB 0
#define DIN_WIDTH 0x00000020
#define DIN_RST 0x0
__INLINE uint32_t gpio_ext_port__din__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = GPIO_EXT_PORT_REG(reg_idx);
ASSERT_ERR((localVal & ~0xFFFFFFFF) == 0);
return (localVal >> 0);
}
/**
* @brief GPIO_INTR_CTRL register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 19:16 MODE_WE 0x0
* 15:13 MODE3 0x0
* 12 MODE_EN3 0
* 11:09 MODE2 0x0
* 08 MODE_EN2 0
* 07:05 MODE1 0x0
* 04 MODE_EN1 0
* 03:01 MODE0 0x0
* 00 MODE_EN0 0
* </pre>
*/
#define GPIO_INTR_CTRL_REG(i) (*(volatile uint32_t *)(0x40001100 + i*GPIO_REG_SIZE))
#define GPIO_INTR_CTRL_ADDR(i) (0x40001100 + i*GPIO_REG_SIZE)
#define GPIO_INTR_CTRL_OFFSET 0x00000100
__INLINE uint32_t gpio_intr_ctrl_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 7);
return GPIO_INTR_CTRL_REG(reg_idx);
}
__INLINE void gpio_intr_ctrl_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 7);
GPIO_INTR_CTRL_REG(reg_idx) = value;
}
// field definitions
#define MODE_WE_MASK 0x000F0000
#define MODE_WE_LSB 16
#define MODE_WE_WIDTH 0x00000004
#define MODE3_MASK 0x0000E000
#define MODE3_LSB 13
#define MODE3_WIDTH 0x00000003
#define MODE_EN3_BIT 0x00001000
#define MODE_EN3_POS 12
#define MODE2_MASK 0x00000E00
#define MODE2_LSB 9
#define MODE2_WIDTH 0x00000003
#define MODE_EN2_BIT 0x00000100
#define MODE_EN2_POS 8
#define MODE1_MASK 0x000000E0
#define MODE1_LSB 5
#define MODE1_WIDTH 0x00000003
#define MODE_EN1_BIT 0x00000010
#define MODE_EN1_POS 4
#define MODE0_MASK 0x0000000E
#define MODE0_LSB 1
#define MODE0_WIDTH 0x00000003
#define MODE_EN0_BIT 0x00000001
#define MODE_EN0_POS 0
#define MODE_WE_RST 0x0
#define MODE3_RST 0x0
#define MODE_EN3_RST 0x0
#define MODE2_RST 0x0
#define MODE_EN2_RST 0x0
#define MODE1_RST 0x0
#define MODE_EN1_RST 0x0
#define MODE0_RST 0x0
#define MODE_EN0_RST 0x0
__INLINE void gpio_intr_ctrl_pack(uint32_t reg_idx, uint8_t modewe, uint8_t mode3, uint8_t modeen3, uint8_t mode2, uint8_t modeen2, uint8_t mode1, uint8_t modeen1, uint8_t mode0, uint8_t modeen0)
{
ASSERT_ERR(reg_idx <= 7);
ASSERT_ERR(((modewe << 16) & ~0x000F0000) == 0);
ASSERT_ERR(((mode3 << 13) & ~0x0000E000) == 0);
ASSERT_ERR(((modeen3 << 12) & ~0x00001000) == 0);
ASSERT_ERR(((mode2 << 9) & ~0x00000E00) == 0);
ASSERT_ERR(((modeen2 << 8) & ~0x00000100) == 0);
ASSERT_ERR(((mode1 << 5) & ~0x000000E0) == 0);
ASSERT_ERR(((modeen1 << 4) & ~0x00000010) == 0);
ASSERT_ERR(((mode0 << 1) & ~0x0000000E) == 0);
ASSERT_ERR(((modeen0 << 0) & ~0x00000001) == 0);
GPIO_INTR_CTRL_REG(reg_idx) = (modewe << 16) | (mode3 << 13) | (modeen3 << 12) | (mode2 << 9) | (modeen2 << 8) | (mode1 << 5) | (modeen1 << 4) | (mode0 << 1) | (modeen0 << 0);
}
__INLINE void gpio_intr_ctrl_unpack(uint32_t reg_idx, uint8_t* modewe, uint8_t* mode3, uint8_t* modeen3, uint8_t* mode2, uint8_t* modeen2, uint8_t* mode1, uint8_t* modeen1, uint8_t* mode0, uint8_t* modeen0)
{
ASSERT_ERR(reg_idx <= 7);
uint32_t localVal = GPIO_INTR_CTRL_REG(reg_idx);
*modewe = (localVal & 0x000F0000) >> 16;
*mode3 = (localVal & 0x0000E000) >> 13;
*modeen3 = (localVal & 0x00001000) >> 12;
*mode2 = (localVal & 0x00000E00) >> 9;
*modeen2 = (localVal & 0x00000100) >> 8;
*mode1 = (localVal & 0x000000E0) >> 5;
*modeen1 = (localVal & 0x00000010) >> 4;
*mode0 = (localVal & 0x0000000E) >> 1;
*modeen0 = (localVal & 0x00000001) >> 0;
}
__INLINE void gpio_intr_ctrl__mode_we__setf(uint32_t reg_idx, uint8_t modewe)
{
ASSERT_ERR(reg_idx <= 7);
ASSERT_ERR(((modewe << 16) & ~0x000F0000) == 0);
GPIO_INTR_CTRL_REG(reg_idx) = (GPIO_INTR_CTRL_REG(reg_idx) & ~0x000F0000) | (modewe << 16);
}
__INLINE uint8_t gpio_intr_ctrl__mode3__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 7);
uint32_t localVal = GPIO_INTR_CTRL_REG(reg_idx);
return ((localVal & 0x0000E000) >> 13);
}
__INLINE void gpio_intr_ctrl__mode3__setf(uint32_t reg_idx, uint8_t mode3)
{
ASSERT_ERR(reg_idx <= 7);
ASSERT_ERR(((mode3 << 13) & ~0x0000E000) == 0);
GPIO_INTR_CTRL_REG(reg_idx) = (GPIO_INTR_CTRL_REG(reg_idx) & ~0x0000E000) | (mode3 << 13);
}
__INLINE uint8_t gpio_intr_ctrl__mode_en3__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 7);
uint32_t localVal = GPIO_INTR_CTRL_REG(reg_idx);
return ((localVal & 0x00001000) >> 12);
}
__INLINE void gpio_intr_ctrl__mode_en3__setf(uint32_t reg_idx, uint8_t modeen3)
{
ASSERT_ERR(reg_idx <= 7);
ASSERT_ERR(((modeen3 << 12) & ~0x00001000) == 0);
GPIO_INTR_CTRL_REG(reg_idx) = (GPIO_INTR_CTRL_REG(reg_idx) & ~0x00001000) | (modeen3 << 12);
}
__INLINE uint8_t gpio_intr_ctrl__mode2__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 7);
uint32_t localVal = GPIO_INTR_CTRL_REG(reg_idx);
return ((localVal & 0x00000E00) >> 9);
}
__INLINE void gpio_intr_ctrl__mode2__setf(uint32_t reg_idx, uint8_t mode2)
{
ASSERT_ERR(reg_idx <= 7);
ASSERT_ERR(((mode2 << 9) & ~0x00000E00) == 0);
GPIO_INTR_CTRL_REG(reg_idx) = (GPIO_INTR_CTRL_REG(reg_idx) & ~0x00000E00) | (mode2 << 9);
}
__INLINE uint8_t gpio_intr_ctrl__mode_en2__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 7);
uint32_t localVal = GPIO_INTR_CTRL_REG(reg_idx);
return ((localVal & 0x00000100) >> 8);
}
__INLINE void gpio_intr_ctrl__mode_en2__setf(uint32_t reg_idx, uint8_t modeen2)
{
ASSERT_ERR(reg_idx <= 7);
ASSERT_ERR(((modeen2 << 8) & ~0x00000100) == 0);
GPIO_INTR_CTRL_REG(reg_idx) = (GPIO_INTR_CTRL_REG(reg_idx) & ~0x00000100) | (modeen2 << 8);
}
__INLINE uint8_t gpio_intr_ctrl__mode1__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 7);
uint32_t localVal = GPIO_INTR_CTRL_REG(reg_idx);
return ((localVal & 0x000000E0) >> 5);
}
__INLINE void gpio_intr_ctrl__mode1__setf(uint32_t reg_idx, uint8_t mode1)
{
ASSERT_ERR(reg_idx <= 7);
ASSERT_ERR(((mode1 << 5) & ~0x000000E0) == 0);
GPIO_INTR_CTRL_REG(reg_idx) = (GPIO_INTR_CTRL_REG(reg_idx) & ~0x000000E0) | (mode1 << 5);
}
__INLINE uint8_t gpio_intr_ctrl__mode_en1__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 7);
uint32_t localVal = GPIO_INTR_CTRL_REG(reg_idx);
return ((localVal & 0x00000010) >> 4);
}
__INLINE void gpio_intr_ctrl__mode_en1__setf(uint32_t reg_idx, uint8_t modeen1)
{
ASSERT_ERR(reg_idx <= 7);
ASSERT_ERR(((modeen1 << 4) & ~0x00000010) == 0);
GPIO_INTR_CTRL_REG(reg_idx) = (GPIO_INTR_CTRL_REG(reg_idx) & ~0x00000010) | (modeen1 << 4);
}
__INLINE uint8_t gpio_intr_ctrl__mode0__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 7);
uint32_t localVal = GPIO_INTR_CTRL_REG(reg_idx);
return ((localVal & 0x0000000E) >> 1);
}
__INLINE void gpio_intr_ctrl__mode0__setf(uint32_t reg_idx, uint8_t mode0)
{
ASSERT_ERR(reg_idx <= 7);
ASSERT_ERR(((mode0 << 1) & ~0x0000000E) == 0);
GPIO_INTR_CTRL_REG(reg_idx) = (GPIO_INTR_CTRL_REG(reg_idx) & ~0x0000000E) | (mode0 << 1);
}
__INLINE uint8_t gpio_intr_ctrl__mode_en0__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 7);
uint32_t localVal = GPIO_INTR_CTRL_REG(reg_idx);
return ((localVal & 0x00000001) >> 0);
}
__INLINE void gpio_intr_ctrl__mode_en0__setf(uint32_t reg_idx, uint8_t modeen0)
{
ASSERT_ERR(reg_idx <= 7);
ASSERT_ERR(((modeen0 << 0) & ~0x00000001) == 0);
GPIO_INTR_CTRL_REG(reg_idx) = (GPIO_INTR_CTRL_REG(reg_idx) & ~0x00000001) | (modeen0 << 0);
}
/**
* @brief GPIO_DEBOUNCE register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:16 DEBEN_WE 0x0
* 15:00 DEBEN 0x0
* </pre>
*/
#define GPIO_DEBOUNCE_REG(i) (*(volatile uint32_t *)(0x40001180 + i*GPIO_REG_SIZE))
#define GPIO_DEBOUNCE_ADDR(i) (0x40001180 + i*GPIO_REG_SIZE)
#define GPIO_DEBOUNCE_OFFSET 0x00000180
__INLINE uint32_t gpio_debounce_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return GPIO_DEBOUNCE_REG(reg_idx);
}
__INLINE void gpio_debounce_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 1);
GPIO_DEBOUNCE_REG(reg_idx) = value;
}
// field definitions
#define DEBEN_WE_MASK 0xFFFF0000
#define DEBEN_WE_LSB 16
#define DEBEN_WE_WIDTH 0x00000010
#define DEBEN_MASK 0x0000FFFF
#define DEBEN_LSB 0
#define DEBEN_WIDTH 0x00000010
#define DEBEN_WE_RST 0x0
#define DEBEN_RST 0x0
__INLINE void gpio_debounce_pack(uint32_t reg_idx, uint16_t debenwe, uint16_t deben)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((debenwe << 16) & ~0xFFFF0000) == 0);
ASSERT_ERR(((deben << 0) & ~0x0000FFFF) == 0);
GPIO_DEBOUNCE_REG(reg_idx) = (debenwe << 16) | (deben << 0);
}
__INLINE void gpio_debounce_unpack(uint32_t reg_idx, uint16_t* debenwe, uint16_t* deben)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = GPIO_DEBOUNCE_REG(reg_idx);
*debenwe = (localVal & 0xFFFF0000) >> 16;
*deben = (localVal & 0x0000FFFF) >> 0;
}
__INLINE void gpio_debounce__deben_we__setf(uint32_t reg_idx, uint16_t debenwe)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((debenwe << 16) & ~0xFFFF0000) == 0);
GPIO_DEBOUNCE_REG(reg_idx) = (GPIO_DEBOUNCE_REG(reg_idx) & ~0xFFFF0000) | (debenwe << 16);
}
__INLINE uint16_t gpio_debounce__deben__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = GPIO_DEBOUNCE_REG(reg_idx);
return ((localVal & 0x0000FFFF) >> 0);
}
__INLINE void gpio_debounce__deben__setf(uint32_t reg_idx, uint16_t deben)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((deben << 0) & ~0x0000FFFF) == 0);
GPIO_DEBOUNCE_REG(reg_idx) = (GPIO_DEBOUNCE_REG(reg_idx) & ~0x0000FFFF) | (deben << 0);
}
/**
* @brief GPIO_INTR_RAW register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 RAW 0x0
* </pre>
*/
#define GPIO_INTR_RAW_REG (*(volatile uint32_t *)(0x400011A0))
#define GPIO_INTR_RAW_ADDR 0x400011A0
#define GPIO_INTR_RAW_OFFSET 0x000001A0
__INLINE uint32_t gpio_intr_raw_get(void)
{
return GPIO_INTR_RAW_REG;
}
// field definitions
#define RAW_MASK 0xFFFFFFFF
#define RAW_LSB 0
#define RAW_WIDTH 0x00000020
#define RAW_RST 0x0
__INLINE uint32_t gpio_intr_raw__raw__getf(void)
{
uint32_t localVal = GPIO_INTR_RAW_REG;
ASSERT_ERR((localVal & ~0xFFFFFFFF) == 0);
return (localVal >> 0);
}
/**
* @brief GPIO_INTR_CLR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 CLR 0x0
* </pre>
*/
#define GPIO_INTR_CLR_REG(i) (*(volatile uint32_t *)(0x400011B0 + i*GPIO_REG_SIZE))
#define GPIO_INTR_CLR_ADDR(i) (0x400011B0 + i*GPIO_REG_SIZE)
#define GPIO_INTR_CLR_OFFSET 0x000001B0
__INLINE void gpio_intr_clr_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 1);
GPIO_INTR_CLR_REG(reg_idx) = value;
}
// field definitions
#define CLR_MASK 0xFFFFFFFF
#define CLR_LSB 0
#define CLR_WIDTH 0x00000020
#define CLR_RST 0x0
__INLINE void gpio_intr_clr__clr__setf(uint32_t reg_idx, uint32_t clr)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((clr << 0) & ~0xFFFFFFFF) == 0);
GPIO_INTR_CLR_REG(reg_idx) = clr << 0;
}
/**
* @brief GPIO_INTR_MASK_C register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:16 MASK_WE 0x0
* 15:00 MASK 0x0
* </pre>
*/
#define GPIO_INTR_MASK_C_REG(i) (*(volatile uint32_t *)(0x40001200 + i*GPIO_REG_SIZE))
#define GPIO_INTR_MASK_C_ADDR(i) (0x40001200 + i*GPIO_REG_SIZE)
#define GPIO_INTR_MASK_C_OFFSET 0x00000200
__INLINE uint32_t gpio_intr_mask_c_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return GPIO_INTR_MASK_C_REG(reg_idx);
}
__INLINE void gpio_intr_mask_c_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 1);
GPIO_INTR_MASK_C_REG(reg_idx) = value;
}
// field definitions
#define MASK_WE_MASK 0xFFFF0000
#define MASK_WE_LSB 16
#define MASK_WE_WIDTH 0x00000010
#define MASK_MASK 0x0000FFFF
#define MASK_LSB 0
#define MASK_WIDTH 0x00000010
#define MASK_WE_RST 0x0
#define MASK_RST 0x0
__INLINE void gpio_intr_mask_c_pack(uint32_t reg_idx, uint16_t maskwe, uint16_t mask)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((maskwe << 16) & ~0xFFFF0000) == 0);
ASSERT_ERR(((mask << 0) & ~0x0000FFFF) == 0);
GPIO_INTR_MASK_C_REG(reg_idx) = (maskwe << 16) | (mask << 0);
}
__INLINE void gpio_intr_mask_c_unpack(uint32_t reg_idx, uint16_t* maskwe, uint16_t* mask)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = GPIO_INTR_MASK_C_REG(reg_idx);
*maskwe = (localVal & 0xFFFF0000) >> 16;
*mask = (localVal & 0x0000FFFF) >> 0;
}
__INLINE void gpio_intr_mask_c__mask_we__setf(uint32_t reg_idx, uint16_t maskwe)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((maskwe << 16) & ~0xFFFF0000) == 0);
GPIO_INTR_MASK_C_REG(reg_idx) = (GPIO_INTR_MASK_C_REG(reg_idx) & ~0xFFFF0000) | (maskwe << 16);
}
__INLINE uint16_t gpio_intr_mask_c__mask__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = GPIO_INTR_MASK_C_REG(reg_idx);
return ((localVal & 0x0000FFFF) >> 0);
}
__INLINE void gpio_intr_mask_c__mask__setf(uint32_t reg_idx, uint16_t mask)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((mask << 0) & ~0x0000FFFF) == 0);
GPIO_INTR_MASK_C_REG(reg_idx) = (GPIO_INTR_MASK_C_REG(reg_idx) & ~0x0000FFFF) | (mask << 0);
}
/**
* @brief GPIO_INTR_STATUS_C register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 STATUS 0x0
* </pre>
*/
#define GPIO_INTR_STATUS_C_REG(i) (*(volatile uint32_t *)(0x40001220 + i*GPIO_REG_SIZE))
#define GPIO_INTR_STATUS_C_ADDR(i) (0x40001220 + i*GPIO_REG_SIZE)
#define GPIO_INTR_STATUS_C_OFFSET 0x00000220
__INLINE uint32_t gpio_intr_status_c_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return GPIO_INTR_STATUS_C_REG(reg_idx);
}
// field definitions
#define STATUS_MASK 0xFFFFFFFF
#define STATUS_LSB 0
#define STATUS_WIDTH 0x00000020
#define STATUS_RST 0x0
__INLINE uint32_t gpio_intr_status_c__status__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = GPIO_INTR_STATUS_C_REG(reg_idx);
ASSERT_ERR((localVal & ~0xFFFFFFFF) == 0);
return (localVal >> 0);
}
#endif // _XC_REG_GPIO_H_
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_i2c.h
+2000
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_i2s.h
+1170
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_offset.h
+67
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@@ -0,0 +1,67 @@
/*!
* \file xc_reg_offset.h
*
* \brief The header of xc registers offset index
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
#ifndef _XC_REG_OFFSET_H_
#define _XC_REG_OFFSET_H_
#define AOTIMER0_IDX 0U
#define AOTIMER1_IDX 1U
// #define AOTIMER_OFFSET {0x00, 0x14}
#define TIMER0_IDX 0U
#define TIMER1_IDX 1U
#define TIMER2_IDX 2U
#define TIMER3_IDX 3U
#define PWM0_IDX 0U
#define PWM1_IDX 1U
#define PWM2_IDX 2U
#define PWM3_IDX 3U
#define PWM4_IDX 4U
#define PWM5_IDX 5U
#define UART0_IDX (uint8_t)0U
#define UART1_IDX (uint8_t)1U
#define UART2_IDX (uint8_t)2U
#define PWM_TIMER0_IDX 0U
#define PWM_TIMER1_IDX 1U
#define PWM_TIMER2_IDX 2U
#define PWM_TIMER3_IDX 3U
#define PWM_TIMER4_IDX 4U
#define PWM_TIMER5_IDX 5U
#if (USE_XIP == 0)
#define SPI0_IDX 0U
#endif
#define SPI1_IDX 1U
#define SPI2_IDX 2U
const static unsigned char aotimer_offset[2] = {0x00, 0x14};
const static unsigned char timer_offset[4] = {0x00, 0x14, 0x28, 0x3C};
const static unsigned short pwm_offset[6] = {0x00, 0x40, 0x400, 0x440, 0x800, 0x840};
const static unsigned short uart_offset[3] ={0x00, 0x1000, 0x1400};
const static unsigned short spi_offset[3] ={0x00, 0x1000, 0x1800};
#include "xc6xxx.h"
#endif // _XC_REG_OFFSET_H_
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_pwm.h
+675
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#ifndef _XC_REG_PWM_H_
#define _XC_REG_PWM_H_
#include <stdint.h>
#define XC_REG_PWM_BASE_ADDR 0x40017000
#define XC_REG_PWM_DECODING_MASK 0x0000003F
/**
* @brief PWM_EN register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 06 pwm_en_all 0
* 05 sleep_en 0
* 04 sleep_incr 0
* 03 EN_SEL 0
* 02:01 MODE 0x0
* 00 EN 0
* </pre>
*/
#define PWM_EN_REG(i) (* ((volatile uint32_t *)(0x40017000 + pwm_offset[i])) )
#define PWM_EN_ADDR(i) (0x40017000 + pwm_offset[i])
#define PWM_EN_OFFSET 0x00000000
__INLINE uint32_t pwm_en_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_EN_REG(reg_idx);
}
__INLINE void pwm_en_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 5);
PWM_EN_REG(reg_idx) = value;
}
// field definitions
#define PWM_EN_ALL_BIT 0x00000040
#define PWM_EN_ALL_POS 6
#define SLEEP_EN_BIT 0x00000020
#define SLEEP_EN_POS 5
#define SLEEP_INCR_BIT 0x00000010
#define SLEEP_INCR_POS 4
#define EN_SEL_BIT 0x00000008
#define EN_SEL_POS 3
#define MODE_MASK 0x00000006
#define MODE_LSB 1
#define MODE_WIDTH 0x00000002
#define EN_BIT 0x00000001
#define EN_POS 0
#define PWM_EN_ALL_RST 0x0
#define SLEEP_EN_RST 0x0
#define SLEEP_INCR_RST 0x0
#define EN_SEL_RST 0x0
#define MODE_RST 0x0
#define EN_RST 0x0
__INLINE void pwm_en_pack(uint32_t reg_idx, uint8_t pwm_en_all, uint8_t sleep_en, uint8_t sleep_incr, uint8_t en_sel, uint8_t mode, uint8_t en)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((pwm_en_all << 6) & ~0x00000040) == 0);
ASSERT_ERR(((sleep_en << 5) & ~0x00000020) == 0);
ASSERT_ERR(((sleep_incr << 4) & ~0x00000010) == 0);
ASSERT_ERR(((en_sel << 3) & ~0x00000008) == 0);
ASSERT_ERR(((mode << 1) & ~0x00000006) == 0);
ASSERT_ERR(((en << 0) & ~0x00000001) == 0);
PWM_EN_REG(reg_idx) = (pwm_en_all << 6) | (sleep_en << 5) | (sleep_incr << 4) | (en_sel << 3) | (mode << 1) | (en << 0);
}
__INLINE void pwm_en_unpack(uint32_t reg_idx, uint8_t* pwm_en_all, uint8_t* sleep_en, uint8_t* sleep_incr, uint8_t* en_sel, uint8_t* mode, uint8_t* en)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_EN_REG(reg_idx);
*pwm_en_all = (localVal & 0x00000040) >> 6;
*sleep_en = (localVal & 0x00000020) >> 5;
*sleep_incr = (localVal & 0x00000010) >> 4;
*en_sel = (localVal & 0x00000008) >> 3;
*mode = (localVal & 0x00000006) >> 1;
*en = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t pwm_en__pwm_en_all__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_EN_REG(reg_idx);
return ((localVal & 0x00000040) >> 6);
}
__INLINE void pwm_en__pwm_en_all__setf(uint32_t reg_idx, uint8_t pwm_en_all)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((pwm_en_all << 6) & ~0x00000040) == 0);
PWM_EN_REG(reg_idx) = (PWM_EN_REG(reg_idx) & ~0x00000040) | (pwm_en_all << 6);
}
__INLINE uint8_t pwm_en__sleep_en__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_EN_REG(reg_idx);
return ((localVal & 0x00000020) >> 5);
}
__INLINE void pwm_en__sleep_en__setf(uint32_t reg_idx, uint8_t sleep_en)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((sleep_en << 5) & ~0x00000020) == 0);
PWM_EN_REG(reg_idx) = (PWM_EN_REG(reg_idx) & ~0x00000020) | (sleep_en << 5);
}
__INLINE uint8_t pwm_en__sleep_incr__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_EN_REG(reg_idx);
return ((localVal & 0x00000010) >> 4);
}
__INLINE void pwm_en__sleep_incr__setf(uint32_t reg_idx, uint8_t sleep_incr)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((sleep_incr << 4) & ~0x00000010) == 0);
PWM_EN_REG(reg_idx) = (PWM_EN_REG(reg_idx) & ~0x00000010) | (sleep_incr << 4);
}
__INLINE uint8_t pwm_en__en_sel__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_EN_REG(reg_idx);
return ((localVal & 0x00000008) >> 3);
}
__INLINE void pwm_en__en_sel__setf(uint32_t reg_idx, uint8_t en_sel)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((en_sel << 3) & ~0x00000008) == 0);
PWM_EN_REG(reg_idx) = (PWM_EN_REG(reg_idx) & ~0x00000008) | (en_sel << 3);
}
__INLINE uint8_t pwm_en__mode__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_EN_REG(reg_idx);
return ((localVal & 0x00000006) >> 1);
}
__INLINE void pwm_en__mode__setf(uint32_t reg_idx, uint8_t mode)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((mode << 1) & ~0x00000006) == 0);
PWM_EN_REG(reg_idx) = (PWM_EN_REG(reg_idx) & ~0x00000006) | (mode << 1);
}
__INLINE uint8_t pwm_en__en__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_EN_REG(reg_idx);
return ((localVal & 0x00000001) >> 0);
}
__INLINE void pwm_en__en__setf(uint32_t reg_idx, uint8_t en)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((en << 0) & ~0x00000001) == 0);
PWM_EN_REG(reg_idx) = (PWM_EN_REG(reg_idx) & ~0x00000001) | (en << 0);
}
/**
* @brief PWM_UP register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 UPDATE 0
* </pre>
*/
#define PWM_UP_REG(i) (* ((volatile uint32_t *)(0x40017004 + pwm_offset[i])) )
#define PWM_UP_ADDR(i) (0x40017004 + pwm_offset[i])
#define PWM_UP_OFFSET 0x00000004
__INLINE uint32_t pwm_up_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_UP_REG(reg_idx);
}
__INLINE void pwm_up_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 5);
PWM_UP_REG(reg_idx) = value;
}
// field definitions
#define UPDATE_BIT 0x00000001
#define UPDATE_POS 0
#define UPDATE_RST 0x0
__INLINE uint8_t pwm_up__update__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_UP_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
__INLINE void pwm_up__update__setf(uint32_t reg_idx, uint8_t update)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((update << 0) & ~0x00000001) == 0);
PWM_UP_REG(reg_idx) = update << 0;
}
/**
* @brief PWM_RST register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 RESET 0
* </pre>
*/
#define PWM_RST_REG(i) (* ((volatile uint32_t *)(0x40017008 + pwm_offset[i])) )
#define PWM_RST_ADDR(i) (0x40017008 + pwm_offset[i])
#define PWM_RST_OFFSET 0x00000008
__INLINE uint32_t pwm_rst_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_RST_REG(reg_idx);
}
__INLINE void pwm_rst_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 5);
PWM_RST_REG(reg_idx) = value;
}
// field definitions
#define RESET_BIT 0x00000001
#define RESET_POS 0
#define RESET_RST 0x0
__INLINE uint8_t pwm_rst__reset__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_RST_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
__INLINE void pwm_rst__reset__setf(uint32_t reg_idx, uint8_t reset)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((reset << 0) & ~0x00000001) == 0);
PWM_RST_REG(reg_idx) = reset << 0;
}
/**
* @brief PWM_PERIOD register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 07:00 PERIOD 0x0
* </pre>
*/
#define PWM_PERIOD_REG(i) (* ((volatile uint32_t *)(0x4001700C + pwm_offset[i])) )
#define PWM_PERIOD_ADDR(i) (0x4001700C + pwm_offset[i])
#define PWM_PERIOD_OFFSET 0x0000000C
__INLINE uint32_t pwm_period_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_PERIOD_REG(reg_idx);
}
__INLINE void pwm_period_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 5);
PWM_PERIOD_REG(reg_idx) = value;
}
// field definitions
#define PERIOD_MASK 0x000000FF
#define PERIOD_LSB 0
#define PERIOD_WIDTH 0x00000008
#define PERIOD_RST 0x0
__INLINE uint8_t pwm_period__period__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_PERIOD_REG(reg_idx);
ASSERT_ERR((localVal & ~0x000000FF) == 0);
return (localVal >> 0);
}
__INLINE void pwm_period__period__setf(uint32_t reg_idx, uint8_t period)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((period << 0) & ~0x000000FF) == 0);
PWM_PERIOD_REG(reg_idx) = period << 0;
}
/**
* @brief PWM_OCPY register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:16 OCPY_RATIO_CONFIG 0x0
* 15:00 OCPY_RATIO 0x0
* </pre>
*/
#define PWM_OCPY_REG(i) (* ((volatile uint32_t *)(0x40017010 + pwm_offset[i])) )
#define PWM_OCPY_ADDR(i) (0x40017010 + pwm_offset[i])
#define PWM_OCPY_OFFSET 0x00000010
__INLINE uint32_t pwm_ocpy_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_OCPY_REG(reg_idx);
}
__INLINE void pwm_ocpy_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 5);
PWM_OCPY_REG(reg_idx) = value;
}
// field definitions
#define OCPY_RATIO_CONFIG_MASK 0xFFFF0000
#define OCPY_RATIO_CONFIG_LSB 16
#define OCPY_RATIO_CONFIG_WIDTH 0x00000010
#define OCPY_RATIO_MASK 0x0000FFFF
#define OCPY_RATIO_LSB 0
#define OCPY_RATIO_WIDTH 0x00000010
#define OCPY_RATIO_CONFIG_RST 0x0
#define OCPY_RATIO_RST 0x0
__INLINE void pwm_ocpy_pack(uint32_t reg_idx, uint16_t ocpy_ratio_config, uint16_t ocpy_ratio)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((ocpy_ratio_config << 16) & ~0xFFFF0000) == 0);
ASSERT_ERR(((ocpy_ratio << 0) & ~0x0000FFFF) == 0);
PWM_OCPY_REG(reg_idx) = (ocpy_ratio_config << 16) | (ocpy_ratio << 0);
}
__INLINE void pwm_ocpy_unpack(uint32_t reg_idx, uint16_t* ocpy_ratio_config, uint16_t* ocpy_ratio)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_OCPY_REG(reg_idx);
*ocpy_ratio_config = (localVal & 0xFFFF0000) >> 16;
*ocpy_ratio = (localVal & 0x0000FFFF) >> 0;
}
__INLINE uint16_t pwm_ocpy__ocpy_ratio_config__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_OCPY_REG(reg_idx);
return ((localVal & 0xFFFF0000) >> 16);
}
__INLINE void pwm_ocpy__ocpy_ratio_config__setf(uint32_t reg_idx, uint16_t ocpy_ratio_config)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((ocpy_ratio_config << 16) & ~0xFFFF0000) == 0);
PWM_OCPY_REG(reg_idx) = (PWM_OCPY_REG(reg_idx) & ~0xFFFF0000) | (ocpy_ratio_config << 16);
}
__INLINE uint16_t pwm_ocpy__ocpy_ratio__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_OCPY_REG(reg_idx);
return ((localVal & 0x0000FFFF) >> 0);
}
__INLINE void pwm_ocpy__ocpy_ratio__setf(uint32_t reg_idx, uint16_t ocpy_ratio)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((ocpy_ratio << 0) & ~0x0000FFFF) == 0);
PWM_OCPY_REG(reg_idx) = (PWM_OCPY_REG(reg_idx) & ~0x0000FFFF) | (ocpy_ratio << 0);
}
/**
* @brief PWM_COMPEN register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 PWMCOMPEN 0
* </pre>
*/
#define PWM_COMPEN_REG(i) (* ((volatile uint32_t *)(0x40017014 + pwm_offset[i])) )
#define PWM_COMPEN_ADDR(i) (0x40017014 + pwm_offset[i])
#define PWM_COMPEN_OFFSET 0x00000014
__INLINE uint32_t pwm_compen_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_COMPEN_REG(reg_idx);
}
__INLINE void pwm_compen_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 5);
PWM_COMPEN_REG(reg_idx) = value;
}
// field definitions
#define PWMCOMPEN_BIT 0x00000001
#define PWMCOMPEN_POS 0
#define PWMCOMPEN_RST 0x0
__INLINE uint8_t pwm_compen__pwmcompen__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_COMPEN_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
__INLINE void pwm_compen__pwmcompen__setf(uint32_t reg_idx, uint8_t pwmcompen)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((pwmcompen << 0) & ~0x00000001) == 0);
PWM_COMPEN_REG(reg_idx) = pwmcompen << 0;
}
/**
* @brief PWM_COMPTIME register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 02:00 COMPTIME 0x0
* </pre>
*/
#define PWM_COMPTIME_REG(i) (* ((volatile uint32_t *)(0x40017018 + pwm_offset[i])) )
#define PWM_COMPTIME_ADDR(i) (0x40017018 + pwm_offset[i])
#define PWM_COMPTIME_OFFSET 0x00000018
__INLINE uint32_t pwm_comptime_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_COMPTIME_REG(reg_idx);
}
__INLINE void pwm_comptime_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 5);
PWM_COMPTIME_REG(reg_idx) = value;
}
// field definitions
#define COMPTIME_MASK 0x00000007
#define COMPTIME_LSB 0
#define COMPTIME_WIDTH 0x00000003
#define COMPTIME_RST 0x0
__INLINE uint8_t pwm_comptime__comptime__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_COMPTIME_REG(reg_idx);
ASSERT_ERR((localVal & ~0x0000003F) == 0);
return (localVal >> 0);
}
__INLINE void pwm_comptime__comptime__setf(uint32_t reg_idx, uint8_t comptime)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((comptime << 0) & ~0x0000003F) == 0);
PWM_COMPTIME_REG(reg_idx) = comptime << 0;
}
/**
* @brief PWM_BREAK_CTL register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 19:17 PWM_BRK_ENABLE 0x0
* 16 PWM_BRK_SYNC 0
* 14:12 PWM_BRK_MASK 0x0
* 11:09 PWM_BRK_INV 0x0
* 08 BRK_MODE 0
* 07 BRK_DBC_EN 0
* 06:01 BRK_DBC_STEP 0x0
* 00 CLEAR 0
* </pre>
*/
#define PWM_BREAK_CTL_REG(i) (* ((volatile uint32_t *)(0x40017020 + pwm_offset[i])) )
#define PWM_BREAK_CTL_ADDR(i) (0x40017020 + pwm_offset[i])
#define PWM_BREAK_CTL_OFFSET 0x00000020
__INLINE uint32_t pwm_break_ctl_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_BREAK_CTL_REG(reg_idx);
}
__INLINE void pwm_break_ctl_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 5);
PWM_BREAK_CTL_REG(reg_idx) = value;
}
// field definitions
#define PWM_BRK_ENABLE_MASK 0x000E0000
#define PWM_BRK_ENABLE_LSB 17
#define PWM_BRK_ENABLE_WIDTH 0x00000003
#define PWM_BRK_SYNC_BIT 0x00010000
#define PWM_BRK_SYNC_POS 16
#define PWM_BRK_MASK_MASK 0x00007000
#define PWM_BRK_MASK_LSB 12
#define PWM_BRK_MASK_WIDTH 0x00000003
#define PWM_BRK_INV_MASK 0x00000E00
#define PWM_BRK_INV_LSB 9
#define PWM_BRK_INV_WIDTH 0x00000003
#define BRK_MODE_BIT 0x00000100
#define BRK_MODE_POS 8
#define BRK_DBC_EN_BIT 0x00000080
#define BRK_DBC_EN_POS 7
#define BRK_DBC_STEP_MASK 0x0000007E
#define BRK_DBC_STEP_LSB 1
#define BRK_DBC_STEP_WIDTH 0x00000006
#define BRK_CLEAR_BIT 0x00000001
#define BRK_CLEAR_POS 0
#define PWM_BRK_ENABLE_RST 0x0
#define PWM_BRK_SYNC_RST 0x0
#define PWM_BRK_MASK_RST 0x0
#define PWM_BRK_INV_RST 0x0
#define BRK_MODE_RST 0x0
#define BRK_DBC_EN_RST 0x0
#define BRK_DBC_STEP_RST 0x0
#define CLEAR_RST 0x0
__INLINE void pwm_break_ctl_pack(uint32_t reg_idx, uint8_t pwm_brk_enable, uint8_t pwm_brk_mask, uint8_t pwm_brk_inv, uint8_t brk_mode, uint8_t brk_dbc_en, uint8_t brk_dbc_step, uint8_t clear)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((pwm_brk_enable << 17) & ~0x000E0000) == 0);
ASSERT_ERR(((pwm_brk_mask << 12) & ~0x00007000) == 0);
ASSERT_ERR(((pwm_brk_inv << 9) & ~0x00000E00) == 0);
ASSERT_ERR(((brk_mode << 8) & ~0x00000100) == 0);
ASSERT_ERR(((brk_dbc_en << 7) & ~0x00000080) == 0);
ASSERT_ERR(((brk_dbc_step << 1) & ~0x0000007E) == 0);
ASSERT_ERR(((clear << 0) & ~0x00000001) == 0);
PWM_BREAK_CTL_REG(reg_idx) = (pwm_brk_enable << 17) | (pwm_brk_mask << 12) | (pwm_brk_inv << 9) | (brk_mode << 8) | (brk_dbc_en << 7) | (brk_dbc_step << 1) | (clear << 0);
}
__INLINE void pwm_break_ctl_unpack(uint32_t reg_idx, uint8_t* pwm_brk_enable, uint8_t* pwm_brk_sync, uint8_t* pwm_brk_mask, uint8_t* pwm_brk_inv, uint8_t* brk_mode, uint8_t* brk_dbc_en, uint8_t* brk_dbc_step, uint8_t* clear)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_BREAK_CTL_REG(reg_idx);
*pwm_brk_enable = (localVal & 0x000E0000) >> 17;
*pwm_brk_sync = (localVal & 0x00010000) >> 16;
*pwm_brk_mask = (localVal & 0x00007000) >> 12;
*pwm_brk_inv = (localVal & 0x00000E00) >> 9;
*brk_mode = (localVal & 0x00000100) >> 8;
*brk_dbc_en = (localVal & 0x00000080) >> 7;
*brk_dbc_step = (localVal & 0x0000007E) >> 1;
*clear = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t pwm_break_ctl__pwm_brk_enable__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_BREAK_CTL_REG(reg_idx);
return ((localVal & 0x000E0000) >> 17);
}
__INLINE void pwm_break_ctl__pwm_brk_enable__setf(uint32_t reg_idx, uint8_t pwm_brk_enable)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((pwm_brk_enable << 17) & ~0x000E0000) == 0);
PWM_BREAK_CTL_REG(reg_idx) = (PWM_BREAK_CTL_REG(reg_idx) & ~0x000E0000) | (pwm_brk_enable << 17);
}
__INLINE uint8_t pwm_break_ctl__pwm_brk_sync__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_BREAK_CTL_REG(reg_idx);
return ((localVal & 0x00010000) >> 16);
}
__INLINE uint8_t pwm_break_ctl__pwm_brk_mask__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_BREAK_CTL_REG(reg_idx);
return ((localVal & 0x00007000) >> 12);
}
__INLINE void pwm_break_ctl__pwm_brk_mask__setf(uint32_t reg_idx, uint8_t pwm_brk_mask)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((pwm_brk_mask << 12) & ~0x00007000) == 0);
PWM_BREAK_CTL_REG(reg_idx) = (PWM_BREAK_CTL_REG(reg_idx) & ~0x00007000) | (pwm_brk_mask << 12);
}
__INLINE uint8_t pwm_break_ctl__pwm_brk_inv__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_BREAK_CTL_REG(reg_idx);
return ((localVal & 0x00000E00) >> 9);
}
__INLINE void pwm_break_ctl__pwm_brk_inv__setf(uint32_t reg_idx, uint8_t pwm_brk_inv)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((pwm_brk_inv << 9) & ~0x00000E00) == 0);
PWM_BREAK_CTL_REG(reg_idx) = (PWM_BREAK_CTL_REG(reg_idx) & ~0x00000E00) | (pwm_brk_inv << 9);
}
__INLINE uint8_t pwm_break_ctl__brk_mode__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_BREAK_CTL_REG(reg_idx);
return ((localVal & 0x00000100) >> 8);
}
__INLINE void pwm_break_ctl__brk_mode__setf(uint32_t reg_idx, uint8_t brk_mode)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((brk_mode << 8) & ~0x00000100) == 0);
PWM_BREAK_CTL_REG(reg_idx) = (PWM_BREAK_CTL_REG(reg_idx) & ~0x00000100) | (brk_mode << 8);
}
__INLINE uint8_t pwm_break_ctl__brk_dbc_en__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_BREAK_CTL_REG(reg_idx);
return ((localVal & 0x00000080) >> 7);
}
__INLINE void pwm_break_ctl__brk_dbc_en__setf(uint32_t reg_idx, uint8_t brk_dbc_en)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((brk_dbc_en << 7) & ~0x00000080) == 0);
PWM_BREAK_CTL_REG(reg_idx) = (PWM_BREAK_CTL_REG(reg_idx) & ~0x00000080) | (brk_dbc_en << 7);
}
__INLINE uint8_t pwm_break_ctl__brk_dbc_step__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_BREAK_CTL_REG(reg_idx);
return ((localVal & 0x0000007E) >> 1);
}
__INLINE void pwm_break_ctl__brk_dbc_step__setf(uint32_t reg_idx, uint8_t brk_dbc_step)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((brk_dbc_step << 1) & ~0x0000007E) == 0);
PWM_BREAK_CTL_REG(reg_idx) = (PWM_BREAK_CTL_REG(reg_idx) & ~0x0000007E) | (brk_dbc_step << 1);
}
__INLINE uint8_t pwm_break_ctl__clear__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_BREAK_CTL_REG(reg_idx);
return ((localVal & 0x00000001) >> 0);
}
__INLINE void pwm_break_ctl__clear__setf(uint32_t reg_idx, uint8_t clear)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((clear << 0) & ~0x00000001) == 0);
PWM_BREAK_CTL_REG(reg_idx) = (PWM_BREAK_CTL_REG(reg_idx) & ~0x00000001) | (clear << 0);
}
#endif // _XC_REG_PWM_H_
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_pwm_comn.h
+487
View File
@@ -0,0 +1,487 @@
#ifndef _XC_REG_PWM_COMN_H_
#define _XC_REG_PWM_COMN_H_
#include <stdint.h>
#define XC_REG_PWM_COMN_BASE_ADDR 0x40017C00
#define XC_REG_PWM_COMN_DECODING_MASK 0x0000003F
#define PWM_COMMON_REG_SIZE 0x04
/**
* @brief CAP_TIM_VAL register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15:00 CAPTURE_VALUE 0x0
* </pre>
*/
#define CAP_TIM_VAL_REG(i) (* ((volatile uint32_t *)(0x40017C00 + i*PWM_COMMON_REG_SIZE)) )
#define CAP_TIM_VAL_ADDR(i) (0x40017C00 + i*PWM_COMMON_REG_SIZE)
#define CAP_TIM_VAL_OFFSET 0x00000000
__INLINE uint32_t cap_tim_val_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
return CAP_TIM_VAL_REG(reg_idx);
}
// field definitions
#define CAPTURE_VALUE_MASK 0x0000FFFF
#define CAPTURE_VALUE_LSB 0
#define CAPTURE_VALUE_WIDTH 0x00000010
#define CAPTURE_VALUE_RST 0x0
__INLINE uint16_t cap_tim_val__capture_value__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_VAL_REG(reg_idx);
ASSERT_ERR((localVal & ~0x0000FFFF) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_CAP_TIM_INT register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 02 CAPTURE_UPD2 0
* 01 CAPTURE_UPD1 0
* 00 CAPTURE_UPD0 0
* </pre>
*/
#define PWM_CAP_TIM_INT_REG (*(volatile uint32_t *)(0x40017C0C))
#define PWM_CAP_TIM_INT_ADDR 0x40017C0C
#define PWM_CAP_TIM_INT_OFFSET 0x0000000C
__INLINE uint32_t pwm_cap_tim_int_get(void)
{
return PWM_CAP_TIM_INT_REG;
}
__INLINE void pwm_cap_tim_int_set(uint32_t value)
{
PWM_CAP_TIM_INT_REG = value;
}
// field definitions
#define CAPTURE_UPD2_BIT 0x00000004
#define CAPTURE_UPD2_POS 2
#define CAPTURE_UPD1_BIT 0x00000002
#define CAPTURE_UPD1_POS 1
#define CAPTURE_UPD0_BIT 0x00000001
#define CAPTURE_UPD0_POS 0
#define CAPTURE_UPD2_RST 0x0
#define CAPTURE_UPD1_RST 0x0
#define CAPTURE_UPD0_RST 0x0
__INLINE void pwm_cap_tim_int_pack(uint8_t capture_upd2, uint8_t capture_upd1, uint8_t capture_upd0)
{
ASSERT_ERR(((capture_upd2 << 2) & ~0x00000004) == 0);
ASSERT_ERR(((capture_upd1 << 1) & ~0x00000002) == 0);
ASSERT_ERR(((capture_upd0 << 0) & ~0x00000001) == 0);
PWM_CAP_TIM_INT_REG = (capture_upd2 << 2) | (capture_upd1 << 1) | (capture_upd0 << 0);
}
__INLINE void pwm_cap_tim_int_unpack(uint8_t* capture_upd2, uint8_t* capture_upd1, uint8_t* capture_upd0)
{
uint32_t localVal = PWM_CAP_TIM_INT_REG;
*capture_upd2 = (localVal & 0x00000004) >> 2;
*capture_upd1 = (localVal & 0x00000002) >> 1;
*capture_upd0 = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t pwm_cap_tim_int__capture_upd2__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_REG;
return ((localVal & 0x00000004) >> 2);
}
__INLINE void pwm_cap_tim_int__capture_upd2__setf(uint8_t capture_upd2)
{
ASSERT_ERR(((capture_upd2 << 2) & ~0x00000004) == 0);
PWM_CAP_TIM_INT_REG = (PWM_CAP_TIM_INT_REG & ~0x00000004) | (capture_upd2 << 2);
}
__INLINE uint8_t pwm_cap_tim_int__capture_upd1__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE void pwm_cap_tim_int__capture_upd1__setf(uint8_t capture_upd1)
{
ASSERT_ERR(((capture_upd1 << 1) & ~0x00000002) == 0);
PWM_CAP_TIM_INT_REG = (PWM_CAP_TIM_INT_REG & ~0x00000002) | (capture_upd1 << 1);
}
__INLINE uint8_t pwm_cap_tim_int__capture_upd0__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_REG;
return ((localVal & 0x00000001) >> 0);
}
__INLINE void pwm_cap_tim_int__capture_upd0__setf(uint8_t capture_upd0)
{
ASSERT_ERR(((capture_upd0 << 0) & ~0x00000001) == 0);
PWM_CAP_TIM_INT_REG = (PWM_CAP_TIM_INT_REG & ~0x00000001) | (capture_upd0 << 0);
}
/**
* @brief PWM_CAP_TIM_INT_EN register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 02 capture_upd2_en 0
* 01 capture_upd1_en 0
* 00 capture_upd0_en 0
* </pre>
*/
#define PWM_CAP_TIM_INT_EN_REG (*(volatile uint32_t *)(0x40017C10))
#define PWM_CAP_TIM_INT_EN_ADDR 0x40017C10
#define PWM_CAP_TIM_INT_EN_OFFSET 0x00000010
__INLINE uint32_t pwm_cap_tim_int_en_get(void)
{
return PWM_CAP_TIM_INT_EN_REG;
}
__INLINE void pwm_cap_tim_int_en_set(uint32_t value)
{
PWM_CAP_TIM_INT_EN_REG = value;
}
// field definitions
#define CAPTURE_UPD_2_EN_BIT 0x00000004
#define CAPTURE_UPD_2_EN_POS 2
#define CAPTURE_UPD_1_EN_BIT 0x00000002
#define CAPTURE_UPD_1_EN_POS 1
#define CAPTURE_UPD_0_EN_BIT 0x00000001
#define CAPTURE_UPD_0_EN_POS 0
#define CAPTURE_UPD_2_EN_RST 0x0
#define CAPTURE_UPD_1_EN_RST 0x0
#define CAPTURE_UPD_0_EN_RST 0x0
__INLINE void pwm_cap_tim_int_en_pack(uint8_t capture_upd2_en, uint8_t capture_upd1_en, uint8_t capture_upd0_en)
{
ASSERT_ERR(((capture_upd2_en << 2) & ~0x00000004) == 0);
ASSERT_ERR(((capture_upd1_en << 1) & ~0x00000002) == 0);
ASSERT_ERR(((capture_upd0_en << 0) & ~0x00000001) == 0);
PWM_CAP_TIM_INT_EN_REG = (capture_upd2_en << 2) | (capture_upd1_en << 1) | (capture_upd0_en << 0);
}
__INLINE void pwm_cap_tim_int_en_unpack(uint8_t* capture_upd2_en, uint8_t* capture_upd1_en, uint8_t* capture_upd0_en)
{
uint32_t localVal = PWM_CAP_TIM_INT_EN_REG;
*capture_upd2_en = (localVal & 0x00000004) >> 2;
*capture_upd1_en = (localVal & 0x00000002) >> 1;
*capture_upd0_en = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t pwm_cap_tim_int_en__capture_upd_2_en__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_EN_REG;
return ((localVal & 0x00000004) >> 2);
}
__INLINE void pwm_cap_tim_int_en__capture_upd_2_en__setf(uint8_t capture_upd2_en)
{
ASSERT_ERR(((capture_upd2_en << 2) & ~0x00000004) == 0);
PWM_CAP_TIM_INT_EN_REG = (PWM_CAP_TIM_INT_EN_REG & ~0x00000004) | (capture_upd2_en << 2);
}
__INLINE uint8_t pwm_cap_tim_int_en__capture_upd_1_en__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_EN_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE void pwm_cap_tim_int_en__capture_upd_1_en__setf(uint8_t capture_upd1_en)
{
ASSERT_ERR(((capture_upd1_en << 1) & ~0x00000002) == 0);
PWM_CAP_TIM_INT_EN_REG = (PWM_CAP_TIM_INT_EN_REG & ~0x00000002) | (capture_upd1_en << 1);
}
__INLINE uint8_t pwm_cap_tim_int_en__capture_upd_0_en__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_EN_REG;
return ((localVal & 0x00000001) >> 0);
}
__INLINE void pwm_cap_tim_int_en__capture_upd_0_en__setf(uint8_t capture_upd0_en)
{
ASSERT_ERR(((capture_upd0_en << 0) & ~0x00000001) == 0);
PWM_CAP_TIM_INT_EN_REG = (PWM_CAP_TIM_INT_EN_REG & ~0x00000001) | (capture_upd0_en << 0);
}
/**
* @brief PWM_CAP_TIM_INT_RAW register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 02 capture_upd2_raw 0
* 01 capture_upd1_raw 0
* 00 capture_upd0_raw 0
* </pre>
*/
#define PWM_CAP_TIM_INT_RAW_REG (*(volatile uint32_t *)(0x40017C14))
#define PWM_CAP_TIM_INT_RAW_ADDR 0x40017C14
#define PWM_CAP_TIM_INT_RAW_OFFSET 0x00000014
__INLINE uint32_t pwm_cap_tim_int_raw_get(void)
{
return PWM_CAP_TIM_INT_RAW_REG;
}
// field definitions
#define CAPTURE_UPD_2_RAW_BIT 0x00000004
#define CAPTURE_UPD_2_RAW_POS 2
#define CAPTURE_UPD_1_RAW_BIT 0x00000002
#define CAPTURE_UPD_1_RAW_POS 1
#define CAPTURE_UPD_0_RAW_BIT 0x00000001
#define CAPTURE_UPD_0_RAW_POS 0
#define CAPTURE_UPD_2_RAW_RST 0x0
#define CAPTURE_UPD_1_RAW_RST 0x0
#define CAPTURE_UPD_0_RAW_RST 0x0
__INLINE void pwm_cap_tim_int_raw_unpack(uint8_t* capture_upd2_raw, uint8_t* capture_upd1_raw, uint8_t* capture_upd0_raw)
{
uint32_t localVal = PWM_CAP_TIM_INT_RAW_REG;
*capture_upd2_raw = (localVal & 0x00000004) >> 2;
*capture_upd1_raw = (localVal & 0x00000002) >> 1;
*capture_upd0_raw = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t pwm_cap_tim_int_raw__capture_upd_2_raw__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_RAW_REG;
return ((localVal & 0x00000004) >> 2);
}
__INLINE uint8_t pwm_cap_tim_int_raw__capture_upd_1_raw__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_RAW_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE uint8_t pwm_cap_tim_int_raw__capture_upd_0_raw__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_RAW_REG;
return ((localVal & 0x00000001) >> 0);
}
/**
* @brief CAP_TIM_CTL register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 23:19 CLK_DIV_VAL 0x0
* 18:16 CAPTURE_SIG_SEL 0x0
* 14 DBC_EN 0
* 13:08 DBC_STEP 0x0
* 05:04 CAPTURE_MODE 0x0
* 03:02 CAPTURE_PSC 0x0
* 01 capture_enable 0
* 00 COMMON_CNT_ENABLE 0
* </pre>
*/
#define CAP_TIM_CTL_REG(i) (* ((volatile uint32_t *)(0x40017C18 + i*PWM_COMMON_REG_SIZE)) )
#define CAP_TIM_CTL_ADDR(i) (0x40017C18 + i*PWM_COMMON_REG_SIZE)
#define CAP_TIM_CTL_OFFSET 0x00000018
__INLINE uint32_t cap_tim_ctl_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
return CAP_TIM_CTL_REG(reg_idx);
}
__INLINE void cap_tim_ctl_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 2);
CAP_TIM_CTL_REG(reg_idx) = value;
}
// field definitions
#define CLK_DIV_VAL_MASK 0x00F80000
#define CLK_DIV_VAL_LSB 19
#define CLK_DIV_VAL_WIDTH 0x00000005
#define CAPTURE_SIG_SEL_MASK 0x00070000
#define CAPTURE_SIG_SEL_LSB 16
#define CAPTURE_SIG_SEL_WIDTH 0x00000003
#define DBC_EN_BIT 0x00004000
#define DBC_EN_POS 14
#define DBC_STEP_MASK 0x00003F00
#define DBC_STEP_LSB 8
#define DBC_STEP_WIDTH 0x00000006
#define CAPTURE_MODE_MASK 0x00000030
#define CAPTURE_MODE_LSB 4
#define CAPTURE_MODE_WIDTH 0x00000002
#define CAPTURE_PSC_MASK 0x0000000C
#define CAPTURE_PSC_LSB 2
#define CAPTURE_PSC_WIDTH 0x00000002
#define CAPTURE_ENABLE_BIT 0x00000002
#define CAPTURE_ENABLE_POS 1
#define COMMON_CNT_ENABLE_BIT 0x00000001
#define COMMON_CNT_ENABLE_POS 0
#define CLK_DIV_VAL_RST 0x0
#define CAPTURE_SIG_SEL_RST 0x0
#define DBC_EN_RST 0x0
#define DBC_STEP_RST 0x0
#define CAPTURE_MODE_RST 0x0
#define CAPTURE_PSC_RST 0x0
#define CAPTURE_ENABLE_RST 0x0
#define COMMON_CNT_ENABLE_RST 0x0
__INLINE void cap_tim_ctl_pack(uint32_t reg_idx, uint8_t clk_div_val, uint8_t capture_sig_sel, uint8_t dbc_en, uint8_t dbc_step, uint8_t capture_mode, uint8_t capture_psc, uint8_t capture_enable, uint8_t common_cnt_enable)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((clk_div_val << 19) & ~0x00F80000) == 0);
ASSERT_ERR(((capture_sig_sel << 16) & ~0x00070000) == 0);
ASSERT_ERR(((dbc_en << 14) & ~0x00004000) == 0);
ASSERT_ERR(((dbc_step << 8) & ~0x00003F00) == 0);
ASSERT_ERR(((capture_mode << 4) & ~0x00000030) == 0);
ASSERT_ERR(((capture_psc << 2) & ~0x0000000C) == 0);
ASSERT_ERR(((capture_enable << 1) & ~0x00000002) == 0);
ASSERT_ERR(((common_cnt_enable << 0) & ~0x00000001) == 0);
CAP_TIM_CTL_REG(reg_idx) = (clk_div_val << 19) | (capture_sig_sel << 16) | (dbc_en << 14) | (dbc_step << 8) | (capture_mode << 4) | (capture_psc << 2) | (capture_enable << 1) | (common_cnt_enable << 0);
}
__INLINE void cap_tim_ctl_unpack(uint32_t reg_idx, uint8_t* clk_div_val, uint8_t* capture_sig_sel, uint8_t* dbc_en, uint8_t* dbc_step, uint8_t* capture_mode, uint8_t* capture_psc, uint8_t* capture_enable, uint8_t* common_cnt_enable)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
*clk_div_val = (localVal & 0x00F80000) >> 19;
*capture_sig_sel = (localVal & 0x00070000) >> 16;
*dbc_en = (localVal & 0x00004000) >> 14;
*dbc_step = (localVal & 0x00003F00) >> 8;
*capture_mode = (localVal & 0x00000030) >> 4;
*capture_psc = (localVal & 0x0000000C) >> 2;
*capture_enable = (localVal & 0x00000002) >> 1;
*common_cnt_enable = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t cap_tim_ctl__clk_div_val__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x00F80000) >> 19);
}
__INLINE void cap_tim_ctl__clk_div_val__setf(uint32_t reg_idx, uint8_t clk_div_val)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((clk_div_val << 19) & ~0x00F80000) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x00F80000) | (clk_div_val << 19);
}
__INLINE uint8_t cap_tim_ctl__capture_sig_sel__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x00070000) >> 16);
}
__INLINE void cap_tim_ctl__capture_sig_sel__setf(uint32_t reg_idx, uint8_t capture_sig_sel)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((capture_sig_sel << 16) & ~0x00070000) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x00070000) | (capture_sig_sel << 16);
}
__INLINE uint8_t cap_tim_ctl__dbc_en__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x00004000) >> 14);
}
__INLINE void cap_tim_ctl__dbc_en__setf(uint32_t reg_idx, uint8_t dbc_en)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((dbc_en << 14) & ~0x00004000) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x00004000) | (dbc_en << 14);
}
__INLINE uint8_t cap_tim_ctl__dbc_step__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x00003F00) >> 8);
}
__INLINE void cap_tim_ctl__dbc_step__setf(uint32_t reg_idx, uint8_t dbc_step)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((dbc_step << 8) & ~0x00003F00) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x00003F00) | (dbc_step << 8);
}
__INLINE uint8_t cap_tim_ctl__capture_mode__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x00000030) >> 4);
}
__INLINE void cap_tim_ctl__capture_mode__setf(uint32_t reg_idx, uint8_t capture_mode)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((capture_mode << 4) & ~0x00000030) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x00000030) | (capture_mode << 4);
}
__INLINE uint8_t cap_tim_ctl__capture_psc__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x0000000C) >> 2);
}
__INLINE void cap_tim_ctl__capture_psc__setf(uint32_t reg_idx, uint8_t capture_psc)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((capture_psc << 2) & ~0x0000000C) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x0000000C) | (capture_psc << 2);
}
__INLINE uint8_t cap_tim_ctl__capture_enable__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x00000002) >> 1);
}
__INLINE void cap_tim_ctl__capture_enable__setf(uint32_t reg_idx, uint8_t capture_enable)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((capture_enable << 1) & ~0x00000002) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x00000002) | (capture_enable << 1);
}
__INLINE uint8_t cap_tim_ctl__common_cnt_enable__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x00000001) >> 0);
}
__INLINE void cap_tim_ctl__common_cnt_enable__setf(uint32_t reg_idx, uint8_t common_cnt_enable)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((common_cnt_enable << 0) & ~0x00000001) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x00000001) | (common_cnt_enable << 0);
}
#endif // _XC_REG_PWM_COMN_H_
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_pwm_timer.h
+453
View File
@@ -0,0 +1,453 @@
#ifndef _XC_REG_PWM_TIMER_H_
#define _XC_REG_PWM_TIMER_H_
#include <stdint.h>
#include "xc_reg_offset.h"
#define XC_REG_PWM_TIMER_BASE_ADDR 0x40017D00
#define XC_REG_PWM_TIMER_DECODING_MASK 0x000000FF
#define PWM_TIMER_REG_SIZE 0x14
#define PWM_LOAD_CNT2_REG_SIZE 0x04
/**
* @brief PWM_TIMER_LOADCOUNT register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15:00 TIMER_LC 0x0
* </pre>
*/
#define PWM_TIMER_LOADCOUNT_REG(i) (* ((volatile uint32_t *)(0x40017D00 + i*PWM_TIMER_REG_SIZE)) )
#define PWM_TIMER_LOADCOUNT_ADDR(i) (0x40017D00 + i*PWM_TIMER_REG_SIZE)
#define PWM_TIMER_LOADCOUNT_OFFSET 0x00000000
__INLINE uint32_t pwm_timer_loadcount_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_TIMER_LOADCOUNT_REG(reg_idx);
}
__INLINE void pwm_timer_loadcount_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 5);
PWM_TIMER_LOADCOUNT_REG(reg_idx) = value;
}
// field definitions
#define TIMER_LC_MASK 0x0000FFFF
#define TIMER_LC_LSB 0
#define TIMER_LC_WIDTH 0x00000010
#define TIMER_LC_RST 0x0
__INLINE uint16_t pwm_timer_loadcount__timer_lc__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_LOADCOUNT_REG(reg_idx);
ASSERT_ERR((localVal & ~0x0000FFFF) == 0);
return (localVal >> 0);
}
__INLINE void pwm_timer_loadcount__timer_lc__setf(uint32_t reg_idx, uint16_t timer_lc)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((timer_lc << 0) & ~0x0000FFFF) == 0);
PWM_TIMER_LOADCOUNT_REG(reg_idx) = timer_lc << 0;
}
/**
* @brief PWM_TIMER_CURRENTVAL register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15:00 TIMER_CV 0x0
* </pre>
*/
#define PWM_TIMER_CURRENTVAL_REG(i) (* ((volatile uint32_t *)(0x40017D04 + i*PWM_TIMER_REG_SIZE)) )
#define PWM_TIMER_CURRENTVAL_ADDR(i) (0x40017D04 + i*PWM_TIMER_REG_SIZE)
#define PWM_TIMER_CURRENTVAL_OFFSET 0x00000004
__INLINE uint32_t pwm_timer_currentval_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_TIMER_CURRENTVAL_REG(reg_idx);
}
// field definitions
#define TIMER_CV_MASK 0x0000FFFF
#define TIMER_CV_LSB 0
#define TIMER_CV_WIDTH 0x00000010
#define TIMER_CV_RST 0x0
__INLINE uint16_t pwm_timer_currentval__timer_cv__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_CURRENTVAL_REG(reg_idx);
ASSERT_ERR((localVal & ~0x0000FFFF) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_TIMER_CONTROLREG register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 04 TIMER_ON10OPWM_EN 0
* 03 TIMER_PWM 0
* 02 TIMER_INT_MASK 0
* 01 TIMER_MODE 0
* 00 TIMER_EN 0
* </pre>
*/
#define PWM_TIMER_CONTROLREG_REG(i) (* ((volatile uint32_t *)(0x40017D08 + i*PWM_TIMER_REG_SIZE)) )
#define PWM_TIMER_CONTROLREG_ADDR(i) (0x40017D08 + i*PWM_TIMER_REG_SIZE)
#define PWM_TIMER_CONTROLREG_OFFSET 0x00000008
__INLINE uint32_t pwm_timer_controlreg_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_TIMER_CONTROLREG_REG(reg_idx);
}
__INLINE void pwm_timer_controlreg_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 5);
PWM_TIMER_CONTROLREG_REG(reg_idx) = value;
}
// field definitions
#define TIMER_ON10OPWM_EN_BIT 0x00000010
#define TIMER_ON10OPWM_EN_POS 4
#define TIMER_PWM_BIT 0x00000008
#define TIMER_PWM_POS 3
#define TIMER_INT_MASK_BIT 0x00000004
#define TIMER_INT_MASK_POS 2
#define TIMER_MODE_BIT 0x00000002
#define TIMER_MODE_POS 1
#define TIMER_EN_BIT 0x00000001
#define TIMER_EN_POS 0
#define TIMER_ON10OPWM_EN_RST 0x0
#define TIMER_PWM_RST 0x0
#define TIMER_INT_MASK_RST 0x0
#define TIMER_MODE_RST 0x0
#define TIMER_EN_RST 0x0
__INLINE void pwm_timer_controlreg_pack(uint32_t reg_idx, uint8_t timer_int_mask, uint8_t timer_mode, uint8_t timer_en)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((timer_int_mask << 2) & ~0x00000004) == 0);
ASSERT_ERR(((timer_mode << 1) & ~0x00000002) == 0);
ASSERT_ERR(((timer_en << 0) & ~0x00000001) == 0);
PWM_TIMER_CONTROLREG_REG(reg_idx) = (timer_int_mask << 2) | (timer_mode << 1) | (timer_en << 0);
}
__INLINE void pwm_timer_controlreg_unpack(uint32_t reg_idx, uint8_t* timer_on10opwm_en, uint8_t* timer_pwm, uint8_t* timer_int_mask, uint8_t* timer_mode, uint8_t* timer_en)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_CONTROLREG_REG(reg_idx);
*timer_on10opwm_en = (localVal & 0x00000010) >> 4;
*timer_pwm = (localVal & 0x00000008) >> 3;
*timer_int_mask = (localVal & 0x00000004) >> 2;
*timer_mode = (localVal & 0x00000002) >> 1;
*timer_en = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t pwm_timer_controlreg__timer_on10opwm_en__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_CONTROLREG_REG(reg_idx);
return ((localVal & 0x00000010) >> 4);
}
__INLINE uint8_t pwm_timer_controlreg__timer_pwm__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_CONTROLREG_REG(reg_idx);
return ((localVal & 0x00000008) >> 3);
}
__INLINE uint8_t pwm_timer_controlreg__timer_int_mask__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_CONTROLREG_REG(reg_idx);
return ((localVal & 0x00000004) >> 2);
}
__INLINE void pwm_timer_controlreg__timer_int_mask__setf(uint32_t reg_idx, uint8_t timer_int_mask)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((timer_int_mask << 2) & ~0x00000004) == 0);
PWM_TIMER_CONTROLREG_REG(reg_idx) = (PWM_TIMER_CONTROLREG_REG(reg_idx) & ~0x00000004) | (timer_int_mask << 2);
}
__INLINE uint8_t pwm_timer_controlreg__timer_mode__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_CONTROLREG_REG(reg_idx);
return ((localVal & 0x00000002) >> 1);
}
__INLINE void pwm_timer_controlreg__timer_mode__setf(uint32_t reg_idx, uint8_t timer_mode)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((timer_mode << 1) & ~0x00000002) == 0);
PWM_TIMER_CONTROLREG_REG(reg_idx) = (PWM_TIMER_CONTROLREG_REG(reg_idx) & ~0x00000002) | (timer_mode << 1);
}
__INLINE uint8_t pwm_timer_controlreg__timer_en__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_CONTROLREG_REG(reg_idx);
return ((localVal & 0x00000001) >> 0);
}
__INLINE void pwm_timer_controlreg__timer_en__setf(uint32_t reg_idx, uint8_t timer_en)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((timer_en << 0) & ~0x00000001) == 0);
PWM_TIMER_CONTROLREG_REG(reg_idx) = (PWM_TIMER_CONTROLREG_REG(reg_idx) & ~0x00000001) | (timer_en << 0);
}
/**
* @brief PWM_TIMER_EOI register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 Timer_EOI 0
* </pre>
*/
#define PWM_TIMER_EOI_REG(i) (* ((volatile uint32_t *)(0x40017D0C + i*PWM_TIMER_REG_SIZE)) )
#define PWM_TIMER_EOI_ADDR(i) (0x40017D0C + i*PWM_TIMER_REG_SIZE)
#define PWM_TIMER_EOI_OFFSET 0x0000000C
__INLINE uint32_t pwm_timer_eoi_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_TIMER_EOI_REG(reg_idx);
}
// field definitions
#define TIMER_EOI_BIT 0x00000001
#define TIMER_EOI_POS 0
#define TIMER_EOI_RST 0x0
__INLINE uint8_t pwm_timer_eoi__timer_eoi__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_EOI_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_TIMER_INTSTAT register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 Timer_IS 0
* </pre>
*/
#define PWM_TIMER_INTSTAT_REG(i) (* ((volatile uint32_t *)(0x40017D10 + i*PWM_TIMER_REG_SIZE)) )
#define PWM_TIMER_INTSTAT_ADDR(i) (0x40017D10 + i*PWM_TIMER_REG_SIZE)
#define PWM_TIMER_INTSTAT_OFFSET 0x00000010
__INLINE uint32_t pwm_timer_intstat_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_TIMER_INTSTAT_REG(reg_idx);
}
// field definitions
#define TIMER_IS_BIT 0x00000001
#define TIMER_IS_POS 0
#define TIMER_IS_RST 0x0
__INLINE uint8_t pwm_timer_intstat__timer_is__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_INTSTAT_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_TIMER_A_TIS register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 05:00 Timers_IS 0x0
* </pre>
*/
#define PWM_TIMER_A_TIS_REG (*(volatile uint32_t *)(0x40017DA0))
#define PWM_TIMER_A_TIS_ADDR 0x40017DA0
#define PWM_TIMER_A_TIS_OFFSET 0x000000A0
__INLINE uint32_t pwm_timer_a_tis_get(void)
{
return PWM_TIMER_A_TIS_REG;
}
// field definitions
#define TIMERS_IS_MASK 0x0000003F
#define TIMERS_IS_LSB 0
#define TIMERS_IS_WIDTH 0x00000006
#define TIMERS_IS_RST 0x0
__INLINE uint8_t pwm_timer_a_tis__timers_is__getf(void)
{
uint32_t localVal = PWM_TIMER_A_TIS_REG;
ASSERT_ERR((localVal & ~0x0000003F) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_TIMER_A_TEOI register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 05:00 TIMERS_EOI 0x0
* </pre>
*/
#define PWM_TIMER_A_TEOI_REG (*(volatile uint32_t *)(0x40017DA4))
#define PWM_TIMER_A_TEOI_ADDR 0x40017DA4
#define PWM_TIMER_A_TEOI_OFFSET 0x000000A4
__INLINE uint32_t pwm_timer_a_teoi_get(void)
{
return PWM_TIMER_A_TEOI_REG;
}
// field definitions
#define TIMERS_EOI_MASK 0x0000003F
#define TIMERS_EOI_LSB 0
#define TIMERS_EOI_WIDTH 0x00000006
#define TIMERS_EOI_RST 0x0
__INLINE uint8_t pwm_timer_a_teoi__timers_eoi__getf(void)
{
uint32_t localVal = PWM_TIMER_A_TEOI_REG;
ASSERT_ERR((localVal & ~0x0000003F) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_TIMER_A_TRIS register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 05:00 TIMERS_RIS 0x0
* </pre>
*/
#define PWM_TIMER_A_TRIS_REG (*(volatile uint32_t *)(0x40017DA8))
#define PWM_TIMER_A_TRIS_ADDR 0x40017DA8
#define PWM_TIMER_A_TRIS_OFFSET 0x000000A8
__INLINE uint32_t pwm_timer_a_tris_get(void)
{
return PWM_TIMER_A_TRIS_REG;
}
// field definitions
#define TIMERS_RIS_MASK 0x0000003F
#define TIMERS_RIS_LSB 0
#define TIMERS_RIS_WIDTH 0x00000006
#define TIMERS_RIS_RST 0x0
__INLINE uint8_t pwm_timer_a_tris__timers_ris__getf(void)
{
uint32_t localVal = PWM_TIMER_A_TRIS_REG;
ASSERT_ERR((localVal & ~0x0000003F) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_TIMER_TCOMP register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 TIMERS_COMP 0x0
* </pre>
*/
#define PWM_TIMER_TCOMP_REG (*(volatile uint32_t *)(0x40017DAC))
#define PWM_TIMER_TCOMP_ADDR 0x40017DAC
#define PWM_TIMER_TCOMP_OFFSET 0x000000AC
__INLINE uint32_t pwm_timer_tcomp_get(void)
{
return PWM_TIMER_TCOMP_REG;
}
// field definitions
#define TIMERS_COMP_MASK 0xFFFFFFFF
#define TIMERS_COMP_LSB 0
#define TIMERS_COMP_WIDTH 0x00000020
#define TIMERS_COMP_RST 0x0
__INLINE uint32_t pwm_timer_tcomp__timers_comp__getf(void)
{
uint32_t localVal = PWM_TIMER_TCOMP_REG;
ASSERT_ERR((localVal & ~0xFFFFFFFF) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_TIMER_LOADCOUNT2 register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 11:00 TIMER_LC2 0x0
* </pre>
*/
#define PWM_TIMER_LOADCOUNT2_REG(i) (* ((volatile uint32_t *)(0x40017DB0 + i*PWM_LOAD_CNT2_REG_SIZE)) )
#define PWM_TIMER_LOADCOUNT2_ADDR(i) (0x40017DB0 + i*PWM_LOAD_CNT2_REG_SIZE)
#define PWM_TIMER_LOADCOUNT2_OFFSET 0x000000B0
__INLINE uint32_t pwm_timer_loadcount2_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_TIMER_LOADCOUNT2_REG(reg_idx);
}
__INLINE void pwm_timer_loadcount2_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 5);
PWM_TIMER_LOADCOUNT2_REG(reg_idx) = value;
}
// field definitions
#define TIMER_LC2_MASK 0x00000FFF
#define TIMER_LC2_LSB 0
#define TIMER_LC2_WIDTH 0x0000000C
#define TIMER_LC2_RST 0x0
__INLINE uint16_t pwm_timer_loadcount2__timer_lc2__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_LOADCOUNT2_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000FFF) == 0);
return (localVal >> 0);
}
__INLINE void pwm_timer_loadcount2__timer_lc2__setf(uint32_t reg_idx, uint16_t timer_lc2)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((timer_lc2 << 0) & ~0x00000FFF) == 0);
PWM_TIMER_LOADCOUNT2_REG(reg_idx) = timer_lc2 << 0;
}
#endif // _XC_REG_PWM_TIMER_H_
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_qdec.h
+665
View File
@@ -0,0 +1,665 @@
#ifndef _XC_REG_QDEC_H_
#define _XC_REG_QDEC_H_
#include <stdint.h>
#include "xc_reg_offset.h"
#define XC_REG_QDEC_BASE_ADDR 0x40016000
#define XC_REG_QDEC_DECODING_MASK 0x0000003F
/**
* @brief QDEC_CTL register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 06 DB_FILTER_EN 0
* 05 SINGLE_SAMPLE_RST_EN 0
* 04 AUTO_CLR_EN 0
* 03 SOFT_CLR 0
* 02 SOFT_RST 0
* 01 QDEC_START 0
* 00 QDEC_EN 0
* </pre>
*/
#define QDEC_CTL_REG (*(volatile uint32_t *)(0x40016000))
#define QDEC_CTL_ADDR 0x40016000
#define QDEC_CTL_OFFSET 0x00000000
__INLINE uint32_t qdec_ctl_get(void)
{
return QDEC_CTL_REG;
}
__INLINE void qdec_ctl_set(uint32_t value)
{
QDEC_CTL_REG = value;
}
// field definitions
#define DB_FILTER_EN_BIT 0x00000040
#define DB_FILTER_EN_POS 6
#define SINGLE_SAMPLE_RST_EN_BIT 0x00000020
#define SINGLE_SAMPLE_RST_EN_POS 5
#define AUTO_CLR_EN_BIT 0x00000010
#define AUTO_CLR_EN_POS 4
#define SOFT_CLR_BIT 0x00000008
#define SOFT_CLR_POS 3
#define SOFT_RST_BIT 0x00000004
#define SOFT_RST_POS 2
#define QDEC_START_BIT 0x00000002
#define QDEC_START_POS 1
#define QDEC_EN_BIT 0x00000001
#define QDEC_EN_POS 0
#define DB_FILTER_EN_RST 0x0
#define SINGLE_SAMPLE_RST_EN_RST 0x0
#define AUTO_CLR_EN_RST 0x0
#define SOFT_CLR_RST 0x0
#define SOFT_RST_RST 0x0
#define QDEC_START_RST 0x0
#define QDEC_EN_RST 0x0
__INLINE void qdec_ctl_pack(uint8_t db_filter_en, uint8_t single_sample_rst_en, uint8_t auto_clr_en, uint8_t soft_clr, uint8_t soft_rst, uint8_t qdec_start, uint8_t qdec_en)
{
ASSERT_ERR(((db_filter_en << 6) & ~0x00000040) == 0);
ASSERT_ERR(((single_sample_rst_en << 5) & ~0x00000020) == 0);
ASSERT_ERR(((auto_clr_en << 4) & ~0x00000010) == 0);
ASSERT_ERR(((soft_clr << 3) & ~0x00000008) == 0);
ASSERT_ERR(((soft_rst << 2) & ~0x00000004) == 0);
ASSERT_ERR(((qdec_start << 1) & ~0x00000002) == 0);
ASSERT_ERR(((qdec_en << 0) & ~0x00000001) == 0);
QDEC_CTL_REG = (db_filter_en << 6) | (single_sample_rst_en << 5) | (auto_clr_en << 4) | (soft_clr << 3) | (soft_rst << 2) | (qdec_start << 1) | (qdec_en << 0);
}
__INLINE void qdec_ctl_unpack(uint8_t* db_filter_en, uint8_t* single_sample_rst_en, uint8_t* auto_clr_en, uint8_t* soft_clr, uint8_t* soft_rst, uint8_t* qdec_start, uint8_t* qdec_en)
{
uint32_t localVal = QDEC_CTL_REG;
*db_filter_en = (localVal & 0x00000040) >> 6;
*single_sample_rst_en = (localVal & 0x00000020) >> 5;
*auto_clr_en = (localVal & 0x00000010) >> 4;
*soft_clr = (localVal & 0x00000008) >> 3;
*soft_rst = (localVal & 0x00000004) >> 2;
*qdec_start = (localVal & 0x00000002) >> 1;
*qdec_en = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t qdec_ctl__db_filter_en__getf(void)
{
uint32_t localVal = QDEC_CTL_REG;
return ((localVal & 0x00000040) >> 6);
}
__INLINE void qdec_ctl__db_filter_en__setf(uint8_t db_filter_en)
{
ASSERT_ERR(((db_filter_en << 6) & ~0x00000040) == 0);
QDEC_CTL_REG = (QDEC_CTL_REG & ~0x00000040) | (db_filter_en << 6);
}
__INLINE uint8_t qdec_ctl__single_sample_rst_en__getf(void)
{
uint32_t localVal = QDEC_CTL_REG;
return ((localVal & 0x00000020) >> 5);
}
__INLINE void qdec_ctl__single_sample_rst_en__setf(uint8_t single_sample_rst_en)
{
ASSERT_ERR(((single_sample_rst_en << 5) & ~0x00000020) == 0);
QDEC_CTL_REG = (QDEC_CTL_REG & ~0x00000020) | (single_sample_rst_en << 5);
}
__INLINE uint8_t qdec_ctl__auto_clr_en__getf(void)
{
uint32_t localVal = QDEC_CTL_REG;
return ((localVal & 0x00000010) >> 4);
}
__INLINE void qdec_ctl__auto_clr_en__setf(uint8_t auto_clr_en)
{
ASSERT_ERR(((auto_clr_en << 4) & ~0x00000010) == 0);
QDEC_CTL_REG = (QDEC_CTL_REG & ~0x00000010) | (auto_clr_en << 4);
}
__INLINE uint8_t qdec_ctl__soft_clr__getf(void)
{
uint32_t localVal = QDEC_CTL_REG;
return ((localVal & 0x00000008) >> 3);
}
__INLINE void qdec_ctl__soft_clr__setf(uint8_t soft_clr)
{
ASSERT_ERR(((soft_clr << 3) & ~0x00000008) == 0);
QDEC_CTL_REG = (QDEC_CTL_REG & ~0x00000008) | (soft_clr << 3);
}
__INLINE uint8_t qdec_ctl__soft_rst__getf(void)
{
uint32_t localVal = QDEC_CTL_REG;
return ((localVal & 0x00000004) >> 2);
}
__INLINE void qdec_ctl__soft_rst__setf(uint8_t soft_rst)
{
ASSERT_ERR(((soft_rst << 2) & ~0x00000004) == 0);
QDEC_CTL_REG = (QDEC_CTL_REG & ~0x00000004) | (soft_rst << 2);
}
__INLINE uint8_t qdec_ctl__qdec_start__getf(void)
{
uint32_t localVal = QDEC_CTL_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE void qdec_ctl__qdec_start__setf(uint8_t qdec_start)
{
ASSERT_ERR(((qdec_start << 1) & ~0x00000002) == 0);
QDEC_CTL_REG = (QDEC_CTL_REG & ~0x00000002) | (qdec_start << 1);
}
__INLINE uint8_t qdec_ctl__qdec_en__getf(void)
{
uint32_t localVal = QDEC_CTL_REG;
return ((localVal & 0x00000001) >> 0);
}
__INLINE void qdec_ctl__qdec_en__setf(uint8_t qdec_en)
{
ASSERT_ERR(((qdec_en << 0) & ~0x00000001) == 0);
QDEC_CTL_REG = (QDEC_CTL_REG & ~0x00000001) | (qdec_en << 0);
}
/**
* @brief QDEC_SAMP_CTL register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 19:16 DB_SAMP_DIV 0x0
* 11:08 QDEC_PTS 0x0
* 04:00 QDEC_DIVIDE 0x0
* </pre>
*/
#define QDEC_SAMP_CTL_REG (*(volatile uint32_t *)(0x40016004))
#define QDEC_SAMP_CTL_ADDR 0x40016004
#define QDEC_SAMP_CTL_OFFSET 0x00000004
__INLINE uint32_t qdec_samp_ctl_get(void)
{
return QDEC_SAMP_CTL_REG;
}
__INLINE void qdec_samp_ctl_set(uint32_t value)
{
QDEC_SAMP_CTL_REG = value;
}
// field definitions
#define DB_SAMP_DIV_MASK 0x000F0000
#define DB_SAMP_DIV_LSB 16
#define DB_SAMP_DIV_WIDTH 0x00000004
#define QDEC_PTS_MASK 0x00000F00
#define QDEC_PTS_LSB 8
#define QDEC_PTS_WIDTH 0x00000004
#define QDEC_DIVIDE_MASK 0x0000001F
#define QDEC_DIVIDE_LSB 0
#define QDEC_DIVIDE_WIDTH 0x00000005
#define DB_SAMP_DIV_RST 0x0
#define QDEC_PTS_RST 0x0
#define QDEC_DIVIDE_RST 0x0
__INLINE void qdec_samp_ctl_pack(uint8_t db_samp_div, uint8_t qdec_pts, uint8_t qdec_divide)
{
ASSERT_ERR(((db_samp_div << 16) & ~0x000F0000) == 0);
ASSERT_ERR(((qdec_pts << 8) & ~0x00000F00) == 0);
ASSERT_ERR(((qdec_divide << 0) & ~0x0000001F) == 0);
QDEC_SAMP_CTL_REG = (db_samp_div << 16) | (qdec_pts << 8) | (qdec_divide << 0);
}
__INLINE void qdec_samp_ctl_unpack(uint8_t* db_samp_div, uint8_t* qdec_pts, uint8_t* qdec_divide)
{
uint32_t localVal = QDEC_SAMP_CTL_REG;
*db_samp_div = (localVal & 0x000F0000) >> 16;
*qdec_pts = (localVal & 0x00000F00) >> 8;
*qdec_divide = (localVal & 0x0000001F) >> 0;
}
__INLINE uint8_t qdec_samp_ctl__db_samp_div__getf(void)
{
uint32_t localVal = QDEC_SAMP_CTL_REG;
return ((localVal & 0x000F0000) >> 16);
}
__INLINE void qdec_samp_ctl__db_samp_div__setf(uint8_t db_samp_div)
{
ASSERT_ERR(((db_samp_div << 16) & ~0x000F0000) == 0);
QDEC_SAMP_CTL_REG = (QDEC_SAMP_CTL_REG & ~0x000F0000) | (db_samp_div << 16);
}
__INLINE uint8_t qdec_samp_ctl__qdec_pts__getf(void)
{
uint32_t localVal = QDEC_SAMP_CTL_REG;
return ((localVal & 0x00000F00) >> 8);
}
__INLINE void qdec_samp_ctl__qdec_pts__setf(uint8_t qdec_pts)
{
ASSERT_ERR(((qdec_pts << 8) & ~0x00000F00) == 0);
QDEC_SAMP_CTL_REG = (QDEC_SAMP_CTL_REG & ~0x00000F00) | (qdec_pts << 8);
}
__INLINE uint8_t qdec_samp_ctl__qdec_divide__getf(void)
{
uint32_t localVal = QDEC_SAMP_CTL_REG;
return ((localVal & 0x0000001F) >> 0);
}
__INLINE void qdec_samp_ctl__qdec_divide__setf(uint8_t qdec_divide)
{
ASSERT_ERR(((qdec_divide << 0) & ~0x0000001F) == 0);
QDEC_SAMP_CTL_REG = (QDEC_SAMP_CTL_REG & ~0x0000001F) | (qdec_divide << 0);
}
/**
* @brief QDEC_SAMPLE register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 01:00 QDEC_SAMPLE 0x0
* </pre>
*/
#define QDEC_SAMPLE_REG (*(volatile uint32_t *)(0x40016008))
#define QDEC_SAMPLE_ADDR 0x40016008
#define QDEC_SAMPLE_OFFSET 0x00000008
__INLINE uint32_t qdec_sample_get(void)
{
return QDEC_SAMPLE_REG;
}
// field definitions
#define QDEC_SAMPLE_MASK 0x00000003
#define QDEC_SAMPLE_LSB 0
#define QDEC_SAMPLE_WIDTH 0x00000002
#define QDEC_SAMPLE_RST 0x0
__INLINE uint8_t qdec_sample__getf(void)
{
uint32_t localVal = QDEC_SAMPLE_REG;
ASSERT_ERR((localVal & ~0x00000003) == 0);
return (localVal >> 0);
}
/**
* @brief QDEC_ACC register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 10:00 ACC 0x0
* </pre>
*/
#define QDEC_ACC_REG (*(volatile uint32_t *)(0x4001600C))
#define QDEC_ACC_ADDR 0x4001600C
#define QDEC_ACC_OFFSET 0x0000000C
__INLINE uint32_t qdec_acc_get(void)
{
return QDEC_ACC_REG;
}
// field definitions
#define ACC_MASK 0x000007FF
#define ACC_LSB 0
#define ACC_WIDTH 0x0000000B
#define ACC_RST 0x0
__INLINE uint16_t qdec_acc__acc__getf(void)
{
uint32_t localVal = QDEC_ACC_REG;
ASSERT_ERR((localVal & ~0x000007FF) == 0);
return (localVal >> 0);
}
/**
* @brief QDEC_ACC_R register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 10:00 ACC_R 0x0
* </pre>
*/
#define QDEC_ACC_R_REG (*(volatile uint32_t *)(0x40016010))
#define QDEC_ACC_R_ADDR 0x40016010
#define QDEC_ACC_R_OFFSET 0x00000010
__INLINE uint32_t qdec_acc_r_get(void)
{
return QDEC_ACC_R_REG;
}
// field definitions
#define ACC_R_MASK 0x000007FF
#define ACC_R_LSB 0
#define ACC_R_WIDTH 0x0000000B
#define ACC_R_RST 0x0
__INLINE uint16_t qdec_acc_r__acc_r__getf(void)
{
uint32_t localVal = QDEC_ACC_R_REG;
ASSERT_ERR((localVal & ~0x000007FF) == 0);
return (localVal >> 0);
}
/**
* @brief QDEC_DB register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 03:00 DB 0x0
* </pre>
*/
#define QDEC_DB_REG (*(volatile uint32_t *)(0x40016014))
#define QDEC_DB_ADDR 0x40016014
#define QDEC_DB_OFFSET 0x00000014
__INLINE uint32_t qdec_db_get(void)
{
return QDEC_DB_REG;
}
// field definitions
#define DB_MASK 0x0000000F
#define DB_LSB 0
#define DB_WIDTH 0x00000004
#define DB_RST 0x0
__INLINE uint8_t qdec_db__db__getf(void)
{
uint32_t localVal = QDEC_DB_REG;
ASSERT_ERR((localVal & ~0x0000000F) == 0);
return (localVal >> 0);
}
/**
* @brief QDEC_DB_R register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 03:00 DB_R 0x0
* </pre>
*/
#define QDEC_DB_R_REG (*(volatile uint32_t *)(0x40016018))
#define QDEC_DB_R_ADDR 0x40016018
#define QDEC_DB_R_OFFSET 0x00000018
__INLINE uint32_t qdec_db_r_get(void)
{
return QDEC_DB_R_REG;
}
// field definitions
#define DB_R_MASK 0x0000000F
#define DB_R_LSB 0
#define DB_R_WIDTH 0x00000004
#define DB_R_RST 0x0
__INLINE uint8_t qdec_db_r__db_r__getf(void)
{
uint32_t localVal = QDEC_DB_R_REG;
ASSERT_ERR((localVal & ~0x0000000F) == 0);
return (localVal >> 0);
}
/**
* @brief QDEC_INT register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 03 DB_OF_RAW 0
* 02 ACC_OF_RAW 0
* 01 SAMPLE_END_RAW 0
* 00 SINGLE_SAMPLE_RAW 0
* </pre>
*/
#define QDEC_INT_REG (*(volatile uint32_t *)(0x4001601C))
#define QDEC_INT_ADDR 0x4001601C
#define QDEC_INT_OFFSET 0x0000001C
__INLINE uint32_t qdec_int_get(void)
{
return QDEC_INT_REG;
}
__INLINE void qdec_int_set(uint32_t value)
{
QDEC_INT_REG = value;
}
// field definitions
#define DB_OF_RAW_BIT 0x00000008
#define DB_OF_RAW_POS 3
#define ACC_OF_RAW_BIT 0x00000004
#define ACC_OF_RAW_POS 2
#define SAMPLE_END_RAW_BIT 0x00000002
#define SAMPLE_END_RAW_POS 1
#define SINGLE_SAMPLE_RAW_BIT 0x00000001
#define SINGLE_SAMPLE_RAW_POS 0
#define DB_OF_RAW_RST 0x0
#define ACC_OF_RAW_RST 0x0
#define SAMPLE_END_RAW_RST 0x0
#define SINGLE_SAMPLE_RAW_RST 0x0
__INLINE void qdec_int_pack(uint8_t db_of_raw, uint8_t acc_of_raw, uint8_t sample_end_raw, uint8_t single_sample_raw)
{
ASSERT_ERR(((db_of_raw << 3) & ~0x00000008) == 0);
ASSERT_ERR(((acc_of_raw << 2) & ~0x00000004) == 0);
ASSERT_ERR(((sample_end_raw << 1) & ~0x00000002) == 0);
ASSERT_ERR(((single_sample_raw << 0) & ~0x00000001) == 0);
QDEC_INT_REG = (db_of_raw << 3) | (acc_of_raw << 2) | (sample_end_raw << 1) | (single_sample_raw << 0);
}
__INLINE void qdec_int_unpack(uint8_t* db_of_raw, uint8_t* acc_of_raw, uint8_t* sample_end_raw, uint8_t* single_sample_raw)
{
uint32_t localVal = QDEC_INT_REG;
*db_of_raw = (localVal & 0x00000008) >> 3;
*acc_of_raw = (localVal & 0x00000004) >> 2;
*sample_end_raw = (localVal & 0x00000002) >> 1;
*single_sample_raw = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t qdec_int__db_of_raw__getf(void)
{
uint32_t localVal = QDEC_INT_REG;
return ((localVal & 0x00000008) >> 3);
}
__INLINE void qdec_int__db_of_raw__setf(uint8_t db_of_raw)
{
ASSERT_ERR(((db_of_raw << 3) & ~0x00000008) == 0);
QDEC_INT_REG = (QDEC_INT_REG & ~0x00000008) | (db_of_raw << 3);
}
__INLINE uint8_t qdec_int__acc_of_raw__getf(void)
{
uint32_t localVal = QDEC_INT_REG;
return ((localVal & 0x00000004) >> 2);
}
__INLINE void qdec_int__acc_of_raw__setf(uint8_t acc_of_raw)
{
ASSERT_ERR(((acc_of_raw << 2) & ~0x00000004) == 0);
QDEC_INT_REG = (QDEC_INT_REG & ~0x00000004) | (acc_of_raw << 2);
}
__INLINE uint8_t qdec_int__sample_end_raw__getf(void)
{
uint32_t localVal = QDEC_INT_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE void qdec_int__sample_end_raw__setf(uint8_t sample_end_raw)
{
ASSERT_ERR(((sample_end_raw << 1) & ~0x00000002) == 0);
QDEC_INT_REG = (QDEC_INT_REG & ~0x00000002) | (sample_end_raw << 1);
}
__INLINE uint8_t qdec_int__single_sample_raw__getf(void)
{
uint32_t localVal = QDEC_INT_REG;
return ((localVal & 0x00000001) >> 0);
}
__INLINE void qdec_int__single_sample_raw__setf(uint8_t single_sample_raw)
{
ASSERT_ERR(((single_sample_raw << 0) & ~0x00000001) == 0);
QDEC_INT_REG = (QDEC_INT_REG & ~0x00000001) | (single_sample_raw << 0);
}
/**
* @brief QDEC_INT_MSK register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 03 DB_OF_MSK 0
* 02 ACC_OF_MSK 0
* 01 SAMPLE_END_MSK 0
* 00 SINGLE_SAMPLE_MSK 0
* </pre>
*/
#define QDEC_INT_MSK_REG (*(volatile uint32_t *)(0x40016020))
#define QDEC_INT_MSK_ADDR 0x40016020
#define QDEC_INT_MSK_OFFSET 0x00000020
__INLINE uint32_t qdec_int_msk_get(void)
{
return QDEC_INT_MSK_REG;
}
__INLINE void qdec_int_msk_set(uint32_t value)
{
QDEC_INT_MSK_REG = value;
}
// field definitions
#define DB_OF_MSK_BIT 0x00000008
#define DB_OF_MSK_POS 3
#define ACC_OF_MSK_BIT 0x00000004
#define ACC_OF_MSK_POS 2
#define SAMPLE_END_MSK_BIT 0x00000002
#define SAMPLE_END_MSK_POS 1
#define SINGLE_SAMPLE_MSK_BIT 0x00000001
#define SINGLE_SAMPLE_MSK_POS 0
#define DB_OF_MSK_RST 0x0
#define ACC_OF_MSK_RST 0x0
#define SAMPLE_END_MSK_RST 0x0
#define SINGLE_SAMPLE_MSK_RST 0x0
__INLINE void qdec_int_msk_pack(uint8_t db_of_msk, uint8_t acc_of_msk, uint8_t sample_end_msk, uint8_t single_sample_msk)
{
ASSERT_ERR(((db_of_msk << 3) & ~0x00000008) == 0);
ASSERT_ERR(((acc_of_msk << 2) & ~0x00000004) == 0);
ASSERT_ERR(((sample_end_msk << 1) & ~0x00000002) == 0);
ASSERT_ERR(((single_sample_msk << 0) & ~0x00000001) == 0);
QDEC_INT_MSK_REG = (db_of_msk << 3) | (acc_of_msk << 2) | (sample_end_msk << 1) | (single_sample_msk << 0);
}
__INLINE void qdec_int_msk_unpack(uint8_t* db_of_msk, uint8_t* acc_of_msk, uint8_t* sample_end_msk, uint8_t* single_sample_msk)
{
uint32_t localVal = QDEC_INT_MSK_REG;
*db_of_msk = (localVal & 0x00000008) >> 3;
*acc_of_msk = (localVal & 0x00000004) >> 2;
*sample_end_msk = (localVal & 0x00000002) >> 1;
*single_sample_msk = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t qdec_int_msk__db_of_msk__getf(void)
{
uint32_t localVal = QDEC_INT_MSK_REG;
return ((localVal & 0x00000008) >> 3);
}
__INLINE void qdec_int_msk__db_of_msk__setf(uint8_t db_of_msk)
{
ASSERT_ERR(((db_of_msk << 3) & ~0x00000008) == 0);
QDEC_INT_MSK_REG = (QDEC_INT_MSK_REG & ~0x00000008) | (db_of_msk << 3);
}
__INLINE uint8_t qdec_int_msk__acc_of_msk__getf(void)
{
uint32_t localVal = QDEC_INT_MSK_REG;
return ((localVal & 0x00000004) >> 2);
}
__INLINE void qdec_int_msk__acc_of_msk__setf(uint8_t acc_of_msk)
{
ASSERT_ERR(((acc_of_msk << 2) & ~0x00000004) == 0);
QDEC_INT_MSK_REG = (QDEC_INT_MSK_REG & ~0x00000004) | (acc_of_msk << 2);
}
__INLINE uint8_t qdec_int_msk__sample_end_msk__getf(void)
{
uint32_t localVal = QDEC_INT_MSK_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE void qdec_int_msk__sample_end_msk__setf(uint8_t sample_end_msk)
{
ASSERT_ERR(((sample_end_msk << 1) & ~0x00000002) == 0);
QDEC_INT_MSK_REG = (QDEC_INT_MSK_REG & ~0x00000002) | (sample_end_msk << 1);
}
__INLINE uint8_t qdec_int_msk__single_sample_msk__getf(void)
{
uint32_t localVal = QDEC_INT_MSK_REG;
return ((localVal & 0x00000001) >> 0);
}
__INLINE void qdec_int_msk__single_sample_msk__setf(uint8_t single_sample_msk)
{
ASSERT_ERR(((single_sample_msk << 0) & ~0x00000001) == 0);
QDEC_INT_MSK_REG = (QDEC_INT_MSK_REG & ~0x00000001) | (single_sample_msk << 0);
}
/**
* @brief QDEC_STAT register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 QDEC_BUSY 0
* </pre>
*/
#define QDEC_STAT_REG (*(volatile uint32_t *)(0x40016024))
#define QDEC_STAT_ADDR 0x40016024
#define QDEC_STAT_OFFSET 0x00000024
__INLINE uint32_t qdec_stat_get(void)
{
return QDEC_STAT_REG;
}
// field definitions
#define QDEC_BUSY_BIT 0x00000001
#define QDEC_BUSY_POS 0
#define QDEC_BUSY_RST 0x0
__INLINE uint8_t qdec_stat__qdec_busy__getf(void)
{
uint32_t localVal = QDEC_STAT_REG;
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
#endif // _XC_REG_QDEC_H_
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_rf.h
+522
View File
@@ -0,0 +1,522 @@
#ifndef _XC_REG_RF_H_
#define _XC_REG_RF_H_
#include <stdint.h>
#include "xc6xxx.h"
#define XC_REG_RF_BASE_ADDR 0x53021000
#define XC_REG_RF_DECODING_MASK 0x000000FF
#ifdef XC62XX_RFANA2_BIT13_SET
#define RF_ANA2_REG (*(volatile uint32_t *)(0x53021008))
/* This code needs to be removed from the mass production chip
Solve the RF short-circuit bug in the chip
*/
__INLINE void rf_ana2_bit13_setf(uint8_t bit13_val)
{
RF_ANA2_REG = (RF_ANA2_REG & ~0x00002000) | (bit13_val << 13);
}
#endif // XC62XX_RFANA2_BIT13_SET
#if defined(XC62XX_CLOCK_CONFIG)
#define RF_ANA25_REG (*(volatile uint32_t *)(0x53021064))
/* Enhance the driving capability of bbpll */
__INLINE void rf_ana25_bit11_12_setf(uint8_t bit11_12_val)
{
ASSERT_ERR(((bit11_12_val << 11) & ~0x00001800) == 0);
RF_ANA25_REG = (RF_ANA25_REG & ~0x00001800) | (bit11_12_val << 11);
}
#endif // XC62XX_CLOCK_CONFIG
/**
* @brief RF_ANA26 register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15 clk_bbpll_en 0
* 14 clk_bbpll_rstn 0
* 13 bbpll_en 0
* 12 bbpll_core64m_en 0
* 11 bbpll_rc16m_sel 0
* 10:09 bbpll_bufmsel 0x1
* 08:06 bbpll_res 0x2
* 05:00 bbpll_loopdiv 0x4
* </pre>
*/
#if defined(M0_LORA_RF_ANALOG_REG26_REG27)
#define RF_ANA26_REG (*(volatile uint32_t *)(0x4002F068))
#define RF_ANA26_ADDR 0x4002F068
#define RF_ANA26_OFFSET 0x00000068
#else
#define RF_ANA26_REG (*(volatile uint32_t *)(0x53021068))
#define RF_ANA26_ADDR 0x53021068
#define RF_ANA26_OFFSET 0x00000068
#endif
__INLINE uint16_t rf_ana26_get(void)
{
return RF_ANA26_REG;
}
__INLINE void rf_ana26_set(uint16_t value)
{
RF_ANA26_REG = value;
}
// field definitions
#define CLK_BBPLL_EN_BIT 0x00008000
#define CLK_BBPLL_EN_POS 15
#define CLK_BBPLL_RSTN_BIT 0x00004000
#define CLK_BBPLL_RSTN_POS 14
#define BBPLL_EN_BIT 0x00002000
#define BBPLL_EN_POS 13
#define BBPLL_CORE_64M_EN_BIT 0x00001000
#define BBPLL_CORE_64M_EN_POS 12
#define BBPLL_RC_16M_SEL_BIT 0x00000800
#define BBPLL_RC_16M_SEL_POS 11
#define BBPLL_BUFMSEL_MASK 0x00000600
#define BBPLL_BUFMSEL_LSB 9
#define BBPLL_BUFMSEL_WIDTH 0x00000002
#define BBPLL_RES_MASK 0x000001C0
#define BBPLL_RES_LSB 6
#define BBPLL_RES_WIDTH 0x00000003
#define BBPLL_LOOPDIV_MASK 0x0000003F
#define BBPLL_LOOPDIV_LSB 0
#define BBPLL_LOOPDIV_WIDTH 0x00000006
#define CLK_BBPLL_EN_RST 0x0
#define CLK_BBPLL_RSTN_RST 0x0
#define BBPLL_EN_RST 0x0
#define BBPLL_CORE_64M_EN_RST 0x0
#define BBPLL_RC_16M_SEL_RST 0x0
#define BBPLL_BUFMSEL_RST 0x1
#define BBPLL_RES_RST 0x2
#define BBPLL_LOOPDIV_RST 0x4
__INLINE void rf_ana26_pack(uint8_t clk_bbpll_en, uint8_t clk_bbpll_rstn, uint8_t bbpll_en, uint8_t bbpll_core64m_en, uint8_t bbpll_rc16m_sel, uint8_t bbpll_bufmsel, uint8_t bbpll_res, uint8_t bbpll_loopdiv)
{
ASSERT_ERR(((clk_bbpll_en << 15) & ~0x00008000) == 0);
ASSERT_ERR(((clk_bbpll_rstn << 14) & ~0x00004000) == 0);
ASSERT_ERR(((bbpll_en << 13) & ~0x00002000) == 0);
ASSERT_ERR(((bbpll_core64m_en << 12) & ~0x00001000) == 0);
ASSERT_ERR(((bbpll_rc16m_sel << 11) & ~0x00000800) == 0);
ASSERT_ERR(((bbpll_bufmsel << 9) & ~0x00000600) == 0);
ASSERT_ERR(((bbpll_res << 6) & ~0x000001C0) == 0);
ASSERT_ERR(((bbpll_loopdiv << 0) & ~0x0000003F) == 0);
RF_ANA26_REG = (clk_bbpll_en << 15) | (clk_bbpll_rstn << 14) | (bbpll_en << 13) | (bbpll_core64m_en << 12) | (bbpll_rc16m_sel << 11) | (bbpll_bufmsel << 9) | (bbpll_res << 6) | (bbpll_loopdiv << 0);
}
__INLINE void rf_ana26_unpack(uint8_t* clk_bbpll_en, uint8_t* clk_bbpll_rstn, uint8_t* bbpll_en, uint8_t* bbpll_core64m_en, uint8_t* bbpll_rc16m_sel, uint8_t* bbpll_bufmsel, uint8_t* bbpll_res, uint8_t* bbpll_loopdiv)
{
uint32_t localVal = RF_ANA26_REG;
*clk_bbpll_en = (localVal & 0x00008000) >> 15;
*clk_bbpll_rstn = (localVal & 0x00004000) >> 14;
*bbpll_en = (localVal & 0x00002000) >> 13;
*bbpll_core64m_en = (localVal & 0x00001000) >> 12;
*bbpll_rc16m_sel = (localVal & 0x00000800) >> 11;
*bbpll_bufmsel = (localVal & 0x00000600) >> 9;
*bbpll_res = (localVal & 0x000001C0) >> 6;
*bbpll_loopdiv = (localVal & 0x0000003F) >> 0;
}
__INLINE uint8_t rf_ana26__clk_bbpll_en__getf(void)
{
uint32_t localVal = RF_ANA26_REG;
return ((localVal & 0x00008000) >> 15);
}
__INLINE void rf_ana26__clk_bbpll_en__setf(uint8_t clk_bbpll_en)
{
ASSERT_ERR(((clk_bbpll_en << 15) & ~0x00008000) == 0);
RF_ANA26_REG = (RF_ANA26_REG & ~0x00008000) | (clk_bbpll_en << 15);
}
__INLINE uint8_t rf_ana26__clk_bbpll_rstn__getf(void)
{
uint32_t localVal = RF_ANA26_REG;
return ((localVal & 0x00004000) >> 14);
}
__INLINE void rf_ana26__clk_bbpll_rstn__setf(uint8_t clk_bbpll_rstn)
{
ASSERT_ERR(((clk_bbpll_rstn << 14) & ~0x00004000) == 0);
RF_ANA26_REG = (RF_ANA26_REG & ~0x00004000) | (clk_bbpll_rstn << 14);
}
__INLINE uint8_t rf_ana26__bbpll_en__getf(void)
{
uint32_t localVal = RF_ANA26_REG;
return ((localVal & 0x00002000) >> 13);
}
__INLINE void rf_ana26__bbpll_en__setf(uint8_t bbpll_en)
{
ASSERT_ERR(((bbpll_en << 13) & ~0x00002000) == 0);
RF_ANA26_REG = (RF_ANA26_REG & ~0x00002000) | (bbpll_en << 13);
}
__INLINE uint8_t rf_ana26__bbpll_core_64m_en__getf(void)
{
uint32_t localVal = RF_ANA26_REG;
return ((localVal & 0x00001000) >> 12);
}
__INLINE void rf_ana26__bbpll_core_64m_en__setf(uint8_t bbpll_core64m_en)
{
ASSERT_ERR(((bbpll_core64m_en << 12) & ~0x00001000) == 0);
RF_ANA26_REG = (RF_ANA26_REG & ~0x00001000) | (bbpll_core64m_en << 12);
}
__INLINE uint8_t rf_ana26__bbpll_rc_16m_sel__getf(void)
{
uint32_t localVal = RF_ANA26_REG;
return ((localVal & 0x00000800) >> 11);
}
__INLINE void rf_ana26__bbpll_rc_16m_sel__setf(uint8_t bbpll_rc16m_sel)
{
ASSERT_ERR(((bbpll_rc16m_sel << 11) & ~0x00000800) == 0);
RF_ANA26_REG = (RF_ANA26_REG & ~0x00000800) | (bbpll_rc16m_sel << 11);
}
__INLINE uint8_t rf_ana26__bbpll_bufmsel__getf(void)
{
uint32_t localVal = RF_ANA26_REG;
return ((localVal & 0x00000600) >> 9);
}
__INLINE void rf_ana26__bbpll_bufmsel__setf(uint8_t bbpll_bufmsel)
{
ASSERT_ERR(((bbpll_bufmsel << 9) & ~0x00000600) == 0);
RF_ANA26_REG = (RF_ANA26_REG & ~0x00000600) | (bbpll_bufmsel << 9);
}
__INLINE uint8_t rf_ana26__bbpll_res__getf(void)
{
uint32_t localVal = RF_ANA26_REG;
return ((localVal & 0x000001C0) >> 6);
}
__INLINE void rf_ana26__bbpll_res__setf(uint8_t bbpll_res)
{
ASSERT_ERR(((bbpll_res << 6) & ~0x000001C0) == 0);
RF_ANA26_REG = (RF_ANA26_REG & ~0x000001C0) | (bbpll_res << 6);
}
__INLINE uint8_t rf_ana26__bbpll_loopdiv__getf(void)
{
uint32_t localVal = RF_ANA26_REG;
return ((localVal & 0x0000003F) >> 0);
}
__INLINE void rf_ana26__bbpll_loopdiv__setf(uint8_t bbpll_loopdiv)
{
ASSERT_ERR(((bbpll_loopdiv << 0) & ~0x0000003F) == 0);
RF_ANA26_REG = (RF_ANA26_REG & ~0x0000003F) | (bbpll_loopdiv << 0);
}
/**
* @brief RF_ANA27 register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15:13 bbpll_dvddres 0x4
* 12:10 bbpll_icp 0x3
* 07 bbpll16m_sel 0
* 01 bbpll_core96m_en 0
* 00 spi_sx_afc_rstn 0
* </pre>
*/
#if defined(M0_LORA_RF_ANALOG_REG26_REG27)
#define RF_ANA27_REG (*(volatile uint32_t *)(0x4002F06C))
#define RF_ANA27_ADDR 0x4002F06C
#define RF_ANA27_OFFSET 0x0000006C
#else
#define RF_ANA27_REG (*(volatile uint32_t *)(0x5302106C))
#define RF_ANA27_ADDR 0x5302106C
#define RF_ANA27_OFFSET 0x0000006C
#endif
__INLINE uint16_t rf_ana27_get(void)
{
return RF_ANA27_REG;
}
__INLINE void rf_ana27_set(uint16_t value)
{
RF_ANA27_REG = value;
}
// field definitions
#define BBPLL_DVDDRES_MASK 0x0000E000
#define BBPLL_DVDDRES_LSB 13
#define BBPLL_DVDDRES_WIDTH 0x00000003
#define BBPLL_ICP_MASK 0x00001C00
#define BBPLL_ICP_LSB 10
#define BBPLL_ICP_WIDTH 0x00000003
#define BBPLL_16M_SEL_BIT 0x00000080
#define BBPLL_16M_SEL_POS 7
#define BBPLL_CORE_96M_EN_BIT 0x00000002
#define BBPLL_CORE_96M_EN_POS 1
#define SPI_SX_AFC_RSTN_BIT 0x00000001
#define SPI_SX_AFC_RSTN_POS 0
#define BBPLL_DVDDRES_RST 0x4
#define BBPLL_ICP_RST 0x3
#define BBPLL_16M_SEL_RST 0x0
#define BBPLL_CORE_96M_EN_RST 0x0
#define SPI_SX_AFC_RSTN_RST 0x0
__INLINE void rf_ana27_pack(uint8_t bbpll_dvddres, uint8_t bbpll_icp, uint8_t bbpll16m_sel, uint8_t bbpll_core96m_en, uint8_t spi_sx_afc_rstn)
{
ASSERT_ERR(((bbpll_dvddres << 13) & ~0x0000E000) == 0);
ASSERT_ERR(((bbpll_icp << 10) & ~0x00001C00) == 0);
ASSERT_ERR(((bbpll16m_sel << 7) & ~0x00000080) == 0);
ASSERT_ERR(((bbpll_core96m_en << 1) & ~0x00000002) == 0);
ASSERT_ERR(((spi_sx_afc_rstn << 0) & ~0x00000001) == 0);
RF_ANA27_REG = (bbpll_dvddres << 13) | (bbpll_icp << 10) | (bbpll16m_sel << 7) | (bbpll_core96m_en << 1) | (spi_sx_afc_rstn << 0);
}
__INLINE void rf_ana27_unpack(uint8_t* bbpll_dvddres, uint8_t* bbpll_icp, uint8_t* bbpll16m_sel, uint8_t* bbpll_core96m_en, uint8_t* spi_sx_afc_rstn)
{
uint32_t localVal = RF_ANA27_REG;
*bbpll_dvddres = (localVal & 0x0000E000) >> 13;
*bbpll_icp = (localVal & 0x00001C00) >> 10;
*bbpll16m_sel = (localVal & 0x00000080) >> 7;
*bbpll_core96m_en = (localVal & 0x00000002) >> 1;
*spi_sx_afc_rstn = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t rf_ana27__bbpll_dvddres__getf(void)
{
uint32_t localVal = RF_ANA27_REG;
return ((localVal & 0x0000E000) >> 13);
}
__INLINE void rf_ana27__bbpll_dvddres__setf(uint8_t bbpll_dvddres)
{
ASSERT_ERR(((bbpll_dvddres << 13) & ~0x0000E000) == 0);
RF_ANA27_REG = (RF_ANA27_REG & ~0x0000E000) | (bbpll_dvddres << 13);
}
__INLINE uint8_t rf_ana27__bbpll_icp__getf(void)
{
uint32_t localVal = RF_ANA27_REG;
return ((localVal & 0x00001C00) >> 10);
}
__INLINE void rf_ana27__bbpll_icp__setf(uint8_t bbpll_icp)
{
ASSERT_ERR(((bbpll_icp << 10) & ~0x00001C00) == 0);
RF_ANA27_REG = (RF_ANA27_REG & ~0x00001C00) | (bbpll_icp << 10);
}
__INLINE uint8_t rf_ana27__bbpll_16m_sel__getf(void)
{
uint32_t localVal = RF_ANA27_REG;
return ((localVal & 0x00000080) >> 7);
}
__INLINE void rf_ana27__bbpll_16m_sel__setf(uint8_t bbpll16m_sel)
{
ASSERT_ERR(((bbpll16m_sel << 7) & ~0x00000080) == 0);
RF_ANA27_REG = (RF_ANA27_REG & ~0x00000080) | (bbpll16m_sel << 7);
}
__INLINE uint8_t rf_ana27__bbpll_core_96m_en__getf(void)
{
uint32_t localVal = RF_ANA27_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE void rf_ana27__bbpll_core_96m_en__setf(uint8_t bbpll_core96m_en)
{
#if (defined(M0_LORA_RF_ANALOG_REG26_REG27) || defined(M4_LORA_RF_ANALOG_REG26_REG27))
ASSERT_ERR(((bbpll_core96m_en << 13) & ~0x00002000) == 0);
RF_ANA27_REG = (RF_ANA27_REG & ~0x00002000) | (bbpll_core96m_en << 13);
#else
ASSERT_ERR(((bbpll_core96m_en << 1) & ~0x00000002) == 0);
RF_ANA27_REG = (RF_ANA27_REG & ~0x00000002) | (bbpll_core96m_en << 1);
#endif
}
__INLINE uint8_t rf_ana27__spi_sx_afc_rstn__getf(void)
{
uint32_t localVal = RF_ANA27_REG;
return ((localVal & 0x00000001) >> 0);
}
__INLINE void rf_ana27__spi_sx_afc_rstn__setf(uint8_t spi_sx_afc_rstn)
{
ASSERT_ERR(((spi_sx_afc_rstn << 0) & ~0x00000001) == 0);
RF_ANA27_REG = (RF_ANA27_REG & ~0x00000001) | (spi_sx_afc_rstn << 0);
}
/**
* @brief BT_RF_PM_REG register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15 bt_en_pm_fc_soft 0
* 14 bt_en_pm 0
* 13:06 ch_cnt_delay 0x80
* 05 da_ism_rstn_soften 0
* 04 da_ism_dac_rstn_soft 0
* 03 da_ism_sx_dsm_resetn_soft 0
* 02 da_ism_sx_afc_resetn_soft 0
* </pre>
*/
#define BT_RF_PM_REG_REG (*(volatile uint32_t *)(0x530210B0))
#define BT_RF_PM_REG_ADDR 0x530210B0
#define BT_RF_PM_REG_OFFSET 0x000000B0
__INLINE uint16_t bt_rf_pm_reg_get(void)
{
return BT_RF_PM_REG_REG;
}
__INLINE void bt_rf_pm_reg_set(uint16_t value)
{
BT_RF_PM_REG_REG = value;
}
// field definitions
#define BT_EN_PM_FC_SOFT_BIT 0x00008000
#define BT_EN_PM_FC_SOFT_POS 15
#define BT_EN_PM_BIT 0x00004000
#define BT_EN_PM_POS 14
#define CH_CNT_DELAY_MASK 0x00003FC0
#define CH_CNT_DELAY_LSB 6
#define CH_CNT_DELAY_WIDTH 0x00000008
#define DA_ISM_RSTN_SOFTEN_BIT 0x00000020
#define DA_ISM_RSTN_SOFTEN_POS 5
#define DA_ISM_DAC_RSTN_SOFT_BIT 0x00000010
#define DA_ISM_DAC_RSTN_SOFT_POS 4
#define DA_ISM_SX_DSM_RESETN_SOFT_BIT 0x00000008
#define DA_ISM_SX_DSM_RESETN_SOFT_POS 3
#define DA_ISM_SX_AFC_RESETN_SOFT_BIT 0x00000004
#define DA_ISM_SX_AFC_RESETN_SOFT_POS 2
#define BT_EN_PM_FC_SOFT_RST 0x0
#define BT_EN_PM_RST 0x0
#define CH_CNT_DELAY_RST 0x80
#define DA_ISM_RSTN_SOFTEN_RST 0x0
#define DA_ISM_DAC_RSTN_SOFT_RST 0x0
#define DA_ISM_SX_DSM_RESETN_SOFT_RST 0x0
#define DA_ISM_SX_AFC_RESETN_SOFT_RST 0x0
__INLINE void bt_rf_pm_reg_pack(uint8_t bt_en_pm_fc_soft, uint8_t bt_en_pm, uint8_t ch_cnt_delay, uint8_t da_ism_rstn_soften, uint8_t da_ism_dac_rstn_soft, uint8_t da_ism_sx_dsm_resetn_soft, uint8_t da_ism_sx_afc_resetn_soft)
{
ASSERT_ERR(((bt_en_pm_fc_soft << 15) & ~0x00008000) == 0);
ASSERT_ERR(((bt_en_pm << 14) & ~0x00004000) == 0);
ASSERT_ERR(((ch_cnt_delay << 6) & ~0x00003FC0) == 0);
ASSERT_ERR(((da_ism_rstn_soften << 5) & ~0x00000020) == 0);
ASSERT_ERR(((da_ism_dac_rstn_soft << 4) & ~0x00000010) == 0);
ASSERT_ERR(((da_ism_sx_dsm_resetn_soft << 3) & ~0x00000008) == 0);
ASSERT_ERR(((da_ism_sx_afc_resetn_soft << 2) & ~0x00000004) == 0);
BT_RF_PM_REG_REG = (bt_en_pm_fc_soft << 15) | (bt_en_pm << 14) | (ch_cnt_delay << 6) | (da_ism_rstn_soften << 5) | (da_ism_dac_rstn_soft << 4) | (da_ism_sx_dsm_resetn_soft << 3) | (da_ism_sx_afc_resetn_soft << 2);
}
__INLINE void bt_rf_pm_reg_unpack(uint8_t* bt_en_pm_fc_soft, uint8_t* bt_en_pm, uint8_t* ch_cnt_delay, uint8_t* da_ism_rstn_soften, uint8_t* da_ism_dac_rstn_soft, uint8_t* da_ism_sx_dsm_resetn_soft, uint8_t* da_ism_sx_afc_resetn_soft)
{
uint32_t localVal = BT_RF_PM_REG_REG;
*bt_en_pm_fc_soft = (localVal & 0x00008000) >> 15;
*bt_en_pm = (localVal & 0x00004000) >> 14;
*ch_cnt_delay = (localVal & 0x00003FC0) >> 6;
*da_ism_rstn_soften = (localVal & 0x00000020) >> 5;
*da_ism_dac_rstn_soft = (localVal & 0x00000010) >> 4;
*da_ism_sx_dsm_resetn_soft = (localVal & 0x00000008) >> 3;
*da_ism_sx_afc_resetn_soft = (localVal & 0x00000004) >> 2;
}
__INLINE uint8_t bt_rf_pm_reg__bt_en_pm_fc_soft__getf(void)
{
uint32_t localVal = BT_RF_PM_REG_REG;
return ((localVal & 0x00008000) >> 15);
}
__INLINE void bt_rf_pm_reg__bt_en_pm_fc_soft__setf(uint8_t bt_en_pm_fc_soft)
{
ASSERT_ERR(((bt_en_pm_fc_soft << 15) & ~0x00008000) == 0);
BT_RF_PM_REG_REG = (BT_RF_PM_REG_REG & ~0x00008000) | (bt_en_pm_fc_soft << 15);
}
__INLINE uint8_t bt_rf_pm_reg__bt_en_pm__getf(void)
{
uint32_t localVal = BT_RF_PM_REG_REG;
return ((localVal & 0x00004000) >> 14);
}
__INLINE void bt_rf_pm_reg__bt_en_pm__setf(uint8_t bt_en_pm)
{
ASSERT_ERR(((bt_en_pm << 14) & ~0x00004000) == 0);
BT_RF_PM_REG_REG = (BT_RF_PM_REG_REG & ~0x00004000) | (bt_en_pm << 14);
}
__INLINE uint8_t bt_rf_pm_reg__ch_cnt_delay__getf(void)
{
uint32_t localVal = BT_RF_PM_REG_REG;
return ((localVal & 0x00003FC0) >> 6);
}
__INLINE void bt_rf_pm_reg__ch_cnt_delay__setf(uint8_t ch_cnt_delay)
{
ASSERT_ERR(((ch_cnt_delay << 6) & ~0x00003FC0) == 0);
BT_RF_PM_REG_REG = (BT_RF_PM_REG_REG & ~0x00003FC0) | (ch_cnt_delay << 6);
}
__INLINE uint8_t bt_rf_pm_reg__da_ism_rstn_soften__getf(void)
{
uint32_t localVal = BT_RF_PM_REG_REG;
return ((localVal & 0x00000020) >> 5);
}
__INLINE void bt_rf_pm_reg__da_ism_rstn_soften__setf(uint8_t da_ism_rstn_soften)
{
ASSERT_ERR(((da_ism_rstn_soften << 5) & ~0x00000020) == 0);
BT_RF_PM_REG_REG = (BT_RF_PM_REG_REG & ~0x00000020) | (da_ism_rstn_soften << 5);
}
__INLINE uint8_t bt_rf_pm_reg__da_ism_dac_rstn_soft__getf(void)
{
uint32_t localVal = BT_RF_PM_REG_REG;
return ((localVal & 0x00000010) >> 4);
}
__INLINE void bt_rf_pm_reg__da_ism_dac_rstn_soft__setf(uint8_t da_ism_dac_rstn_soft)
{
ASSERT_ERR(((da_ism_dac_rstn_soft << 4) & ~0x00000010) == 0);
BT_RF_PM_REG_REG = (BT_RF_PM_REG_REG & ~0x00000010) | (da_ism_dac_rstn_soft << 4);
}
__INLINE uint8_t bt_rf_pm_reg__da_ism_sx_dsm_resetn_soft__getf(void)
{
uint32_t localVal = BT_RF_PM_REG_REG;
return ((localVal & 0x00000008) >> 3);
}
__INLINE void bt_rf_pm_reg__da_ism_sx_dsm_resetn_soft__setf(uint8_t da_ism_sx_dsm_resetn_soft)
{
ASSERT_ERR(((da_ism_sx_dsm_resetn_soft << 3) & ~0x00000008) == 0);
BT_RF_PM_REG_REG = (BT_RF_PM_REG_REG & ~0x00000008) | (da_ism_sx_dsm_resetn_soft << 3);
}
__INLINE uint8_t bt_rf_pm_reg__da_ism_sx_afc_resetn_soft__getf(void)
{
uint32_t localVal = BT_RF_PM_REG_REG;
return ((localVal & 0x00000004) >> 2);
}
__INLINE void bt_rf_pm_reg__da_ism_sx_afc_resetn_soft__setf(uint8_t da_ism_sx_afc_resetn_soft)
{
ASSERT_ERR(((da_ism_sx_afc_resetn_soft << 2) & ~0x00000004) == 0);
BT_RF_PM_REG_REG = (BT_RF_PM_REG_REG & ~0x00000004) | (da_ism_sx_afc_resetn_soft << 2);
}
#endif // _XC_REG_RF_H_
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_rtc.h
+3058
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_spi.h
+1376
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_timer.h
+207
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#ifndef _XC_REG_TIMER_H_
#define _XC_REG_TIMER_H_
#include <stdint.h>
#define XC_REG_TIMER_BASE_ADDR 0x40003000
#define XC_REG_TIMER_DECODING_MASK 0x0000001F
/**
* @brief TIMER_TLC register definition
*/
#define TIMER_TLC_REG(i) (*(volatile uint32_t *)(0x40003000 + timer_offset[i]))
#define TIMER_TLC_ADDR(i) (0x40003000 + timer_offset[i])
#define TIMER_TLC_OFFSET 0x00000000
__INLINE uint32_t timer_tlc_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
return TIMER_TLC_REG(reg_idx);
}
__INLINE void timer_tlc_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 3);
TIMER_TLC_REG(reg_idx) = value;
}
/**
* @brief TIMER_TCV register definition
*/
#define TIMER_TCV_REG(i) (*(volatile uint32_t *)(0x40003004 + timer_offset[i]))
#define TIMER_TCV_ADDR(i) (0x40003004 + timer_offset[i])
#define TIMER_TCV_OFFSET 0x00000004
__INLINE uint32_t timer_tcv_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
return TIMER_TCV_REG(reg_idx);
}
/**
* @brief TIMER_TCR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 02 TIM 0
* 01 TMS 0
* 00 TES 0
* </pre>
*/
#define TIMER_TCR_REG(i) (*(volatile uint32_t *)(0x40003008 + timer_offset[i]))
#define TIMER_TCR_ADDR(i) (0x40003008 + timer_offset[i])
#define TIMER_TCR_OFFSET 0x00000008
__INLINE uint32_t timer_tcr_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
return TIMER_TCR_REG(reg_idx);
}
__INLINE void timer_tcr_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 3);
TIMER_TCR_REG(reg_idx) = value;
}
// field definitions
#define TIM_BIT 0x00000004
#define TIM_POS 2
#define TMS_BIT 0x00000002
#define TMS_POS 1
#define TES_BIT 0x00000001
#define TES_POS 0
#define TIM_RST 0x0
#define TMS_RST 0x0
#define TES_RST 0x0
__INLINE void timer_tcr_pack(uint32_t reg_idx, uint8_t tim, uint8_t tms, uint8_t tes)
{
ASSERT_ERR(reg_idx <= 3);
ASSERT_ERR(((tim << 2) & ~0x00000004) == 0);
ASSERT_ERR(((tms << 1) & ~0x00000002) == 0);
ASSERT_ERR(((tes << 0) & ~0x00000001) == 0);
TIMER_TCR_REG(reg_idx) = (tim << 2) | (tms << 1) | (tes << 0);
}
__INLINE void timer_tcr_unpack(uint32_t reg_idx, uint8_t* tim, uint8_t* tms, uint8_t* tes)
{
ASSERT_ERR(reg_idx <= 3);
uint32_t localVal = TIMER_TCR_REG(reg_idx);
*tim = (localVal & 0x00000004) >> 2;
*tms = (localVal & 0x00000002) >> 1;
*tes = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t timer_tcr__tim__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
uint32_t localVal = TIMER_TCR_REG(reg_idx);
return ((localVal & 0x00000004) >> 2);
}
__INLINE void timer_tcr__tim__setf(uint32_t reg_idx, uint8_t tim)
{
ASSERT_ERR(reg_idx <= 3);
ASSERT_ERR(((tim << 2) & ~0x00000004) == 0);
TIMER_TCR_REG(reg_idx) = (TIMER_TCR_REG(reg_idx) & ~0x00000004) | (tim << 2);
}
__INLINE uint8_t timer_tcr__tms__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
uint32_t localVal = TIMER_TCR_REG(reg_idx);
return ((localVal & 0x00000002) >> 1);
}
__INLINE void timer_tcr__tms__setf(uint32_t reg_idx, uint8_t tms)
{
ASSERT_ERR(reg_idx <= 3);
ASSERT_ERR(((tms << 1) & ~0x00000002) == 0);
TIMER_TCR_REG(reg_idx) = (TIMER_TCR_REG(reg_idx) & ~0x00000002) | (tms << 1);
}
__INLINE uint8_t timer_tcr__tes__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
uint32_t localVal = TIMER_TCR_REG(reg_idx);
return ((localVal & 0x00000001) >> 0);
}
__INLINE void timer_tcr__tes__setf(uint32_t reg_idx, uint8_t tes)
{
ASSERT_ERR(reg_idx <= 3);
ASSERT_ERR(((tes << 0) & ~0x00000001) == 0);
TIMER_TCR_REG(reg_idx) = (TIMER_TCR_REG(reg_idx) & ~0x00000001) | (tes << 0);
}
/**
* @brief TIMER_TIC register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 INTR 0
* </pre>
*/
#define TIMER_TIC_REG(i) (*(volatile uint32_t *)(0x4000300C + timer_offset[i]))
#define TIMER_TIC_ADDR(i) (0x4000300C + timer_offset[i])
#define TIMER_TIC_OFFSET 0x0000000C
__INLINE uint32_t timer_tic_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
return TIMER_TIC_REG(reg_idx);
}
// field definitions
#define INTR_BIT 0x00000001
#define INTR_POS 0
#define INTR_RST 0x0
__INLINE uint8_t timer_tic__intr__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
uint32_t localVal = TIMER_TIC_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
/**
* @brief TIMER_TIS register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 STAT 0
* </pre>
*/
#define TIMER_TIS_REG(i) (*(volatile uint32_t *)(0x40003010 + timer_offset[i]))
#define TIMER_TIS_ADDR(i) (0x40003010 + timer_offset[i])
#define TIMER_TIS_OFFSET 0x00000010
__INLINE uint32_t timer_tis_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
return TIMER_TIS_REG(reg_idx);
}
// field definitions
#define STAT_BIT 0x00000001
#define STAT_POS 0
#define STAT_RST 0x0
__INLINE uint8_t timer_tis__stat__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
uint32_t localVal = TIMER_TIS_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
#endif // _XC_REG_TIMER_H_
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_uart.h
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#ifndef _XC_REG_UART_H_
#define _XC_REG_UART_H_
#include <stdint.h>
#include "xc_reg_offset.h"
#define XC_REG_UART_BASE_ADDR 0x40010000
#define XC_REG_UART_DECODING_MASK 0x000000FF
/**
* @brief UART_RBR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 07:00 RBR 0x0
* </pre>
*/
#define UART_RBR_REG(i) (* ((volatile uint32_t *)(0x40010000 + uart_offset[i])) )
#define UART_RBR_ADDR(i) (0x40010000 + uart_offset[i])
#define UART_RBR_OFFSET 0x00000000
__INLINE uint32_t uart_rbr_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
return UART_RBR_REG(reg_idx);
}
// field definitions
#define RBR_MASK 0x000000FF
#define RBR_LSB 0
#define RBR_WIDTH 0x00000008
#define RBR_RST 0x0
__INLINE uint8_t uart_rbr__rbr__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_RBR_REG(reg_idx);
ASSERT_ERR((localVal & ~0x000000FF) == 0);
return (localVal >> 0);
}
/**
* @brief UART_THR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 07:00 THR 0x0
* </pre>
*/
#define UART_THR_REG(i) (* ((volatile uint32_t *)(0x40010000 + uart_offset[i])) )
#define UART_THR_ADDR(i) (0x40010000 + uart_offset[i])
#define UART_THR_OFFSET 0x00000000
__INLINE void uart_thr_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 2);
UART_THR_REG(reg_idx) = value;
}
// field definitions
#define THR_MASK 0x000000FF
#define THR_LSB 0
#define THR_WIDTH 0x00000008
#define THR_RST 0x0
__INLINE void uart_thr__thr__setf(uint32_t reg_idx, uint8_t thr)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((thr << 0) & ~0x000000FF) == 0);
UART_THR_REG(reg_idx) = thr << 0;
}
/**
* @brief UART_DLL register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 07:00 DLL 0x0
* </pre>
*/
#define UART_DLL_REG(i) (* ((volatile uint32_t *)(0x40010000 + uart_offset[i])) )
#define UART_DLL_ADDR(i) (0x40010000 + uart_offset[i])
#define UART_DLL_OFFSET 0x00000000
__INLINE uint32_t uart_dll_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
return UART_DLL_REG(reg_idx);
}
__INLINE void uart_dll_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 2);
UART_DLL_REG(reg_idx) = value;
}
// field definitions
#define DLL_MASK 0x000000FF
#define DLL_LSB 0
#define DLL_WIDTH 0x00000008
#define DLL_RST 0x0
__INLINE uint8_t uart_dll__dll__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_DLL_REG(reg_idx);
ASSERT_ERR((localVal & ~0x000000FF) == 0);
return (localVal >> 0);
}
__INLINE void uart_dll__dll__setf(uint32_t reg_idx, uint8_t dll)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((dll << 0) & ~0x000000FF) == 0);
UART_DLL_REG(reg_idx) = dll << 0;
}
/**
* @brief UART_IER register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 07 PTIME 0
* 03 EMSI 0
* 02 ETSI 0
* 01 ETHEI 0
* 00 ERDAI 0
* </pre>
*/
#define UART_IER_REG(i) (* ((volatile uint32_t *)(0x40010004 + uart_offset[i])) )
#define UART_IER_ADDR(i) (0x40010004 + uart_offset[i])
#define UART_IER_OFFSET 0x00000004
__INLINE uint32_t uart_ier_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
return UART_IER_REG(reg_idx);
}
__INLINE void uart_ier_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 2);
UART_IER_REG(reg_idx) = value;
}
// field definitions
#define PTIME_BIT 0x00000080
#define PTIME_POS 7
#define EMSI_BIT 0x00000008
#define EMSI_POS 3
#define ETSI_BIT 0x00000004
#define ETSI_POS 2
#define ETHEI_BIT 0x00000002
#define ETHEI_POS 1
#define ERDAI_BIT 0x00000001
#define ERDAI_POS 0
#define PTIME_RST 0x0
#define EMSI_RST 0x0
#define ETSI_RST 0x0
#define ETHEI_RST 0x0
#define ERDAI_RST 0x0
__INLINE void uart_ier_pack(uint32_t reg_idx, uint8_t ptime, uint8_t emsi, uint8_t etsi, uint8_t ethei, uint8_t erdai)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((ptime << 7) & ~0x00000080) == 0);
ASSERT_ERR(((emsi << 3) & ~0x00000008) == 0);
ASSERT_ERR(((etsi << 2) & ~0x00000004) == 0);
ASSERT_ERR(((ethei << 1) & ~0x00000002) == 0);
ASSERT_ERR(((erdai << 0) & ~0x00000001) == 0);
UART_IER_REG(reg_idx) = (ptime << 7) | (emsi << 3) | (etsi << 2) | (ethei << 1) | (erdai << 0);
}
__INLINE void uart_ier_unpack(uint32_t reg_idx, uint8_t* ptime, uint8_t* emsi, uint8_t* etsi, uint8_t* ethei, uint8_t* erdai)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_IER_REG(reg_idx);
*ptime = (localVal & 0x00000080) >> 7;
*emsi = (localVal & 0x00000008) >> 3;
*etsi = (localVal & 0x00000004) >> 2;
*ethei = (localVal & 0x00000002) >> 1;
*erdai = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t uart_ier__ptime__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_IER_REG(reg_idx);
return ((localVal & 0x00000080) >> 7);
}
__INLINE void uart_ier__ptime__setf(uint32_t reg_idx, uint8_t ptime)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((ptime << 7) & ~0x00000080) == 0);
UART_IER_REG(reg_idx) = (UART_IER_REG(reg_idx) & ~0x00000080) | (ptime << 7);
}
__INLINE uint8_t uart_ier__emsi__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_IER_REG(reg_idx);
return ((localVal & 0x00000008) >> 3);
}
__INLINE void uart_ier__emsi__setf(uint32_t reg_idx, uint8_t emsi)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((emsi << 3) & ~0x00000008) == 0);
UART_IER_REG(reg_idx) = (UART_IER_REG(reg_idx) & ~0x00000008) | (emsi << 3);
}
__INLINE uint8_t uart_ier__etsi__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_IER_REG(reg_idx);
return ((localVal & 0x00000004) >> 2);
}
__INLINE void uart_ier__etsi__setf(uint32_t reg_idx, uint8_t etsi)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((etsi << 2) & ~0x00000004) == 0);
UART_IER_REG(reg_idx) = (UART_IER_REG(reg_idx) & ~0x00000004) | (etsi << 2);
}
__INLINE uint8_t uart_ier__ethei__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_IER_REG(reg_idx);
return ((localVal & 0x00000002) >> 1);
}
__INLINE void uart_ier__ethei__setf(uint32_t reg_idx, uint8_t ethei)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((ethei << 1) & ~0x00000002) == 0);
UART_IER_REG(reg_idx) = (UART_IER_REG(reg_idx) & ~0x00000002) | (ethei << 1);
}
__INLINE uint8_t uart_ier__erdai__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_IER_REG(reg_idx);
return ((localVal & 0x00000001) >> 0);
}
__INLINE void uart_ier__erdai__setf(uint32_t reg_idx, uint8_t erdai)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((erdai << 0) & ~0x00000001) == 0);
UART_IER_REG(reg_idx) = (UART_IER_REG(reg_idx) & ~0x00000001) | (erdai << 0);
}
/**
* @brief UART_DLH register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 07:00 DLH 0x0
* </pre>
*/
#define UART_DLH_REG(i) (* ((volatile uint32_t *)(0x40010004 + uart_offset[i])) )
#define UART_DLH_ADDR(i) (0x40010004 + uart_offset[i])
#define UART_DLH_OFFSET 0x00000004
__INLINE uint32_t uart_dlh_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
return UART_DLH_REG(reg_idx);
}
__INLINE void uart_dlh_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 2);
UART_DLH_REG(reg_idx) = value;
}
// field definitions
#define DLH_MASK 0x000000FF
#define DLH_LSB 0
#define DLH_WIDTH 0x00000008
#define DLH_RST 0x0
__INLINE uint8_t uart_dlh__dlh__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_DLH_REG(reg_idx);
ASSERT_ERR((localVal & ~0x000000FF) == 0);
return (localVal >> 0);
}
__INLINE void uart_dlh__dlh__setf(uint32_t reg_idx, uint8_t dlh)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((dlh << 0) & ~0x000000FF) == 0);
UART_DLH_REG(reg_idx) = dlh << 0;
}
/**
* @brief UART_IIR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 07:06 FS 0x0
* 03:00 IID 0x0
* </pre>
*/
#define UART_IIR_REG(i) (* ((volatile uint32_t *)(0x40010008 + uart_offset[i])) )
#define UART_IIR_ADDR(i) (0x40010008 + uart_offset[i])
#define UART_IIR_OFFSET 0x00000008
__INLINE uint32_t uart_iir_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
return UART_IIR_REG(reg_idx);
}
// field definitions
#define FS_MASK 0x000000C0
#define FS_LSB 6
#define FS_WIDTH 0x00000002
#define IID_MASK 0x0000000F
#define IID_LSB 0
#define IID_WIDTH 0x00000004
#define FS_RST 0x0
#define IID_RST 0x0
__INLINE void uart_iir_unpack(uint32_t reg_idx, uint8_t* fs, uint8_t* iid)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_IIR_REG(reg_idx);
*fs = (localVal & 0x000000C0) >> 6;
*iid = (localVal & 0x0000000F) >> 0;
}
__INLINE uint8_t uart_iir__fs__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_IIR_REG(reg_idx);
return ((localVal & 0x000000C0) >> 6);
}
__INLINE uint8_t uart_iir__iid__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_IIR_REG(reg_idx);
return ((localVal & 0x0000000F) >> 0);
}
/**
* @brief UART_FCR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 07:06 RCVR_Trigger 0x0
* 05:04 TX_Empty_Trigger 0x0
* 02 XMIT_FIFO_Reset 0
* 01 RCVR_FIFO_Reset 0
* 00 FIFO_ENABLE 0
* </pre>
*/
#define UART_FCR_REG(i) (* ((volatile uint32_t *)(0x40010008 + uart_offset[i])) )
#define UART_FCR_ADDR(i) (0x40010008 + uart_offset[i])
#define UART_FCR_OFFSET 0x00000008
__INLINE void uart_fcr_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 2);
UART_FCR_REG(reg_idx) = value;
}
// field definitions
#define RCVR__TRIGGER_MASK 0x000000C0
#define RCVR__TRIGGER_LSB 6
#define RCVR__TRIGGER_WIDTH 0x00000002
#define TX__EMPTY__TRIGGER_MASK 0x00000030
#define TX__EMPTY__TRIGGER_LSB 4
#define TX__EMPTY__TRIGGER_WIDTH 0x00000002
#define XMIT_FIFO__RESET_BIT 0x00000004
#define XMIT_FIFO__RESET_POS 2
#define RCVR_FIFO__RESET_BIT 0x00000002
#define RCVR_FIFO__RESET_POS 1
#define FIFO_ENABLE_BIT 0x00000001
#define FIFO_ENABLE_POS 0
#define RCVR__TRIGGER_RST 0x0
#define TX__EMPTY__TRIGGER_RST 0x0
#define XMIT_FIFO__RESET_RST 0x0
#define RCVR_FIFO__RESET_RST 0x0
#define FIFO_ENABLE_RST 0x0
__INLINE void uart_fcr_pack(uint32_t reg_idx, uint8_t rcvr_trigger, uint8_t tx_empty_trigger, uint8_t xmit_fifo_reset, uint8_t rcvr_fifo_reset, uint8_t fifo_enable)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((rcvr_trigger << 6) & ~0x000000C0) == 0);
ASSERT_ERR(((tx_empty_trigger << 4) & ~0x00000030) == 0);
ASSERT_ERR(((xmit_fifo_reset << 2) & ~0x00000004) == 0);
ASSERT_ERR(((rcvr_fifo_reset << 1) & ~0x00000002) == 0);
ASSERT_ERR(((fifo_enable << 0) & ~0x00000001) == 0);
UART_FCR_REG(reg_idx) = (rcvr_trigger << 6) | (tx_empty_trigger << 4) | (xmit_fifo_reset << 2) | (rcvr_fifo_reset << 1) | (fifo_enable << 0);
}
__INLINE void uart_fcr__rcvr__trigger__setf(uint32_t reg_idx, uint8_t rcvr_trigger)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((rcvr_trigger << 6) & ~0x000000C0) == 0);
UART_FCR_REG(reg_idx) = (UART_FCR_REG(reg_idx) & ~0x000000C0) | (rcvr_trigger << 6);
}
__INLINE void uart_fcr__tx__empty__trigger__setf(uint32_t reg_idx, uint8_t tx_empty_trigger)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((tx_empty_trigger << 4) & ~0x00000030) == 0);
UART_FCR_REG(reg_idx) = (UART_FCR_REG(reg_idx) & ~0x00000030) | (tx_empty_trigger << 4);
}
__INLINE void uart_fcr__xmit_fifo__reset__setf(uint32_t reg_idx, uint8_t xmit_fifo_reset)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((xmit_fifo_reset << 2) & ~0x00000004) == 0);
UART_FCR_REG(reg_idx) = (UART_FCR_REG(reg_idx) & ~0x00000004) | (xmit_fifo_reset << 2);
}
__INLINE void uart_fcr__rcvr_fifo__reset__setf(uint32_t reg_idx, uint8_t rcvr_fifo_reset)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((rcvr_fifo_reset << 1) & ~0x00000002) == 0);
UART_FCR_REG(reg_idx) = (UART_FCR_REG(reg_idx) & ~0x00000002) | (rcvr_fifo_reset << 1);
}
__INLINE void uart_fcr__fifo_enable__setf(uint32_t reg_idx, uint8_t fifo_enable)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((fifo_enable << 0) & ~0x00000001) == 0);
UART_FCR_REG(reg_idx) = (UART_FCR_REG(reg_idx) & ~0x00000001) | (fifo_enable << 0);
}
/**
* @brief UART_TCR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 07 DLAB 0
* 06 Brk 0
* 04 EPS 0
* 03 PEN 0
* 02 STOP 0
* 01:00 CLS 0x0
* </pre>
*/
#define UART_TCR_REG(i) (* ((volatile uint32_t *)(0x4001000C + uart_offset[i])) )
#define UART_TCR_ADDR(i) (0x4001000C + uart_offset[i])
#define UART_TCR_OFFSET 0x0000000C
__INLINE uint32_t uart_tcr_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
return UART_TCR_REG(reg_idx);
}
__INLINE void uart_tcr_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 2);
UART_TCR_REG(reg_idx) = value;
}
// field definitions
#define DLAB_BIT 0x00000080
#define DLAB_POS 7
#define BRK_BIT 0x00000040
#define BRK_POS 6
#define EPS_BIT 0x00000010
#define EPS_POS 4
#define PEN_BIT 0x00000008
#define PEN_POS 3
#define STOP_BIT 0x00000004
#define STOP_POS 2
#define CLS_MASK 0x00000003
#define CLS_LSB 0
#define CLS_WIDTH 0x00000002
#define DLAB_RST 0x0
#define BRK_RST 0x0
#define EPS_RST 0x0
#define PEN_RST 0x0
#define STOP_RST 0x0
#define CLS_RST 0x0
__INLINE void uart_tcr_pack(uint32_t reg_idx, uint8_t dlab, uint8_t brk, uint8_t eps, uint8_t pen, uint8_t stop, uint8_t cls)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((dlab << 7) & ~0x00000080) == 0);
ASSERT_ERR(((brk << 6) & ~0x00000040) == 0);
ASSERT_ERR(((eps << 4) & ~0x00000010) == 0);
ASSERT_ERR(((pen << 3) & ~0x00000008) == 0);
ASSERT_ERR(((stop << 2) & ~0x00000004) == 0);
ASSERT_ERR(((cls << 0) & ~0x00000003) == 0);
UART_TCR_REG(reg_idx) = (dlab << 7) | (brk << 6) | (eps << 4) | (pen << 3) | (stop << 2) | (cls << 0);
}
__INLINE void uart_tcr_unpack(uint32_t reg_idx, uint8_t* dlab, uint8_t* brk, uint8_t* eps, uint8_t* pen, uint8_t* stop, uint8_t* cls)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_TCR_REG(reg_idx);
*dlab = (localVal & 0x00000080) >> 7;
*brk = (localVal & 0x00000040) >> 6;
*eps = (localVal & 0x00000010) >> 4;
*pen = (localVal & 0x00000008) >> 3;
*stop = (localVal & 0x00000004) >> 2;
*cls = (localVal & 0x00000003) >> 0;
}
__INLINE uint8_t uart_tcr__dlab__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_TCR_REG(reg_idx);
return ((localVal & 0x00000080) >> 7);
}
__INLINE void uart_tcr__dlab__setf(uint32_t reg_idx, uint8_t dlab)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((dlab << 7) & ~0x00000080) == 0);
UART_TCR_REG(reg_idx) = (UART_TCR_REG(reg_idx) & ~0x00000080) | (dlab << 7);
}
__INLINE uint8_t uart_tcr__brk__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_TCR_REG(reg_idx);
return ((localVal & 0x00000040) >> 6);
}
__INLINE void uart_tcr__brk__setf(uint32_t reg_idx, uint8_t brk)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((brk << 6) & ~0x00000040) == 0);
UART_TCR_REG(reg_idx) = (UART_TCR_REG(reg_idx) & ~0x00000040) | (brk << 6);
}
__INLINE uint8_t uart_tcr__eps__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_TCR_REG(reg_idx);
return ((localVal & 0x00000010) >> 4);
}
__INLINE void uart_tcr__eps__setf(uint32_t reg_idx, uint8_t eps)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((eps << 4) & ~0x00000010) == 0);
UART_TCR_REG(reg_idx) = (UART_TCR_REG(reg_idx) & ~0x00000010) | (eps << 4);
}
__INLINE uint8_t uart_tcr__pen__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_TCR_REG(reg_idx);
return ((localVal & 0x00000008) >> 3);
}
__INLINE void uart_tcr__pen__setf(uint32_t reg_idx, uint8_t pen)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((pen << 3) & ~0x00000008) == 0);
UART_TCR_REG(reg_idx) = (UART_TCR_REG(reg_idx) & ~0x00000008) | (pen << 3);
}
__INLINE uint8_t uart_tcr__stop__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_TCR_REG(reg_idx);
return ((localVal & 0x00000004) >> 2);
}
__INLINE void uart_tcr__stop__setf(uint32_t reg_idx, uint8_t stop)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((stop << 2) & ~0x00000004) == 0);
UART_TCR_REG(reg_idx) = (UART_TCR_REG(reg_idx) & ~0x00000004) | (stop << 2);
}
__INLINE uint8_t uart_tcr__cls__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_TCR_REG(reg_idx);
return ((localVal & 0x00000003) >> 0);
}
__INLINE void uart_tcr__cls__setf(uint32_t reg_idx, uint8_t cls)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((cls << 0) & ~0x00000003) == 0);
UART_TCR_REG(reg_idx) = (UART_TCR_REG(reg_idx) & ~0x00000003) | (cls << 0);
}
/**
* @brief UART_MCR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 05 AFCE 0
* 00 RTS 0
* </pre>
*/
#define UART_MCR_REG(i) (* ((volatile uint32_t *)(0x40010010 + uart_offset[i])) )
#define UART_MCR_ADDR(i) (0x40010010 + uart_offset[i])
#define UART_MCR_OFFSET 0x00000010
__INLINE uint32_t uart_mcr_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
return UART_MCR_REG(reg_idx);
}
__INLINE void uart_mcr_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 2);
UART_MCR_REG(reg_idx) = value;
}
// field definitions
#define AFCE_BIT 0x00000020
#define AFCE_POS 5
#define RTS_BIT 0x00000001
#define RTS_POS 0
#define AFCE_RST 0x0
#define RTS_RST 0x0
__INLINE void uart_mcr_pack(uint32_t reg_idx, uint8_t afce, uint8_t rts)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((afce << 5) & ~0x00000020) == 0);
ASSERT_ERR(((rts << 0) & ~0x00000001) == 0);
UART_MCR_REG(reg_idx) = (afce << 5) | (rts << 0);
}
__INLINE void uart_mcr_unpack(uint32_t reg_idx, uint8_t* afce, uint8_t* rts)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_MCR_REG(reg_idx);
*afce = (localVal & 0x00000020) >> 5;
*rts = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t uart_mcr__afce__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_MCR_REG(reg_idx);
return ((localVal & 0x00000020) >> 5);
}
__INLINE void uart_mcr__afce__setf(uint32_t reg_idx, uint8_t afce)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((afce << 5) & ~0x00000020) == 0);
UART_MCR_REG(reg_idx) = (UART_MCR_REG(reg_idx) & ~0x00000020) | (afce << 5);
}
__INLINE uint8_t uart_mcr__rts__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_MCR_REG(reg_idx);
return ((localVal & 0x00000001) >> 0);
}
__INLINE void uart_mcr__rts__setf(uint32_t reg_idx, uint8_t rts)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((rts << 0) & ~0x00000001) == 0);
UART_MCR_REG(reg_idx) = (UART_MCR_REG(reg_idx) & ~0x00000001) | (rts << 0);
}
/**
* @brief UART_TSR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 07 RX_FIFO_ERROR 0
* 05 THRE 0
* 04 BI 0
* 03 FE 0
* 02 PE 0
* 01 OE 0
* 00 DR 0
* </pre>
*/
#define UART_TSR_REG(i) (* ((volatile uint32_t *)(0x40010014 + uart_offset[i])) )
#define UART_TSR_ADDR(i) (0x40010014 + uart_offset[i])
#define UART_TSR_OFFSET 0x00000014
__INLINE uint32_t uart_tsr_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
return UART_TSR_REG(reg_idx);
}
// field definitions
#define RX_FIFO_ERROR_BIT 0x00000080
#define RX_FIFO_ERROR_POS 7
#define THRE_BIT 0x00000020
#define THRE_POS 5
#define BI_BIT 0x00000010
#define BI_POS 4
#define FE_BIT 0x00000008
#define FE_POS 3
#define PE_BIT 0x00000004
#define PE_POS 2
#define OE_BIT 0x00000002
#define OE_POS 1
#define DR_BIT 0x00000001
#define DR_POS 0
#define RX_FIFO_ERROR_RST 0x0
#define THRE_RST 0x0
#define BI_RST 0x0
#define FE_RST 0x0
#define PE_RST 0x0
#define OE_RST 0x0
#define DR_RST 0x0
__INLINE void uart_tsr_unpack(uint32_t reg_idx, uint8_t* rx_fifo_error, uint8_t* thre, uint8_t* bi, uint8_t* fe, uint8_t* pe, uint8_t* oe, uint8_t* dr)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_TSR_REG(reg_idx);
*rx_fifo_error = (localVal & 0x00000080) >> 7;
*thre = (localVal & 0x00000020) >> 5;
*bi = (localVal & 0x00000010) >> 4;
*fe = (localVal & 0x00000008) >> 3;
*pe = (localVal & 0x00000004) >> 2;
*oe = (localVal & 0x00000002) >> 1;
*dr = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t uart_tsr__rx_fifo_error__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_TSR_REG(reg_idx);
return ((localVal & 0x00000080) >> 7);
}
__INLINE uint8_t uart_tsr__thre__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_TSR_REG(reg_idx);
return ((localVal & 0x00000020) >> 5);
}
__INLINE uint8_t uart_tsr__bi__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_TSR_REG(reg_idx);
return ((localVal & 0x00000010) >> 4);
}
__INLINE uint8_t uart_tsr__fe__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_TSR_REG(reg_idx);
return ((localVal & 0x00000008) >> 3);
}
__INLINE uint8_t uart_tsr__pe__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_TSR_REG(reg_idx);
return ((localVal & 0x00000004) >> 2);
}
__INLINE uint8_t uart_tsr__oe__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_TSR_REG(reg_idx);
return ((localVal & 0x00000002) >> 1);
}
__INLINE uint8_t uart_tsr__dr__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_TSR_REG(reg_idx);
return ((localVal & 0x00000001) >> 0);
}
/**
* @brief UART_MSR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 04 CTS 0
* 00 DCTS 0
* </pre>
*/
#define UART_MSR_REG(i) (* ((volatile uint32_t *)(0x40010018 + uart_offset[i])) )
#define UART_MSR_ADDR(i) (0x40010018 + uart_offset[i])
#define UART_MSR_OFFSET 0x00000018
__INLINE uint32_t uart_msr_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
return UART_MSR_REG(reg_idx);
}
// field definitions
#define CTS_BIT 0x00000010
#define CTS_POS 4
#define DCTS_BIT 0x00000001
#define DCTS_POS 0
#define CTS_RST 0x0
#define DCTS_RST 0x0
__INLINE void uart_msr_unpack(uint32_t reg_idx, uint8_t* cts, uint8_t* dcts)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_MSR_REG(reg_idx);
*cts = (localVal & 0x00000010) >> 4;
*dcts = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t uart_msr__cts__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_MSR_REG(reg_idx);
return ((localVal & 0x00000010) >> 4);
}
__INLINE uint8_t uart_msr__dcts__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_MSR_REG(reg_idx);
return ((localVal & 0x00000001) >> 0);
}
/**
* @brief UART_USR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 BUSY 0
* </pre>
*/
#define UART_USR_REG(i) (* ((volatile uint32_t *)(0x4001007C + uart_offset[i])) )
#define UART_USR_ADDR(i) (0x4001007C + uart_offset[i])
#define UART_USR_OFFSET 0x0000007C
__INLINE uint32_t uart_usr_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
return UART_USR_REG(reg_idx);
}
// field definitions
#define BUSY_BIT 0x00000001
#define BUSY_POS 0
#define BUSY_RST 0x0
__INLINE uint8_t uart_usr__busy__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_USR_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
#endif // _XC_REG_UART_H_
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_wdt.h
+270
View File
@@ -0,0 +1,270 @@
#ifndef _XC_REG_WDT_H_
#define _XC_REG_WDT_H_
#include <stdint.h>
#define XC_REG_WDT_BASE_ADDR 0x40004000
#define XC_REG_WDT_DECODING_MASK 0x0000001F
/**
* @brief WDT_CR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 04:02 WDT_RPL 0x0
* 01 WDT_RMOD 0
* 00 WDT_EN 0
* </pre>
*/
#define WDT_CR_REG (*(volatile uint32_t *)(0x40004000))
#define WDT_CR_ADDR 0x40004000
#define WDT_CR_OFFSET 0x00000000
__INLINE uint32_t wdt_cr_get(void)
{
return WDT_CR_REG;
}
__INLINE void wdt_cr_set(uint32_t value)
{
WDT_CR_REG = value;
}
// field definitions
#define WDT_RPL_MASK 0x0000001C
#define WDT_RPL_LSB 2
#define WDT_RPL_WIDTH 0x00000003
#define WDT_RMOD_BIT 0x00000002
#define WDT_RMOD_POS 1
#define WDT_EN_BIT 0x00000001
#define WDT_EN_POS 0
#define WDT_RPL_RST 0x0
#define WDT_RMOD_RST 0x0
#define WDT_EN_RST 0x0
__INLINE void wdt_cr_pack(uint8_t wdt_rpl, uint8_t wdt_rmod, uint8_t wdt_en)
{
ASSERT_ERR(((wdt_rpl << 2) & ~0x0000001C) == 0);
ASSERT_ERR(((wdt_rmod << 1) & ~0x00000002) == 0);
ASSERT_ERR(((wdt_en << 0) & ~0x00000001) == 0);
WDT_CR_REG = (wdt_rpl << 2) | (wdt_rmod << 1) | (wdt_en << 0);
}
__INLINE void wdt_cr_unpack(uint8_t* wdt_rpl, uint8_t* wdt_rmod, uint8_t* wdt_en)
{
uint32_t localVal = WDT_CR_REG;
*wdt_rpl = (localVal & 0x0000001C) >> 2;
*wdt_rmod = (localVal & 0x00000002) >> 1;
*wdt_en = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t wdt_cr__wdt_rpl__getf(void)
{
uint32_t localVal = WDT_CR_REG;
return ((localVal & 0x0000001C) >> 2);
}
__INLINE void wdt_cr__wdt_rpl__setf(uint8_t wdt_rpl)
{
ASSERT_ERR(((wdt_rpl << 2) & ~0x0000001C) == 0);
WDT_CR_REG = (WDT_CR_REG & ~0x0000001C) | (wdt_rpl << 2);
}
__INLINE uint8_t wdt_cr__wdt_rmod__getf(void)
{
uint32_t localVal = WDT_CR_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE void wdt_cr__wdt_rmod__setf(uint8_t wdt_rmod)
{
ASSERT_ERR(((wdt_rmod << 1) & ~0x00000002) == 0);
WDT_CR_REG = (WDT_CR_REG & ~0x00000002) | (wdt_rmod << 1);
}
__INLINE uint8_t wdt_cr__wdt_en__getf(void)
{
uint32_t localVal = WDT_CR_REG;
return ((localVal & 0x00000001) >> 0);
}
__INLINE void wdt_cr__wdt_en__setf(uint8_t wdt_en)
{
ASSERT_ERR(((wdt_en << 0) & ~0x00000001) == 0);
WDT_CR_REG = (WDT_CR_REG & ~0x00000001) | (wdt_en << 0);
}
/**
* @brief WDT_TORR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 03:00 WDT_TOP 0x0
* </pre>
*/
#define WDT_TORR_REG (*(volatile uint32_t *)(0x40004004))
#define WDT_TORR_ADDR 0x40004004
#define WDT_TORR_OFFSET 0x00000004
__INLINE uint32_t wdt_torr_get(void)
{
return WDT_TORR_REG;
}
__INLINE void wdt_torr_set(uint32_t value)
{
WDT_TORR_REG = value;
}
// field definitions
#define WDT_TOP_MASK 0x0000000F
#define WDT_TOP_LSB 0
#define WDT_TOP_WIDTH 0x00000004
#define WDT_TOP_RST 0x0
__INLINE uint8_t wdt_torr__wdt_top__getf(void)
{
uint32_t localVal = WDT_TORR_REG;
ASSERT_ERR((localVal & ~0x0000000F) == 0);
return (localVal >> 0);
}
__INLINE void wdt_torr__wdt_top__setf(uint8_t wdt_top)
{
ASSERT_ERR(((wdt_top << 0) & ~0x0000000F) == 0);
WDT_TORR_REG = wdt_top << 0;
}
/**
* @brief WDT_CCVR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 WDT_CCVR 0x0
* </pre>
*/
#define WDT_CCVR_REG (*(volatile uint32_t *)(0x40004008))
#define WDT_CCVR_ADDR 0x40004008
#define WDT_CCVR_OFFSET 0x00000008
__INLINE uint32_t wdt_ccvr_get(void)
{
return WDT_CCVR_REG;
}
__INLINE void wdt_ccvr_set(uint32_t value)
{
WDT_CCVR_REG = value;
}
// field definitions
#define WDT_CCVR_MASK 0xFFFFFFFF
#define WDT_CCVR_LSB 0
#define WDT_CCVR_WIDTH 0x00000020
#define WDT_CCVR_RST 0x0
__INLINE uint32_t wdt_ccvr__getf(void)
{
uint32_t localVal = WDT_CCVR_REG;
ASSERT_ERR((localVal & ~0xFFFFFFFF) == 0);
return (localVal >> 0);
}
/**
* @brief WDT_CRR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 07:00 WDT_CRR 0x0
* </pre>
*/
#define WDT_CRR_REG (*(volatile uint32_t *)(0x4000400C))
#define WDT_CRR_ADDR 0x4000400C
#define WDT_CRR_OFFSET 0x0000000C
__INLINE void wdt_crr_set(uint32_t value)
{
WDT_CRR_REG = value;
}
// field definitions
#define WDT_CRR_MASK 0x000000FF
#define WDT_CRR_LSB 0
#define WDT_CRR_WIDTH 0x00000008
#define WDT_CRR_RST 0x0
__INLINE void wdt_crr__setf(uint8_t wdt_crr)
{
ASSERT_ERR(((wdt_crr << 0) & ~0x000000FF) == 0);
WDT_CRR_REG = wdt_crr << 0;
}
/**
* @brief WDT_STAT register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 WDT_STAT 0
* </pre>
*/
#define WDT_STAT_REG (*(volatile uint32_t *)(0x40004010))
#define WDT_STAT_ADDR 0x40004010
#define WDT_STAT_OFFSET 0x00000010
__INLINE uint32_t wdt_stat_get(void)
{
return WDT_STAT_REG;
}
// field definitions
#define WDT_STAT_BIT 0x00000001
#define WDT_STAT_POS 0
#define WDT_STAT_RST 0x0
__INLINE uint8_t wdt_stat__getf(void)
{
uint32_t localVal = WDT_STAT_REG;
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
/**
* @brief WDT_ICR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 WDT_ICR 0
* </pre>
*/
#define WDT_ICR_REG (*(volatile uint32_t *)(0x40004014))
#define WDT_ICR_ADDR 0x40004014
#define WDT_ICR_OFFSET 0x00000014
__INLINE uint32_t wdt_icr_get(void)
{
return WDT_ICR_REG;
}
// field definitions
#define WDT_ICR_BIT 0x00000001
#define WDT_ICR_POS 0
#define WDT_ICR_RST 0x0
__INLINE uint8_t wdt_icr__getf(void)
{
uint32_t localVal = WDT_ICR_REG;
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
#endif // _XC_REG_WDT_H_
component/xc6xx_drivers/Drivers/CMSIS/core_cm0.c
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/**************************************************************************//**
* @file core_cm0.c
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Source File
* @version V2.00
* @date 10. September 2010
*
* @note
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
/* define compiler specific symbols */
#if defined(__CC_ARM)
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined(__ICCARM__)
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE \
inline /*!< inline keyword for IAR Compiler. Only avaiable in High \
optimization mode! */
#elif defined(__GNUC__)
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#elif defined(__TASKING__)
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#endif
/* ########################## Core Instruction Access
* ######################### */
#if defined(__CC_ARM) /*------------------ RealView Compiler \
----------------*/
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#if (__ARMCC_VERSION < 400677)
__ASM uint32_t __REV16(uint32_t value) { rev16 r0, r0 bx lr }
#endif /* __ARMCC_VERSION */
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign
extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#if (__ARMCC_VERSION < 400677)
__ASM int32_t __REVSH(int32_t value) { revsh r0, r0 bx lr }
#endif /* __ARMCC_VERSION */
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __CLREX(void) { clrex }
#endif /* __ARMCC_VERSION */
#elif (defined( \
__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
/* obsolete */
#elif (defined( \
__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* obsolete */
#elif (defined( \
__TASKING__)) /*--------------- TASKING Compiler -----------------*/
/* obsolete */
#endif
/* ########################### Core Function Access
* ########################### */
#if defined(__CC_ARM) /*------------------ RealView Compiler \
----------------*/
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_CONTROL(void) { mrs r0, control bx lr }
#endif /* __ARMCC_VERSION */
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_CONTROL(uint32_t control) { msr control, r0 bx lr }
#endif /* __ARMCC_VERSION */
/** \brief Get ISPR Register
This function returns the content of the ISPR Register.
\return ISPR Register value
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_IPSR(void) { mrs r0, ipsr bx lr }
#endif /* __ARMCC_VERSION */
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_APSR(void) { mrs r0, apsr bx lr }
#endif /* __ARMCC_VERSION */
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_xPSR(void) { mrs r0, xpsr bx lr }
#endif /* __ARMCC_VERSION */
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_PSP(void) { mrs r0, psp bx lr }
#endif /* __ARMCC_VERSION */
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_PSP(uint32_t topOfProcStack) { msr psp, r0 bx lr }
#endif /* __ARMCC_VERSION */
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_MSP(void) { mrs r0, msp bx lr }
#endif /* __ARMCC_VERSION */
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_MSP(uint32_t mainStackPointer) { msr msp, r0 bx lr }
#endif /* __ARMCC_VERSION */
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the
Priority Mask Register.
\return Priority Mask value
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_PRIMASK(void) { mrs r0, primask bx lr }
#endif /* __ARMCC_VERSION */
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_PRIMASK(uint32_t priMask) { msr primask, r0 bx lr }
#endif /* __ARMCC_VERSION */
#elif (defined( \
__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
/* obsolete */
#elif (defined( \
__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* obsolete */
#elif (defined( \
__TASKING__)) /*--------------- TASKING Compiler -----------------*/
/* obsolete */
#endif
component/xc6xx_drivers/Drivers/CMSIS/core_cm0.h
+703
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/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V2.01
* @date 06. December 2010
*
* @note
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
/** \mainpage CMSIS Cortex-M0
This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
It consists of:
- Cortex-M Core Register Definitions
- Cortex-M functions
- Cortex-M instructions
The CMSIS Cortex-M0 Core Peripheral Access Layer contains C and assembly functions that ease
access to the Cortex-M Core
*/
/** \defgroup CMSIS_LintCinfiguration CMSIS Lint Configuration
List of Lint messages which will be suppressed and not shown:
- not yet checked
.
Note: To re-enable a Message, insert a space before 'lint' *
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
This file defines all structures and symbols for CMSIS core:
- CMSIS version number
- Cortex-M core
- Cortex-M core Revision Number
@{
*/
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00) /*!< Cortex core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __forceinline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#endif
#include <stdint.h> /*!< standard types definitions */
#include "core_cmInstr.h" /*!< Core Instruction Access */
#include "core_cmFunc.h" /*!< Core Function Access */
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
/* IO definitions (access restrictions to peripheral registers) */
#ifdef __cplusplus
#define __I volatile /*!< defines 'read only' permissions */
#else
#define __I volatile const /*!< defines 'read only' permissions */
#endif
#define __O volatile /*!< defines 'write only' permissions */
#define __IO volatile /*!< defines 'read / write' permissions */
/*@} end of group CMSIS_core_definitions */
/*******************************************************************************
* Register Abstraction
******************************************************************************/
/** \defgroup CMSIS_core_register CMSIS Core Register
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core Debug Register
*/
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CORE CMSIS Core
Type definitions for the Cortex-M Core Registers
@{
*/
/** \brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
#else
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
#endif
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
#else
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/** \brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/*@} end of group CMSIS_CORE */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC CMSIS NVIC
Type definitions for the Cortex-M NVIC Registers
@{
*/
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31];
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31];
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31];
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31];
uint32_t RESERVED4[64];
__IO uint32_t IPR[8]; /*!< Offset: 0x3EC (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SCB CMSIS SCB
Type definitions for the Cortex-M System Control Block Registers
@{
*/
/** \brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPU ID Base Register */
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control State Register */
uint32_t RESERVED0;
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt / Reset Control Register */
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
uint32_t RESERVED2[2];
__IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/* SCB Debug Fault Status Register Definitions */
#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
/*@} end of group CMSIS_SCB */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick CMSIS SysTick
Type definitions for the Cortex-M System Timer Registers
@{
*/
/** \brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug CMSIS Core Debug
Type definitions for the Cortex-M Core Debug Registers
@{
*/
/** \brief Structure type to access the Core Debug Register (CoreDebug).
*/
typedef struct
{
__IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
__IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
} CoreDebug_Type;
/* Debug Halting Control and Status Register */
#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register */
#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register */
#define CoreDebug_DEMCR_DWTENA_Pos 24 /*!< CoreDebug DEMCR: DWTENA Position */
#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
/*@} end of group CMSIS_CoreDebug */
/** \ingroup CMSIS_core_register
@{
*/
/* Memory mapping of Cortex-M0 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
******************************************************************************/
/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
*/
/* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
/** \brief Enable External Interrupt
This function enables a device specific interupt in the NVIC interrupt controller.
The interrupt number cannot be a negative value.
\param [in] IRQn Number of the external interrupt to enable
*/
static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Disable External Interrupt
This function disables a device specific interupt in the NVIC interrupt controller.
The interrupt number cannot be a negative value.
\param [in] IRQn Number of the external interrupt to disable
*/
static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Get Pending Interrupt
This function reads the pending register in the NVIC and returns the pending bit
for the specified interrupt.
\param [in] IRQn Number of the interrupt for get pending
\return 0 Interrupt status is not pending
\return 1 Interrupt status is pending
*/
static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/** \brief Set Pending Interrupt
This function sets the pending bit for the specified interrupt.
The interrupt number cannot be a negative value.
\param [in] IRQn Number of the interrupt for set pending
*/
static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Clear Pending Interrupt
This function clears the pending bit for the specified interrupt.
The interrupt number cannot be a negative value.
\param [in] IRQn Number of the interrupt for clear pending
*/
static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
/** \brief Set Interrupt Priority
This function sets the priority for the specified interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
Note: The priority cannot be set for every core interrupt.
\param [in] IRQn Number of the interrupt for set priority
\param [in] priority Priority to set
*/
static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0) {
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
else {
NVIC->IPR[_IP_IDX(IRQn)] = (NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
}
/** \brief Get Interrupt Priority
This function reads the priority for the specified interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
The returned priority value is automatically aligned to the implemented
priority bits of the microcontroller.
\param [in] IRQn Number of the interrupt for get priority
\return Interrupt Priority
*/
static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
else {
return((uint32_t)((NVIC->IPR[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
}
/** \brief System Reset
This function initiate a system reset request to reset the MCU.
*/
static __INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
while(1); /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
@{
*/
#if (__Vendor_SysTickConfig == 0)
/** \brief System Tick Configuration
This function initialises the system tick timer and its interrupt and start the system tick timer.
Counter is in free running mode to generate periodical interrupts.
\param [in] ticks Number of ticks between two interrupts
\return 0 Function succeeded
\return 1 Function failed
*/
static __INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
#ifdef __cplusplus
}
#endif
/*lint -restore */
component/xc6xx_drivers/Drivers/CMSIS/core_cm4.h
+1812
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File diff suppressed because it is too large Load Diff
component/xc6xx_drivers/Drivers/CMSIS/core_cmFunc.h
+844
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@@ -0,0 +1,844 @@
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V2.01
* @date 06. December 2010
*
* @note
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMFUNC_H__
#define __CORE_CMFUNC_H__
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
/* ARM armcc specific functions */
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_CONTROL(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
#endif /* __ARMCC_VERSION */
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_CONTROL(uint32_t control);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
#endif /* __ARMCC_VERSION */
/** \brief Get ISPR Register
This function returns the content of the ISPR Register.
\return ISPR Register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_IPSR(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
#endif /* __ARMCC_VERSION */
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_APSR(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
#endif /* __ARMCC_VERSION */
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_xPSR(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
#endif /* __ARMCC_VERSION */
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_PSP(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
#endif /* __ARMCC_VERSION */
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_PSP(uint32_t topOfProcStack);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
#endif /* __ARMCC_VERSION */
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_MSP(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
#endif /* __ARMCC_VERSION */
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_MSP(uint32_t topOfMainStack);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
#endif /* __ARMCC_VERSION */
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_PRIMASK(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
#endif /* __ARMCC_VERSION */
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_PRIMASK(uint32_t priMask);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#endif /* __ARMCC_VERSION */
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_BASEPRI(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
#endif /* __ARMCC_VERSION */
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_BASEPRI(uint32_t basePri);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
#endif /* __ARMCC_VERSION */
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_FAULTMASK(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
#endif /* __ARMCC_VERSION */
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_FAULTMASK(uint32_t faultMask);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & 1);
}
#endif /* __ARMCC_VERSION */
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
static __INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
static __INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
/* IAR iccarm specific functions */
#if defined (__ICCARM__)
#include <intrinsics.h> /* IAR Intrinsics */
#endif
#pragma diag_suppress=Pe940
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_irq __enable_interrupt
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_irq __disable_interrupt
/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */
/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */
/** \brief Get ISPR Register
This function returns the content of the ISPR Register.
\return ISPR Register value
*/
static uint32_t __get_IPSR(void)
{
__ASM("mrs r0, ipsr");
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
static uint32_t __get_APSR(void)
{
__ASM("mrs r0, apsr");
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
static uint32_t __get_xPSR(void)
{
__ASM("mrs r0, psr"); // assembler does not know "xpsr"
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
static uint32_t __get_PSP(void)
{
__ASM("mrs r0, psp");
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
static void __set_PSP(uint32_t topOfProcStack)
{
__ASM("msr psp, r0");
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
static uint32_t __get_MSP(void)
{
__ASM("mrs r0, msp");
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
static void __set_MSP(uint32_t topOfMainStack)
{
__ASM("msr msp, r0");
}
/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */
/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
static __INLINE void __enable_fault_irq(void)
{
__ASM ("cpsie f");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
static __INLINE void __disable_fault_irq(void)
{
__ASM ("cpsid f");
}
/* intrinsic unsigned long __get_BASEPRI( void ); (see intrinsic.h) */
/* intrinsic void __set_BASEPRI( unsigned long ); (see intrinsic.h) */
/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */
/* intrinsic void __set_FAULTMASK(unsigned long); (see intrinsic.h) */
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
static uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1)
__ASM("vmrs r0, fpscr");
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
static void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1)
__ASM("vmsr fpscr, r0");
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#pragma diag_default=Pe940
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
/** \brief Get ISPR Register
This function returns the content of the ISPR Register.
\return ISPR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1)
uint32_t result;
__ASM volatile ("MRS %0, fpscr" : "=r" (result) );
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1)
__ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) );
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H__ */
component/xc6xx_drivers/Drivers/CMSIS/core_cmInstr.h
+776
View File
@@ -0,0 +1,776 @@
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V2.01
* @date 06. December 2010
*
* @note
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMINSTR_H__
#define __CORE_CMINSTR_H__
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
/* ARM armcc specific functions */
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#if (__ARMCC_VERSION < 400677)
extern uint32_t __REV16(uint32_t value);
#else /* (__ARMCC_VERSION >= 400677) */
static __INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#if (__ARMCC_VERSION < 400677)
extern int32_t __REVSH(int32_t value);
#else /* (__ARMCC_VERSION >= 400677) */
static __INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#if (__ARMCC_VERSION < 400000)
extern void __CLREX(void);
#else /* (__ARMCC_VERSION >= 400000) */
#define __CLREX __clrex
#endif /* __ARMCC_VERSION */
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
/* IAR iccarm specific functions */
#include <intrinsics.h> /* IAR Intrinsics */
#pragma diag_suppress=Pe940
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __no_operation
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
static __INLINE void __WFI(void)
{
__ASM ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
static __INLINE void __WFE(void)
{
__ASM ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
static __INLINE void __SEV(void)
{
__ASM ("sev");
}
/* intrinsic void __ISB(void) (see intrinsics.h) */
/* intrinsic void __DSB(void) (see intrinsics.h) */
/* intrinsic void __DMB(void) (see intrinsics.h) */
/* intrinsic uint32_t __REV(uint32_t value) (see intrinsics.h) */
/* intrinsic __SSAT (see intrinsics.h) */
/* intrinsic __USAT (see intrinsics.h) */
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
static uint32_t __REV16(uint32_t value)
{
__ASM("rev16 r0, r0");
}
/* intrinsic uint32_t __REVSH(uint32_t value) (see intrinsics.h */
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
static uint32_t __RBIT(uint32_t value)
{
__ASM("rbit r0, r0");
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
static uint8_t __LDREXB(volatile uint8_t *addr)
{
__ASM("ldrexb r0, [r0]");
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
static uint16_t __LDREXH(volatile uint16_t *addr)
{
__ASM("ldrexh r0, [r0]");
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
/* intrinsic unsigned long __LDREX(unsigned long *) (see intrinsics.h) */
static uint32_t __LDREXW(volatile uint32_t *addr)
{
__ASM("ldrex r0, [r0]");
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
__ASM("strexb r0, r0, [r1]");
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
__ASM("strexh r0, r0, [r1]");
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
/* intrinsic unsigned long __STREX(unsigned long, unsigned long) (see intrinsics.h )*/
static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
__ASM("strex r0, r0, [r1]");
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
static __INLINE void __CLREX(void)
{
__ASM ("clrex");
}
/* intrinsic unsigned char __CLZ( unsigned long ) (see intrinsics.h) */
#endif /* (__CORTEX_M >= 0x03) */
#pragma diag_default=Pe940
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
{
uint32_t result;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint8_t result;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint16_t result;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
{
__ASM volatile ("clrex");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
{
uint8_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H__ */
component/xc6xx_drivers/Drivers/CMSIS/core_cmSimd.h
+639
View File
@@ -0,0 +1,639 @@
/**************************************************************************//**
@file core_cmSimd.h
@brief CMSIS Cortex-M SIMD Header File
@version V4.00
@date 22. August 2014
@note
******************************************************************************/
/* Copyright (c) 2009 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifndef __CORE_CMSIMD_H
#define __CORE_CMSIMD_H
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
Hardware Abstraction Layer
******************************************************************************/
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32) ) >> 32))
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#define __SSAT16(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
#define __USAT16(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u
{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ // Little endian
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else // Big endian
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u
{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ // Little endian
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else // Big endian
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u
{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ // Little endian
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else // Big endian
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u
{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ // Little endian
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else // Big endian
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
#define __PKHBT(ARG1,ARG2,ARG3) \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
#define __PKHTB(ARG1,ARG2,ARG3) \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
if (ARG3 == 0) \
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
else \
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
{
int32_t result;
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/* not yet supported */
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
/* Cosmic specific functions */
#include <cmsis_csm.h>
#endif
/*@} end of group CMSIS_SIMD_intrinsics */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CMSIMD_H */
component/xc6xx_drivers/Drivers/CMSIS/xc_drv_config.h
+142
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@@ -0,0 +1,142 @@
#ifndef _XC_DRV_CONFIG_H_
#define _XC_DRV_CONFIG_H_
#include <stdint.h>
#ifndef ADC_OFF
#define ADC_ON 1
#else
#define ADC_ON 0
#endif
#ifndef AOTIMER_OFF
#define AOTIMER_ON 1
#else
#define AOTIMER_ON 0
#endif
#ifndef CALIB_OFF
#define CALIB_ON 1
#else
#define CALIB_ON 0
#endif
#ifndef DMA_OFF
#define DMA_ON 1
#else
#define DMA_ON 0
#endif
#ifndef FMC_SPI_OFF
#define FMC_SPI_ON 1
#else
#define FMC_SPI_ON 0
#endif
#ifndef FMC_SPI_DMA_OFF
#define FMC_SPI_DMA_ON 1
#else
#define FMC_SPI_DMA_ON 0
#endif
#ifndef GPIO_OFF
#define GPIO_ON 1
#else
#define GPIO_ON 0
#endif
#ifndef I2C_OFF
#define I2C_ON 1
#else
#define I2C_ON 0
#endif
#ifndef PGA_OFF
#define PGA_ON 1
#else
#define PGA_ON 0
#endif
#ifndef PWM_OFF
#define PWM_ON 1
#else
#define PWM_ON 0
#endif
#ifndef PWR_OFF
#define PWR_ON 1
#else
#define PWR_ON 0
#endif
#ifndef QDEC_OFF
#define QDEC_ON 1
#else
#define QDEC_ON 0
#endif
#ifndef RTC_OFF
#define RTC_ON 1
#else
#define RTC_ON 0
#endif
#ifndef SPI_OFF
#define SPI_ON 1
#else
#define SPI_ON 0
#endif
#ifndef SPI_DMA_OFF
#define SPI_DMA_ON 1
#else
#define SPI_DMA_ON 0
#endif
#ifndef SW_I2C_OFF
#define SW_I2C_ON 1
#else
#define SW_I2C_ON 0
#endif
#ifndef TIMER_OFF
#define TIMER_ON 1
#else
#define TIMER_ON 0
#endif
#ifndef UART_OFF
#define UART_ON 1
#else
#define UART_ON 0
#endif
#ifndef UART_DMA_OFF
#define UART_DMA_ON 1
#else
#define UART_DMA_ON 0
#endif
#ifndef WDT_OFF
#define WDT_ON 1
#else
#define WDT_ON 0
#endif
#ifndef BOR_OFF
#define BOR_ON 1
#else
#define BOR_ON 0
#endif
#endif // _XC_DRV_CONFIG_H_
component/xc6xx_drivers/Drivers/Startup/lora/startup_xinc.s
+234
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@@ -0,0 +1,234 @@
;/*****************************************************************************
; * @file: startup_xinc.s
; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
; * Device xinc.
; *****************************************************************************/
Stack_Size EQU 0x00000600
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; ToDo: Add here the vectors for the device specific external interrupts handler
DCD 0 ; 0 BLE Handler
DCD DMAS_Handler ; 1
DCD CPR_Handler ; 2
DCD GPIO_Handler ; 3
DCD RTC_Handler ; 4
DCD TIMER0_Handler ; 5
DCD TIMER1_Handler
DCD TIMER2_Handler
DCD TIMER3_Handler
DCD WDT_Handler
DCD I2C_Handler
DCD UART0_Handler
DCD UART1_Handler
DCD SPI0_Handler
DCD SPI1_Handler
DCD 0
DCD 0
DCD GADC_Handler ; 17
DCD 0 ; 18
DCD 0 ; 19
DCD 0 ; 20
DCD 0 ; 21
DCD SUB1G_Handler ; 22
DCD PWM_Handler ; 23
DCD BOR_Handler ; 24
DCD 0 ; 25
DCD 0 ; 26
DCD AOTIMER0_Handler ; 27
DCD AOTIMER1_Handler ; 28
DCD CMP_Handler ; 29
DCD FMC_Handler ; 30
DCD CAN_Handler ; 31
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR r0, =0x4000013C ; remap
LDR r1, =0x10000001
STR r1, [r0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
Default_Handler PROC
;EXPORT BLE_Handler [WEAK]
EXPORT DMAS_Handler [WEAK]
EXPORT CPR_Handler [WEAK]
EXPORT GPIO_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT TIMER2_Handler [WEAK]
EXPORT TIMER3_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT I2C_Handler [WEAK]
EXPORT UART0_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
EXPORT SPI0_Handler [WEAK]
EXPORT SPI1_Handler [WEAK]
;EXPORT KBS_Handler [WEAK]
;EXPORT QDEC_Handler [WEAK]
EXPORT GADC_Handler [WEAK]
EXPORT AOTIMER0_Handler [WEAK]
EXPORT AOTIMER1_Handler [WEAK]
EXPORT CMP_Handler [WEAK]
EXPORT FMC_Handler [WEAK]
EXPORT CAN_Handler [WEAK]
;EXPORT SIM_Handler [WEAK]
;EXPORT AES_Handler [WEAK]
EXPORT PendSV_Handler [WEAK]
EXPORT SysTick_Handler [WEAK]
EXPORT SUB1G_Handler [WEAK]
EXPORT PWM_Handler [WEAK]
EXPORT BOR_Handler [WEAK]
PendSV_Handler
SysTick_Handler
;BLE_Handler
DMAS_Handler
CPR_Handler
GPIO_Handler
RTC_Handler
TIMER0_Handler
TIMER1_Handler
TIMER2_Handler
TIMER3_Handler
WDT_Handler
I2C_Handler
UART0_Handler
UART1_Handler
SPI0_Handler
SPI1_Handler
;KBS_Handler
;QDEC_Handler
GADC_Handler
;SIM_Handler
;AES_Handler
AOTIMER0_Handler
AOTIMER1_Handler
CMP_Handler
FMC_Handler
CAN_Handler
SUB1G_Handler
PWM_Handler
BOR_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
END
component/xc6xx_drivers/Drivers/Startup/system_it_xinc.c
+231
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@@ -0,0 +1,231 @@
/*!
* \file system_it_xinc.c
*
* \brief Target system interruption implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "system_it_xinc.h"
/*------------------------------------------------------------------------------------
Func Prototype
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
/**
****************************************************************************************
* @brief This function handles NMI exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void NMI_Handler(void)
{
/* USER CODE BEGIN NonMaskableInt_IRQn */
DEBUG("%s\n", __func__);
/* USER CODE END NonMaskableInt_IRQn */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles Hard Fault exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void HardFault_Handler(void)
{
/* USER CODE BEGIN HardFault_IRQn */
DEBUG("%s\n", __func__);
/* USER CODE END HardFault_IRQn */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles Memory Manage exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void MemManage_Handler(void)
{
/* USER CODE BEGIN */
DEBUG("%s\n", __func__);
/* USER CODE END */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles Bus Fault exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void BusFault_Handler(void)
{
/* USER CODE BEGIN */
DEBUG("%s\n", __func__);
/* USER CODE END */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles Usage Fault exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void UsageFault_Handler(void)
{
/* USER CODE BEGIN */
DEBUG("%s\n", __func__);
/* USER CODE END */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles SVCall exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void SVC_Handler(void)
{
/* USER CODE BEGIN SVCall_IRQn */
DEBUG("%s\n", __func__);
/* USER CODE END SVCall_IRQn */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles Debug Monitor exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void DebugMon_Handler(void)
{
/* USER CODE BEGIN */
DEBUG("%s\n", __func__);
/* USER CODE END */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles PendSVC exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void PendSV_Handler(void)
{
/* USER CODE BEGIN PendSV_IRQn */
DEBUG("%s\n", __func__);
/* USER CODE END PendSV_IRQn */
while (1)
{
}
}
/****************************** Hard Fault Handler Functions *******************************/
/*------------------------------------------------------------------------------------
Private Functions
-------------------------------------------------------------------------------------*/
void HardFault_Handler_c(unsigned int * HardFault_args)
{
/*栈帧里面内容：*/
unsigned int stack_r0; //压栈的 R0
unsigned int stack_r1; //压栈的 R1
unsigned int stack_r2; //压栈的 R2
unsigned int stack_r3; //压栈的 R3
unsigned int stack_r12; //压栈的 R12
unsigned int stack_lr; //压栈的 lr
unsigned int stack_pc; //压栈的 pc
unsigned int stack_psr; //压栈的 psr
stack_r0 = ((unsigned int)HardFault_args[0]);
stack_r1 = ((unsigned int)HardFault_args[1]);
stack_r2 = ((unsigned int)HardFault_args[2]);
stack_r3 = ((unsigned int)HardFault_args[3]);
stack_r12 = ((unsigned int)HardFault_args[4]);
stack_lr = ((unsigned int)HardFault_args[5]);
stack_pc = ((unsigned int)HardFault_args[6]);
stack_psr = ((unsigned int)HardFault_args[7]);
DEBUG("----%s----\n", __func__);
DEBUG("R0=%x\n",stack_r0);
DEBUG("R1=%x\n",stack_r1);
DEBUG("R2=%x\n",stack_r2);
DEBUG("R3=%x\n",stack_r3);
DEBUG("R12=%x\n",stack_r12);
DEBUG("LR[R14]=%x\n",stack_lr);
DEBUG("PC[R15]=%x\n",stack_pc);
DEBUG("PSR=%x\n",stack_psr);
DEBUG("SCB_SHCSR=%x\n",SCB->SHCSR);
DEBUG("---------------------------\n");
while(1);
}
/*******************************************************************************************/
component/xc6xx_drivers/Drivers/Startup/system_it_xinc.h
+56
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@@ -0,0 +1,56 @@
/*!
* \file system_it_xinc.h
*
* \brief The header of system_it_xinc.c
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __SYSTEM_IT_XINC_H__
#define __SYSTEM_IT_XINC_H__
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "xc6xxx.h"
/*------------------------------------------------------------------------------------
Exported Functions
-------------------------------------------------------------------------------------*/
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void HardFault_Handler_c(unsigned int *HardFault_args);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_IT_XINC_H__ */
component/xc6xx_drivers/Drivers/Startup/system_xinc.c
+108
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@@ -0,0 +1,108 @@
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system
*
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include <stdio.h>
#include "xc6xxx.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
#define __DEBUG_OUT_PORT 0
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
#define VECTOR_NUM 48
void set_vector(void)
{
#if (USE_XIP == 1)
GLOBAL_INT_DISABLE();
for (uint32_t i = 0, *Pvector = (uint32_t *)(0x11001000 + 0),
*_vector_table = (uint32_t *)(0x10000000);
i < VECTOR_NUM; i++) // copy vertor table
{
_vector_table[i] = *Pvector++;
}
*((volatile unsigned int *)(0x4000013C)) =
0x10000001; // inter vertor table remap
GLOBAL_INT_RESTORE();
#endif
}
static void WDT_ResetInit(void)
{
//cpr_ctlapbclken_grctl__wdt_pclk_en__setf(DISABLE);
cpr_rstctl_ctlapb_sw__wdt_rstn__setf(RSTCTL_ENABLE);
cpr_rstctl_ctlapb_sw__wdt_rstn__setf(RSTCTL_DISABLE);
}
void SystemInit(void)
{
WDT_ResetInit();
#if (USE_XIP == 1)
set_vector();
#endif
}
__RAM_CODE int sendchar(int c)
{
unsigned int status;
#if (__DEBUG_OUT_PORT == 1)
for (;;) {
status = (*((volatile unsigned *)(0x40011000 + 0x14)));
status &= 0x20;
if (status == 0x20)
break;
}
(*((volatile unsigned *)(0x40011000 + 0x00))) = c;
return (1);
#else
for (;;) {
status = (*((volatile unsigned *)(0x40010000 + 0x14)));
status &= 0x20;
if (status == 0x20)
break;
}
(*((volatile unsigned *)(0x40010000 + 0x00))) = c;
return (1);
#endif
}
struct __FILE
{
int handle; /* Add whatever you need here */
};
FILE __stdout;
__RAM_CODE int fputc(int ch, FILE *f) { return (sendchar(ch)); }
int ferror(FILE *f)
{
/* Your implementation of ferror */
return EOF;
}
void _ttywrch(int ch) { sendchar(ch); }
void _sys_exit(int return_code)
{
label:
goto label; /* endless loop */
}
component/xc6xx_drivers/Drivers/Startup/xc20xx/startup_xinc.s
+234
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@@ -0,0 +1,234 @@
;/*****************************************************************************
; * @file: startup_xinc.s
; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
; * Device xinc.
; *****************************************************************************/
Stack_Size EQU 0x00000600
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; ToDo: Add here the vectors for the device specific external interrupts handler
DCD 0 ; 0 BLE Handler
DCD DMAS_Handler ; 1
DCD CPR_Handler ; 2
DCD GPIO_Handler ; 3
DCD RTC_Handler ; 4
DCD TIMER0_Handler ; 5
DCD TIMER1_Handler
DCD TIMER2_Handler
DCD TIMER3_Handler
DCD WDT_Handler
DCD I2C_Handler
DCD UART0_Handler
DCD UART1_Handler
DCD SPI0_Handler
DCD SPI1_Handler
DCD 0
DCD 0
DCD GADC_Handler ; 17
DCD 0 ; 18
DCD 0 ; 19
DCD 0 ; 20
DCD 0 ; 21
DCD SUB1G_Handler ; 22
DCD PWM_Handler ; 23
DCD MPU_Handler ; 24
DCD 0 ; 25
DCD 0 ; 26
DCD AOTIMER0_Handler ; 27
DCD AOTIMER1_Handler ; 28
DCD CMP_Handler ; 29
DCD FMC_Handler ; 30
DCD CAN_Handler ; 31
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR r0, =0x4000013C ; remap
LDR r1, =0x10000001
STR r1, [r0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
Default_Handler PROC
;EXPORT BLE_Handler [WEAK]
EXPORT DMAS_Handler [WEAK]
EXPORT CPR_Handler [WEAK]
EXPORT GPIO_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT TIMER2_Handler [WEAK]
EXPORT TIMER3_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT I2C_Handler [WEAK]
EXPORT UART0_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
EXPORT SPI0_Handler [WEAK]
EXPORT SPI1_Handler [WEAK]
;EXPORT KBS_Handler [WEAK]
;EXPORT QDEC_Handler [WEAK]
EXPORT GADC_Handler [WEAK]
EXPORT AOTIMER0_Handler [WEAK]
EXPORT AOTIMER1_Handler [WEAK]
EXPORT CMP_Handler [WEAK]
EXPORT FMC_Handler [WEAK]
EXPORT CAN_Handler [WEAK]
;EXPORT SIM_Handler [WEAK]
;EXPORT AES_Handler [WEAK]
EXPORT PendSV_Handler [WEAK]
EXPORT SysTick_Handler [WEAK]
EXPORT SUB1G_Handler [WEAK]
EXPORT PWM_Handler [WEAK]
EXPORT MPU_Handler [WEAK]
PendSV_Handler
SysTick_Handler
;BLE_Handler
DMAS_Handler
CPR_Handler
GPIO_Handler
RTC_Handler
TIMER0_Handler
TIMER1_Handler
TIMER2_Handler
TIMER3_Handler
WDT_Handler
I2C_Handler
UART0_Handler
UART1_Handler
SPI0_Handler
SPI1_Handler
;KBS_Handler
;QDEC_Handler
GADC_Handler
;SIM_Handler
;AES_Handler
AOTIMER0_Handler
AOTIMER1_Handler
CMP_Handler
FMC_Handler
CAN_Handler
SUB1G_Handler
PWM_Handler
MPU_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
END
component/xc6xx_drivers/Drivers/Startup/xc26xx/startup_xinc.s
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;/*****************************************************************************
; * @file: startup_xinc.s
; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
; * Device xinc.
; *****************************************************************************/
Stack_Size EQU 0x00000600
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; ToDo: Add here the vectors for the device specific external interrupts handler
DCD 0 ; 0 BLE Handler
DCD DMAS_Handler ; 1
DCD CPR_Handler ; 2
DCD GPIO_Handler ; 3
DCD RTC_Handler ; 4
DCD TIMER0_Handler ; 5
DCD TIMER1_Handler
DCD TIMER2_Handler
DCD TIMER3_Handler
DCD WDT_Handler
DCD I2C_Handler
DCD UART0_Handler
DCD UART1_Handler
DCD SPI0_Handler
DCD SPI1_Handler
DCD 0
DCD 0
DCD GADC_Handler ; 17
DCD 0 ; 18
DCD 0 ; 19
DCD 0 ; 20
DCD 0 ; 21
DCD SUB1G_Handler ; 22
DCD PWM_Handler ; 23
DCD MPU_Handler ; 24
DCD 0 ; 25
DCD 0 ; 26
DCD AOTIMER0_Handler ; 27
DCD AOTIMER1_Handler ; 28
DCD CMP_Handler ; 29
DCD FMC_Handler ; 30
DCD CAN_Handler ; 31
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR r0, =0x4000013C ; remap
LDR r1, =0x10000001
STR r1, [r0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
Default_Handler PROC
;EXPORT BLE_Handler [WEAK]
EXPORT DMAS_Handler [WEAK]
EXPORT CPR_Handler [WEAK]
EXPORT GPIO_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT TIMER2_Handler [WEAK]
EXPORT TIMER3_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT I2C_Handler [WEAK]
EXPORT UART0_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
EXPORT SPI0_Handler [WEAK]
EXPORT SPI1_Handler [WEAK]
;EXPORT KBS_Handler [WEAK]
;EXPORT QDEC_Handler [WEAK]
EXPORT GADC_Handler [WEAK]
EXPORT AOTIMER0_Handler [WEAK]
EXPORT AOTIMER1_Handler [WEAK]
EXPORT CMP_Handler [WEAK]
EXPORT FMC_Handler [WEAK]
EXPORT CAN_Handler [WEAK]
;EXPORT SIM_Handler [WEAK]
;EXPORT AES_Handler [WEAK]
EXPORT PendSV_Handler [WEAK]
EXPORT SysTick_Handler [WEAK]
EXPORT SUB1G_Handler [WEAK]
EXPORT PWM_Handler [WEAK]
EXPORT MPU_Handler [WEAK]
PendSV_Handler
SysTick_Handler
;BLE_Handler
DMAS_Handler
CPR_Handler
GPIO_Handler
RTC_Handler
TIMER0_Handler
TIMER1_Handler
TIMER2_Handler
TIMER3_Handler
WDT_Handler
I2C_Handler
UART0_Handler
UART1_Handler
SPI0_Handler
SPI1_Handler
;KBS_Handler
;QDEC_Handler
GADC_Handler
;SIM_Handler
;AES_Handler
AOTIMER0_Handler
AOTIMER1_Handler
CMP_Handler
FMC_Handler
CAN_Handler
SUB1G_Handler
PWM_Handler
MPU_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
END
component/xc6xx_drivers/Drivers/Startup/xc60xx/startup_xinc.s
+257
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;/*****************************************************************************
; * @file: startup_xinc.s
; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
; * Device xinc.
; *****************************************************************************/
Stack_Size EQU 0x00001000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; ToDo: Add here the vectors for the device specific external interrupts handler
DCD BLE_Handler ; 0
DCD DMA_Handler ; 1
DCD CPR_Handler ; 2
DCD GPIO_Handler ; 3
DCD RTC_Handler ; 4
DCD TIMER0_Handler ; 5
DCD TIMER1_Handler ; 6
DCD TIMER2_Handler ; 7
DCD TIMER3_Handler ; 8
DCD WDT_Handler ; 9
DCD I2C_Handler ; 10
DCD UART0_Handler ; 11
DCD UART1_Handler ; 12
DCD SPI0_Handler ; 13
DCD SPI1_Handler ; 14
DCD 0 ; 15
DCD 0 ; 16
DCD GADC_Handler ; 17
DCD PWM_Handler ; 18
DCD AES_Handler ; 19
DCD USB_Handler ; 20
DCD AUDIO_Handler ; 21
DCD RF24G_Handler ; 22
DCD SPI2_Handler ; 23
DCD MPU_Handler ; 24
DCD UART2_Handler ; 25
DCD I2S_Handler ; 26
DCD AOTIMER0_Handler ; 27
DCD AOTIMER1_Handler ; 28
DCD CMP_Handler ; 29
DCD FMC_Handler ; 30
DCD CAN_Handler ; 31
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR r0, =0x4000013C ; remap
LDR r1, =0x10000001
STR r1, [r0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
IMPORT HardFault_Handler_c ;函数声明
movs r0, #4 ;判断主栈指针还是进程栈指针
mov r1, lr
tst r0, r1
beq hf_used_msp ;如果是主栈指针
mrs r0, psp ;否则是进程栈指针,把进程栈指针地址付给 R0
ldr r1, =HardFault_Handler_c ;跳转到 HardFault 中断程序
bx r1
hf_used_msp
mrs r0, msp ;把主栈指针地址赋给 R0
ldr r1, =HardFault_Handler_c
bx r1
;EXPORT HardFault_Handler [WEAK]
;B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT BLE_Handler [WEAK]
EXPORT DMA_Handler [WEAK]
EXPORT CPR_Handler [WEAK]
EXPORT GPIO_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT TIMER2_Handler [WEAK]
EXPORT TIMER3_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT I2C_Handler [WEAK]
EXPORT UART0_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
EXPORT SPI0_Handler [WEAK]
EXPORT SPI1_Handler [WEAK]
;EXPORT KBS_Handler [WEAK]
;EXPORT QDEC_Handler [WEAK]
EXPORT GADC_Handler [WEAK]
EXPORT PWM_Handler [WEAK]
EXPORT AES_Handler [WEAK]
EXPORT PendSV_Handler [WEAK]
EXPORT SysTick_Handler [WEAK]
EXPORT USB_Handler [WEAK];20
EXPORT AUDIO_Handler [WEAK];21
EXPORT RF24G_Handler [WEAK];22
EXPORT SPI2_Handler [WEAK];23
EXPORT MPU_Handler [WEAK];24
EXPORT UART2_Handler [WEAK];25
EXPORT I2S_Handler [WEAK];26
EXPORT AOTIMER0_Handler [WEAK];27
EXPORT AOTIMER1_Handler [WEAK];28
EXPORT CMP_Handler [WEAK];29
EXPORT FMC_Handler [WEAK];30
EXPORT CAN_Handler [WEAK];31
PendSV_Handler
SysTick_Handler
BLE_Handler
RF24G_Handler
DMA_Handler
CPR_Handler
GPIO_Handler
RTC_Handler
TIMER0_Handler
TIMER1_Handler
TIMER2_Handler
TIMER3_Handler
WDT_Handler
I2C_Handler
I2S_Handler
UART0_Handler
UART1_Handler
UART2_Handler
SPI0_Handler
SPI1_Handler
SPI2_Handler
MPU_Handler
;KBS_Handler
;QDEC_Handler
GADC_Handler
PWM_Handler
AUDIO_Handler
;SIM_Handler
AES_Handler
AOTIMER0_Handler
AOTIMER1_Handler
CMP_Handler
FMC_Handler
CAN_Handler
USB_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
END
component/xc6xx_drivers/Drivers/Startup/xc62xx/rom_symdefs.txt
+28
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@@ -0,0 +1,28 @@
#<SYMDEFS># ARM Linker, 5060750: Last Updated: Wed Jan 15 19:05:47 2025
0x00000809 T _memset_w
0x00000823 T _memset
0x00000841 T __aeabi_memclr
0x00000841 T __rt_memclr
0x00000845 T __aeabi_memclr4
0x00000845 T __aeabi_memclr8
0x00000845 T __rt_memclr_w
0x00000849 T __aeabi_uread4
0x00000849 T __rt_uread4
0x0000086d T ram_memcpy_bytes
0x000008ab T xc_fmc_status_wait_idle
0x000008b5 T xc_fmc_spi_write_nbyte
0x0000095b T xc_fmc_spi_read_nbyte
0x000009d3 T xc_fmc_spi_enable
0x000009ef T xc_fmc_spi_disable
0x00000a07 T xc_fmc_spi_init_oprt
0x00000a8d T xc_fmc_spi_flash_power_down
0x00000ab5 T xc_fmc_spi_flash_wake_up
;0x00000b45 T xc_fmc_spi_flash_erase_sector
;0x00000b85 T xc_fmc_spi_flash_rdid
;0x00000bcb T xc_fmc_spi_flash_erase_page
;0x00000c1b T xc_fmc_spi_flash_write_page
;0x00000c9d T xc_fmc_spi_otp_read_page
;0x00000d2f T xc_fmc_spi_flash_read_page
;0x00000d9d T xc_fmc_spi_flash_write
;0x00000e5d T xc_fmc_spi_flash_read
;0x00000eff T xc_fmc_spi_flash_ruid
component/xc6xx_drivers/Drivers/Startup/xc62xx/startup_xinc.s
+257
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@@ -0,0 +1,257 @@
;/*****************************************************************************
; * @file: startup_xinc.s
; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
; * Device xinc.
; *****************************************************************************/
Stack_Size EQU 0x00001000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; ToDo: Add here the vectors for the device specific external interrupts handler
DCD BLE_Handler ; 0
DCD DMA_Handler ; 1
DCD CPR_Handler ; 2
DCD GPIO_Handler ; 3
DCD RTC_Handler ; 4
DCD TIMER0_Handler ; 5
DCD TIMER1_Handler ; 6
DCD TIMER2_Handler ; 7
DCD TIMER3_Handler ; 8
DCD WDT_Handler ; 9
DCD I2C_Handler ; 10
DCD UART0_Handler ; 11
DCD UART1_Handler ; 12
DCD SPI0_Handler ; 13
DCD SPI1_Handler ; 14
DCD 0 ; 15
DCD 0 ; 16
DCD GADC_Handler ; 17
DCD PWM_Handler ; 18
DCD AES_Handler ; 19
DCD USB_Handler ; 20
DCD AUDIO_Handler ; 21
DCD RF24G_Handler ; 22
DCD SPI2_Handler ; 23
DCD MPU_Handler ; 24
DCD UART2_Handler ; 25
DCD I2S_Handler ; 26
DCD AOTIMER0_Handler ; 27
DCD AOTIMER1_Handler ; 28
DCD CMP_Handler ; 29
DCD FMC_Handler ; 30
DCD CAN_Handler ; 31
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR r0, =0x4000013C ; remap
LDR r1, =0x10000001
STR r1, [r0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
IMPORT HardFault_Handler_c ;函数声明
movs r0, #4 ;判断主栈指针还是进程栈指针
mov r1, lr
tst r0, r1
beq hf_used_msp ;如果是主栈指针
mrs r0, psp ;否则是进程栈指针,把进程栈指针地址付给 R0
ldr r1, =HardFault_Handler_c ;跳转到 HardFault 中断程序
bx r1
hf_used_msp
mrs r0, msp ;把主栈指针地址赋给 R0
ldr r1, =HardFault_Handler_c
bx r1
;EXPORT HardFault_Handler [WEAK]
;B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT BLE_Handler [WEAK]
EXPORT DMA_Handler [WEAK]
EXPORT CPR_Handler [WEAK]
EXPORT GPIO_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT TIMER2_Handler [WEAK]
EXPORT TIMER3_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT I2C_Handler [WEAK]
EXPORT UART0_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
EXPORT SPI0_Handler [WEAK]
EXPORT SPI1_Handler [WEAK]
;EXPORT KBS_Handler [WEAK]
;EXPORT QDEC_Handler [WEAK]
EXPORT GADC_Handler [WEAK]
EXPORT PWM_Handler [WEAK]
EXPORT AES_Handler [WEAK]
EXPORT PendSV_Handler [WEAK]
EXPORT SysTick_Handler [WEAK]
EXPORT USB_Handler [WEAK];20
EXPORT AUDIO_Handler [WEAK];21
EXPORT RF24G_Handler [WEAK];22
EXPORT SPI2_Handler [WEAK];23
EXPORT MPU_Handler [WEAK];24
EXPORT UART2_Handler [WEAK];25
EXPORT I2S_Handler [WEAK];26
EXPORT AOTIMER0_Handler [WEAK];27
EXPORT AOTIMER1_Handler [WEAK];28
EXPORT CMP_Handler [WEAK];29
EXPORT FMC_Handler [WEAK];30
EXPORT CAN_Handler [WEAK];31
PendSV_Handler
SysTick_Handler
BLE_Handler
RF24G_Handler
DMA_Handler
CPR_Handler
GPIO_Handler
RTC_Handler
TIMER0_Handler
TIMER1_Handler
TIMER2_Handler
TIMER3_Handler
WDT_Handler
I2C_Handler
I2S_Handler
UART0_Handler
UART1_Handler
UART2_Handler
SPI0_Handler
SPI1_Handler
SPI2_Handler
MPU_Handler
;KBS_Handler
;QDEC_Handler
GADC_Handler
PWM_Handler
AUDIO_Handler
;SIM_Handler
AES_Handler
AOTIMER0_Handler
AOTIMER1_Handler
CMP_Handler
FMC_Handler
CAN_Handler
USB_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
END
component/xc6xx_drivers/Drivers/Startup/xc65xx/startup_xinc.s
+257
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@@ -0,0 +1,257 @@
;/*****************************************************************************
; * @file: startup_xinc.s
; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
; * Device xinc.
; *****************************************************************************/
Stack_Size EQU 0x00001000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; ToDo: Add here the vectors for the device specific external interrupts handler
DCD BLE_Handler ; 0
DCD DMA_Handler ; 1
DCD CPR_Handler ; 2
DCD GPIO_Handler ; 3
DCD RTC_Handler ; 4
DCD TIMER0_Handler ; 5
DCD TIMER1_Handler ; 6
DCD TIMER2_Handler ; 7
DCD TIMER3_Handler ; 8
DCD WDT_Handler ; 9
DCD I2C_Handler ; 10
DCD UART0_Handler ; 11
DCD UART1_Handler ; 12
DCD SPI0_Handler ; 13
DCD SPI1_Handler ; 14
DCD 0 ; 15
DCD 0 ; 16
DCD GADC_Handler ; 17
DCD PWM_Handler ; 18
DCD AES_Handler ; 19
DCD USB_Handler ; 20
DCD AUDIO_Handler ; 21
DCD RF24G_Handler ; 22
DCD SPI2_Handler ; 23
DCD MPU_Handler ; 24
DCD UART2_Handler ; 25
DCD I2S_Handler ; 26
DCD AOTIMER0_Handler ; 27
DCD AOTIMER1_Handler ; 28
DCD CMP_Handler ; 29
DCD FMC_Handler ; 30
DCD CAN_Handler ; 31
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR r0, =0x4000013C ; remap
LDR r1, =0x10000001
STR r1, [r0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
IMPORT HardFault_Handler_c ;函数声明
movs r0, #4 ;判断主栈指针还是进程栈指针
mov r1, lr
tst r0, r1
beq hf_used_msp ;如果是主栈指针
mrs r0, psp ;否则是进程栈指针,把进程栈指针地址付给 R0
ldr r1, =HardFault_Handler_c ;跳转到 HardFault 中断程序
bx r1
hf_used_msp
mrs r0, msp ;把主栈指针地址赋给 R0
ldr r1, =HardFault_Handler_c
bx r1
;EXPORT HardFault_Handler [WEAK]
;B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT BLE_Handler [WEAK]
EXPORT DMA_Handler [WEAK]
EXPORT CPR_Handler [WEAK]
EXPORT GPIO_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT TIMER2_Handler [WEAK]
EXPORT TIMER3_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT I2C_Handler [WEAK]
EXPORT UART0_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
EXPORT SPI0_Handler [WEAK]
EXPORT SPI1_Handler [WEAK]
;EXPORT KBS_Handler [WEAK]
;EXPORT QDEC_Handler [WEAK]
EXPORT GADC_Handler [WEAK]
EXPORT PWM_Handler [WEAK]
EXPORT AES_Handler [WEAK]
EXPORT PendSV_Handler [WEAK]
EXPORT SysTick_Handler [WEAK]
EXPORT USB_Handler [WEAK];20
EXPORT AUDIO_Handler [WEAK];21
EXPORT RF24G_Handler [WEAK];22
EXPORT SPI2_Handler [WEAK];23
EXPORT MPU_Handler [WEAK];24
EXPORT UART2_Handler [WEAK];25
EXPORT I2S_Handler [WEAK];26
EXPORT AOTIMER0_Handler [WEAK];27
EXPORT AOTIMER1_Handler [WEAK];28
EXPORT CMP_Handler [WEAK];29
EXPORT FMC_Handler [WEAK];30
EXPORT CAN_Handler [WEAK];31
PendSV_Handler
SysTick_Handler
BLE_Handler
RF24G_Handler
DMA_Handler
CPR_Handler
GPIO_Handler
RTC_Handler
TIMER0_Handler
TIMER1_Handler
TIMER2_Handler
TIMER3_Handler
WDT_Handler
I2C_Handler
I2S_Handler
UART0_Handler
UART1_Handler
UART2_Handler
SPI0_Handler
SPI1_Handler
SPI2_Handler
MPU_Handler
;KBS_Handler
;QDEC_Handler
GADC_Handler
PWM_Handler
AUDIO_Handler
;SIM_Handler
AES_Handler
AOTIMER0_Handler
AOTIMER1_Handler
CMP_Handler
FMC_Handler
CAN_Handler
USB_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
END
component/xc6xx_drivers/Drivers/Startup/xc6axx/startup_xinc.s
+262
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;/*****************************************************************************
; * @file: startup_xinc.s
; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
; * Device xinc.
; *****************************************************************************/
Stack_Size EQU 0x00001000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; ToDo: Add here the vectors for the device specific external interrupts handler
DCD BLE_Handler ; 0
DCD DMA_Handler ; 1
DCD CPR_Handler ; 2
DCD GPIO_Handler ; 3
DCD RTC_Handler ; 4
DCD TIMER0_Handler ; 5
DCD TIMER1_Handler ; 6
DCD TIMER2_Handler ; 7
DCD TIMER3_Handler ; 8
DCD WDT_Handler ; 9
DCD I2C_Handler ; 10
DCD UART0_Handler ; 11
DCD UART1_Handler ; 12
DCD SPI0_Handler ; 13
DCD SPI1_Handler ; 14
DCD 0 ; 15
DCD 0 ; 16
DCD GADC_Handler ; 17
DCD PWM_Handler ; 18
DCD AES_Handler ; 19
DCD USB_Handler ; 20
DCD 0 ; 21
DCD RF24G_Handler ; 22
DCD SPI2_Handler ; 23
DCD MPU_Handler ; 24
DCD UART2_Handler ; 25
DCD I2S_Handler ; 26
DCD AOTIMER0_Handler ; 27
DCD AOTIMER1_Handler ; 28
DCD CMP_Handler ; 29
DCD FMC_Handler ; 30
DCD 0 ; 31
DCD 0 ; 32
DCD BLE_IRQHandler ; 33
DCD BT_DM_Handler ; 34
DCD BT_Dbg_Handler ; 35
DCD 0 ; 36
DCD 0 ; 37
DCD 0 ; 38
DCD 0 ; 39
DCD 0 ; 40
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR r0, =0x4000013C ; remap
LDR r1, =0x10000001
STR r1, [r0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
IMPORT HardFault_Handler_c ;函数声明
movs r0, #4 ;判断主栈指针还是进程栈指针
mov r1, lr
tst r0, r1
beq hf_used_msp ;如果是主栈指针
mrs r0, psp ;否则是进程栈指针,把进程栈指针地址付给 R0
ldr r1, =HardFault_Handler_c ;跳转到 HardFault 中断程序
bx r1
hf_used_msp
mrs r0, msp ;把主栈指针地址赋给 R0
ldr r1, =HardFault_Handler_c
bx r1
;EXPORT HardFault_Handler [WEAK]
;B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT PendSV_Handler [WEAK] ; -2
EXPORT SysTick_Handler [WEAK] ; -1
EXPORT BLE_Handler [WEAK] ; 0
EXPORT DMA_Handler [WEAK] ; 1
EXPORT CPR_Handler [WEAK] ; 2
EXPORT GPIO_Handler [WEAK] ; 3
EXPORT RTC_Handler [WEAK] ; 4
EXPORT TIMER0_Handler [WEAK] ; 5
EXPORT TIMER1_Handler [WEAK] ; 6
EXPORT TIMER2_Handler [WEAK] ; 7
EXPORT TIMER3_Handler [WEAK] ; 8
EXPORT WDT_Handler [WEAK] ; 9
EXPORT I2C_Handler [WEAK] ; 10
EXPORT UART0_Handler [WEAK] ; 11
EXPORT UART1_Handler [WEAK] ; 12
EXPORT SPI0_Handler [WEAK] ; 13
EXPORT SPI1_Handler [WEAK] ; 14
;EXPORT KBS_Handler [WEAK] ; 15
;EXPORT QDEC_Handler [WEAK] ; 16
EXPORT GADC_Handler [WEAK] ; 17
EXPORT PWM_Handler [WEAK] ; 18
EXPORT AES_Handler [WEAK] ; 19
EXPORT USB_Handler [WEAK] ; 20
EXPORT AUDIO_Handler [WEAK] ; 21
EXPORT RF24G_Handler [WEAK] ; 22
EXPORT SPI2_Handler [WEAK] ; 23
EXPORT MPU_Handler [WEAK] ; 24
EXPORT UART2_Handler [WEAK] ; 25
EXPORT I2S_Handler [WEAK] ; 26
EXPORT AOTIMER0_Handler [WEAK] ; 27
EXPORT AOTIMER1_Handler [WEAK] ; 28
EXPORT CMP_Handler [WEAK] ; 29
EXPORT FMC_Handler [WEAK] ; 30
EXPORT BLE_IRQHandler [WEAK] ; 33
EXPORT BT_DM_Handler [WEAK] ; 34
EXPORT BT_Dbg_Handler [WEAK] ; 35
PendSV_Handler
SysTick_Handler
BLE_Handler
RF24G_Handler
DMA_Handler
CPR_Handler
GPIO_Handler
RTC_Handler
TIMER0_Handler
TIMER1_Handler
TIMER2_Handler
TIMER3_Handler
WDT_Handler
I2C_Handler
I2S_Handler
UART0_Handler
UART1_Handler
UART2_Handler
SPI0_Handler
SPI1_Handler
SPI2_Handler
MPU_Handler
;KBS_Handler
;QDEC_Handler
GADC_Handler
PWM_Handler
AUDIO_Handler
;SIM_Handler
AES_Handler
AOTIMER0_Handler
AOTIMER1_Handler
CMP_Handler
FMC_Handler
BLE_IRQHandler
BT_DM_Handler
BT_Dbg_Handler
USB_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
END
component/xc6xx_drivers/Drivers/USB/FatFS/inc/diskio.h
+106
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/*!
* \file diskio.h
*
* \brief Target disk I/O implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _DISKIO_DEFINED
#define _DISKIO_DEFINED
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "integer.h"
/*------------------------------------------------------------------------------------
Macros
------------------------------------------- -----------------------------------------*/
#define _USE_WRITE 1 /* 1: Enable disk_write function */
#define _USE_IOCTL 1 /* 1: Enable disk_ioctl function */
/* Disk Status Bits (DSTATUS) */
#define STA_NOINIT 0x01 /* Drive not initialized */
#define STA_NODISK 0x02 /* No medium in the drive */
#define STA_PROTECT 0x04 /* Write protected */
/* Command code for disk_ioctrl fucntion */
/* Generic command (Used by FatFs) */
#define CTRL_SYNC 0 /* Complete pending write process (needed at _FS_READONLY == 0) */
#define GET_SECTOR_COUNT 1 /* Get media size (needed at _USE_MKFS == 1) */
#define GET_SECTOR_SIZE 2 /* Get sector size (needed at _MAX_SS != _MIN_SS) */
#define GET_BLOCK_SIZE 3 /* Get erase block size (needed at _USE_MKFS == 1) */
#define CTRL_TRIM 4 /* Inform device that the data on the block of sectors is no longer used (needed at _USE_TRIM == 1) */
/* Generic command (Not used by FatFs) */
#define CTRL_POWER 5 /* Get/Set power status */
#define CTRL_LOCK 6 /* Lock/Unlock media removal */
#define CTRL_EJECT 7 /* Eject media */
#define CTRL_FORMAT 8 /* Create physical format on the media */
/* MMC/SDC specific ioctl command */
#define MMC_GET_TYPE 10 /* Get card type */
#define MMC_GET_CSD 11 /* Get CSD */
#define MMC_GET_CID 12 /* Get CID */
#define MMC_GET_OCR 13 /* Get OCR */
#define MMC_GET_SDSTAT 14 /* Get SD status */
/* ATA/CF specific ioctl command */
#define ATA_GET_REV 20 /* Get F/W revision */
#define ATA_GET_MODEL 21 /* Get model name */
#define ATA_GET_SN 22 /* Get serial number */
/*------------------------------------------------------------------------------------
Typedef
------------------------------------------------------------------------------------*/
/* Status of Disk Functions */
typedef BYTE DSTATUS;
/* Results of Disk Functions */
typedef enum {
RES_OK = 0, /* 0: Successful */
RES_ERROR, /* 1: R/W Error */
RES_WRPRT, /* 2: Write Protected */
RES_NOTRDY, /* 3: Not Ready */
RES_PARERR /* 4: Invalid Parameter */
} DRESULT;
/*------------------------------------------------------------------------------------
Exported Functions
-------------------------------------------------------------------------------------*/
DSTATUS disk_initialize (BYTE pdrv);
DSTATUS disk_status (BYTE pdrv);
DRESULT disk_read (BYTE pdrv, BYTE* buff, DWORD sector, UINT count);
DRESULT disk_write (BYTE pdrv, const BYTE* buff, DWORD sector, UINT count);
DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);
DWORD get_fattime (void);
#ifdef __cplusplus
}
#endif
#endif
component/xc6xx_drivers/Drivers/USB/FatFS/inc/fatfs.h
+54
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@@ -0,0 +1,54 @@
/*!
* \file fatfs.h
*
* \brief Target FatFS implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __fatfs_H
#define __fatfs_H
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "ff.h"
#include "ff_gen_drv.h"
/*------------------------------------------------------------------------------------
Global Variables
-------------------------------------------------------------------------------------*/
extern char Path[4]; /* USER logical drive path */
extern FATFS FatFS; /* File system object for USER logical drive */
extern FIL File; /* File object for USER */
/*------------------------------------------------------------------------------------
Exported Functions
------------------------------------------- -----------------------------------------*/
void FATFS_Init(void);
#ifdef __cplusplus
}
#endif
#endif /*__fatfs_H */
component/xc6xx_drivers/Drivers/USB/FatFS/inc/ff.h
+362
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/*----------------------------------------------------------------------------/
/ FatFs - Generic FAT file system module R0.12c /
/-----------------------------------------------------------------------------/
/
/ Copyright (C) 2017, ChaN, all right reserved.
/
/ FatFs module is an open source software. Redistribution and use of FatFs in
/ source and binary forms, with or without modification, are permitted provided
/ that the following condition is met:
/ 1. Redistributions of source code must retain the above copyright notice,
/ this condition and the following disclaimer.
/
/ This software is provided by the copyright holder and contributors "AS IS"
/ and any warranties related to this software are DISCLAIMED.
/ The copyright owner or contributors be NOT LIABLE for any damages caused
/ by use of this software.
/----------------------------------------------------------------------------*/
#ifndef _FF_H
#define _FF_H 68300 /* Revision ID */
#ifdef __cplusplus
extern "C" {
#endif
#include "integer.h" /* Basic integer types */
#include "ffconf.h" /* FatFs configuration options */
#if _FF_H != _FFCONF
#error Wrong configuration file (ffconf.h).
#endif
/* Definitions of volume management */
#if _MULTI_PARTITION /* Multiple partition configuration */
typedef struct {
BYTE pd; /* Physical drive number */
BYTE pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */
} PARTITION;
extern PARTITION VolToPart[]; /* Volume - Partition resolution table */
#endif
/* Type of path name strings on FatFs API */
#if _LFN_UNICODE /* Unicode (UTF-16) string */
#if _USE_LFN == 0
#error _LFN_UNICODE must be 0 at non-LFN cfg.
#endif
#ifndef _INC_TCHAR
typedef WCHAR TCHAR;
#define _T(x) L ## x
#define _TEXT(x) L ## x
#endif
#else /* ANSI/OEM string */
#ifndef _INC_TCHAR
typedef char TCHAR;
#define _T(x) x
#define _TEXT(x) x
#endif
#endif
/* Type of file size variables */
#if _FS_EXFAT
#if _USE_LFN == 0
#error LFN must be enabled when enable exFAT
#endif
typedef QWORD FSIZE_t;
#else
typedef DWORD FSIZE_t;
#endif
/* File system object structure (FATFS) */
typedef struct {
BYTE fs_type; /* File system type (0:N/A) */
BYTE drv; /* Physical drive number */
BYTE n_fats; /* Number of FATs (1 or 2) */
BYTE wflag; /* win[] flag (b0:dirty) */
BYTE fsi_flag; /* FSINFO flags (b7:disabled, b0:dirty) */
WORD id; /* File system mount ID */
WORD n_rootdir; /* Number of root directory entries (FAT12/16) */
WORD csize; /* Cluster size [sectors] */
#if _MAX_SS != _MIN_SS
WORD ssize; /* Sector size (512, 1024, 2048 or 4096) */
#endif
#if _USE_LFN != 0
WCHAR* lfnbuf; /* LFN working buffer */
#endif
#if _FS_EXFAT
BYTE* dirbuf; /* Directory entry block scratchpad buffer */
#endif
#if _FS_REENTRANT
_SYNC_t sobj; /* Identifier of sync object */
#endif
#if !_FS_READONLY
DWORD last_clst; /* Last allocated cluster */
DWORD free_clst; /* Number of free clusters */
#endif
#if _FS_RPATH != 0
DWORD cdir; /* Current directory start cluster (0:root) */
#if _FS_EXFAT
DWORD cdc_scl; /* Containing directory start cluster (invalid when cdir is 0) */
DWORD cdc_size; /* b31-b8:Size of containing directory, b7-b0: Chain status */
DWORD cdc_ofs; /* Offset in the containing directory (invalid when cdir is 0) */
#endif
#endif
DWORD n_fatent; /* Number of FAT entries (number of clusters + 2) */
DWORD fsize; /* Size of an FAT [sectors] */
DWORD volbase; /* Volume base sector */
DWORD fatbase; /* FAT base sector */
DWORD dirbase; /* Root directory base sector/cluster */
DWORD database; /* Data base sector */
DWORD winsect; /* Current sector appearing in the win[] */
BYTE win[_MAX_SS]; /* Disk access window for Directory, FAT (and file data at tiny cfg) */
} FATFS;
/* Object ID and allocation information (_FDID) */
typedef struct {
FATFS* fs; /* Pointer to the owner file system object */
WORD id; /* Owner file system mount ID */
BYTE attr; /* Object attribute */
BYTE stat; /* Object chain status (b1-0: =0:not contiguous, =2:contiguous (no data on FAT), =3:flagmented in this session, b2:sub-directory stretched) */
DWORD sclust; /* Object start cluster (0:no cluster or root directory) */
FSIZE_t objsize; /* Object size (valid when sclust != 0) */
#if _FS_EXFAT
DWORD n_cont; /* Size of first fragment, clusters - 1 (valid when stat == 3) */
DWORD n_frag; /* Size of last fragment needs to be written (valid when not zero) */
DWORD c_scl; /* Containing directory start cluster (valid when sclust != 0) */
DWORD c_size; /* b31-b8:Size of containing directory, b7-b0: Chain status (valid when c_scl != 0) */
DWORD c_ofs; /* Offset in the containing directory (valid when sclust != 0 and non-directory object) */
#endif
#if _FS_LOCK != 0
UINT lockid; /* File lock ID origin from 1 (index of file semaphore table Files[]) */
#endif
} _FDID;
/* File object structure (FIL) */
typedef struct {
_FDID obj; /* Object identifier (must be the 1st member to detect invalid object pointer) */
BYTE flag; /* File status flags */
BYTE err; /* Abort flag (error code) */
FSIZE_t fptr; /* File read/write pointer (Zeroed on file open) */
DWORD clust; /* Current cluster of fpter (invalid when fptr is 0) */
DWORD sect; /* Sector number appearing in buf[] (0:invalid) */
#if !_FS_READONLY
DWORD dir_sect; /* Sector number containing the directory entry */
BYTE* dir_ptr; /* Pointer to the directory entry in the win[] */
#endif
#if _USE_FASTSEEK
DWORD* cltbl; /* Pointer to the cluster link map table (nulled on open, set by application) */
#endif
#if !_FS_TINY
BYTE buf[_MAX_SS]; /* File private data read/write window */
#endif
} FIL;
/* Directory object structure (DIR) */
typedef struct {
_FDID obj; /* Object identifier */
DWORD dptr; /* Current read/write offset */
DWORD clust; /* Current cluster */
DWORD sect; /* Current sector (0:Read operation has terminated) */
BYTE* dir; /* Pointer to the directory item in the win[] */
BYTE fn[12]; /* SFN (in/out) {body[8],ext[3],status[1]} */
#if _USE_LFN != 0
DWORD blk_ofs; /* Offset of current entry block being processed (0xFFFFFFFF:Invalid) */
#endif
#if _USE_FIND
const TCHAR* pat; /* Pointer to the name matching pattern */
#endif
} DIR;
/* File information structure (FILINFO) */
typedef struct {
FSIZE_t fsize; /* File size */
WORD fdate; /* Modified date */
WORD ftime; /* Modified time */
BYTE fattrib; /* File attribute */
#if _USE_LFN != 0
TCHAR altname[13]; /* Alternative file name */
TCHAR fname[_MAX_LFN + 1]; /* Primary file name */
#else
TCHAR fname[13]; /* File name */
#endif
} FILINFO;
/* File function return code (FRESULT) */
typedef enum {
FR_OK = 0, /* (0) Succeeded */
FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */
FR_INT_ERR, /* (2) Assertion failed */
FR_NOT_READY, /* (3) The physical drive cannot work */
FR_NO_FILE, /* (4) Could not find the file */
FR_NO_PATH, /* (5) Could not find the path */
FR_INVALID_NAME, /* (6) The path name format is invalid */
FR_DENIED, /* (7) Access denied due to prohibited access or directory full */
FR_EXIST, /* (8) Access denied due to prohibited access */
FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */
FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */
FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */
FR_NOT_ENABLED, /* (12) The volume has no work area */
FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */
FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any problem */
FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */
FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */
FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */
FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > _FS_LOCK */
FR_INVALID_PARAMETER /* (19) Given parameter is invalid */
} FRESULT;
/*--------------------------------------------------------------*/
/* FatFs module application interface */
FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode); /* Open or create a file */
FRESULT f_close (FIL* fp); /* Close an open file object */
FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br); /* Read data from the file */
FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw); /* Write data to the file */
FRESULT f_lseek (FIL* fp, FSIZE_t ofs); /* Move file pointer of the file object */
FRESULT f_truncate (FIL* fp); /* Truncate the file */
FRESULT f_sync (FIL* fp); /* Flush cached data of the writing file */
FRESULT f_opendir (DIR* dp, const TCHAR* path); /* Open a directory */
FRESULT f_closedir (DIR* dp); /* Close an open directory */
FRESULT f_readdir (DIR* dp, FILINFO* fno); /* Read a directory item */
FRESULT f_findfirst (DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern); /* Find first file */
FRESULT f_findnext (DIR* dp, FILINFO* fno); /* Find next file */
FRESULT f_mkdir (const TCHAR* path); /* Create a sub directory */
FRESULT f_unlink (const TCHAR* path); /* Delete an existing file or directory */
FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new); /* Rename/Move a file or directory */
FRESULT f_stat (const TCHAR* path, FILINFO* fno); /* Get file status */
FRESULT f_chmod (const TCHAR* path, BYTE attr, BYTE mask); /* Change attribute of a file/dir */
FRESULT f_utime (const TCHAR* path, const FILINFO* fno); /* Change timestamp of a file/dir */
FRESULT f_chdir (const TCHAR* path); /* Change current directory */
FRESULT f_chdrive (const TCHAR* path); /* Change current drive */
FRESULT f_getcwd (TCHAR* buff, UINT len); /* Get current directory */
FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs); /* Get number of free clusters on the drive */
FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn); /* Get volume label */
FRESULT f_setlabel (const TCHAR* label); /* Set volume label */
FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf); /* Forward data to the stream */
FRESULT f_expand (FIL* fp, FSIZE_t szf, BYTE opt); /* Allocate a contiguous block to the file */
FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt); /* Mount/Unmount a logical drive */
FRESULT f_mkfs (const TCHAR* path, BYTE opt, DWORD au, void* work, UINT len); /* Create a FAT volume */
FRESULT f_fdisk (BYTE pdrv, const DWORD* szt, void* work); /* Divide a physical drive into some partitions */
int f_putc (TCHAR c, FIL* fp); /* Put a character to the file */
int f_puts (const TCHAR* str, FIL* cp); /* Put a string to the file */
int f_printf (FIL* fp, const TCHAR* str, ...); /* Put a formatted string to the file */
TCHAR* f_gets (TCHAR* buff, int len, FIL* fp); /* Get a string from the file */
#define f_eof(fp) ((int)((fp)->fptr == (fp)->obj.objsize))
#define f_error(fp) ((fp)->err)
#define f_tell(fp) ((fp)->fptr)
#define f_size(fp) ((fp)->obj.objsize)
#define f_rewind(fp) f_lseek((fp), 0)
#define f_rewinddir(dp) f_readdir((dp), 0)
#define f_rmdir(path) f_unlink(path)
#define f_unmount(path) f_mount(0, path, 0)
#ifndef EOF
#define EOF (-1)
#endif
/*--------------------------------------------------------------*/
/* Additional user defined functions */
/* RTC function */
#if !_FS_READONLY && !_FS_NORTC
DWORD get_fattime (void);
#endif
/* Unicode support functions */
#if _USE_LFN != 0 /* Unicode - OEM code conversion */
WCHAR ff_convert (WCHAR chr, UINT dir); /* OEM-Unicode bidirectional conversion */
WCHAR ff_wtoupper (WCHAR chr); /* Unicode upper-case conversion */
#if _USE_LFN == 3 /* Memory functions */
void* ff_memalloc (UINT msize); /* Allocate memory block */
void ff_memfree (void* mblock); /* Free memory block */
#endif
#endif
/* Sync functions */
#if _FS_REENTRANT
int ff_cre_syncobj (BYTE vol, _SYNC_t* sobj); /* Create a sync object */
int ff_req_grant (_SYNC_t sobj); /* Lock sync object */
void ff_rel_grant (_SYNC_t sobj); /* Unlock sync object */
int ff_del_syncobj (_SYNC_t sobj); /* Delete a sync object */
#endif
/*--------------------------------------------------------------*/
/* Flags and offset address */
/* File access mode and open method flags (3rd argument of f_open) */
#define FA_READ 0x01
#define FA_WRITE 0x02
#define FA_OPEN_EXISTING 0x00
#define FA_CREATE_NEW 0x04
#define FA_CREATE_ALWAYS 0x08
#define FA_OPEN_ALWAYS 0x10
#define FA_OPEN_APPEND 0x30
/* Fast seek controls (2nd argument of f_lseek) */
#define CREATE_LINKMAP ((FSIZE_t)0 - 1)
/* Format options (2nd argument of f_mkfs) */
#define FM_FAT 0x01
#define FM_FAT32 0x02
#define FM_EXFAT 0x04
#define FM_ANY 0x07
#define FM_SFD 0x08
/* Filesystem type (FATFS.fs_type) */
#define FS_FAT12 1
#define FS_FAT16 2
#define FS_FAT32 3
#define FS_EXFAT 4
/* File attribute bits for directory entry (FILINFO.fattrib) */
#define AM_RDO 0x01 /* Read only */
#define AM_HID 0x02 /* Hidden */
#define AM_SYS 0x04 /* System */
#define AM_DIR 0x10 /* Directory */
#define AM_ARC 0x20 /* Archive */
#ifdef __cplusplus
}
#endif
#endif /* _FATFS */
component/xc6xx_drivers/Drivers/USB/FatFS/inc/ff_gen_drv.h
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/**
******************************************************************************
* @file ff_gen_drv.h
* @author MCD Application Team
* @brief Header for ff_gen_drv.c module.
*****************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics. All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
**/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __FF_GEN_DRV_H
#define __FF_GEN_DRV_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "diskio.h"
#include "ff.h"
#include "stdint.h"
/* Exported types ------------------------------------------------------------*/
/**
* @brief Disk IO Driver structure definition
*/
typedef struct
{
DSTATUS (*disk_initialize) (BYTE); /*!< Initialize Disk Drive */
DSTATUS (*disk_status) (BYTE); /*!< Get Disk Status */
DRESULT (*disk_read) (BYTE, BYTE*, DWORD, UINT); /*!< Read Sector(s) */
#if _USE_WRITE == 1
DRESULT (*disk_write) (BYTE, const BYTE*, DWORD, UINT); /*!< Write Sector(s) when _USE_WRITE = 0 */
#endif /* _USE_WRITE == 1 */
#if _USE_IOCTL == 1
DRESULT (*disk_ioctl) (BYTE, BYTE, void*); /*!< I/O control operation when _USE_IOCTL = 1 */
#endif /* _USE_IOCTL == 1 */
}Diskio_drvTypeDef;
/**
* @brief Global Disk IO Drivers structure definition
*/
typedef struct
{
uint8_t is_initialized[_VOLUMES];
const Diskio_drvTypeDef *drv[_VOLUMES];
uint8_t lun[_VOLUMES];
volatile uint8_t nbr;
}Disk_drvTypeDef;
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
uint8_t FATFS_LinkDriver(const Diskio_drvTypeDef *drv, char *path);
uint8_t FATFS_UnLinkDriver(char *path);
uint8_t FATFS_LinkDriverEx(const Diskio_drvTypeDef *drv, char *path, BYTE lun);
uint8_t FATFS_UnLinkDriverEx(char *path, BYTE lun);
uint8_t FATFS_GetAttachedDriversNbr(void);
#ifdef __cplusplus
}
#endif
#endif /* __FF_GEN_DRV_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
component/xc6xx_drivers/Drivers/USB/FatFS/inc/ffconf.h
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/* USER CODE BEGIN Header */
/**
******************************************************************************
* FatFs - Generic FAT file system module R0.12c (C)ChaN, 2017
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
#ifndef _FFCONF
#define _FFCONF 68300 /* Revision ID */
/*-----------------------------------------------------------------------------/
/ Additional user header to be used
/-----------------------------------------------------------------------------*/
//#include "main.h"
//#include "stm32f4xx_hal.h"
/*-----------------------------------------------------------------------------/
/ Function Configurations
/-----------------------------------------------------------------------------*/
#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */
/* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
/ Read-only configuration removes writing API functions, f_write(), f_sync(),
/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree()
/ and optional writing functions as well. */
#define _FS_MINIMIZE 0 /* 0 to 3 */
/* This option defines minimization level to remove some basic API functions.
/
/ 0: All basic functions are enabled.
/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename()
/ are removed.
/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
/ 3: f_lseek() function is removed in addition to 2. */
#define _USE_STRFUNC 2 /* 0:Disable or 1-2:Enable */
/* This option switches string functions, f_gets(), f_putc(), f_puts() and
/ f_printf().
/
/ 0: Disable string functions.
/ 1: Enable without LF-CRLF conversion.
/ 2: Enable with LF-CRLF conversion. */
#define _USE_FIND 0
/* This option switches filtered directory read functions, f_findfirst() and
/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */
#define _USE_MKFS 1
/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
#define _USE_FASTSEEK 1
/* This option switches fast seek feature. (0:Disable or 1:Enable) */
#define _USE_EXPAND 0
/* This option switches f_expand function. (0:Disable or 1:Enable) */
#define _USE_CHMOD 0
/* This option switches attribute manipulation functions, f_chmod() and f_utime().
/ (0:Disable or 1:Enable) Also _FS_READONLY needs to be 0 to enable this option. */
#define _USE_LABEL 1
/* This option switches volume label functions, f_getlabel() and f_setlabel().
/ (0:Disable or 1:Enable) */
#define _USE_FORWARD 0
/* This option switches f_forward() function. (0:Disable or 1:Enable) */
/*-----------------------------------------------------------------------------/
/ Locale and Namespace Configurations
/-----------------------------------------------------------------------------*/
#define _CODE_PAGE 437//850
/* This option specifies the OEM code page to be used on the target system.
/ Incorrect setting of the code page can cause a file open failure.
/
/ 1 - ASCII (No extended character. Non-LFN cfg. only)
/ 437 - U.S.
/ 720 - Arabic
/ 737 - Greek
/ 771 - KBL
/ 775 - Baltic
/ 850 - Latin 1
/ 852 - Latin 2
/ 855 - Cyrillic
/ 857 - Turkish
/ 860 - Portuguese
/ 861 - Icelandic
/ 862 - Hebrew
/ 863 - Canadian French
/ 864 - Arabic
/ 865 - Nordic
/ 866 - Russian
/ 869 - Greek 2
/ 932 - Japanese (DBCS)
/ 936 - Simplified Chinese (DBCS)
/ 949 - Korean (DBCS)
/ 950 - Traditional Chinese (DBCS)
*/
#define _USE_LFN 0 /* 0 to 3 */
#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */
/* The _USE_LFN switches the support of long file name (LFN).
/
/ 0: Disable support of LFN. _MAX_LFN has no effect.
/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
/ 2: Enable LFN with dynamic working buffer on the STACK.
/ 3: Enable LFN with dynamic working buffer on the HEAP.
/
/ To enable the LFN, Unicode handling functions (option/unicode.c) must be added
/ to the project. The working buffer occupies (_MAX_LFN + 1) * 2 bytes and
/ additional 608 bytes at exFAT enabled. _MAX_LFN can be in range from 12 to 255.
/ It should be set 255 to support full featured LFN operations.
/ When use stack for the working buffer, take care on stack overflow. When use heap
/ memory for the working buffer, memory management functions, ff_memalloc() and
/ ff_memfree(), must be added to the project. */
#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */
/* This option switches character encoding on the API. (0:ANSI/OEM or 1:UTF-16)
/ To use Unicode string for the path name, enable LFN and set _LFN_UNICODE = 1.
/ This option also affects behavior of string I/O functions. */
#define _STRF_ENCODE 3
/* When _LFN_UNICODE == 1, this option selects the character encoding ON THE FILE to
/ be read/written via string I/O functions, f_gets(), f_putc(), f_puts and f_printf().
/
/ 0: ANSI/OEM
/ 1: UTF-16LE
/ 2: UTF-16BE
/ 3: UTF-8
/
/ This option has no effect when _LFN_UNICODE == 0. */
#define _FS_RPATH 0 /* 0 to 2 */
/* This option configures support of relative path.
/
/ 0: Disable relative path and remove related functions.
/ 1: Enable relative path. f_chdir() and f_chdrive() are available.
/ 2: f_getcwd() function is available in addition to 1.
*/
/*---------------------------------------------------------------------------/
/ Drive/Volume Configurations
/----------------------------------------------------------------------------*/
#define _VOLUMES 1
/* Number of volumes (logical drives) to be used. */
/* USER CODE BEGIN Volumes */
#define _STR_VOLUME_ID 0 /* 0:Use only 0-9 for drive ID, 1:Use strings for drive ID */
#define _VOLUME_STRS "RAM","NAND","CF","SD1","SD2","USB1","USB2","USB3"
/* _STR_VOLUME_ID switches string support of volume ID.
/ When _STR_VOLUME_ID is set to 1, also pre-defined strings can be used as drive
/ number in the path name. _VOLUME_STRS defines the drive ID strings for each
/ logical drives. Number of items must be equal to _VOLUMES. Valid characters for
/ the drive ID strings are: A-Z and 0-9. */
/* USER CODE END Volumes */
#define _MULTI_PARTITION 0 /* 0:Single partition, 1:Multiple partition */
/* This option switches support of multi-partition on a physical drive.
/ By default (0), each logical drive number is bound to the same physical drive
/ number and only an FAT volume found on the physical drive will be mounted.
/ When multi-partition is enabled (1), each logical drive number can be bound to
/ arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk()
/ function will be available. */
#define _MIN_SS 512 /* 512, 1024, 2048 or 4096 */
#define _MAX_SS 512//4096 /* 512, 1024, 2048 or 4096 */
/* These options configure the range of sector size to be supported. (512, 1024,
/ 2048 or 4096) Always set both 512 for most systems, all type of memory cards and
/ harddisk. But a larger value may be required for on-board flash memory and some
/ type of optical media. When _MAX_SS is larger than _MIN_SS, FatFs is configured
/ to variable sector size and GET_SECTOR_SIZE command must be implemented to the
/ disk_ioctl() function. */
#define _USE_TRIM 0
/* This option switches support of ATA-TRIM. (0:Disable or 1:Enable)
/ To enable Trim function, also CTRL_TRIM command should be implemented to the
/ disk_ioctl() function. */
#define _FS_NOFSINFO 0 /* 0,1,2 or 3 */
/* If you need to know correct free space on the FAT32 volume, set bit 0 of this
/ option, and f_getfree() function at first time after volume mount will force
/ a full FAT scan. Bit 1 controls the use of last allocated cluster number.
/
/ bit0=0: Use free cluster count in the FSINFO if available.
/ bit0=1: Do not trust free cluster count in the FSINFO.
/ bit1=0: Use last allocated cluster number in the FSINFO if available.
/ bit1=1: Do not trust last allocated cluster number in the FSINFO.
*/
/*---------------------------------------------------------------------------/
/ System Configurations
/----------------------------------------------------------------------------*/
#define _FS_TINY 0 /* 0:Normal or 1:Tiny */
/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
/ At the tiny configuration, size of file object (FIL) is reduced _MAX_SS bytes.
/ Instead of private sector buffer eliminated from the file object, common sector
/ buffer in the file system object (FATFS) is used for the file data transfer. */
#define _FS_EXFAT 0
/* This option switches support of exFAT file system. (0:Disable or 1:Enable)
/ When enable exFAT, also LFN needs to be enabled. (_USE_LFN >= 1)
/ Note that enabling exFAT discards C89 compatibility. */
#define _FS_NORTC 0
#define _NORTC_MON 6
#define _NORTC_MDAY 4
#define _NORTC_YEAR 2015
/* The option _FS_NORTC switches timestamp functiton. If the system does not have
/ any RTC function or valid timestamp is not needed, set _FS_NORTC = 1 to disable
/ the timestamp function. All objects modified by FatFs will have a fixed timestamp
/ defined by _NORTC_MON, _NORTC_MDAY and _NORTC_YEAR in local time.
/ To enable timestamp function (_FS_NORTC = 0), get_fattime() function need to be
/ added to the project to get current time form real-time clock. _NORTC_MON,
/ _NORTC_MDAY and _NORTC_YEAR have no effect.
/ These options have no effect at read-only configuration (_FS_READONLY = 1). */
#define _FS_LOCK 2 /* 0:Disable or >=1:Enable */
/* The option _FS_LOCK switches file lock function to control duplicated file open
/ and illegal operation to open objects. This option must be 0 when _FS_READONLY
/ is 1.
/
/ 0: Disable file lock function. To avoid volume corruption, application program
/ should avoid illegal open, remove and rename to the open objects.
/ >0: Enable file lock function. The value defines how many files/sub-directories
/ can be opened simultaneously under file lock control. Note that the file
/ lock control is independent of re-entrancy. */
#define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */
#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */
#define _SYNC_t NULL
/* The option _FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs
/ module itself. Note that regardless of this option, file access to different
/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs()
/ and f_fdisk() function, are always not re-entrant. Only file/directory access
/ to the same volume is under control of this function.
/
/ 0: Disable re-entrancy. _FS_TIMEOUT and _SYNC_t have no effect.
/ 1: Enable re-entrancy. Also user provided synchronization handlers,
/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj()
/ function, must be added to the project. Samples are available in
/ option/syscall.c.
/
/ The _FS_TIMEOUT defines timeout period in unit of time tick.
/ The _SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*,
/ SemaphoreHandle_t and etc.. A header file for O/S definitions needs to be
/ included somewhere in the scope of ff.h. */
/* define the ff_malloc ff_free macros as standard malloc free */
#if !defined(ff_malloc) && !defined(ff_free)
#include <stdlib.h>
#define ff_malloc malloc
#define ff_free free
#endif
#endif /* _FFCONF */
component/xc6xx_drivers/Drivers/USB/FatFS/inc/integer.h
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/*-------------------------------------------*/
/* Integer type definitions for FatFs module */
/*-------------------------------------------*/
#ifndef _FF_INTEGER
#define _FF_INTEGER
#ifdef _WIN32 /* FatFs development platform */
#include <windows.h>
#include <tchar.h>
typedef unsigned __int64 QWORD;
#else /* Embedded platform */
/* These types MUST be 16-bit or 32-bit */
typedef int INT;
typedef unsigned int UINT;
/* This type MUST be 8-bit */
typedef unsigned char BYTE;
/* These types MUST be 16-bit */
typedef short SHORT;
typedef unsigned short WORD;
typedef unsigned short WCHAR;
/* These types MUST be 32-bit */
typedef long LONG;
typedef unsigned long DWORD;
/* This type MUST be 64-bit (Remove this for ANSI C (C89) compatibility) */
typedef unsigned long long QWORD;
#endif
#endif
component/xc6xx_drivers/Drivers/USB/FatFS/src/diskio.c
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/*!
* \file diskio.c
*
* \brief Target disk I/O implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "diskio.h"
#include "ff_gen_drv.h"
#include "usbd_msc_flash.h"
#include "time_conv.h"
/*------------------------------------------------------------------------------------
Macros
------------------------------------------- -----------------------------------------*/
#if defined ( __GNUC__ )
#ifndef __weak
#define __weak __attribute__((weak))
#endif
#endif
#define DEV_USB 0 /* Example: Map USB MSD to physical drive 0 */
/*------------------------------------------------------------------------------------
Global Variables
------------------------------------------- -----------------------------------------*/
extern Disk_drvTypeDef disk;
/*------------------------------------------------------------------------------------
Functions
------------------------------------------- -----------------------------------------*/
/**
* @brief Gets Disk Status
* @param pdrv: Physical drive number (0..)
* @retval DSTATUS: Operation status
*/
DSTATUS disk_status (
BYTE pdrv /* Physical drive number to identify the drive */
)
{
DSTATUS stat = STA_NOINIT;
// stat = disk.drv[pdrv]->disk_status(disk.lun[pdrv]);
if( FAT_FLASH_ID == Fat_Flash_ReadID( ) )
{
stat = RES_OK;
}
else
{
stat = STA_NOINIT;
}
return stat;
}
/**
* @brief Initializes a Drive
* @param pdrv: Physical drive number (0..)
* @retval DSTATUS: Operation status
*/
DSTATUS disk_initialize (
BYTE pdrv /* Physical drive nmuber to identify the drive */
)
{
DSTATUS stat = STA_NOINIT;
switch(pdrv)
{
case DEV_USB:
{
if( true == Disk_Init() )
stat = RES_OK;
}
break;
}
// if(disk.is_initialized[pdrv] == 0)
// {
// disk.is_initialized[pdrv] = 1;
// stat = disk.drv[pdrv]->disk_initialize(disk.lun[pdrv]);
// }
return stat;
}
/**
* @brief Reads Sector(s)
* @param pdrv: Physical drive number (0..)
* @param *buff: Data buffer to store read data
* @param sector: Sector address (LBA)
* @param count: Number of sectors to read (1..128)
* @retval DRESULT: Operation result
*/
DRESULT disk_read (
BYTE pdrv, /* Physical drive nmuber to identify the drive */
BYTE *buff, /* Data buffer to store read data */
DWORD sector, /* Sector address in LBA */
UINT count /* Number of sectors to read */
)
{
DRESULT res = RES_ERROR;
switch (pdrv)
{
case DEV_USB:
{
if( Disk_UnitRead(sector, count, buff) == true )
{
res = RES_OK;
}
}
break;
}
// res = disk.drv[pdrv]->disk_read(disk.lun[pdrv], buff, sector, count);
return res;
}
/**
* @brief Writes Sector(s)
* @param pdrv: Physical drive number (0..)
* @param *buff: Data to be written
* @param sector: Sector address (LBA)
* @param count: Number of sectors to write (1..128)
* @retval DRESULT: Operation result
*/
#if _USE_WRITE == 1
DRESULT disk_write (
BYTE pdrv, /* Physical drive nmuber to identify the drive */
const BYTE *buff, /* Data to be written */
DWORD sector, /* Sector address in LBA */
UINT count /* Number of sectors to write */
)
{
DRESULT res = RES_ERROR;
switch(pdrv)
{
case DEV_USB:
{
if( Disk_UnitWrite(sector, count, (uint8_t *)buff) == true )
{
res = RES_OK;
}
}
break;
}
// res = disk.drv[pdrv]->disk_write(disk.lun[pdrv], buff, sector, count);
return res;
}
#endif /* _USE_WRITE == 1 */
/**
* @brief I/O control operation
* @param pdrv: Physical drive number (0..)
* @param cmd: Control code
* @param *buff: Buffer to send/receive control data
* @retval DRESULT: Operation result
*/
#if _USE_IOCTL == 1
DRESULT disk_ioctl (
BYTE pdrv, /* Physical drive nmuber (0..) */
BYTE cmd, /* Control code */
void *buff /* Buffer to send/receive control data */
)
{
DRESULT res = RES_PARERR;
switch(pdrv)
{
case DEV_USB:
{
switch(cmd)
{
case CTRL_SYNC:
res = RES_OK;
break;
case GET_SECTOR_COUNT:
{
*(DWORD *)buff = Disk_UnitCount( );
res = RES_OK;
break;
}
case GET_SECTOR_SIZE:
{
*(DWORD *)buff = Disk_UnitSize( );
res = RES_OK;
break;
}
case GET_BLOCK_SIZE:
{
*(DWORD *)buff = 1;
res = RES_OK;
break;
}
default:
res = RES_PARERR;
break;
}
}
break;
}
// res = disk.drv[pdrv]->disk_ioctl(disk.lun[pdrv], cmd, buff);
return res;
}
#endif /* _USE_IOCTL == 1 */
/**
* @brief Gets Time from RTC
* @param None
* @retval Time in DWORD
*/
__weak DWORD get_fattime (void)
{
uint32_t fattime;
// utc sec convert to utc date
DateTime_t tmp_date = UTC_SecToDate(Utc_TotalSec);
tmp_date = UTC_DateToZoneDate(TIME_ZONE, YEAR_BASE, tmp_date.year, tmp_date.month,
tmp_date.day, tmp_date.hour, tmp_date.min,
tmp_date.sec, tmp_date.week);
fattime = ((YEAR_BASE + tmp_date.year - 1980) << 25) | (tmp_date.month << 21) |
(tmp_date.day << 16) | (tmp_date.hour <<11) | (tmp_date.min << 5) |
(tmp_date.sec >> 1);
return fattime;
}
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
component/xc6xx_drivers/Drivers/USB/FatFS/src/fatfs.c
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/*!
* \file fatfs.c
*
* \brief Target FatFS implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "fatfs.h"
#include "xc6xxx.h"
/*------------------------------------------------------------------------------------
Local Variables
-------------------------------------------------------------------------------------*/
char Path[4]; /* Logical drive path */
FATFS FatFS; /* File system object for Logical drive */
FIL File; /* File object */
DIR Dir;
uint8_t buffer[_MAX_SS];
/*------------------------------------------------------------------------------------
Functions
------------------------------------------------------------------------------------*/
/**
* @brief FatFS Initalization
* @param void
* @retval void
*/
void FATFS_Init(void)
{
FRESULT res;
DEBUG("FatFS Init\r\n");
res = f_mount(&FatFS, "0:", 1);
DEBUG("Mount FRESULT: %d\r\n", res);
res = f_opendir(&Dir, "0:");
DEBUG("Read Dir: %d\r\n", res);
if (FR_NO_FILESYSTEM == res) {
res = f_mkfs("0:", FM_FAT, _MAX_SS, buffer, sizeof(buffer));
DEBUG("Format FRESULT: %d\r\n", res);
res = f_unmount("0:");
DEBUG("Umount FRESULT: %d\r\n", res);
// res = f_setlabel( "XinChip" );
// DEBUG("Set label: %d\r\n", res);
res = f_mount(&FatFS, "0:", 1);
DEBUG("Remount FRESULT: %d\r\n", res);
res = f_unmount("0:");
DEBUG("Umount FRESULT: %d\r\n", res);
} else {
res = f_unmount("0:");
DEBUG("Umount FRESULT: %d\r\n", res);
}
}
component/xc6xx_drivers/Drivers/USB/FatFS/src/ff.c
+6142
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File diff suppressed because it is too large Load Diff
component/xc6xx_drivers/Drivers/USB/FatFS/src/ff_gen_drv.c
+122
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@@ -0,0 +1,122 @@
/**
******************************************************************************
* @file ff_gen_drv.c
* @author MCD Application Team
* @brief FatFs generic low level driver.
*****************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics. All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
**/
/* Includes ------------------------------------------------------------------*/
#include "ff_gen_drv.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
Disk_drvTypeDef disk = {{0},{0},{0},0};
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/**
* @brief Links a compatible diskio driver/lun id and increments the number of active
* linked drivers.
* @note The number of linked drivers (volumes) is up to 10 due to FatFs limits.
* @param drv: pointer to the disk IO Driver structure
* @param path: pointer to the logical drive path
* @param lun : only used for USB Key Disk to add multi-lun management
else the parameter must be equal to 0
* @retval Returns 0 in case of success, otherwise 1.
*/
uint8_t FATFS_LinkDriverEx(const Diskio_drvTypeDef *drv, char *path, uint8_t lun)
{
uint8_t ret = 1;
uint8_t DiskNum = 0;
if(disk.nbr < _VOLUMES)
{
disk.is_initialized[disk.nbr] = 0;
disk.drv[disk.nbr] = drv;
disk.lun[disk.nbr] = lun;
DiskNum = disk.nbr++;
path[0] = DiskNum + '0';
path[1] = ':';
path[2] = '/';
path[3] = 0;
ret = 0;
}
return ret;
}
/**
* @brief Links a compatible diskio driver and increments the number of active
* linked drivers.
* @note The number of linked drivers (volumes) is up to 10 due to FatFs limits
* @param drv: pointer to the disk IO Driver structure
* @param path: pointer to the logical drive path
* @retval Returns 0 in case of success, otherwise 1.
*/
uint8_t FATFS_LinkDriver(const Diskio_drvTypeDef *drv, char *path)
{
return FATFS_LinkDriverEx(drv, path, 0);
}
/**
* @brief Unlinks a diskio driver and decrements the number of active linked
* drivers.
* @param path: pointer to the logical drive path
* @param lun : not used
* @retval Returns 0 in case of success, otherwise 1.
*/
uint8_t FATFS_UnLinkDriverEx(char *path, uint8_t lun)
{
uint8_t DiskNum = 0;
uint8_t ret = 1;
if(disk.nbr >= 1)
{
DiskNum = path[0] - '0';
if(disk.drv[DiskNum] != 0)
{
disk.drv[DiskNum] = 0;
disk.lun[DiskNum] = 0;
disk.nbr--;
ret = 0;
}
}
return ret;
}
/**
* @brief Unlinks a diskio driver and decrements the number of active linked
* drivers.
* @param path: pointer to the logical drive path
* @retval Returns 0 in case of success, otherwise 1.
*/
uint8_t FATFS_UnLinkDriver(char *path)
{
return FATFS_UnLinkDriverEx(path, 0);
}
/**
* @brief Gets number of linked drivers to the FatFs module.
* @param None
* @retval Number of attached drivers.
*/
uint8_t FATFS_GetAttachedDriversNbr(void)
{
return disk.nbr;
}
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
component/xc6xx_drivers/Drivers/USB/Middlewares/Library/Class/CDC/Inc/usbd_cdc.h
+183
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@@ -0,0 +1,183 @@
/*!
* \file usbd_cdc.h
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author MCD Application Team
*
* \author ( XinChip ) Alex-J
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USB_CDC_H
#define __USB_CDC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "usbd_ioreq.h"
/** @defgroup usbd_cdc
* @brief This file is the Header file for usbd_cdc.c
* @{
*/
/** @defgroup usbd_cdc_Exported_Defines
* @{
*/
#ifndef CDC_IN_EP
#define CDC_IN_EP 0x81U /* EP1 for data IN */
#endif /* CDC_IN_EP */
#ifndef CDC_OUT_EP
#define CDC_OUT_EP 0x01U /* EP1 for data OUT */
#endif /* CDC_OUT_EP */
#ifndef CDC_CMD_EP
#define CDC_CMD_EP 0x82U /* EP2 for CDC commands */
#endif /* CDC_CMD_EP */
#define SECOND_CDC_OUT_EP 0x03U /* EP3 for CDC data OUT */
#define SECOND_CDC_IN_EP 0x83U /* EP3 for CDC data IN */
#define SECOND_CDC_CMD_EP 0x84U /* EP4 for CDC commands */
#ifndef CDC_HS_BINTERVAL
#define CDC_HS_BINTERVAL 0x10U
#endif /* CDC_HS_BINTERVAL */
#ifndef CDC_FS_BINTERVAL
#define CDC_FS_BINTERVAL 0x10U
#endif /* CDC_FS_BINTERVAL */
/* CDC Endpoints parameters: you can fine tune these values depending on the needed baudrates and performance. */
#define CDC_DATA_HS_MAX_PACKET_SIZE 512U /* Endpoint IN & OUT Packet size */
#define CDC_DATA_FS_MAX_PACKET_SIZE 64U /* Endpoint IN & OUT Packet size */
#define CDC_CMD_PACKET_SIZE 8U /* Control Endpoint Packet size */
#define USB_CDC_CONFIG_DESC_SIZ 67U
#define CDC_DATA_HS_IN_PACKET_SIZE CDC_DATA_HS_MAX_PACKET_SIZE
#define CDC_DATA_HS_OUT_PACKET_SIZE CDC_DATA_HS_MAX_PACKET_SIZE
#define CDC_DATA_FS_IN_PACKET_SIZE CDC_DATA_FS_MAX_PACKET_SIZE
#define CDC_DATA_FS_OUT_PACKET_SIZE CDC_DATA_FS_MAX_PACKET_SIZE
#define CDC_REQ_MAX_DATA_SIZE 0x7U
/*---------------------------------------------------------------------*/
/* CDC definitions */
/*---------------------------------------------------------------------*/
#define CDC_SEND_ENCAPSULATED_COMMAND 0x00U
#define CDC_GET_ENCAPSULATED_RESPONSE 0x01U
#define CDC_SET_COMM_FEATURE 0x02U
#define CDC_GET_COMM_FEATURE 0x03U
#define CDC_CLEAR_COMM_FEATURE 0x04U
#define CDC_SET_LINE_CODING 0x20U
#define CDC_GET_LINE_CODING 0x21U
#define CDC_SET_CONTROL_LINE_STATE 0x22U
#define CDC_SEND_BREAK 0x23U
/**
* @}
*/
/** @defgroup USBD_CORE_Exported_TypesDefinitions
* @{
*/
/**
* @}
*/
typedef struct
{
uint32_t bitrate;
uint8_t format;
uint8_t paritytype;
uint8_t datatype;
} USBD_CDC_LineCodingTypeDef;
typedef struct _USBD_CDC_Itf
{
int8_t (* Init)(void);
int8_t (* DeInit)(void);
int8_t (* Control)(uint8_t cmd, uint8_t *pbuf, uint16_t length);
int8_t (* Receive)(uint8_t *Buf, uint32_t *Len);
int8_t (* TransmitCplt)(uint8_t *Buf, uint32_t *Len, uint8_t epnum);
} USBD_CDC_ItfTypeDef;
typedef struct
{
uint32_t data[CDC_DATA_FS_MAX_PACKET_SIZE / 4U]; /* Force 32-bit alignment */
uint8_t CmdOpCode;
uint8_t CmdLength;
uint8_t *RxBuffer;
uint8_t *TxBuffer;
uint32_t RxLength;
uint32_t TxLength;
__IO uint32_t TxState;
__IO uint32_t RxState;
} USBD_CDC_HandleTypeDef;
/** @defgroup USBD_CORE_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup USBD_CORE_Exported_Variables
* @{
*/
extern USBD_ClassTypeDef USBD_CDC;
#define USBD_CDC_CLASS &USBD_CDC
/**
* @}
*/
/** @defgroup USB_CORE_Exported_Functions
* @{
*/
uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev,
USBD_CDC_ItfTypeDef *fops);
uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff,
uint32_t length);
uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff);
uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev);
uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __USB_CDC_H */
/**
* @}
*/
/**
* @}
*/
component/xc6xx_drivers/Drivers/USB/Middlewares/Library/Class/CDC/Src/usbd_cdc.c
+877
View File
@@ -0,0 +1,877 @@
/*!
* \file usbd_cdc.c
*
* \brief This file provides the high layer firmware functions to manage the
* following functionalities of the USB CDC Class:
* - Initialization and Configuration of high and low layer
* - Enumeration as CDC Device (and enumeration for each implemented
* memory interface)
* - OUT/IN data transfer
* - Command IN transfer (class requests management)
* - Error management
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author MCD Application Team
*
* \author ( XinChip ) Alex-J
*
******************************************************************************
* @verbatim
*
* ===================================================================
* CDC Class Driver Description
* ===================================================================
* This driver manages the "Universal Serial Bus Class Definitions for Communications Devices
* Revision 1.2 November 16, 2007" and the sub-protocol specification of "Universal Serial Bus
* Communications Class Subclass Specification for PSTN Devices Revision 1.2 February 9, 2007"
* This driver implements the following aspects of the specification:
* - Device descriptor management
* - Configuration descriptor management
* - Enumeration as CDC device with 2 data endpoints (IN and OUT) and 1 command endpoint (IN)
* - Requests management (as described in section 6.2 in specification)
* - Abstract Control Model compliant
* - Union Functional collection (using 1 IN endpoint for control)
* - Data interface class
*
* These aspects may be enriched or modified for a specific user application.
*
* This driver doesn't implement the following aspects of the specification
* (but it is possible to manage these features with some modifications on this driver):
* - Any class-specific aspect relative to communication classes should be managed by user application.
* - All communication classes other than PSTN are not managed
*
* @endverbatim
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "usbd_cdc.h"
#include "usbd_ctlreq.h"
/** @defgroup USBD_CDC
* @brief usbd core module
* @{
*/
/** @defgroup USBD_CDC_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup USBD_CDC_Private_Defines
* @{
*/
/**
* @}
*/
/** @defgroup USBD_CDC_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup USBD_CDC_Private_FunctionPrototypes
* @{
*/
static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum);
static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum);
static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev);
#ifndef USE_USBD_COMPOSITE
static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length);
static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length);
static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length);
uint8_t *USBD_CDC_GetDeviceQualifierDescriptor(uint16_t *length);
#endif /* USE_USBD_COMPOSITE */
#ifndef USE_USBD_COMPOSITE
/* USB Standard Device Descriptor */
__ALIGN_BEGIN static uint8_t USBD_CDC_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END =
{
USB_LEN_DEV_QUALIFIER_DESC,
USB_DESC_TYPE_DEVICE_QUALIFIER,
0x00,
0x02,
0x00,
0x00,
0x00,
0x40,
0x01,
0x00,
};
#endif /* USE_USBD_COMPOSITE */
/**
* @}
*/
/** @defgroup USBD_CDC_Private_Variables
* @{
*/
/* CDC interface class callbacks structure */
USBD_ClassTypeDef USBD_CDC =
{
USBD_CDC_Init,
USBD_CDC_DeInit,
USBD_CDC_Setup,
NULL, /* EP0_TxSent */
USBD_CDC_EP0_RxReady,
USBD_CDC_DataIn,
USBD_CDC_DataOut,
NULL,
NULL,
NULL,
#ifdef USE_USBD_COMPOSITE
NULL,
NULL,
NULL,
NULL,
#else
USBD_CDC_GetHSCfgDesc,
USBD_CDC_GetFSCfgDesc,
USBD_CDC_GetOtherSpeedCfgDesc,
USBD_CDC_GetDeviceQualifierDescriptor,
#endif /* USE_USBD_COMPOSITE */
};
#ifndef USE_USBD_COMPOSITE
/* USB CDC device Configuration Descriptor */
__ALIGN_BEGIN static uint8_t USBD_CDC_CfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END =
{
/* Configuration Descriptor */
0x09, /* bLength: Configuration Descriptor size */
USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */
USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength */
0x00,
0x02, /* bNumInterfaces: 2 interfaces */
0x01, /* bConfigurationValue: Configuration value */
0x00, /* iConfiguration: Index of string descriptor
describing the configuration */
#if (USBD_SELF_POWERED == 1U)
0xE0, /* bmAttributes: Bus Powered according to user configuration */
#else
0xA0, /* bmAttributes: Bus Powered according to user configuration */
#endif /* USBD_SELF_POWERED */
USBD_MAX_POWER, /* MaxPower (mA) */
/*---------------------------------------------------------------------------*/
/* Interface Descriptor */
0x09, /* bLength: Interface Descriptor size */
USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */
/* Interface descriptor type */
0x00, /* bInterfaceNumber: Number of Interface */
0x00, /* bAlternateSetting: Alternate setting */
0x01, /* bNumEndpoints: One endpoint used */
0x02, /* bInterfaceClass: Communication Interface Class */
0x02, /* bInterfaceSubClass: Abstract Control Model */
0x01, /* bInterfaceProtocol: Common AT commands */
0x00, /* iInterface */
/* Header Functional Descriptor */
0x05, /* bLength: Endpoint Descriptor size */
0x24, /* bDescriptorType: CS_INTERFACE */
0x00, /* bDescriptorSubtype: Header Func Desc */
0x10, /* bcdCDC: spec release number */
0x01,
/* Call Management Functional Descriptor */
0x05, /* bFunctionLength */
0x24, /* bDescriptorType: CS_INTERFACE */
0x01, /* bDescriptorSubtype: Call Management Func Desc */
0x00, /* bmCapabilities: D0+D1 */
0x01, /* bDataInterface */
/* ACM Functional Descriptor */
0x04, /* bFunctionLength */
0x24, /* bDescriptorType: CS_INTERFACE */
0x02, /* bDescriptorSubtype: Abstract Control Management desc */
0x02, /* bmCapabilities */
/* Union Functional Descriptor */
0x05, /* bFunctionLength */
0x24, /* bDescriptorType: CS_INTERFACE */
0x06, /* bDescriptorSubtype: Union func desc */
0x00, /* bMasterInterface: Communication class interface */
0x01, /* bSlaveInterface0: Data Class Interface */
/* Endpoint 2 Descriptor */
0x07, /* bLength: Endpoint Descriptor size */
USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */
CDC_CMD_EP, /* bEndpointAddress */
0x03, /* bmAttributes: Interrupt */
LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize */
HIBYTE(CDC_CMD_PACKET_SIZE),
CDC_FS_BINTERVAL, /* bInterval */
/*---------------------------------------------------------------------------*/
/* Data class interface descriptor */
0x09, /* bLength: Endpoint Descriptor size */
USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */
0x01, /* bInterfaceNumber: Number of Interface */
0x00, /* bAlternateSetting: Alternate setting */
0x02, /* bNumEndpoints: Two endpoints used */
0x0A, /* bInterfaceClass: CDC */
0x00, /* bInterfaceSubClass */
0x00, /* bInterfaceProtocol */
0x00, /* iInterface */
/* Endpoint OUT Descriptor */
0x07, /* bLength: Endpoint Descriptor size */
USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */
CDC_OUT_EP, /* bEndpointAddress */
0x02, /* bmAttributes: Bulk */
LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize */
HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE),
0x00, /* bInterval */
/* Endpoint IN Descriptor */
0x07, /* bLength: Endpoint Descriptor size */
USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */
CDC_IN_EP, /* bEndpointAddress */
0x02, /* bmAttributes: Bulk */
LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize */
HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE),
0x00 /* bInterval */
};
#endif /* USE_USBD_COMPOSITE */
static uint8_t CDCInEpAdd = CDC_IN_EP;
static uint8_t CDCOutEpAdd = CDC_OUT_EP;
static uint8_t CDCCmdEpAdd = CDC_CMD_EP;
/**
* @}
*/
/** @defgroup USBD_CDC_Private_Functions
* @{
*/
/**
* @brief USBD_CDC_Init
* Initialize the CDC interface
* @param pdev: device instance
* @param cfgidx: Configuration index
* @retval status
*/
static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
UNUSED(cfgidx);
USBD_CDC_HandleTypeDef *hcdc;
hcdc = (USBD_CDC_HandleTypeDef *)USBD_malloc(sizeof(USBD_CDC_HandleTypeDef));
if (hcdc == NULL)
{
pdev->pClassDataCmsit[pdev->classId] = NULL;
return (uint8_t)USBD_EMEM;
}
(void)USBD_memset(hcdc, 0, sizeof(USBD_CDC_HandleTypeDef));
pdev->pClassDataCmsit[pdev->classId] = (void *)hcdc;
pdev->pClassData = pdev->pClassDataCmsit[pdev->classId];
#ifdef USE_USBD_COMPOSITE
/* Get the Endpoints addresses allocated for this class instance */
CDCInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_BULK);
CDCOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_BULK);
CDCCmdEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR);
#endif /* USE_USBD_COMPOSITE */
if (pdev->dev_speed == USBD_SPEED_HIGH)
{
/* Open EP IN */
(void)USBD_LL_OpenEP(pdev, CDCInEpAdd, USBD_EP_TYPE_BULK,
CDC_DATA_HS_IN_PACKET_SIZE);
pdev->ep_in[CDCInEpAdd & 0xFU].is_used = 1U;
/* Open EP OUT */
(void)USBD_LL_OpenEP(pdev, CDCOutEpAdd, USBD_EP_TYPE_BULK,
CDC_DATA_HS_OUT_PACKET_SIZE);
pdev->ep_out[CDCOutEpAdd & 0xFU].is_used = 1U;
/* Set bInterval for CDC CMD Endpoint */
pdev->ep_in[CDCCmdEpAdd & 0xFU].bInterval = CDC_HS_BINTERVAL;
}
else
{
/* Open EP IN */
(void)USBD_LL_OpenEP(pdev, CDCInEpAdd, USBD_EP_TYPE_BULK,
CDC_DATA_FS_IN_PACKET_SIZE);
pdev->ep_in[CDCInEpAdd & 0xFU].is_used = 1U;
/* Open EP OUT */
(void)USBD_LL_OpenEP(pdev, CDCOutEpAdd, USBD_EP_TYPE_BULK,
CDC_DATA_FS_OUT_PACKET_SIZE);
pdev->ep_out[CDCOutEpAdd & 0xFU].is_used = 1U;
/* Set bInterval for CMD Endpoint */
pdev->ep_in[CDCCmdEpAdd & 0xFU].bInterval = CDC_FS_BINTERVAL;
}
/* Open Command IN EP */
(void)USBD_LL_OpenEP(pdev, CDCCmdEpAdd, USBD_EP_TYPE_INTR, CDC_CMD_PACKET_SIZE);
pdev->ep_in[CDCCmdEpAdd & 0xFU].is_used = 1U;
hcdc->RxBuffer = NULL;
/* Init physical Interface components */
((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Init();
/* Init Xfer states */
hcdc->TxState = 0U;
hcdc->RxState = 0U;
if (hcdc->RxBuffer == NULL)
{
return (uint8_t)USBD_EMEM;
}
if (pdev->dev_speed == USBD_SPEED_HIGH)
{
/* Prepare Out endpoint to receive next packet */
(void)USBD_LL_PrepareReceive(pdev, CDCOutEpAdd, hcdc->RxBuffer,
CDC_DATA_HS_OUT_PACKET_SIZE);
}
else
{
/* Prepare Out endpoint to receive next packet */
(void)USBD_LL_PrepareReceive(pdev, CDCOutEpAdd, hcdc->RxBuffer,
CDC_DATA_FS_OUT_PACKET_SIZE);
}
return (uint8_t)USBD_OK;
}
/**
* @brief USBD_CDC_Init
* DeInitialize the CDC layer
* @param pdev: device instance
* @param cfgidx: Configuration index
* @retval status
*/
static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
UNUSED(cfgidx);
#ifdef USE_USBD_COMPOSITE
/* Get the Endpoints addresses allocated for this CDC class instance */
CDCInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_BULK);
CDCOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_BULK);
CDCCmdEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR);
#endif /* USE_USBD_COMPOSITE */
/* Close EP IN */
(void)USBD_LL_CloseEP(pdev, CDCInEpAdd);
pdev->ep_in[CDCInEpAdd & 0xFU].is_used = 0U;
/* Close EP OUT */
(void)USBD_LL_CloseEP(pdev, CDCOutEpAdd);
pdev->ep_out[CDCOutEpAdd & 0xFU].is_used = 0U;
/* Close Command IN EP */
(void)USBD_LL_CloseEP(pdev, CDCCmdEpAdd);
pdev->ep_in[CDCCmdEpAdd & 0xFU].is_used = 0U;
pdev->ep_in[CDCCmdEpAdd & 0xFU].bInterval = 0U;
/* DeInit physical Interface components */
if (pdev->pClassDataCmsit[pdev->classId] != NULL)
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->DeInit();
(void)USBD_free(pdev->pClassDataCmsit[pdev->classId]);
pdev->pClassDataCmsit[pdev->classId] = NULL;
pdev->pClassData = NULL;
}
return (uint8_t)USBD_OK;
}
/**
* @brief USBD_CDC_Setup
* Handle the CDC specific requests
* @param pdev: instance
* @param req: usb requests
* @retval status
*/
static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
uint16_t len;
uint8_t ifalt = 0U;
uint16_t status_info = 0U;
USBD_StatusTypeDef ret = USBD_OK;
if (hcdc == NULL)
{
return (uint8_t)USBD_FAIL;
}
switch (req->bmRequest & USB_REQ_TYPE_MASK)
{
case USB_REQ_TYPE_CLASS:
if (req->wLength != 0U)
{
if ((req->bmRequest & 0x80U) != 0U)
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(req->bRequest,
(uint8_t *)hcdc->data,
req->wLength);
len = MIN(CDC_REQ_MAX_DATA_SIZE, req->wLength);
(void)USBD_CtlSendData(pdev, (uint8_t *)hcdc->data, len);
}
else
{
hcdc->CmdOpCode = req->bRequest;
hcdc->CmdLength = (uint8_t)MIN(req->wLength, USB_MAX_EP0_SIZE);
(void)USBD_CtlPrepareRx(pdev, (uint8_t *)hcdc->data, hcdc->CmdLength);
}
}
else
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(req->bRequest,
(uint8_t *)req, 0U);
}
break;
case USB_REQ_TYPE_STANDARD:
switch (req->bRequest)
{
case USB_REQ_GET_STATUS:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
(void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U);
}
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
case USB_REQ_GET_INTERFACE:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
(void)USBD_CtlSendData(pdev, &ifalt, 1U);
}
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
case USB_REQ_SET_INTERFACE:
if (pdev->dev_state != USBD_STATE_CONFIGURED)
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
case USB_REQ_CLEAR_FEATURE:
break;
default:
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
break;
}
break;
default:
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
break;
}
return (uint8_t)ret;
}
/**
* @brief USBD_CDC_DataIn
* Data sent on non-control IN endpoint
* @param pdev: device instance
* @param epnum: endpoint number
* @retval status
*/
static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum)
{
USBD_CDC_HandleTypeDef *hcdc;
PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef *)pdev->pData;
if (pdev->pClassDataCmsit[pdev->classId] == NULL)
{
return (uint8_t)USBD_FAIL;
}
hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
if ((pdev->ep_in[epnum & 0xFU].total_length > 0U) &&
((pdev->ep_in[epnum & 0xFU].total_length % hpcd->IN_ep[epnum & 0xFU].maxpacket) == 0U))
{
/* Update the packet total length */
pdev->ep_in[epnum & 0xFU].total_length = 0U;
/* Send ZLP */
(void)USBD_LL_Transmit(pdev, epnum, NULL, 0U);
}
else
{
hcdc->TxState = 0U;
if (((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->TransmitCplt != NULL)
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->TransmitCplt(hcdc->TxBuffer, &hcdc->TxLength, epnum);
}
}
return (uint8_t)USBD_OK;
}
/**
* @brief USBD_CDC_DataOut
* Data received on non-control Out endpoint
* @param pdev: device instance
* @param epnum: endpoint number
* @retval status
*/
static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum)
{
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
if (pdev->pClassDataCmsit[pdev->classId] == NULL)
{
return (uint8_t)USBD_FAIL;
}
/* Get the received data length */
hcdc->RxLength = USBD_LL_GetRxDataSize(pdev, epnum);
/* USB data will be immediately processed, this allow next USB traffic being
NAKed till the end of the application Xfer */
((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Receive(hcdc->RxBuffer, &hcdc->RxLength);
return (uint8_t)USBD_OK;
}
/**
* @brief USBD_CDC_EP0_RxReady
* Handle EP0 Rx Ready event
* @param pdev: device instance
* @retval status
*/
static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev)
{
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
if (hcdc == NULL)
{
return (uint8_t)USBD_FAIL;
}
if ((pdev->pUserData[pdev->classId] != NULL) && (hcdc->CmdOpCode != 0xFFU))
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(hcdc->CmdOpCode,
(uint8_t *)hcdc->data,
(uint16_t)hcdc->CmdLength);
hcdc->CmdOpCode = 0xFFU;
}
return (uint8_t)USBD_OK;
}
#ifndef USE_USBD_COMPOSITE
/**
* @brief USBD_CDC_GetFSCfgDesc
* Return configuration descriptor
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length)
{
USBD_EpDescTypeDef *pEpCmdDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_CMD_EP);
USBD_EpDescTypeDef *pEpOutDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_OUT_EP);
USBD_EpDescTypeDef *pEpInDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_IN_EP);
if (pEpCmdDesc != NULL)
{
pEpCmdDesc->bInterval = CDC_FS_BINTERVAL;
}
if (pEpOutDesc != NULL)
{
pEpOutDesc->wMaxPacketSize = CDC_DATA_FS_MAX_PACKET_SIZE;
}
if (pEpInDesc != NULL)
{
pEpInDesc->wMaxPacketSize = CDC_DATA_FS_MAX_PACKET_SIZE;
}
*length = (uint16_t)sizeof(USBD_CDC_CfgDesc);
return USBD_CDC_CfgDesc;
}
/**
* @brief USBD_CDC_GetHSCfgDesc
* Return configuration descriptor
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length)
{
USBD_EpDescTypeDef *pEpCmdDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_CMD_EP);
USBD_EpDescTypeDef *pEpOutDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_OUT_EP);
USBD_EpDescTypeDef *pEpInDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_IN_EP);
if (pEpCmdDesc != NULL)
{
pEpCmdDesc->bInterval = CDC_HS_BINTERVAL;
}
if (pEpOutDesc != NULL)
{
pEpOutDesc->wMaxPacketSize = CDC_DATA_HS_MAX_PACKET_SIZE;
}
if (pEpInDesc != NULL)
{
pEpInDesc->wMaxPacketSize = CDC_DATA_HS_MAX_PACKET_SIZE;
}
*length = (uint16_t)sizeof(USBD_CDC_CfgDesc);
return USBD_CDC_CfgDesc;
}
/**
* @brief USBD_CDC_GetOtherSpeedCfgDesc
* Return configuration descriptor
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length)
{
USBD_EpDescTypeDef *pEpCmdDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_CMD_EP);
USBD_EpDescTypeDef *pEpOutDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_OUT_EP);
USBD_EpDescTypeDef *pEpInDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_IN_EP);
if (pEpCmdDesc != NULL)
{
pEpCmdDesc->bInterval = CDC_FS_BINTERVAL;
}
if (pEpOutDesc != NULL)
{
pEpOutDesc->wMaxPacketSize = CDC_DATA_FS_MAX_PACKET_SIZE;
}
if (pEpInDesc != NULL)
{
pEpInDesc->wMaxPacketSize = CDC_DATA_FS_MAX_PACKET_SIZE;
}
*length = (uint16_t)sizeof(USBD_CDC_CfgDesc);
return USBD_CDC_CfgDesc;
}
/**
* @brief USBD_CDC_GetDeviceQualifierDescriptor
* return Device Qualifier descriptor
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
uint8_t *USBD_CDC_GetDeviceQualifierDescriptor(uint16_t *length)
{
*length = (uint16_t)sizeof(USBD_CDC_DeviceQualifierDesc);
return USBD_CDC_DeviceQualifierDesc;
}
#endif /* USE_USBD_COMPOSITE */
/**
* @brief USBD_CDC_RegisterInterface
* @param pdev: device instance
* @param fops: CD Interface callback
* @retval status
*/
uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev,
USBD_CDC_ItfTypeDef *fops)
{
if (fops == NULL)
{
return (uint8_t)USBD_FAIL;
}
pdev->pUserData[pdev->classId] = fops;
return (uint8_t)USBD_OK;
}
/**
* @brief USBD_CDC_SetTxBuffer
* @param pdev: device instance
* @param pbuff: Tx Buffer
* @param length: Tx Buffer length
* @retval status
*/
uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev,
uint8_t *pbuff, uint32_t length)
{
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
if (hcdc == NULL)
{
return (uint8_t)USBD_FAIL;
}
hcdc->TxBuffer = pbuff;
hcdc->TxLength = length;
return (uint8_t)USBD_OK;
}
/**
* @brief USBD_CDC_SetRxBuffer
* @param pdev: device instance
* @param pbuff: Rx Buffer
* @retval status
*/
uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff)
{
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
if (hcdc == NULL)
{
return (uint8_t)USBD_FAIL;
}
hcdc->RxBuffer = pbuff;
return (uint8_t)USBD_OK;
}
/**
* @brief USBD_CDC_TransmitPacket
* Transmit packet on IN endpoint
* @param pdev: device instance
* @retval status
*/
uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev)
{
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
USBD_StatusTypeDef ret = USBD_BUSY;
#ifdef USE_USBD_COMPOSITE
/* Get the Endpoints addresses allocated for this class instance */
CDCInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_BULK);
#endif /* USE_USBD_COMPOSITE */
if (pdev->pClassDataCmsit[pdev->classId] == NULL)
{
return (uint8_t)USBD_FAIL;
}
if (hcdc->TxState == 0U)
{
/* Tx Transfer in progress */
hcdc->TxState = 1U;
/* Update the packet total length */
pdev->ep_in[CDCInEpAdd & 0xFU].total_length = hcdc->TxLength;
/* Transmit next packet */
(void)USBD_LL_Transmit(pdev, CDCInEpAdd, hcdc->TxBuffer, hcdc->TxLength);
ret = USBD_OK;
}
return (uint8_t)ret;
}
/**
* @brief USBD_CDC_ReceivePacket
* prepare OUT Endpoint for reception
* @param pdev: device instance
* @retval status
*/
uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev)
{
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
#ifdef USE_USBD_COMPOSITE
/* Get the Endpoints addresses allocated for this class instance */
CDCOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_BULK);
#endif /* USE_USBD_COMPOSITE */
if (pdev->pClassDataCmsit[pdev->classId] == NULL)
{
return (uint8_t)USBD_FAIL;
}
if (pdev->dev_speed == USBD_SPEED_HIGH)
{
/* Prepare Out endpoint to receive next packet */
(void)USBD_LL_PrepareReceive(pdev, CDCOutEpAdd, hcdc->RxBuffer,
CDC_DATA_HS_OUT_PACKET_SIZE);
}
else
{
/* Prepare Out endpoint to receive next packet */
(void)USBD_LL_PrepareReceive(pdev, CDCOutEpAdd, hcdc->RxBuffer,
CDC_DATA_FS_OUT_PACKET_SIZE);
}
return (uint8_t)USBD_OK;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
component/xc6xx_drivers/Drivers/USB/Middlewares/Library/Class/CompositeBuilder/Inc/usbd_composite_builder.h
+308
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@@ -0,0 +1,308 @@
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USBD_COMPOSITE_BUILDER_H__
#define __USBD_COMPOSITE_BUILDER_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "usbd_ioreq.h"
#if USBD_CMPSIT_ACTIVATE_HID_MOUSE == 1U
#include "usbd_hid_mouse.h"
#endif /* USBD_CMPSIT_ACTIVATE_HID_MOUSE */
#if USBD_CMPSIT_ACTIVATE_HID_KEYBOARD == 1U
#include "usbd_hid_keyboard.h"
#endif /* USBD_CMPSIT_ACTIVATE_HID_KEYBOARD */
#if USBD_CMPSIT_ACTIVATE_HID_CUSTOM == 1U
#include "usbd_hid_custom.h"
#endif /* USBD_CMPSIT_ACTIVATE_HID_CUSTOM */
#if USBD_CMPSIT_ACTIVATE_MSC == 1U
#include "usbd_msc.h"
#endif /* USBD_CMPSIT_ACTIVATE_MSC */
#if USBD_CMPSIT_ACTIVATE_CDC == 1U
#include "usbd_cdc.h"
#endif /* USBD_CMPSIT_ACTIVATE_CDC */
#if USBD_CMPSIT_ACTIVATE_DFU == 1U
#include "usbd_dfu.h"
#endif /* USBD_CMPSIT_ACTIVATE_DFU */
#if USBD_CMPSIT_ACTIVATE_RNDIS == 1U
#include "usbd_cdc_rndis.h"
#endif /* USBD_CMPSIT_ACTIVATE_RNDIS */
#if USBD_CMPSIT_ACTIVATE_CDC_ECM == 1U
#include "usbd_cdc_ecm.h"
#ifndef __USBD_CDC_ECM_IF_H
#include "usbd_cdc_ecm_if_template.h"
#endif /* __USBD_CDC_ECM_IF_H */
#endif /* USBD_CMPSIT_ACTIVATE_CDC_ECM */
#if USBD_CMPSIT_ACTIVATE_AUDIO == 1
#include "usbd_audio.h"
#endif /* USBD_CMPSIT_ACTIVATE_AUDIO */
#if USBD_CMPSIT_ACTIVATE_CUSTOMHID == 1
#include "usbd_customhid.h"
#endif /* USBD_CMPSIT_ACTIVATE_CUSTOMHID */
#if USBD_CMPSIT_ACTIVATE_VIDEO == 1
#include "usbd_video.h"
#endif /* USBD_CMPSIT_ACTIVATE_VIDEO */
#if USBD_CMPSIT_ACTIVATE_PRINTER == 1
#include "usbd_printer.h"
#endif /* USBD_CMPSIT_ACTIVATE_PRINTER */
#if USBD_CMPSIT_ACTIVATE_CCID == 1U
#include "usbd_ccid.h"
#endif /* USBD_CMPSIT_ACTIVATE_CCID */
#if USBD_CMPSIT_ACTIVATE_MTP == 1U
#include "usbd_mtp.h"
#endif /* USBD_CMPSIT_ACTIVATE_MTP */
#if USBD_CMPSIT_ACTIVATE_MICROPHONE == 1U
#include "usbd_microphone.h"
#endif /* USBD_CMPSIT_ACTIVATE_MICROPHONE */
#if USBD_CMPSIT_ACTIVATE_HEADPHONE == 1U
#include "usbd_headphone.h"
#endif /* USBD_CMPSIT_ACTIVATE_HEADPHONE */
/* Private defines -----------------------------------------------------------*/
/* By default all classes are deactivated, in order to activate a class
define its value to zero */
#ifndef USBD_CMPSIT_ACTIVATE_HID_MOUSE
#define USBD_CMPSIT_ACTIVATE_HID_MOUSE 0U
#endif /* USBD_CMPSIT_ACTIVATE_HID_MOUSE */
#ifndef USBD_CMPSIT_ACTIVATE_HID_KEYBOARD
#define USBD_CMPSIT_ACTIVATE_HID_KEYBOARD 0U
#endif /* USBD_CMPSIT_ACTIVATE_HID_MOUSE */
#ifndef USBD_CMPSIT_ACTIVATE_HID_CUSTOM
#define USBD_CMPSIT_ACTIVATE_HID_CUSTOM 0U
#endif /* USBD_CMPSIT_ACTIVATE_HID_MOUSE */
#ifndef USBD_CMPSIT_ACTIVATE_MSC
#define USBD_CMPSIT_ACTIVATE_MSC 0U
#endif /* USBD_CMPSIT_ACTIVATE_MSC */
#ifndef USBD_CMPSIT_ACTIVATE_DFU
#define USBD_CMPSIT_ACTIVATE_DFU 0U
#endif /* USBD_CMPSIT_ACTIVATE_DFU */
#ifndef USBD_CMPSIT_ACTIVATE_CDC
#define USBD_CMPSIT_ACTIVATE_CDC 0U
#endif /* USBD_CMPSIT_ACTIVATE_CDC */
#ifndef USBD_CMPSIT_ACTIVATE_CDC_ECM
#define USBD_CMPSIT_ACTIVATE_CDC_ECM 0U
#endif /* USBD_CMPSIT_ACTIVATE_CDC_ECM */
#ifndef USBD_CMPSIT_ACTIVATE_RNDIS
#define USBD_CMPSIT_ACTIVATE_RNDIS 0U
#endif /* USBD_CMPSIT_ACTIVATE_RNDIS */
#ifndef USBD_CMPSIT_ACTIVATE_AUDIO
#define USBD_CMPSIT_ACTIVATE_AUDIO 0U
#endif /* USBD_CMPSIT_ACTIVATE_AUDIO */
#ifndef USBD_CMPSIT_ACTIVATE_CUSTOMHID
#define USBD_CMPSIT_ACTIVATE_CUSTOMHID 0U
#endif /* USBD_CMPSIT_ACTIVATE_CUSTOMHID */
#ifndef USBD_CMPSIT_ACTIVATE_VIDEO
#define USBD_CMPSIT_ACTIVATE_VIDEO 0U
#endif /* USBD_CMPSIT_ACTIVATE_VIDEO */
#ifndef USBD_CMPSIT_ACTIVATE_PRINTER
#define USBD_CMPSIT_ACTIVATE_PRINTER 0U
#endif /* USBD_CMPSIT_ACTIVATE_PRINTER */
#ifndef USBD_CMPSIT_ACTIVATE_CCID
#define USBD_CMPSIT_ACTIVATE_CCID 0U
#endif /* USBD_CMPSIT_ACTIVATE_CCID */
#ifndef USBD_CMPSIT_ACTIVATE_MTP
#define USBD_CMPSIT_ACTIVATE_MTP 0U
#endif /* USBD_CMPSIT_ACTIVATE_MTP */
#ifndef USBD_CMPSIT_ACTIVATE_MICROPHONE
#define USBD_CMPSIT_ACTIVATE_MICROPHONE 0U
#endif /* USBD_CMPSIT_ACTIVATE_MICROPHONE */
#ifndef USBD_CMPSIT_ACTIVATE_HEADPHONE
#define USBD_CMPSIT_ACTIVATE_HEADPHONE 0U
#endif /* USBD_CMPSIT_ACTIVATE_HEADPHONE */
/* This is the maximum supported configuration descriptor size
User may define this value in usbd_conf.h in order to optimize footprint */
#ifndef USBD_CMPST_MAX_CONFDESC_SZ
#define USBD_CMPST_MAX_CONFDESC_SZ 512U
#endif /* USBD_CMPST_MAX_CONFDESC_SZ */
#ifndef USBD_CONFIG_STR_DESC_IDX
#define USBD_CONFIG_STR_DESC_IDX 2U
#endif /* USBD_CONFIG_STR_DESC_IDX */
#define AUDIO_SMAPLE_RATE_HZ 16000U
/* Exported types ------------------------------------------------------------*/
/* USB Iad descriptors structure */
typedef struct
{
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bFirstInterface;
uint8_t bInterfaceCount;
uint8_t bFunctionClass;
uint8_t bFunctionSubClass;
uint8_t bFunctionProtocol;
uint8_t iFunction;
} USBD_IadDescTypeDef;
/* USB interface descriptors structure */
typedef struct
{
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bInterfaceNumber;
uint8_t bAlternateSetting;
uint8_t bNumEndpoints;
uint8_t bInterfaceClass;
uint8_t bInterfaceSubClass;
uint8_t bInterfaceProtocol;
uint8_t iInterface;
} USBD_IfDescTypeDef;
#if (USBD_CMPSIT_ACTIVATE_CDC == 1) || (USBD_CMPSIT_ACTIVATE_RNDIS == 1) || (USBD_CMPSIT_ACTIVATE_CDC_ECM == 1) || (USBD_CMPSIT_ACTIVATE_MULTI_CDC == 1)
typedef struct
{
/*
* CDC Class specification revision 1.2
* Table 15: Class-Specific Descriptor Header Format
*/
/* Header Functional Descriptor */
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bDescriptorSubtype;
uint16_t bcdCDC;
} __PACKED USBD_CDCHeaderFuncDescTypeDef;
typedef struct
{
/* Call Management Functional Descriptor */
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bDescriptorSubtype;
uint8_t bmCapabilities;
uint8_t bDataInterface;
} USBD_CDCCallMgmFuncDescTypeDef;
typedef struct
{
/* ACM Functional Descriptor */
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bDescriptorSubtype;
uint8_t bmCapabilities;
} USBD_CDCACMFuncDescTypeDef;
typedef struct
{
/*
* CDC Class specification revision 1.2
* Table 16: Union Interface Functional Descriptor
*/
/* Union Functional Descriptor */
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bDescriptorSubtype;
uint8_t bMasterInterface;
uint8_t bSlaveInterface;
} USBD_CDCUnionFuncDescTypeDef;
#endif /* (USBD_CMPSIT_ACTIVATE_CDC == 1) || (USBD_CMPSIT_ACTIVATE_RNDIS == 1) || (USBD_CMPSIT_ACTIVATE_CDC_ECM == 1)*/
extern USBD_ClassTypeDef USBD_CMPSIT;
/* Exported functions prototypes ---------------------------------------------*/
uint8_t USBD_CMPSIT_AddToConfDesc(USBD_HandleTypeDef *pdev);
#ifdef USE_USBD_COMPOSITE
uint8_t USBD_CMPSIT_AddClass(USBD_HandleTypeDef *pdev,
USBD_ClassTypeDef *pclass,
USBD_CompositeClassTypeDef class,
uint8_t cfgidx);
uint32_t USBD_CMPSIT_SetClassID(USBD_HandleTypeDef *pdev,
USBD_CompositeClassTypeDef Class,
uint32_t Instance);
uint32_t USBD_CMPSIT_GetClassID(USBD_HandleTypeDef *pdev,
USBD_CompositeClassTypeDef Class,
uint32_t Instance);
uint8_t USBD_CMPSIT_GetClassID_ByAdd(USBD_HandleTypeDef *pdev,
uint8_t ep_add,
uint8_t ep_type);
#endif /* USE_USBD_COMPOSITE */
uint8_t USBD_CMPST_ClearConfDesc(USBD_HandleTypeDef *pdev);
/* Private macro -----------------------------------------------------------*/
#define __USBD_CMPSIT_SET_EP(epadd, eptype, epsize, HSinterval, FSinterval) \
do { \
/* Append Endpoint descriptor to Configuration descriptor */ \
pEpDesc = ((USBD_EpDescTypeDef*)((uint32_t)pConf + *Sze)); \
pEpDesc->bLength = (uint8_t)sizeof(USBD_EpDescTypeDef); \
pEpDesc->bDescriptorType = USB_DESC_TYPE_ENDPOINT; \
pEpDesc->bEndpointAddress = (epadd); \
pEpDesc->bmAttributes = (eptype); \
pEpDesc->wMaxPacketSize = (epsize); \
if(speed == (uint8_t)USBD_SPEED_HIGH) \
{ \
pEpDesc->bInterval = HSinterval; \
} \
else \
{ \
pEpDesc->bInterval = FSinterval; \
} \
*Sze += (uint32_t)sizeof(USBD_EpDescTypeDef); \
} while(0)
#define __USBD_CMPSIT_SET_IF(ifnum, alt, eps, class, subclass, protocol, istring) \
do { \
/* Interface Descriptor */ \
pIfDesc = ((USBD_IfDescTypeDef*)((uint32_t)pConf + *Sze)); \
pIfDesc->bLength = (uint8_t)sizeof(USBD_IfDescTypeDef); \
pIfDesc->bDescriptorType = USB_DESC_TYPE_INTERFACE; \
pIfDesc->bInterfaceNumber = ifnum; \
pIfDesc->bAlternateSetting = alt; \
pIfDesc->bNumEndpoints = eps; \
pIfDesc->bInterfaceClass = class; \
pIfDesc->bInterfaceSubClass = subclass; \
pIfDesc->bInterfaceProtocol = protocol; \
pIfDesc->iInterface = istring; \
*Sze += (uint32_t)sizeof(USBD_IfDescTypeDef); \
} while(0)
#ifdef __cplusplus
}
#endif
#endif /* __USBD_COMPOSITE_BUILDER_H__ */
/**
* @}
*/
component/xc6xx_drivers/Drivers/USB/Middlewares/Library/Class/CompositeBuilder/Src/usbd_composite_builder.c
+2511
View File
File diff suppressed because it is too large Load Diff
component/xc6xx_drivers/Drivers/USB/Middlewares/Library/Class/HID/Inc/usbd_hid_custom.h
+179
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@@ -0,0 +1,179 @@
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USB_HID_CUSTOM_H
#define __USB_HID_CUSTOM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "usbd_ioreq.h"
/** @defgroup USBD_HID
* @brief This file is the Header file for usbd_hid.c
* @{
*/
/** @defgroup USBD_HID_Exported_Defines
* @{
*/
#ifndef HID_CUSTOM_EPIN_ADDR
#define HID_CUSTOM_EPIN_ADDR 0x83U
#endif /* HID_EPIN_ADDR */
#define HID_CUSTOM_EPIN_SIZE 0x40U
#ifndef HID_CUSTOM_EPOUT_ADDR
#define HID_CUSTOM_EPOUT_ADDR 0x03U
#endif /* HID_CUSTOM_EPOUT_ADDR */
#define HID_CUSTOM_EPOUT_SIZE 0x40U
#define USB_HID_CUSTOM_CONFIG_DESC_SIZ 41U
#define USB_HID_CUSTOM_DESC_SIZ 9U
#define HID_CUSTOM_REPORT_DESC_SIZE 38+45U
#define HID_CUSTOM_DESCRIPTOR_TYPE 0x21U
#define HID_CUSTOM_REPORT_DESC 0x22U
#ifndef HID_CUSTOM_HS_BINTERVAL
#define HID_CUSTOM_HS_BINTERVAL 0x07U
#endif /* HID_HS_BINTERVAL */
#ifndef HID_CUSTOM_FS_BINTERVAL
#define HID_CUSTOM_FS_BINTERVAL 0x0AU
#endif /* HID_FS_BINTERVAL */
#ifndef USBD_CUSTOM_OUTREPORT_BUF_SIZE
#define USBD_CUSTOM_OUTREPORT_BUF_SIZE 0x02U
#endif /* USBD_CUSTOM_OUTREPORT_BUF_SIZE */
#define HID_CUSTOM_REQ_SET_PROTOCOL 0x0BU
#define HID_CUSTOM_REQ_GET_PROTOCOL 0x03U
#define HID_CUSTOM_REQ_SET_IDLE 0x0AU
#define HID_CUSTOM_REQ_GET_IDLE 0x02U
#define HID_CUSTOM_REQ_SET_REPORT 0x09U
#define HID_CUSTOM_REQ_GET_REPORT 0x01U
#ifndef HID_CUSTOM_EP0_SET_REPORT_BUF_SIZE
#define HID_CUSTOM_EP0_SET_REPORT_BUF_SIZE 0x10U
#endif /* HID_CUSTOM_EP0_SET_REPORT_BUF_SIZE */
#ifndef HID_CUSTOM_EP0_GET_REPORT_BUF_SIZE
#define HID_CUSTOM_EP0_GET_REPORT_BUF_SIZE 0x10U
#endif /* HID_CUSTOM_EP0_GET_REPORT_BUF_SIZE */
/**
* @}
*/
#define USB_DFU_REPORT_MAP \
0x06, 0x86, 0x19, /* Usage Page (ByteX)*/\
0x09, 0x10, /* Usage (0x10)*/\
0xA1, 0x01, /* Collection (Application)*/\
0x85, 0xFA, /* Report ID (-79)*/\
0x15, 0x00, /* Logical Minimum (0)*/\
0x25, 0xFF, /* Logical Maximum (-1)*/\
0x09, 0x00, /* Usage (Unassigned)*/\
0x19, 0x00, /* Usage (Unassigned)*/\
0x29, 0xFF, /* Usage Maximum (0xFF)*/\
0x75, 0x08, /* Report Size (8)*/\
0x95, 63, /* Report Count (63)*/\
0x81, 0x02, /* Input (Data,Var,Abs,No Wrap,Linear,Preferred State,No Null Position)*/\
0x85, 0xFB, /* Report ID (-78)*/\
0x15, 0x00, /* Logical Minimum (0)*/\
0x25, 0xFF, /* Logical Maximum (-1)*/\
0x09, 0x00, /* Usage (Unassigned)*/\
0x19, 0x00, /* Usage (Unassigned)*/\
0x29, 0xFF, /* Usage Maximum (0xFF)*/\
0x75, 0x08, /* Report Size (8)*/\
0x96, 0xFF, 0x01, /* Report Count (511)*/\
0x91, 0x02, /* Output (Data,Var,Abs,No Wrap,Linear,Preferred State,No Null Position,Non-volatile)*/\
0xC0
/** @defgroup USBD_CORE_Exported_TypesDefinitions
* @{
*/
typedef enum
{
CUSTOM_HID_IDLE = 0,
CUSTOM_HID_BUSY,
} HID_Custom_StateTypeDef;
typedef struct
{
uint8_t EP0_ReportBuff[HID_CUSTOM_EP0_SET_REPORT_BUF_SIZE];
uint8_t EP0_ReportLen;
uint8_t Report_buf[USBD_CUSTOM_OUTREPORT_BUF_SIZE];
uint32_t Protocol;
uint32_t IdleState;
uint32_t AltSetting;
HID_Custom_StateTypeDef state;
} USBD_HID_Custom_HandleTypeDef;
/*
* HID Class specification version 1.1
* 6.2.1 HID Descriptor
*/
typedef struct
{
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t bcdHID;
uint8_t bCountryCode;
uint8_t bNumDescriptors;
uint8_t bHIDDescriptorType;
uint16_t wItemLength;
} __PACKED USBD_HID_CustomDescTypeDef;
/**
* @}
*/
/** @defgroup USBD_CORE_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup USBD_CORE_Exported_Variables
* @{
*/
extern USBD_ClassTypeDef USBD_HID_CUSTOM;
#define USBD_HID_CUSTOM_CLASS &USBD_HID_CUSTOM
/**
* @}
*/
/** @defgroup USB_CORE_Exported_Functions
* @{
*/
uint8_t USBD_HID_CUSTOM_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len);
uint32_t USBD_HID_CUSTOM_GetPollingInterval(USBD_HandleTypeDef *pdev);
uint8_t USBD_HID_Custom_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len);
uint8_t USBD_HID_Custom_FirstSendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __USB_HID_H */
/**
* @}
*/
/**
* @}
*/
component/xc6xx_drivers/Drivers/USB/Middlewares/Library/Class/HID/Inc/usbd_hid_keyboard.h
+156
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/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USB_HID_KEYBOARD_H
#define __USB_HID_KEYBOARD_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "usbd_ioreq.h"
/** @defgroup USBD_HID
* @brief This file is the Header file for usbd_hid.c
* @{
*/
/** @defgroup USBD_HID_Exported_Defines
* @{
*/
#ifndef HID_KEYBOARD_EPIN_ADDR
#define HID_KEYBOARD_EPIN_ADDR 0x82U
#endif /* HID_EPIN_ADDR */
#define HID_KEYBOARD_EPIN_SIZE 0x08U
#ifndef HID_KEYBOARD_EPOUT_ADDR
#define HID_KEYBOARD_EPOUT_ADDR 0x02U
#endif /* HID_EPIN_ADDR */
#define HID_KEYBOARD_EPOUT_SIZE 0x01U
#define USB_HID_KEYBOARD_CONFIG_DESC_SIZ 41U
#define USB_HID_KEYBOARD_DESC_SIZ 9U
#define HID_KEYBOARD_REPORT_DESC_SIZE 63U
#define HID_KEYBOARD_DESCRIPTOR_TYPE 0x21U
#define HID_KEYBOARD_REPORT_DESC 0x22U
#ifndef HID_KEYBOARD_HS_BINTERVAL
#define HID_KEYBOARD_HS_BINTERVAL 0x07U
#endif /* HID_HS_BINTERVAL */
#ifndef HID_KEYBOARD_FS_BINTERVAL
#define HID_KEYBOARD_FS_BINTERVAL 0x0AU
#endif /* HID_FS_BINTERVAL */
#ifndef USBD_KEYBOARD_OUTREPORT_BUF_SIZE
#define USBD_KEYBOARD_OUTREPORT_BUF_SIZE 0x02U
#endif /* USBD_KEYBOARD_OUTREPORT_BUF_SIZE */
#define HID_KEYBOARD_REQ_SET_PROTOCOL 0x0BU
#define HID_KEYBOARD_REQ_GET_PROTOCOL 0x03U
#define HID_KEYBOARD_REQ_SET_IDLE 0x0AU
#define HID_KEYBOARD_REQ_GET_IDLE 0x02U
#define HID_KEYBOARD_REQ_SET_REPORT 0x09U
#define HID_KEYBOARD_REQ_GET_REPORT 0x01U
#ifndef HID_KEYBOARD_EP0_SET_REPORT_BUF_SIZE
#define HID_KEYBOARD_EP0_SET_REPORT_BUF_SIZE 0x10U
#endif /* HID_KEYBOARD_EP0_SET_REPORT_BUF_SIZE */
#ifndef HID_KEYBOARD_EP0_GET_REPORT_BUF_SIZE
#define HID_KEYBOARD_EP0_GET_REPORT_BUF_SIZE 0x10U
#endif /* HID_KEYBOARD_EP0_GET_REPORT_BUF_SIZE */
/**
* @}
*/
/** @defgroup USBD_CORE_Exported_TypesDefinitions
* @{
*/
typedef enum
{
KEYBOARD_HID_IDLE = 0,
KEYBOARD_HID_BUSY,
} HID_Keyboard_StateTypeDef;
typedef struct
{
uint8_t EP0_ReportBuff[HID_KEYBOARD_EP0_SET_REPORT_BUF_SIZE];
uint8_t EP0_ReportLen;
uint8_t Report_buf[USBD_KEYBOARD_OUTREPORT_BUF_SIZE];
uint32_t Protocol;
uint32_t IdleState;
uint32_t AltSetting;
HID_Keyboard_StateTypeDef state;
} USBD_HID_Keyboard_HandleTypeDef;
/*
* HID Class specification version 1.1
* 6.2.1 HID Descriptor
*/
typedef struct
{
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t bcdHID;
uint8_t bCountryCode;
uint8_t bNumDescriptors;
uint8_t bHIDDescriptorType;
uint16_t wItemLength;
} __PACKED USBD_HID_KeyboardDescTypeDef;
/**
* @}
*/
/** @defgroup USBD_CORE_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup USBD_CORE_Exported_Variables
* @{
*/
extern USBD_ClassTypeDef USBD_HID_KEYBOARD;
#define USBD_HID_KEYBOARD_CLASS &USBD_HID_KEYBOARD
/**
* @}
*/
/** @defgroup USB_CORE_Exported_Functions
* @{
*/
uint8_t USBD_HID_Keyboard_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len);
uint32_t USBD_HID_GetPollingInterval(USBD_HandleTypeDef *pdev);
uint8_t USBD_HID_Keyboard_FirstSendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __USB_HID_H */
/**
* @}
*/
/**
* @}
*/
component/xc6xx_drivers/Drivers/USB/Middlewares/Library/Class/HID/Inc/usbd_hid_mouse.h
+172
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/*!
* \file usbd_hid.h
*
* \brief This file provides the HID core functions.
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author MCD Application Team
*
* \author ( XinChip ) Alex-J
*
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USB_HID_MOUSE_H
#define __USB_HID_MOUSE_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "usbd_ioreq.h"
/** @defgroup USBD_HID
* @brief This file is the Header file for usbd_hid.c
* @{
*/
/** @defgroup USBD_HID_Exported_Defines
* @{
*/
#ifndef HID_MOUSE_EPIN_ADDR
#define HID_MOUSE_EPIN_ADDR 0x81U
#endif /* HID_EPIN_ADDR */
#define HID_MOUSE_EPIN_SIZE 0x04U
#define USB_HID_MOUSE_CONFIG_DESC_SIZ 34U
#define USB_HID_MOUSE_DESC_SIZ 9U
#define HID_MOUSE_REPORT_DESC_SIZE 74U
#define HID_MOUSE_DESCRIPTOR_TYPE 0x21U
#define HID_MOUSE_REPORT_DESC 0x22U
#ifndef HID_MOUSE_HS_BINTERVAL
#define HID_MOUSE_HS_BINTERVAL 0x07U
#endif /* HID_HS_BINTERVAL */
#ifndef HID_MOUSE_FS_BINTERVAL
#define HID_MOUSE_FS_BINTERVAL 0x01U
#endif /* HID_FS_BINTERVAL */
#define HID_MOUSE_REQ_SET_PROTOCOL 0x0BU
#define HID_MOUSE_REQ_GET_PROTOCOL 0x03U
#define HID_MOUSE_REQ_SET_IDLE 0x0AU
#define HID_MOUSE_REQ_GET_IDLE 0x02U
#define HID_MOUSE_REQ_SET_REPORT 0x09U
#define HID_MOUSE_REQ_GET_REPORT 0x01U
#ifndef HID_MOUSE_EP0_SET_REPORT_BUF_SIZE
#define HID_MOUSE_EP0_SET_REPORT_BUF_SIZE 0x10U
#endif /* HID_MOUSE_EP0_SET_REPORT_BUF_SIZE */
#ifndef HID_MOUSE_EP0_GET_REPORT_BUF_SIZE
#define HID_MOUSE_EP0_GET_REPORT_BUF_SIZE 0x10U
#endif /* HID_MOUSE_EP0_GET_REPORT_BUF_SIZE */
/**
* @}
*/
/** @defgroup USBD_CORE_Exported_TypesDefinitions
* @{
*/
typedef enum
{
MOUSE_HID_IDLE = 0,
MOUSE_HID_BUSY,
} HID_Mouse_StateTypeDef;
typedef struct
{
uint8_t EP0_ReportBuff[HID_MOUSE_EP0_SET_REPORT_BUF_SIZE];
uint8_t EP0_ReportLen;
uint32_t Protocol;
uint32_t IdleState;
uint32_t AltSetting;
HID_Mouse_StateTypeDef state;
} USBD_HID_Mouse_HandleTypeDef;
/*
* HID Class specification version 1.1
* 6.2.1 HID Descriptor
*/
typedef struct
{
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t bcdHID;
uint8_t bCountryCode;
uint8_t bNumDescriptors;
uint8_t bHIDDescriptorType;
uint16_t wItemLength;
} __PACKED USBD_HID_MouseDescTypeDef;
/**
* @}
*/
/** @defgroup USBD_CORE_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup USBD_CORE_Exported_Variables
* @{
*/
extern USBD_ClassTypeDef USBD_HID_MOUSE;
#define USBD_HID_MOUSE_CLASS &USBD_HID_MOUSE
/**
* @}
*/
/** @defgroup USB_CORE_Exported_Functions
* @{
*/
uint8_t USBD_HID_Mouse_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len);
uint32_t USBD_HID_GetPollingInterval(USBD_HandleTypeDef *pdev);
uint8_t USBD_HID_Mouse_FirstSendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __USB_HID_H */
/**
* @}
*/
/**
* @}
*/
component/xc6xx_drivers/Drivers/USB/Middlewares/Library/Class/HID/Src/usbd_hid_custom.c
+879
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/*!
* \file usbd_hid_custom.c
*
* \brief This file provides the HID core functions.
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author MCD Application Team
*
* \author ( XinChip ) Alex-J
*
* @verbatim
*
* ===================================================================
* HID Class Description
* ===================================================================
* This module manages the HID class V1.11 following the "Device Class Definition
* for Human Interface Devices (HID) Version 1.11 Jun 27, 2001".
* This driver implements the following aspects of the specification:
* - The Boot Interface Subclass
* - The Mouse protocol
* - Usage Page : Generic Desktop
* - Usage : Custom
* - Collection : Application
*
* @note In HS mode and when the DMA is used, all variables and data structures
* dealing with the DMA during the transaction process should be 32-bit aligned.
*
*
* @endverbatim
*
*/
/* Includes ------------------------------------------------------------------*/
#include "usbd_hid_custom.h"
#include "usbd_ctlreq.h"
#ifdef USE_USBD_COMPOSITE
#include "usbd_composite_builder.h"
#endif
/** @defgroup USBD_HID
* @brief usbd core module
* @{
*/
/** @defgroup USBD_HID_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup USBD_HID_Private_Defines
* @{
*/
/**
* @}
*/
/** @defgroup USBD_HID_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup USBD_HID_Private_FunctionPrototypes
* @{
*/
static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
static uint8_t USBD_HID_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum);
static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum);
static uint8_t USBD_HID_EP0_RxReady(USBD_HandleTypeDef *pdev);
static uint8_t USBD_HID_Custom_SetReport_Setup_Stage(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *setup_data);
static uint8_t USBD_HID_Custom_SetReport_Token_Stage(USBD_HandleTypeDef *pdev);
static uint8_t USBD_HID_Custom_GetReport_Token_Stage(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *setup_data);
#ifndef USE_USBD_COMPOSITE
static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length);
static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length);
static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length);
static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length);
#endif /* USE_USBD_COMPOSITE */
/**
* @}
*/
/** @defgroup USBD_HID_Private_Variables
* @{
*/
USBD_ClassTypeDef USBD_HID_CUSTOM =
{
USBD_HID_Init,
USBD_HID_DeInit,
USBD_HID_Setup,
NULL, /* EP0_TxSent */
USBD_HID_EP0_RxReady, /* EP0_RxReady */
USBD_HID_DataIn, /* DataIn */
USBD_HID_DataOut, /* DataOut */
NULL, /* SOF */
NULL,
NULL,
#ifdef USE_USBD_COMPOSITE
NULL,
NULL,
NULL,
NULL,
#else
USBD_HID_GetHSCfgDesc,
USBD_HID_GetFSCfgDesc,
USBD_HID_GetOtherSpeedCfgDesc,
USBD_HID_GetDeviceQualifierDesc,
#endif /* USE_USBD_COMPOSITE */
};
#ifndef USE_USBD_COMPOSITE
/* USB HID device FS Configuration Descriptor */
__ALIGN_BEGIN static uint8_t USBD_HID_CUSTOM_CfgDesc[USB_HID_CUSTOM_CONFIG_DESC_SIZ] __ALIGN_END =
{
0x09, /* bLength: Configuration Descriptor size */
USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */
USB_HID_CUSTOM_CONFIG_DESC_SIZ, /* wTotalLength: Bytes returned */
0x00,
0x01, /* bNumInterfaces: 1 interface */
0x01, /* bConfigurationValue: Configuration value */
0x00, /* iConfiguration: Index of string descriptor
describing the configuration */
#if (USBD_SELF_POWERED == 1U)
0xE0, /* bmAttributes: Bus Powered according to user configuration */
#else
0xA0, /* bmAttributes: Bus Powered according to user configuration */
#endif /* USBD_SELF_POWERED */
USBD_MAX_POWER, /* MaxPower (mA) */
/************** Descriptor of Custom interface ****************/
/* 09 */
0x09, /* bLength: Interface Descriptor size */
USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */
0x00, /* bInterfaceNumber: Number of Interface */
0x00, /* bAlternateSetting: Alternate setting */
0x02, /* bNumEndpoints */
0x03, /* bInterfaceClass: HID */
0x00, /* bInterfaceSubClass : 1=BOOT, 0=no boot */
0x00, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */
0, /* iInterface: Index of string descriptor */
/******************** Descriptor of Joystick Custom HID ********************/
/* 18 */
0x09, /* bLength: HID Descriptor size */
HID_CUSTOM_DESCRIPTOR_TYPE, /* bDescriptorType: HID */
0x11, /* bcdHID: HID Class Spec release number */
0x01,
0x00, /* bCountryCode: Hardware target country */
0x01, /* bNumDescriptors: Number of HID class descriptors to follow */
0x22, /* bDescriptorType */
HID_CUSTOM_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */
0x00,
/******************** Descriptor of Custom endpoint ********************/
/* 27 */
0x07, /* bLength: Endpoint Descriptor size */
USB_DESC_TYPE_ENDPOINT, /* bDescriptorType:*/
HID_CUSTOM_EPIN_ADDR, /* bEndpointAddress: Endpoint Address (IN) */
0x03, /* bmAttributes: Interrupt endpoint */
HID_CUSTOM_EPIN_SIZE, /* wMaxPacketSize: 4 Bytes max */
0x00,
HID_CUSTOM_FS_BINTERVAL, /* bInterval: Polling Interval */
/******************** Descriptor of Custom endpoint ********************/
/* 34 */
0x07, /* bLength: Endpoint Descriptor size */
USB_DESC_TYPE_ENDPOINT, /* bDescriptorType:*/
HID_CUSTOM_EPOUT_ADDR, /* bEndpointAddress: Endpoint Address (IN) */
0x03, /* bmAttributes: Interrupt endpoint */
HID_CUSTOM_EPOUT_SIZE, /* wMaxPacketSize: 4 Bytes max */
0x00,
HID_CUSTOM_FS_BINTERVAL, /* bInterval: Polling Interval */
/* 41 */
};
#endif /* USE_USBD_COMPOSITE */
/* USB HID device Configuration Descriptor */
__ALIGN_BEGIN static uint8_t USBD_HID_Desc[USB_HID_CUSTOM_DESC_SIZ] __ALIGN_END =
{
/* 18 */
0x09, /* bLength: HID Descriptor size */
HID_CUSTOM_DESCRIPTOR_TYPE, /* bDescriptorType: HID */
0x11, /* bcdHID: HID Class Spec release number */
0x01,
0x00, /* bCountryCode: Hardware target country */
0x01, /* bNumDescriptors: Number of HID class descriptors to follow */
0x22, /* bDescriptorType */
HID_CUSTOM_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */
0x00,
};
#ifndef USE_USBD_COMPOSITE
/* USB Standard Device Descriptor */
__ALIGN_BEGIN static uint8_t USBD_HID_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END =
{
USB_LEN_DEV_QUALIFIER_DESC,
USB_DESC_TYPE_DEVICE_QUALIFIER,
0x00,
0x02,
0x00,
0x00,
0x00,
0x40,
0x01,
0x00,
};
#endif /* USE_USBD_COMPOSITE */
__ALIGN_BEGIN static uint8_t HID_Custom_ReportDesc[HID_CUSTOM_REPORT_DESC_SIZE] __ALIGN_END =
{
0x06, 0x00, 0xff, //USAGE_PAGE(Vendor Defined Page 1)
0x09, 0x01, //USAGE(Vendor Usage 1)
0xa1, 0x01, //COLLECTION (Application)
0x85, 0x01, //REPORT ID (0x01)
0x09, 0x01, //USAGE(Vendor Usage 1)
0x15, 0x00, //LOGICAL_MINIMUM (0)
0x26, 0xff, 0x00, //LOGICAL_MAXIMUM (255)
0x95, 0x40-0x01, //REPORT_COUNT (63)
0x75, 0x08, //REPORT_SIZE (8)
0x81, 0x02, //INPUT (Data,Var,Abs)
0x85, 0x02, //REPORT ID (0x02)
0x09, 0x01, //USAGE(Vendor Usage 1)
0x15, 0x00, //LOGICAL_MINIMUM (0)
0x26, 0xff, 0x00, //LOGICAL_MAXIMUM (255)
0x95, 0x40-0x01, //REPORT_COUNT (63)
0x75, 0x08, //REPORT_SIZE (8)
0x91, 0x02, //OUTPUT (Data,Var,Abs)
0xc0, //END_COLLECTION
USB_DFU_REPORT_MAP
};
static uint8_t HIDInEpAdd = HID_CUSTOM_EPIN_ADDR;
/**
* @}
*/
/** @defgroup USBD_HID_Private_Functions
* @{
*/
/**
* @brief USBD_HID_Init
* Initialize the HID interface
* @param pdev: device instance
* @param cfgidx: Configuration index
* @retval status
*/
static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
UNUSED(cfgidx);
USBD_HID_Custom_HandleTypeDef *hhid;
hhid = (USBD_HID_Custom_HandleTypeDef *)USBD_malloc(sizeof(USBD_HID_Custom_HandleTypeDef));
DEBUG("sizeof(USBD_HID_Custom_HandleTypeDef)=0x%x\n",sizeof(USBD_HID_Custom_HandleTypeDef));
if (hhid == NULL)
{
pdev->pClassDataCmsit[pdev->classId] = NULL;
return (uint8_t)USBD_EMEM;
}
pdev->pClassDataCmsit[pdev->classId] = (void *)hhid;
pdev->pClassData = pdev->pClassDataCmsit[pdev->classId];
#ifdef USE_USBD_COMPOSITE
/* Get the Endpoints addresses allocated for this class instance */
HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR);
#endif /* USE_USBD_COMPOSITE */
if (pdev->dev_speed == USBD_SPEED_HIGH)
{
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_CUSTOM_HS_BINTERVAL;
}
else /* LOW and FULL-speed endpoints */
{
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_CUSTOM_FS_BINTERVAL;
}
/* Open EP IN */
(void)USBD_LL_OpenEP(pdev, HIDInEpAdd, USBD_EP_TYPE_INTR, HID_CUSTOM_EPIN_SIZE);
pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 1U;
/* Open EP OUT */
(void)USBD_LL_OpenEP(pdev, HID_CUSTOM_EPOUT_ADDR, USBD_EP_TYPE_INTR, HID_CUSTOM_EPOUT_SIZE);
pdev->ep_out[HID_CUSTOM_EPOUT_ADDR & 0xFU].is_used = 1U;
/* Prepare Out endpoint to receive 1st packet */
(void)USBD_LL_PrepareReceive(pdev, HID_CUSTOM_EPOUT_ADDR, hhid->Report_buf,
HID_CUSTOM_EPOUT_SIZE);
hhid->state = CUSTOM_HID_IDLE;
return (uint8_t)USBD_OK;
}
/**
* @brief USBD_HID_DeInit
* DeInitialize the HID layer
* @param pdev: device instance
* @param cfgidx: Configuration index
* @retval status
*/
static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
UNUSED(cfgidx);
#ifdef USE_USBD_COMPOSITE
/* Get the Endpoints addresses allocated for this class instance */
HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR);
#endif /* USE_USBD_COMPOSITE */
/* Close HID EPs */
(void)USBD_LL_CloseEP(pdev, HIDInEpAdd);
pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 0U;
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = 0U;
/* Free allocated memory */
if (pdev->pClassDataCmsit[pdev->classId] != NULL)
{
(void)USBD_free(pdev->pClassDataCmsit[pdev->classId]);
pdev->pClassDataCmsit[pdev->classId] = NULL;
}
return (uint8_t)USBD_OK;
}
/**
* @brief USBD_HID_Setup
* Handle the HID specific requests
* @param pdev: instance
* @param req: usb requests
* @retval status
*/
static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
USBD_HID_Custom_HandleTypeDef *hhid = (USBD_HID_Custom_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
USBD_StatusTypeDef ret = USBD_OK;
uint16_t len;
uint8_t *pbuf;
uint16_t status_info = 0U;
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
switch (req->bmRequest & USB_REQ_TYPE_MASK)
{
case USB_REQ_TYPE_CLASS :
switch (req->bRequest)
{
case HID_CUSTOM_REQ_SET_PROTOCOL:
hhid->Protocol = (uint8_t)(req->wValue);
break;
case HID_CUSTOM_REQ_GET_PROTOCOL:
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->Protocol, 1U);
break;
case HID_CUSTOM_REQ_SET_IDLE:
hhid->IdleState = (uint8_t)(req->wValue >> 8);
break;
case HID_CUSTOM_REQ_GET_IDLE:
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->IdleState, 1U);
break;
case HID_CUSTOM_REQ_SET_REPORT:
USBD_HID_Custom_SetReport_Setup_Stage(pdev, req);
break;
case HID_CUSTOM_REQ_GET_REPORT:
USBD_HID_Custom_GetReport_Token_Stage(pdev, req);
break;
default:
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
break;
}
break;
case USB_REQ_TYPE_STANDARD:
switch (req->bRequest)
{
case USB_REQ_GET_STATUS:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
(void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U);
}
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
case USB_REQ_GET_DESCRIPTOR:
if ((req->wValue >> 8) == HID_CUSTOM_REPORT_DESC)
{
len = MIN(HID_CUSTOM_REPORT_DESC_SIZE, req->wLength);
pbuf = HID_Custom_ReportDesc;
}
else if ((req->wValue >> 8) == HID_CUSTOM_DESCRIPTOR_TYPE)
{
pbuf = USBD_HID_Desc;
len = MIN(USB_HID_CUSTOM_DESC_SIZ, req->wLength);
}
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
break;
}
(void)USBD_CtlSendData(pdev, pbuf, len);
break;
case USB_REQ_GET_INTERFACE :
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->AltSetting, 1U);
}
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
case USB_REQ_SET_INTERFACE:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
hhid->AltSetting = (uint8_t)(req->wValue);
}
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
case USB_REQ_CLEAR_FEATURE:
break;
default:
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
break;
}
break;
default:
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
break;
}
return (uint8_t)ret;
}
/**
* @brief USBD_HID_Custom_SendReport
* Send HID Report
* @param pdev: device instance
* @param buff: pointer to report
* @retval status
*/
uint8_t USBD_HID_Custom_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len)
{
#ifdef USE_USBD_COMPOSITE
uint8_t class_id;
class_id = USBD_CMPSIT_GetClassID_ByAdd(pdev, HID_CUSTOM_EPIN_ADDR, USBD_EP_TYPE_INTR);
USBD_HID_Custom_HandleTypeDef *hhid = (USBD_HID_Custom_HandleTypeDef *)pdev->pClassDataCmsit[class_id];
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
if (hhid->state == CUSTOM_HID_IDLE)
{
hhid->state = CUSTOM_HID_BUSY;
(void)USBD_LL_Transmit(pdev, HID_CUSTOM_EPIN_ADDR, report, len);
}
}
return (uint8_t)USBD_OK;
#else
USBD_HID_Custom_HandleTypeDef *hhid = (USBD_HID_Custom_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
if (hhid->state == CUSTOM_HID_IDLE)
{
hhid->state = CUSTOM_HID_BUSY;
(void)USBD_LL_Transmit(pdev, HID_CUSTOM_EPIN_ADDR, report, len);
}
}
return (uint8_t)USBD_OK;
#endif
}
extern uint8_t epnm_flag;
/**
* @brief USBD_HID_Custom_FirstSendReport
* Send HID Report
* @param pdev: device instance
* @param buff: pointer to report
* @retval status
*/
uint8_t USBD_HID_Custom_FirstSendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len)
{
#ifdef USE_USBD_COMPOSITE
uint8_t class_id;
uint8_t ep_id = HID_CUSTOM_EPIN_ADDR & 0xF;
class_id = USBD_CMPSIT_GetClassID_ByAdd(pdev, HID_CUSTOM_EPIN_ADDR, USBD_EP_TYPE_INTR);
USBD_HID_Custom_HandleTypeDef *hhid = (USBD_HID_Custom_HandleTypeDef *)pdev->pClassDataCmsit[class_id];
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
PCD_HandleTypeDef *pcd = (PCD_HandleTypeDef *)(pdev->pData);
uint32_t USBx_BASE = (uint32_t)(PCD_HandleTypeDef *)pcd->Instance;
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
if ((hhid->state == CUSTOM_HID_IDLE)||(epnm_flag == 0x01))
{
if(USBx_INEP(ep_id)->DIEPINT & USB_OTG_DIEPINT_ITTXFE)
{
USBx_INEP(ep_id)->DIEPINT |= USB_OTG_DIEPINT_ITTXFE;
hhid->state = CUSTOM_HID_BUSY;
(void)USBD_LL_Transmit(pdev, HID_CUSTOM_EPIN_ADDR, report, len);
}
else{
if(USBx_INEP(ep_id)->DIEPINT&USB_OTG_DIEPINT_NAK){
USBx_INEP(ep_id)->DIEPINT |= USB_OTG_DIEPINT_NAK;
USBx_INEP(ep_id)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
}
}
if(epnm_flag == 0x01){
epnm_flag = 0x00;
}
}
}
return (uint8_t)USBD_OK;
#else
uint8_t ep_id = HID_CUSTOM_EPIN_ADDR & 0xF;
USBD_HID_Custom_HandleTypeDef *hhid = (USBD_HID_Custom_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
PCD_HandleTypeDef *pcd = (PCD_HandleTypeDef *)(pdev->pData);
uint32_t USBx_BASE = (uint32_t)(PCD_HandleTypeDef *)pcd->Instance;
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
if ((hhid->state == CUSTOM_HID_IDLE)||(epnm_flag == 0x01))
{
if(USBx_INEP(ep_id)->DIEPINT&USB_OTG_DIEPINT_ITTXFE)
{
USBx_INEP(ep_id)->DIEPINT |= USB_OTG_DIEPINT_ITTXFE;
hhid->state = CUSTOM_HID_BUSY;
(void)USBD_LL_Transmit(pdev, HID_CUSTOM_EPIN_ADDR, report, len);
}
else{
if(USBx_INEP(ep_id)->DIEPINT&USB_OTG_DIEPINT_NAK){
USBx_INEP(ep_id)->DIEPINT |= USB_OTG_DIEPINT_NAK;
USBx_INEP(ep_id)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
}
}
if(epnm_flag == 0x01){
epnm_flag = 0x00;
}
}
}
return (uint8_t)USBD_OK;
#endif
}
/**
* @brief USBD_HID_GetPollingInterval
* return polling interval from endpoint descriptor
* @param pdev: device instance
* @retval polling interval
*/
uint32_t USBD_HID_Custom_GetPollingInterval(USBD_HandleTypeDef *pdev)
{
uint32_t polling_interval;
/* HIGH-speed endpoints */
if (pdev->dev_speed == USBD_SPEED_HIGH)
{
/* Sets the data transfer polling interval for high speed transfers.
Values between 1..16 are allowed. Values correspond to interval
of 2 ^ (bInterval-1). This option (8 ms, corresponds to HID_HS_BINTERVAL */
polling_interval = (((1U << (HID_CUSTOM_HS_BINTERVAL - 1U))) / 8U);
}
else /* LOW and FULL-speed endpoints */
{
/* Sets the data transfer polling interval for low and full
speed transfers */
polling_interval = HID_CUSTOM_FS_BINTERVAL;
}
return ((uint32_t)(polling_interval));
}
#ifndef USE_USBD_COMPOSITE
/**
* @brief USBD_HID_GetCfgFSDesc
* return FS configuration descriptor
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length)
{
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CUSTOM_CfgDesc, HID_CUSTOM_EPIN_ADDR);
if (pEpDesc != NULL)
{
pEpDesc->bInterval = HID_CUSTOM_FS_BINTERVAL;
}
*length = (uint16_t)sizeof(USBD_HID_CUSTOM_CfgDesc);
return USBD_HID_CUSTOM_CfgDesc;
}
/**
* @brief USBD_HID_GetCfgHSDesc
* return HS configuration descriptor
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length)
{
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CUSTOM_CfgDesc, HID_CUSTOM_EPIN_ADDR);
if (pEpDesc != NULL)
{
pEpDesc->bInterval = HID_CUSTOM_HS_BINTERVAL;
}
*length = (uint16_t)sizeof(USBD_HID_CUSTOM_CfgDesc);
return USBD_HID_CUSTOM_CfgDesc;
}
/**
* @brief USBD_HID_GetOtherSpeedCfgDesc
* return other speed configuration descriptor
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length)
{
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CUSTOM_CfgDesc, HID_CUSTOM_EPIN_ADDR);
if (pEpDesc != NULL)
{
pEpDesc->bInterval = HID_CUSTOM_FS_BINTERVAL;
}
*length = (uint16_t)sizeof(USBD_HID_CUSTOM_CfgDesc);
return USBD_HID_CUSTOM_CfgDesc;
}
#endif /* USE_USBD_COMPOSITE */
/**
* @brief USBD_HID_DataIn
* handle data IN Stage
* @param pdev: device instance
* @param epnum: endpoint index
* @retval status
*/
static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum)
{
UNUSED(epnum);
/* Ensure that the FIFO is empty before a new transfer, this condition could
be caused by a new transfer before the end of the previous transfer */
((USBD_HID_Custom_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId])->state = CUSTOM_HID_IDLE;
return (uint8_t)USBD_OK;
}
extern PCD_HandleTypeDef hpcd_USB_OTG_FS;
/**
* @brief USBD_HID_DataOut
* handle data OUT Stage
* @param pdev: device instance
* @param epnum: endpoint index
* @retval status
*/
static uint8_t USBD_HID_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum)
{
UNUSED(epnum);
uint8_t size_num;
USBD_HID_Custom_HandleTypeDef *hhid;
hhid = pdev->pClassData;
/* Ensure that the FIFO is empty before a new transfer, this condition could
be caused by a new transfer before the end of the previous transfer */
size_num = HAL_PCD_EP_GetRxCount(&hpcd_USB_OTG_FS,HID_CUSTOM_EPOUT_ADDR);
(void)USBD_LL_PrepareReceive(pdev, HID_CUSTOM_EPOUT_ADDR, hhid->Report_buf,HID_CUSTOM_EPOUT_SIZE);
for(int i=0;i<size_num;i++)
{
DEBUG("0x%x ",hhid->Report_buf[i]);
}
DEBUG("\n");
hhid->state = CUSTOM_HID_IDLE;
return (uint8_t)USBD_OK;
}
static uint8_t USBD_HID_EP0_RxReady(USBD_HandleTypeDef *pdev)
{
DEBUG("Custom USBD_HID_EP0_RxReady\r\n");
USBD_HID_Custom_SetReport_Token_Stage(pdev);
return (uint8_t)USBD_OK;
}
uint8_t USBD_HID_Custom_SetReport_Setup_Stage(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *setup_data)
{
uint8_t report_type;
uint8_t report_id;
#ifdef USE_USBD_COMPOSITE
uint8_t class_id;
class_id = USBD_CMPSIT_GetClassID_ByAdd(pdev, HID_CUSTOM_EPIN_ADDR, USBD_EP_TYPE_INTR);
USBD_HID_Custom_HandleTypeDef *hhid = (USBD_HID_Custom_HandleTypeDef *)pdev->pClassDataCmsit[class_id];
#else
USBD_HID_Custom_HandleTypeDef *hhid = (USBD_HID_Custom_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
#endif
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
report_type = (setup_data->wValue >> 8) & 0xFF;
report_id = setup_data->wValue & 0xFF;
hhid->EP0_ReportLen = setup_data->wLength;
DEBUG("Setup_Stage report_type=%02x, report_id=%02x, report_len=%d\r\n",report_type, report_id, hhid->EP0_ReportLen);
(void)USBD_CtlPrepareRx(pdev, hhid->EP0_ReportBuff, hhid->EP0_ReportLen);
return (uint8_t)USBD_OK;
}
uint8_t USBD_HID_Custom_SetReport_Token_Stage(USBD_HandleTypeDef *pdev)
{
#ifdef USE_USBD_COMPOSITE
uint8_t class_id;
class_id = USBD_CMPSIT_GetClassID_ByAdd(pdev, HID_CUSTOM_EPIN_ADDR, USBD_EP_TYPE_INTR);
USBD_HID_Custom_HandleTypeDef *hhid = (USBD_HID_Custom_HandleTypeDef *)pdev->pClassDataCmsit[class_id];
#else
USBD_HID_Custom_HandleTypeDef *hhid = (USBD_HID_Custom_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
#endif
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
DEBUG("Token_Stage recv len = %d\n", hhid->EP0_ReportLen);
for(int i=0;i<hhid->EP0_ReportLen;i++){
DEBUG("0x%x ", hhid->EP0_ReportBuff[i]);
}DEBUG("\n");
return (uint8_t)USBD_OK;
}
uint8_t USBD_HID_Custom_GetReport_Token_Stage(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *setup_data)
{
uint16_t report_length;
uint8_t data[HID_CUSTOM_EP0_GET_REPORT_BUF_SIZE];
DEBUG("%s,%d\n",__func__,__LINE__);
#ifdef USE_USBD_COMPOSITE
uint8_t class_id;
class_id = USBD_CMPSIT_GetClassID_ByAdd(pdev, HID_CUSTOM_EPIN_ADDR, USBD_EP_TYPE_INTR);
USBD_HID_Custom_HandleTypeDef *hhid = (USBD_HID_Custom_HandleTypeDef *)pdev->pClassDataCmsit[class_id];
#else
USBD_HID_Custom_HandleTypeDef *hhid = (USBD_HID_Custom_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
#endif
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
for(int i=0;i<HID_CUSTOM_EP0_GET_REPORT_BUF_SIZE;i++)
{
data[i] = i;
}
report_length = setup_data->wLength;
USBD_CtlSendData(pdev, data, report_length);
return (uint8_t)USBD_OK;
}
#ifndef USE_USBD_COMPOSITE
/**
* @brief DeviceQualifierDescriptor
* return Device Qualifier descriptor
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length)
{
*length = (uint16_t)sizeof(USBD_HID_DeviceQualifierDesc);
return USBD_HID_DeviceQualifierDesc;
}
#endif /* USE_USBD_COMPOSITE */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
component/xc6xx_drivers/Drivers/USB/Middlewares/Library/Class/HID/Src/usbd_hid_keyboard.c
+864
View File
@@ -0,0 +1,864 @@
/*!
* \file usbd_hid_keyboard.c
*
* \brief This file provides the HID core functions.
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author MCD Application Team
*
* \author ( XinChip ) Alex-J
*
* @verbatim
*
* ===================================================================
* HID Class Description
* ===================================================================
* This module manages the HID class V1.11 following the "Device Class Definition
* for Human Interface Devices (HID) Version 1.11 Jun 27, 2001".
* This driver implements the following aspects of the specification:
* - The Boot Interface Subclass
* - The Mouse protocol
* - Usage Page : Generic Desktop
* - Usage : Keyboard
* - Collection : Application
*
* @note In HS mode and when the DMA is used, all variables and data structures
* dealing with the DMA during the transaction process should be 32-bit aligned.
*
*
* @endverbatim
*
*/
/* Includes ------------------------------------------------------------------*/
#include "usbd_hid_keyboard.h"
#include "usbd_ctlreq.h"
#ifdef USE_USBD_COMPOSITE
#include "usbd_composite_builder.h"
#endif
/** @defgroup USBD_HID
* @brief usbd core module
* @{
*/
/** @defgroup USBD_HID_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup USBD_HID_Private_Defines
* @{
*/
/**
* @}
*/
/** @defgroup USBD_HID_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup USBD_HID_Private_FunctionPrototypes
* @{
*/
static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum);
static uint8_t USBD_HID_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum);
static uint8_t USBD_HID_EP0_RxReady(USBD_HandleTypeDef *pdev);
static uint8_t USBD_HID_Keyboard_SetReport_Setup_Stage(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *setup_data);
static uint8_t USBD_HID_Keyboard_SetReport_Token_Stage(USBD_HandleTypeDef *pdev);
static uint8_t USBD_HID_Keyboard_GetReport_Token_Stage(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *setup_data);
#ifndef USE_USBD_COMPOSITE
static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length);
static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length);
static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length);
static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length);
#endif /* USE_USBD_COMPOSITE */
/**
* @}
*/
/** @defgroup USBD_HID_Private_Variables
* @{
*/
USBD_ClassTypeDef USBD_HID_KEYBOARD =
{
USBD_HID_Init,
USBD_HID_DeInit,
USBD_HID_Setup,
NULL, /* EP0_TxSent */
USBD_HID_EP0_RxReady, /* EP0_RxReady */
USBD_HID_DataIn, /* DataIn */
USBD_HID_DataOut, /* DataOut */
NULL, /* SOF */
NULL,
NULL,
#ifdef USE_USBD_COMPOSITE
NULL,
NULL,
NULL,
NULL,
#else
USBD_HID_GetHSCfgDesc,
USBD_HID_GetFSCfgDesc,
USBD_HID_GetOtherSpeedCfgDesc,
USBD_HID_GetDeviceQualifierDesc,
#endif /* USE_USBD_COMPOSITE */
};
#ifndef USE_USBD_COMPOSITE
/* USB HID device FS Configuration Descriptor */
__ALIGN_BEGIN static uint8_t USBD_HID_CfgDesc[USB_HID_KEYBOARD_CONFIG_DESC_SIZ] __ALIGN_END =
{
0x09, /* bLength: Configuration Descriptor size */
USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */
USB_HID_KEYBOARD_CONFIG_DESC_SIZ, /* wTotalLength: Bytes returned */
0x00,
0x01, /* bNumInterfaces: 1 interface */
0x01, /* bConfigurationValue: Configuration value */
0x00, /* iConfiguration: Index of string descriptor
describing the configuration */
#if (USBD_SELF_POWERED == 1U)
0xE0, /* bmAttributes: Bus Powered according to user configuration */
#else
0xA0, /* bmAttributes: Bus Powered according to user configuration */
#endif /* USBD_SELF_POWERED */
USBD_MAX_POWER, /* MaxPower (mA) */
/************** Descriptor of Keyboard interface ****************/
/* 09 */
0x09, /* bLength: Interface Descriptor size */
USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */
0x00, /* bInterfaceNumber: Number of Interface */
0x00, /* bAlternateSetting: Alternate setting */
0x02, /* bNumEndpoints */
0x03, /* bInterfaceClass: HID */
0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */
0x01, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */
0, /* iInterface: Index of string descriptor */
/******************** Descriptor of Keyboard HID ********************/
/* 18 */
0x09, /* bLength: HID Descriptor size */
HID_KEYBOARD_DESCRIPTOR_TYPE, /* bDescriptorType: HID */
0x11, /* bcdHID: HID Class Spec release number */
0x01,
0x00, /* bCountryCode: Hardware target country */
0x01, /* bNumDescriptors: Number of HID class descriptors to follow */
0x22, /* bDescriptorType */
HID_KEYBOARD_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */
0x00,
/******************** Descriptor of Keyboard endpoint ********************/
/* 27 */
0x07, /* bLength: Endpoint Descriptor size */
USB_DESC_TYPE_ENDPOINT, /* bDescriptorType:*/
HID_KEYBOARD_EPIN_ADDR, /* bEndpointAddress: Endpoint Address (IN) */
0x03, /* bmAttributes: Interrupt endpoint */
HID_KEYBOARD_EPIN_SIZE, /* wMaxPacketSize: 4 Byte max */
0x00,
HID_KEYBOARD_FS_BINTERVAL, /* bInterval: Polling Interval */
/* 34 */
0x07, /* bLength: Endpoint Descriptor size */
USB_DESC_TYPE_ENDPOINT, /* bDescriptorType:*/
HID_KEYBOARD_EPOUT_ADDR, /* bEndpointAddress: Endpoint Address (IN) */
0x03, /* bmAttributes: Interrupt endpoint */
HID_KEYBOARD_EPOUT_SIZE, /* wMaxPacketSize: 4 Byte max */
0x00,
HID_KEYBOARD_FS_BINTERVAL, /* bInterval: Polling Interval */
/* 41 */
};
#endif /* USE_USBD_COMPOSITE */
/* USB HID device Configuration Descriptor */
__ALIGN_BEGIN static uint8_t USBD_HID_Desc[USB_HID_KEYBOARD_DESC_SIZ] __ALIGN_END =
{
/* 18 */
0x09, /* bLength: HID Descriptor size */
HID_KEYBOARD_DESCRIPTOR_TYPE, /* bDescriptorType: HID */
0x11, /* bcdHID: HID Class Spec release number */
0x01,
0x00, /* bCountryCode: Hardware target country */
0x01, /* bNumDescriptors: Number of HID class descriptors to follow */
0x22, /* bDescriptorType */
HID_KEYBOARD_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */
0x00,
};
#ifndef USE_USBD_COMPOSITE
/* USB Standard Device Descriptor */
__ALIGN_BEGIN static uint8_t USBD_HID_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END =
{
USB_LEN_DEV_QUALIFIER_DESC,
USB_DESC_TYPE_DEVICE_QUALIFIER,
0x00,
0x02,
0x00,
0x00,
0x00,
0x40,
0x01,
0x00,
};
#endif /* USE_USBD_COMPOSITE */
__ALIGN_BEGIN static uint8_t HID_Keyboard_ReportDesc[HID_KEYBOARD_REPORT_DESC_SIZE] __ALIGN_END =
{
0x05, 0x01, // Usage Page (Generic Desktop Ctrls)
0x09, 0x06, // Usage (Keyboard)
0xA1, 0x01, // Collection (Application)
0x05, 0x07, // Usage Page (Kbrd/Keypad)
0x19, 0xE0, // Usage Minimum (0xE0)
0x29, 0xE7, // Usage Maximum (0xE7)
0x15, 0x00, // Logical Minimum (0)
0x25, 0x01, // Logical Maximum (1)
0x75, 0x01, // Report Size (1)
0x95, 0x08, // Report Count (8)
0x81, 0x02, // Input (Data,Var,Abs,No Wrap,Linear,Preferred State,No Null Position)
0x95, 0x01, // Report Count (1)
0x75, 0x08, // Report Size (8)
0x81, 0x03, // Input (Const,Var,Abs,No Wrap,Linear,Preferred State,No Null Position)
0x95, 0x05, // Report Count (5)
0x75, 0x01, // Report Size (1)
0x05, 0x08, // Usage Page (LEDs)
0x19, 0x01, // Usage Minimum (Num Lock)
0x29, 0x05, // Usage Maximum (Kana)
0x91, 0x02, // Output (Data,Var,Abs,No Wrap,Linear,Preferred State,No Null Position,Non-volatile)
0x95, 0x01, // Report Count (1)
0x75, 0x03, // Report Size (3)
0x91, 0x03, // Output (Const,Var,Abs,No Wrap,Linear,Preferred State,No Null Position,Non-volatile)
0x95, 0x06, // Report Count (6)
0x75, 0x08, // Report Size (8)
0x15, 0x00, // Logical Minimum (0)
0x25, 0x65, // Logical Maximum (101)
0x05, 0x07, // Usage Page (Kbrd/Keypad)
0x19, 0x00, // Usage Minimum (Reserved (no event indicated))
0x29, 0x65, // Usage Maximum (0x65)
0x81, 0x00, // Input (Data,Array,Abs,No Wrap,Linear,Preferred State,No Null Position)
0xC0, // End Collection
};
static uint8_t HIDInEpAdd = HID_KEYBOARD_EPIN_ADDR;
/**
* @}
*/
/** @defgroup USBD_HID_Private_Functions
* @{
*/
/**
* @brief USBD_HID_Init
* Initialize the HID interface
* @param pdev: device instance
* @param cfgidx: Configuration index
* @retval status
*/
static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
UNUSED(cfgidx);
USBD_HID_Keyboard_HandleTypeDef *hhid;
hhid = (USBD_HID_Keyboard_HandleTypeDef *)USBD_malloc(sizeof(USBD_HID_Keyboard_HandleTypeDef));
DEBUG("sizeof(USBD_HID_Keyboard_HandleTypeDef)=0x%x\n",sizeof(USBD_HID_Keyboard_HandleTypeDef));
if (hhid == NULL)
{
pdev->pClassDataCmsit[pdev->classId] = NULL;
return (uint8_t)USBD_EMEM;
}
pdev->pClassDataCmsit[pdev->classId] = (void *)hhid;
pdev->pClassData = pdev->pClassDataCmsit[pdev->classId];
#ifdef USE_USBD_COMPOSITE
/* Get the Endpoints addresses allocated for this class instance */
HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR);
#endif /* USE_USBD_COMPOSITE */
if (pdev->dev_speed == USBD_SPEED_HIGH)
{
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_KEYBOARD_HS_BINTERVAL;
}
else /* LOW and FULL-speed endpoints */
{
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_KEYBOARD_FS_BINTERVAL;
}
/* Open EP IN */
(void)USBD_LL_OpenEP(pdev, HIDInEpAdd, USBD_EP_TYPE_INTR, HID_KEYBOARD_EPIN_SIZE);
pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 1U;
/* Open EP OUT */
(void)USBD_LL_OpenEP(pdev, HID_KEYBOARD_EPOUT_ADDR, USBD_EP_TYPE_INTR, HID_KEYBOARD_EPOUT_SIZE);
pdev->ep_out[HID_KEYBOARD_EPOUT_ADDR & 0xFU].is_used = 1U;
/* Prepare Out endpoint to receive 1st packet */
(void)USBD_LL_PrepareReceive(pdev, HID_KEYBOARD_EPOUT_ADDR, hhid->Report_buf,
USBD_KEYBOARD_OUTREPORT_BUF_SIZE);
hhid->state = KEYBOARD_HID_IDLE;
return (uint8_t)USBD_OK;
}
/**
* @brief USBD_HID_DeInit
* DeInitialize the HID layer
* @param pdev: device instance
* @param cfgidx: Configuration index
* @retval status
*/
static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
UNUSED(cfgidx);
#ifdef USE_USBD_COMPOSITE
/* Get the Endpoints addresses allocated for this class instance */
HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR);
#endif /* USE_USBD_COMPOSITE */
/* Close HID EPs */
(void)USBD_LL_CloseEP(pdev, HIDInEpAdd);
pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 0U;
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = 0U;
/* Free allocated memory */
if (pdev->pClassDataCmsit[pdev->classId] != NULL)
{
(void)USBD_free(pdev->pClassDataCmsit[pdev->classId]);
pdev->pClassDataCmsit[pdev->classId] = NULL;
}
return (uint8_t)USBD_OK;
}
/**
* @brief USBD_HID_Setup
* Handle the HID specific requests
* @param pdev: instance
* @param req: usb requests
* @retval status
*/
static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
USBD_HID_Keyboard_HandleTypeDef *hhid = (USBD_HID_Keyboard_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
USBD_StatusTypeDef ret = USBD_OK;
uint16_t len;
uint8_t *pbuf;
uint16_t status_info = 0U;
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
switch (req->bmRequest & USB_REQ_TYPE_MASK)
{
case USB_REQ_TYPE_CLASS :
switch (req->bRequest)
{
case HID_KEYBOARD_REQ_SET_PROTOCOL:
hhid->Protocol = (uint8_t)(req->wValue);
break;
case HID_KEYBOARD_REQ_GET_PROTOCOL:
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->Protocol, 1U);
break;
case HID_KEYBOARD_REQ_SET_IDLE:
hhid->IdleState = (uint8_t)(req->wValue >> 8);
break;
case HID_KEYBOARD_REQ_GET_IDLE:
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->IdleState, 1U);
break;
case HID_KEYBOARD_REQ_SET_REPORT:
USBD_HID_Keyboard_SetReport_Setup_Stage(pdev, req);
break;
case HID_KEYBOARD_REQ_GET_REPORT:
USBD_HID_Keyboard_GetReport_Token_Stage(pdev, req);
break;
default:
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
break;
}
break;
case USB_REQ_TYPE_STANDARD:
switch (req->bRequest)
{
case USB_REQ_GET_STATUS:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
(void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U);
}
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
case USB_REQ_GET_DESCRIPTOR:
if ((req->wValue >> 8) == HID_KEYBOARD_REPORT_DESC)
{
len = MIN(HID_KEYBOARD_REPORT_DESC_SIZE, req->wLength);
pbuf = HID_Keyboard_ReportDesc;
}
else if ((req->wValue >> 8) == HID_KEYBOARD_DESCRIPTOR_TYPE)
{
pbuf = USBD_HID_Desc;
len = MIN(USB_HID_KEYBOARD_DESC_SIZ, req->wLength);
}
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
break;
}
(void)USBD_CtlSendData(pdev, pbuf, len);
break;
case USB_REQ_GET_INTERFACE :
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->AltSetting, 1U);
}
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
case USB_REQ_SET_INTERFACE:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
hhid->AltSetting = (uint8_t)(req->wValue);
}
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
case USB_REQ_CLEAR_FEATURE:
break;
default:
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
break;
}
break;
default:
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
break;
}
return (uint8_t)ret;
}
/**
* @brief USBD_HID_Keyboard_SendReport
* Send HID Report
* @param pdev: device instance
* @param buff: pointer to report
* @retval status
*/
uint8_t USBD_HID_Keyboard_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len)
{
#ifdef USE_USBD_COMPOSITE
uint8_t class_id;
class_id = USBD_CMPSIT_GetClassID_ByAdd(pdev, HID_KEYBOARD_EPIN_ADDR, USBD_EP_TYPE_INTR);
USBD_HID_Keyboard_HandleTypeDef *hhid = (USBD_HID_Keyboard_HandleTypeDef *)pdev->pClassDataCmsit[class_id];
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
if (hhid->state == KEYBOARD_HID_IDLE)
{
hhid->state = KEYBOARD_HID_BUSY;
(void)USBD_LL_Transmit(pdev, HID_KEYBOARD_EPIN_ADDR, report, len);
}
}
#endif
return (uint8_t)USBD_OK;
}
extern uint8_t epnm_flag;
uint8_t USBD_HID_Keyboard_FirstSendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len)
{
#ifdef USE_USBD_COMPOSITE
static uint8_t first_send_flag = 0;
uint8_t class_id;
uint8_t ep_id = HID_KEYBOARD_EPIN_ADDR & 0xF;
if(first_send_flag == 1){
return (uint8_t)USBD_OK;
}
class_id = USBD_CMPSIT_GetClassID_ByAdd(pdev, HID_KEYBOARD_EPIN_ADDR, USBD_EP_TYPE_INTR);
USBD_HID_Keyboard_HandleTypeDef *hhid = (USBD_HID_Keyboard_HandleTypeDef *)pdev->pClassDataCmsit[class_id];
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
PCD_HandleTypeDef *pcd = (PCD_HandleTypeDef *)(pdev->pData);
uint32_t USBx_BASE = (uint32_t)(PCD_HandleTypeDef *)pcd->Instance;
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
if ((hhid->state == KEYBOARD_HID_IDLE)||(epnm_flag == 0x01))
{
if(USBx_INEP(ep_id)->DIEPINT&USB_OTG_DIEPINT_ITTXFE)
{
USBx_INEP(ep_id)->DIEPINT |= USB_OTG_DIEPINT_ITTXFE;
hhid->state = KEYBOARD_HID_BUSY;
(void)USBD_LL_Transmit(pdev, HID_KEYBOARD_EPIN_ADDR, report, len);
}
else{
if(USBx_INEP(ep_id)->DIEPINT&USB_OTG_DIEPINT_NAK){
USBx_INEP(ep_id)->DIEPINT |= USB_OTG_DIEPINT_NAK;
USBx_INEP(ep_id)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
}
}
if(epnm_flag == 0x01){
epnm_flag = 0x00;
}
}
}
return (uint8_t)USBD_OK;
#else
uint8_t ep_id = HID_KEYBOARD_EPIN_ADDR & 0xF;
USBD_HID_Keyboard_HandleTypeDef *hhid = (USBD_HID_Keyboard_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
PCD_HandleTypeDef *pcd = (PCD_HandleTypeDef *)(pdev->pData);
uint32_t USBx_BASE = (uint32_t)(PCD_HandleTypeDef *)pcd->Instance;
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
if ((hhid->state == KEYBOARD_HID_IDLE)||(epnm_flag == 0x01))
{
if(USBx_INEP(ep_id)->DIEPINT&USB_OTG_DIEPINT_ITTXFE)
{
USBx_INEP(ep_id)->DIEPINT |= USB_OTG_DIEPINT_ITTXFE ;
hhid->state = KEYBOARD_HID_BUSY;
(void)USBD_LL_Transmit(pdev, HID_KEYBOARD_EPIN_ADDR, report, len);
}
else{
if(USBx_INEP(ep_id)->DIEPINT&USB_OTG_DIEPINT_NAK){
USBx_INEP(ep_id)->DIEPINT |= USB_OTG_DIEPINT_NAK;
USBx_INEP(ep_id)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
}
}
if(epnm_flag == 0x01){
epnm_flag = 0x00;
}
}
}
return (uint8_t)USBD_OK;
#endif
}
/**
* @brief USBD_HID_GetPollingInterval
* return polling interval from endpoint descriptor
* @param pdev: device instance
* @retval polling interval
*/
uint32_t USBD_HID_KEYBOARD_GetPollingInterval(USBD_HandleTypeDef *pdev)
{
uint32_t polling_interval;
/* HIGH-speed endpoints */
if (pdev->dev_speed == USBD_SPEED_HIGH)
{
/* Sets the data transfer polling interval for high speed transfers.
Values between 1..16 are allowed. Values correspond to interval
of 2 ^ (bInterval-1). This option (8 ms, corresponds to HID_HS_BINTERVAL */
polling_interval = (((1U << (HID_KEYBOARD_HS_BINTERVAL - 1U))) / 8U);
}
else /* LOW and FULL-speed endpoints */
{
/* Sets the data transfer polling interval for low and full
speed transfers */
polling_interval = HID_KEYBOARD_FS_BINTERVAL;
}
return ((uint32_t)(polling_interval));
}
#ifndef USE_USBD_COMPOSITE
/**
* @brief USBD_HID_GetCfgFSDesc
* return FS configuration descriptor
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length)
{
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_KEYBOARD_EPIN_ADDR);
if (pEpDesc != NULL)
{
pEpDesc->bInterval = HID_KEYBOARD_FS_BINTERVAL;
}
*length = (uint16_t)sizeof(USBD_HID_CfgDesc);
return USBD_HID_CfgDesc;
}
/**
* @brief USBD_HID_GetCfgHSDesc
* return HS configuration descriptor
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length)
{
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_KEYBOARD_EPIN_ADDR);
if (pEpDesc != NULL)
{
pEpDesc->bInterval = HID_KEYBOARD_HS_BINTERVAL;
}
*length = (uint16_t)sizeof(USBD_HID_CfgDesc);
return USBD_HID_CfgDesc;
}
/**
* @brief USBD_HID_GetOtherSpeedCfgDesc
* return other speed configuration descriptor
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length)
{
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_KEYBOARD_EPIN_ADDR);
if (pEpDesc != NULL)
{
pEpDesc->bInterval = HID_KEYBOARD_FS_BINTERVAL;
}
*length = (uint16_t)sizeof(USBD_HID_CfgDesc);
return USBD_HID_CfgDesc;
}
#endif /* USE_USBD_COMPOSITE */
/**
* @brief USBD_HID_DataIn
* handle data IN Stage
* @param pdev: device instance
* @param epnum: endpoint index
* @retval status
*/
static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum)
{
UNUSED(epnum);
/* Ensure that the FIFO is empty before a new transfer, this condition could
be caused by a new transfer before the end of the previous transfer */
((USBD_HID_Keyboard_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId])->state = KEYBOARD_HID_IDLE;
return (uint8_t)USBD_OK;
}
extern PCD_HandleTypeDef hpcd_USB_OTG_FS;
/**
* @brief USBD_CUSTOM_HID_DataOut
* handle data OUT Stage
* @param pdev: device instance
* @param epnum: endpoint index
* @retval status
*/
static uint8_t USBD_HID_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum)
{
DEBUG("line=%d,epnum=0x%x\n",__LINE__,epnum);
uint8_t size_num;
USBD_HID_Keyboard_HandleTypeDef *hhid;
hhid = pdev->pClassData;
/* Ensure that the FIFO is empty before a new transfer, this condition could
be caused by a new transfer before the end of the previous transfer */
size_num = HAL_PCD_EP_GetRxCount(&hpcd_USB_OTG_FS,HID_KEYBOARD_EPOUT_ADDR);
(void)USBD_LL_PrepareReceive(pdev, HID_KEYBOARD_EPOUT_ADDR, hhid->Report_buf,HID_KEYBOARD_EPOUT_SIZE);
for(int i=0;i<size_num;i++)
{
DEBUG("0x%x ", hhid->Report_buf[i]);
}
DEBUG("\n");
hhid->state = KEYBOARD_HID_IDLE;
return (uint8_t)USBD_OK;
}
static uint8_t USBD_HID_EP0_RxReady(USBD_HandleTypeDef *pdev)
{
DEBUG("Keyboard USBD_HID_EP0_RxReady\r\n");
USBD_HID_Keyboard_SetReport_Token_Stage(pdev);
return (uint8_t)USBD_OK;
}
uint8_t USBD_HID_Keyboard_SetReport_Setup_Stage(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *setup_data)
{
uint8_t report_type;
uint8_t report_id;
#ifdef USE_USBD_COMPOSITE
uint8_t class_id;
class_id = USBD_CMPSIT_GetClassID_ByAdd(pdev, HID_KEYBOARD_EPIN_ADDR, USBD_EP_TYPE_INTR);
USBD_HID_Keyboard_HandleTypeDef *hhid = (USBD_HID_Keyboard_HandleTypeDef *)pdev->pClassDataCmsit[class_id];
#else
USBD_HID_Keyboard_HandleTypeDef *hhid = (USBD_HID_Keyboard_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
#endif
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
report_type = (setup_data->wValue >> 8) & 0xFF;
report_id = setup_data->wValue & 0xFF;
hhid->EP0_ReportLen = setup_data->wLength;
DEBUG("Setup_Stage report_type=%02x, report_id=%02x, report_len=%d\r\n",report_type, report_id, hhid->EP0_ReportLen);
(void)USBD_CtlPrepareRx(pdev, hhid->EP0_ReportBuff, hhid->EP0_ReportLen);
return (uint8_t)USBD_OK;
}
uint8_t USBD_HID_Keyboard_SetReport_Token_Stage(USBD_HandleTypeDef *pdev)
{
#ifdef USE_USBD_COMPOSITE
uint8_t class_id;
class_id = USBD_CMPSIT_GetClassID_ByAdd(pdev, HID_KEYBOARD_EPIN_ADDR, USBD_EP_TYPE_INTR);
USBD_HID_Keyboard_HandleTypeDef *hhid = (USBD_HID_Keyboard_HandleTypeDef *)pdev->pClassDataCmsit[class_id];
#else
USBD_HID_Keyboard_HandleTypeDef *hhid = (USBD_HID_Keyboard_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
#endif
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
DEBUG("Token_Stage recv len = %d\n", hhid->EP0_ReportLen);
for(int i=0;i<hhid->EP0_ReportLen;i++){
DEBUG("0x%x ", hhid->EP0_ReportBuff[i]);
}DEBUG("\n");
return (uint8_t)USBD_OK;
}
uint8_t USBD_HID_Keyboard_GetReport_Token_Stage(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *setup_data)
{
uint16_t report_length;
uint8_t data[HID_KEYBOARD_EP0_GET_REPORT_BUF_SIZE];
DEBUG("%s,%d\n",__func__,__LINE__);
#ifdef USE_USBD_COMPOSITE
uint8_t class_id;
class_id = USBD_CMPSIT_GetClassID_ByAdd(pdev, HID_KEYBOARD_EPIN_ADDR, USBD_EP_TYPE_INTR);
USBD_HID_Keyboard_HandleTypeDef *hhid = (USBD_HID_Keyboard_HandleTypeDef *)pdev->pClassDataCmsit[class_id];
#else
USBD_HID_Keyboard_HandleTypeDef *hhid = (USBD_HID_Keyboard_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
#endif
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
for(int i=0;i<HID_KEYBOARD_EP0_GET_REPORT_BUF_SIZE;i++)
{
data[i] = i;
}
report_length = setup_data->wLength;
USBD_CtlSendData(pdev, data, report_length);
return (uint8_t)USBD_OK;
}
#ifndef USE_USBD_COMPOSITE
/**
* @brief DeviceQualifierDescriptor
* return Device Qualifier descriptor
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length)
{
*length = (uint16_t)sizeof(USBD_HID_DeviceQualifierDesc);
return USBD_HID_DeviceQualifierDesc;
}
#endif /* USE_USBD_COMPOSITE */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
component/xc6xx_drivers/Drivers/USB/Middlewares/Library/Class/HID/Src/usbd_hid_mouse.c
+842
View File
@@ -0,0 +1,842 @@
/*!
* \file usbd_hid_mouse.c
*
* \brief This file provides the HID core functions.
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author MCD Application Team
*
* \author ( XinChip ) Alex-J
*
* @verbatim
*
* ===================================================================
* HID Class Description
* ===================================================================
* This module manages the HID class V1.11 following the "Device Class Definition
* for Human Interface Devices (HID) Version 1.11 Jun 27, 2001".
* This driver implements the following aspects of the specification:
* - The Boot Interface Subclass
* - The Mouse protocol
* - Usage Page : Generic Desktop
* - Usage : Mouse
* - Collection : Application
*
* @note In HS mode and when the DMA is used, all variables and data structures
* dealing with the DMA during the transaction process should be 32-bit aligned.
*
*
* @endverbatim
*
*/
/* Includes ------------------------------------------------------------------*/
#include "usbd_hid_mouse.h"
#include "usbd_ctlreq.h"
#ifdef USE_USBD_COMPOSITE
#include "usbd_composite_builder.h"
#endif
/** @defgroup USBD_HID
* @brief usbd core module
* @{
*/
/** @defgroup USBD_HID_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup USBD_HID_Private_Defines
* @{
*/
/**
* @}
*/
/** @defgroup USBD_HID_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup USBD_HID_Private_FunctionPrototypes
* @{
*/
static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum);
static uint8_t USBD_HID_EP0_RxReady(USBD_HandleTypeDef *pdev);
static uint8_t USBD_HID_Mouse_SetReport_Setup_Stage(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *setup_data);
static uint8_t USBD_HID_Mouse_SetReport_Token_Stage(USBD_HandleTypeDef *pdev);
static uint8_t USBD_HID_Mouse_GetReport_Token_Stage(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *setup_data);
#ifndef USE_USBD_COMPOSITE
static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length);
static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length);
static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length);
static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length);
#endif /* USE_USBD_COMPOSITE */
/**
* @}
*/
/** @defgroup USBD_HID_Private_Variables
* @{
*/
USBD_ClassTypeDef USBD_HID_MOUSE =
{
USBD_HID_Init,
USBD_HID_DeInit,
USBD_HID_Setup,
NULL, /* EP0_TxSent */
USBD_HID_EP0_RxReady, /* EP0_RxReady */
USBD_HID_DataIn, /* DataIn */
NULL, /* DataOut */
NULL, /* SOF */
NULL,
NULL,
#ifdef USE_USBD_COMPOSITE
NULL,
NULL,
NULL,
NULL,
#else
USBD_HID_GetHSCfgDesc,
USBD_HID_GetFSCfgDesc,
USBD_HID_GetOtherSpeedCfgDesc,
USBD_HID_GetDeviceQualifierDesc,
#endif /* USE_USBD_COMPOSITE */
};
#ifndef USE_USBD_COMPOSITE
/* USB HID device FS Configuration Descriptor */
__ALIGN_BEGIN static uint8_t USBD_HID_CfgDesc[USB_HID_MOUSE_CONFIG_DESC_SIZ] __ALIGN_END =
{
0x09, /* bLength: Configuration Descriptor size */
USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */
USB_HID_MOUSE_CONFIG_DESC_SIZ, /* wTotalLength: Bytes returned */
0x00,
0x01, /* bNumInterfaces: 1 interface */
0x01, /* bConfigurationValue: Configuration value */
0x00, /* iConfiguration: Index of string descriptor
describing the configuration */
#if (USBD_SELF_POWERED == 1U)
0xE0, /* bmAttributes: Bus Powered according to user configuration */
#else
0xA0, /* bmAttributes: Bus Powered according to user configuration */
#endif /* USBD_SELF_POWERED */
USBD_MAX_POWER, /* MaxPower (mA) */
/************** Descriptor of Joystick Mouse interface ****************/
/* 09 */
0x09, /* bLength: Interface Descriptor size */
USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */
0x00, /* bInterfaceNumber: Number of Interface */
0x00, /* bAlternateSetting: Alternate setting */
0x01, /* bNumEndpoints */
0x03, /* bInterfaceClass: HID */
0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */
0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */
0, /* iInterface: Index of string descriptor */
/******************** Descriptor of Joystick Mouse HID ********************/
/* 18 */
0x09, /* bLength: HID Descriptor size */
HID_MOUSE_DESCRIPTOR_TYPE, /* bDescriptorType: HID */
0x11, /* bcdHID: HID Class Spec release number */
0x01,
0x00, /* bCountryCode: Hardware target country */
0x01, /* bNumDescriptors: Number of HID class descriptors to follow */
0x22, /* bDescriptorType */
HID_MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */
0x00,
/******************** Descriptor of Mouse endpoint ********************/
/* 27 */
0x07, /* bLength: Endpoint Descriptor size */
USB_DESC_TYPE_ENDPOINT, /* bDescriptorType:*/
HID_MOUSE_EPIN_ADDR, /* bEndpointAddress: Endpoint Address (IN) */
0x03, /* bmAttributes: Interrupt endpoint */
HID_MOUSE_EPIN_SIZE, /* wMaxPacketSize: 4 Bytes max */
0x00,
HID_MOUSE_FS_BINTERVAL, /* bInterval: Polling Interval */
/* 34 */
};
#endif /* USE_USBD_COMPOSITE */
/* USB HID device Configuration Descriptor */
__ALIGN_BEGIN static uint8_t USBD_HID_Desc[USB_HID_MOUSE_DESC_SIZ] __ALIGN_END =
{
/* 18 */
0x09, /* bLength: HID Descriptor size */
HID_MOUSE_DESCRIPTOR_TYPE, /* bDescriptorType: HID */
0x11, /* bcdHID: HID Class Spec release number */
0x01,
0x00, /* bCountryCode: Hardware target country */
0x01, /* bNumDescriptors: Number of HID class descriptors to follow */
0x22, /* bDescriptorType */
HID_MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */
0x00,
};
#ifndef USE_USBD_COMPOSITE
/* USB Standard Device Descriptor */
__ALIGN_BEGIN static uint8_t USBD_HID_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END =
{
USB_LEN_DEV_QUALIFIER_DESC,
USB_DESC_TYPE_DEVICE_QUALIFIER,
0x00,
0x02,
0x00,
0x00,
0x00,
0x40,
0x01,
0x00,
};
#endif /* USE_USBD_COMPOSITE */
__ALIGN_BEGIN static uint8_t HID_MOUSE_ReportDesc[HID_MOUSE_REPORT_DESC_SIZE] __ALIGN_END =
{
0x05, 0x01, /* Usage Page (Generic Desktop Ctrls) */
0x09, 0x02, /* Usage (Mouse) */
0xA1, 0x01, /* Collection (Application) */
0x09, 0x01, /* Usage (Pointer) */
0xA1, 0x00, /* Collection (Physical) */
0x05, 0x09, /* Usage Page (Button) */
0x19, 0x01, /* Usage Minimum (0x01) */
0x29, 0x03, /* Usage Maximum (0x03) */
0x15, 0x00, /* Logical Minimum (0) */
0x25, 0x01, /* Logical Maximum (1) */
0x95, 0x03, /* Report Count (3) */
0x75, 0x01, /* Report Size (1) */
0x81, 0x02, /* Input (Data,Var,Abs) */
0x95, 0x01, /* Report Count (1) */
0x75, 0x05, /* Report Size (5) */
0x81, 0x01, /* Input (Const,Array,Abs) */
0x05, 0x01, /* Usage Page (Generic Desktop Ctrls) */
0x09, 0x30, /* Usage (X) */
0x09, 0x31, /* Usage (Y) */
0x09, 0x38, /* Usage (Wheel) */
0x15, 0x81, /* Logical Minimum (-127) */
0x25, 0x7F, /* Logical Maximum (127) */
0x75, 0x08, /* Report Size (8) */
0x95, 0x03, /* Report Count (3) */
0x81, 0x06, /* Input (Data,Var,Rel) */
0xC0, /* End Collection */
0x09, 0x3C, /* Usage (Motion Wakeup) */
0x05, 0xFF, /* Usage Page (Reserved 0xFF) */
0x09, 0x01, /* Usage (0x01) */
0x15, 0x00, /* Logical Minimum (0) */
0x25, 0x01, /* Logical Maximum (1) */
0x75, 0x01, /* Report Size (1) */
0x95, 0x02, /* Report Count (2) */
0xB1, 0x22, /* Feature (Data,Var,Abs,NoWrp) */
0x75, 0x06, /* Report Size (6) */
0x95, 0x01, /* Report Count (1) */
0xB1, 0x01, /* Feature (Const,Array,Abs,NoWrp) */
0xC0 /* End Collection */
};
static uint8_t HIDInEpAdd = HID_MOUSE_EPIN_ADDR;
/**
* @}
*/
/** @defgroup USBD_HID_Private_Functions
* @{
*/
/**
* @brief USBD_HID_Init
* Initialize the HID interface
* @param pdev: device instance
* @param cfgidx: Configuration index
* @retval status
*/
static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
UNUSED(cfgidx);
USBD_HID_Mouse_HandleTypeDef *hhid;
hhid = (USBD_HID_Mouse_HandleTypeDef *)USBD_malloc(sizeof(USBD_HID_Mouse_HandleTypeDef));
printf("sizeof(USBD_HID_Mouse_HandleTypeDef)=0x%x\n",sizeof(USBD_HID_Mouse_HandleTypeDef));
if (hhid == NULL)
{
pdev->pClassDataCmsit[pdev->classId] = NULL;
return (uint8_t)USBD_EMEM;
}
pdev->pClassDataCmsit[pdev->classId] = (void *)hhid;
pdev->pClassData = pdev->pClassDataCmsit[pdev->classId];
#ifdef USE_USBD_COMPOSITE
/* Get the Endpoints addresses allocated for this class instance */
HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR);
#endif /* USE_USBD_COMPOSITE */
if (pdev->dev_speed == USBD_SPEED_HIGH)
{
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_MOUSE_HS_BINTERVAL;
}
else /* LOW and FULL-speed endpoints */
{
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_MOUSE_FS_BINTERVAL;
}
/* Open EP IN */
(void)USBD_LL_OpenEP(pdev, HIDInEpAdd, USBD_EP_TYPE_INTR, HID_MOUSE_EPIN_SIZE);
pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 1U;
hhid->state = MOUSE_HID_IDLE;
return (uint8_t)USBD_OK;
}
/**
* @brief USBD_HID_DeInit
* DeInitialize the HID layer
* @param pdev: device instance
* @param cfgidx: Configuration index
* @retval status
*/
static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
UNUSED(cfgidx);
#ifdef USE_USBD_COMPOSITE
/* Get the Endpoints addresses allocated for this class instance */
HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR);
#endif /* USE_USBD_COMPOSITE */
/* Close HID EPs */
(void)USBD_LL_CloseEP(pdev, HIDInEpAdd);
pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 0U;
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = 0U;
/* Free allocated memory */
if (pdev->pClassDataCmsit[pdev->classId] != NULL)
{
(void)USBD_free(pdev->pClassDataCmsit[pdev->classId]);
pdev->pClassDataCmsit[pdev->classId] = NULL;
}
return (uint8_t)USBD_OK;
}
/**
* @brief USBD_HID_Setup
* Handle the HID specific requests
* @param pdev: instance
* @param req: usb requests
* @retval status
*/
static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
USBD_HID_Mouse_HandleTypeDef *hhid = (USBD_HID_Mouse_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
USBD_StatusTypeDef ret = USBD_OK;
uint16_t len;
uint8_t *pbuf;
uint16_t status_info = 0U;
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
switch (req->bmRequest & USB_REQ_TYPE_MASK)
{
case USB_REQ_TYPE_CLASS :
switch (req->bRequest)
{
case HID_MOUSE_REQ_SET_PROTOCOL:
hhid->Protocol = (uint8_t)(req->wValue);
break;
case HID_MOUSE_REQ_GET_PROTOCOL:
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->Protocol, 1U);
break;
case HID_MOUSE_REQ_SET_IDLE:
hhid->IdleState = (uint8_t)(req->wValue >> 8);
break;
case HID_MOUSE_REQ_GET_IDLE:
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->IdleState, 1U);
break;
case HID_MOUSE_REQ_SET_REPORT:
USBD_HID_Mouse_SetReport_Setup_Stage(pdev, req);
break;
case HID_MOUSE_REQ_GET_REPORT:
USBD_HID_Mouse_GetReport_Token_Stage(pdev, req);
break;
default:
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
break;
}
break;
case USB_REQ_TYPE_STANDARD:
switch (req->bRequest)
{
case USB_REQ_GET_STATUS:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
(void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U);
}
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
case USB_REQ_GET_DESCRIPTOR:
if ((req->wValue >> 8) == HID_MOUSE_REPORT_DESC)
{
len = MIN(HID_MOUSE_REPORT_DESC_SIZE, req->wLength);
pbuf = HID_MOUSE_ReportDesc;
}
else if ((req->wValue >> 8) == HID_MOUSE_DESCRIPTOR_TYPE)
{
pbuf = USBD_HID_Desc;
len = MIN(USB_HID_MOUSE_DESC_SIZ, req->wLength);
}
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
break;
}
(void)USBD_CtlSendData(pdev, pbuf, len);
break;
case USB_REQ_GET_INTERFACE :
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->AltSetting, 1U);
}
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
case USB_REQ_SET_INTERFACE:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
hhid->AltSetting = (uint8_t)(req->wValue);
}
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
case USB_REQ_CLEAR_FEATURE:
break;
default:
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
break;
}
break;
default:
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
break;
}
return (uint8_t)ret;
}
/**
* @brief USBD_HID_Mouse_SendReport
* Send HID Report
* @param pdev: device instance
* @param buff: pointer to report
* @retval status
*/
uint8_t USBD_HID_Mouse_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len)
{
#ifdef USE_USBD_COMPOSITE
uint8_t class_id;
class_id = USBD_CMPSIT_GetClassID_ByAdd(pdev, HID_MOUSE_EPIN_ADDR, USBD_EP_TYPE_INTR);
USBD_HID_Mouse_HandleTypeDef *hhid = (USBD_HID_Mouse_HandleTypeDef *)pdev->pClassDataCmsit[class_id];
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
if (hhid->state == MOUSE_HID_IDLE)
{
hhid->state = MOUSE_HID_BUSY;
(void)USBD_LL_Transmit(pdev, HID_MOUSE_EPIN_ADDR, report, len);
}
}
return (uint8_t)USBD_OK;
#else
USBD_HID_Mouse_HandleTypeDef *hhid = (USBD_HID_Mouse_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
if (hhid->state == MOUSE_HID_IDLE)
{
hhid->state = MOUSE_HID_BUSY;
(void)USBD_LL_Transmit(pdev, HID_MOUSE_EPIN_ADDR, report, len);
}
}
return (uint8_t)USBD_OK;
#endif
}
extern uint8_t epnm_flag;
uint8_t USBD_HID_Mouse_FirstSendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len)
{
#ifdef USE_USBD_COMPOSITE
uint8_t class_id;
uint8_t ep_id = HID_MOUSE_EPIN_ADDR & 0xF;
class_id = USBD_CMPSIT_GetClassID_ByAdd(pdev, HID_MOUSE_EPIN_ADDR, USBD_EP_TYPE_INTR);
USBD_HID_Mouse_HandleTypeDef *hhid = (USBD_HID_Mouse_HandleTypeDef *)pdev->pClassDataCmsit[class_id];
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
PCD_HandleTypeDef *pcd = (PCD_HandleTypeDef *)(pdev->pData);
uint32_t USBx_BASE = (uint32_t)(PCD_HandleTypeDef *)pcd->Instance;
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
if ((hhid->state == MOUSE_HID_IDLE)||(epnm_flag == 0x01))
{
if(USBx_INEP(ep_id)->DIEPINT&USB_OTG_DIEPINT_ITTXFE)
{
USBx_INEP(ep_id)->DIEPINT |= USB_OTG_DIEPINT_ITTXFE;
hhid->state = MOUSE_HID_BUSY;
(void)USBD_LL_Transmit(pdev, HID_MOUSE_EPIN_ADDR, report, len);
}
else{
if(USBx_INEP(ep_id)->DIEPINT&USB_OTG_DIEPINT_NAK){
USBx_INEP(ep_id)->DIEPINT |= USB_OTG_DIEPINT_NAK;
USBx_INEP(ep_id)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
}
}
if(epnm_flag == 0x01){
epnm_flag = 0x00;
}
}
}
return (uint8_t)USBD_OK;
#else
uint8_t ep_id = HID_MOUSE_EPIN_ADDR & 0xF;
USBD_HID_Mouse_HandleTypeDef *hhid = (USBD_HID_Mouse_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
PCD_HandleTypeDef *pcd = (PCD_HandleTypeDef *)(pdev->pData);
uint32_t USBx_BASE = (uint32_t)(PCD_HandleTypeDef *)pcd->Instance;
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
if ((hhid->state == MOUSE_HID_IDLE)||(epnm_flag == 0x01))
{
if(USBx_INEP(ep_id)->DIEPINT&USB_OTG_DIEPINT_ITTXFE)
{
USBx_INEP(ep_id)->DIEPINT |= USB_OTG_DIEPINT_ITTXFE;
hhid->state = MOUSE_HID_BUSY;
(void)USBD_LL_Transmit(pdev, HID_MOUSE_EPIN_ADDR, report, len);
}
else{
if(USBx_INEP(ep_id)->DIEPINT&USB_OTG_DIEPINT_NAK){
USBx_INEP(ep_id)->DIEPINT |= USB_OTG_DIEPINT_NAK;
USBx_INEP(ep_id)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
}
}
if(epnm_flag == 0x01){
epnm_flag = 0x00;
}
}
}
return (uint8_t)USBD_OK;
#endif
}
/**
* @brief USBD_HID_GetPollingInterval
* return polling interval from endpoint descriptor
* @param pdev: device instance
* @retval polling interval
*/
uint32_t USBD_HID_GetPollingInterval(USBD_HandleTypeDef *pdev)
{
uint32_t polling_interval;
/* HIGH-speed endpoints */
if (pdev->dev_speed == USBD_SPEED_HIGH)
{
/* Sets the data transfer polling interval for high speed transfers.
Values between 1..16 are allowed. Values correspond to interval
of 2 ^ (bInterval-1). This option (8 ms, corresponds to HID_MOUSE_HS_BINTERVAL */
polling_interval = (((1U << (HID_MOUSE_HS_BINTERVAL - 1U))) / 8U);
}
else /* LOW and FULL-speed endpoints */
{
/* Sets the data transfer polling interval for low and full
speed transfers */
polling_interval = HID_MOUSE_FS_BINTERVAL;
}
return ((uint32_t)(polling_interval));
}
#ifndef USE_USBD_COMPOSITE
/**
* @brief USBD_HID_GetCfgFSDesc
* return FS configuration descriptor
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length)
{
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_MOUSE_EPIN_ADDR);
if (pEpDesc != NULL)
{
pEpDesc->bInterval = HID_MOUSE_FS_BINTERVAL;
}
*length = (uint16_t)sizeof(USBD_HID_CfgDesc);
return USBD_HID_CfgDesc;
}
/**
* @brief USBD_HID_GetCfgHSDesc
* return HS configuration descriptor
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length)
{
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_MOUSE_EPIN_ADDR);
if (pEpDesc != NULL)
{
pEpDesc->bInterval = HID_MOUSE_HS_BINTERVAL;
}
*length = (uint16_t)sizeof(USBD_HID_CfgDesc);
return USBD_HID_CfgDesc;
}
/**
* @brief USBD_HID_GetOtherSpeedCfgDesc
* return other speed configuration descriptor
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length)
{
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_MOUSE_EPIN_ADDR);
if (pEpDesc != NULL)
{
pEpDesc->bInterval = HID_MOUSE_FS_BINTERVAL;
}
*length = (uint16_t)sizeof(USBD_HID_CfgDesc);
return USBD_HID_CfgDesc;
}
#endif /* USE_USBD_COMPOSITE */
/**
* @brief USBD_HID_DataIn
* handle data IN Stage
* @param pdev: device instance
* @param epnum: endpoint index
* @retval status
*/
static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum)
{
UNUSED(epnum);
/* Ensure that the FIFO is empty before a new transfer, this condition could
be caused by a new transfer before the end of the previous transfer */
((USBD_HID_Mouse_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId])->state = MOUSE_HID_IDLE;
#ifdef APP_USB_MOUSE_FAST_SEND_DATA
extern void app_usb_mouse_fast_send_data(USBD_HandleTypeDef *pdev);
app_usb_mouse_fast_send_data(pdev);
#endif
return (uint8_t)USBD_OK;
}
static uint8_t USBD_HID_EP0_RxReady(USBD_HandleTypeDef *pdev)
{
DEBUG("Mouse USBD_HID_EP0_RxReady\r\n");
USBD_HID_Mouse_SetReport_Token_Stage(pdev);
return (uint8_t)USBD_OK;
}
uint8_t USBD_HID_Mouse_SetReport_Setup_Stage(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *setup_data)
{
uint8_t report_type;
uint8_t report_id;
#ifdef USE_USBD_COMPOSITE
uint8_t class_id;
class_id = USBD_CMPSIT_GetClassID_ByAdd(pdev, HID_MOUSE_EPIN_ADDR, USBD_EP_TYPE_INTR);
USBD_HID_Mouse_HandleTypeDef *hhid = (USBD_HID_Mouse_HandleTypeDef *)pdev->pClassDataCmsit[class_id];
#else
USBD_HID_Mouse_HandleTypeDef *hhid = (USBD_HID_Mouse_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
#endif
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
report_type = (setup_data->wValue >> 8) & 0xFF;
report_id = setup_data->wValue & 0xFF;
hhid->EP0_ReportLen = setup_data->wLength;
DEBUG("Setup_Stage report_type=%02x, report_id=%02x, report_len=%d\r\n",report_type, report_id, hhid->EP0_ReportLen);
(void)USBD_CtlPrepareRx(pdev, hhid->EP0_ReportBuff, hhid->EP0_ReportLen);
return (uint8_t)USBD_OK;
}
uint8_t USBD_HID_Mouse_SetReport_Token_Stage(USBD_HandleTypeDef *pdev)
{
#ifdef USE_USBD_COMPOSITE
uint8_t class_id;
class_id = USBD_CMPSIT_GetClassID_ByAdd(pdev, HID_MOUSE_EPIN_ADDR, USBD_EP_TYPE_INTR);
USBD_HID_Mouse_HandleTypeDef *hhid = (USBD_HID_Mouse_HandleTypeDef *)pdev->pClassDataCmsit[class_id];
#else
USBD_HID_Mouse_HandleTypeDef *hhid = (USBD_HID_Mouse_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
#endif
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
DEBUG("Token_Stage recv len = %d\n", hhid->EP0_ReportLen);
for(int i=0;i<hhid->EP0_ReportLen;i++){
DEBUG("0x%x ", hhid->EP0_ReportBuff[i]);
}DEBUG("\n");
return (uint8_t)USBD_OK;
}
uint8_t USBD_HID_Mouse_GetReport_Token_Stage(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *setup_data)
{
uint16_t report_length;
uint8_t data[HID_MOUSE_EP0_GET_REPORT_BUF_SIZE];
DEBUG("%s,%d\n",__func__,__LINE__);
#ifdef USE_USBD_COMPOSITE
uint8_t class_id;
class_id = USBD_CMPSIT_GetClassID_ByAdd(pdev, HID_MOUSE_EPIN_ADDR, USBD_EP_TYPE_INTR);
USBD_HID_Mouse_HandleTypeDef *hhid = (USBD_HID_Mouse_HandleTypeDef *)pdev->pClassDataCmsit[class_id];
#else
USBD_HID_Mouse_HandleTypeDef *hhid = (USBD_HID_Mouse_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
#endif
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
for(int i=0;i<HID_MOUSE_EP0_GET_REPORT_BUF_SIZE;i++)
{
data[i] = i;
}
report_length = setup_data->wLength;
USBD_CtlSendData(pdev, data, report_length);
return (uint8_t)USBD_OK;
}
#ifndef USE_USBD_COMPOSITE
/**
* @brief DeviceQualifierDescriptor
* return Device Qualifier descriptor
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length)
{
*length = (uint16_t)sizeof(USBD_HID_DeviceQualifierDesc);
return USBD_HID_DeviceQualifierDesc;
}
#endif /* USE_USBD_COMPOSITE */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
component/xc6xx_drivers/Drivers/USB/Middlewares/Library/Class/HID_COMPOSITE/Inc/usbd_hid_custom.h
+180
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@@ -0,0 +1,180 @@
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USB_HID_CUSTOM_H
#define __USB_HID_CUSTOM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "usbd_ioreq.h"
/** @defgroup USBD_HID
* @brief This file is the Header file for usbd_hid.c
* @{
*/
/** @defgroup USBD_HID_Exported_Defines
* @{
*/
#ifndef HID_CUSTOM_EPIN_ADDR
#define HID_CUSTOM_EPIN_ADDR 0x83U
#endif /* HID_EPIN_ADDR */
#define HID_CUSTOM_EPIN_SIZE 0x40U
#ifndef HID_CUSTOM_EPOUT_ADDR
#define HID_CUSTOM_EPOUT_ADDR 0x03U
#endif /* HID_CUSTOM_EPOUT_ADDR */
#define HID_CUSTOM_EPOUT_SIZE 0x40U
#define USB_HID_CUSTOM_CONFIG_DESC_SIZ 34U
#define USB_HID_CUSTOM_DESC_SIZ 9U
#define HID_CUSTOM_REPORT_DESC_SIZE 38+45U
#define HID_CUSTOM_DESCRIPTOR_TYPE 0x21U
#define HID_CUSTOM_REPORT_DESC 0x22U
#ifndef HID_CUSTOM_HS_BINTERVAL
#define HID_CUSTOM_HS_BINTERVAL 0x07U
#endif /* HID_HS_BINTERVAL */
#ifndef HID_CUSTOM_FS_BINTERVAL
#define HID_CUSTOM_FS_BINTERVAL 0x0AU
#endif /* HID_FS_BINTERVAL */
#ifndef USBD_CUSTOM_OUTREPORT_BUF_SIZE
#define USBD_CUSTOM_OUTREPORT_BUF_SIZE 0x02U
#endif /* USBD_CUSTOM_OUTREPORT_BUF_SIZE */
#define HID_CUSTOM_REQ_SET_PROTOCOL 0x0BU
#define HID_CUSTOM_REQ_GET_PROTOCOL 0x03U
#define HID_CUSTOM_REQ_SET_IDLE 0x0AU
#define HID_CUSTOM_REQ_GET_IDLE 0x02U
#define HID_CUSTOM_REQ_SET_REPORT 0x09U
#define HID_CUSTOM_REQ_GET_REPORT 0x01U
#ifndef HID_CUSTOM_EP0_SET_REPORT_BUF_SIZE
#define HID_CUSTOM_EP0_SET_REPORT_BUF_SIZE 0x10U
#endif /* HID_CUSTOM_EP0_SET_REPORT_BUF_SIZE */
#ifndef HID_CUSTOM_EP0_GET_REPORT_BUF_SIZE
#define HID_CUSTOM_EP0_GET_REPORT_BUF_SIZE 0x10U
#endif /* HID_CUSTOM_EP0_GET_REPORT_BUF_SIZE */
/**
* @}
*/
#define USB_DFU_REPORT_MAP \
0x06, 0x86, 0x19, /* Usage Page (ByteX)*/\
0x09, 0x10, /* Usage (0x10)*/\
0xA1, 0x01, /* Collection (Application)*/\
0x85, 0xFA, /* Report ID (-79)*/\
0x15, 0x00, /* Logical Minimum (0)*/\
0x25, 0xFF, /* Logical Maximum (-1)*/\
0x09, 0x00, /* Usage (Unassigned)*/\
0x19, 0x00, /* Usage (Unassigned)*/\
0x29, 0xFF, /* Usage Maximum (0xFF)*/\
0x75, 0x08, /* Report Size (8)*/\
0x95, 63, /* Report Count (63)*/\
0x81, 0x02, /* Input (Data,Var,Abs,No Wrap,Linear,Preferred State,No Null Position)*/\
0x85, 0xFB, /* Report ID (-78)*/\
0x15, 0x00, /* Logical Minimum (0)*/\
0x25, 0xFF, /* Logical Maximum (-1)*/\
0x09, 0x00, /* Usage (Unassigned)*/\
0x19, 0x00, /* Usage (Unassigned)*/\
0x29, 0xFF, /* Usage Maximum (0xFF)*/\
0x75, 0x08, /* Report Size (8)*/\
0x96, 0xFF, 0x01, /* Report Count (511)*/\
0x91, 0x02, /* Output (Data,Var,Abs,No Wrap,Linear,Preferred State,No Null Position,Non-volatile)*/\
0xC0
/** @defgroup USBD_CORE_Exported_TypesDefinitions
* @{
*/
typedef enum
{
CUSTOM_HID_IDLE = 0,
CUSTOM_HID_BUSY,
} HID_Custom_StateTypeDef;
typedef struct
{
uint8_t EP0_ReportBuff[HID_CUSTOM_EP0_SET_REPORT_BUF_SIZE];
uint8_t EP0_ReportLen;
uint8_t Report_buf[USBD_CUSTOM_OUTREPORT_BUF_SIZE];
uint32_t Protocol;
uint32_t IdleState;
uint32_t AltSetting;
HID_Custom_StateTypeDef state;
} USBD_HID_Custom_HandleTypeDef;
/*
* HID Class specification version 1.1
* 6.2.1 HID Descriptor
*/
typedef struct
{
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t bcdHID;
uint8_t bCountryCode;
uint8_t bNumDescriptors;
uint8_t bHIDDescriptorType;
uint16_t wItemLength;
} __PACKED USBD_HID_CustomDescTypeDef;
/**
* @}
*/
/** @defgroup USBD_CORE_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup USBD_CORE_Exported_Variables
* @{
*/
extern USBD_ClassTypeDef USBD_HID_CUSTOM;
#define USBD_HID_CUSTOM_CLASS &USBD_HID_CUSTOM
/**
* @}
*/
/** @defgroup USB_CORE_Exported_Functions
* @{
*/
uint8_t USBD_HID_CUSTOM_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len);
uint32_t USBD_HID_CUSTOM_GetPollingInterval(USBD_HandleTypeDef *pdev);
uint8_t USBD_HID_Custom_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len);
uint8_t USBD_HID_Custom_FirstSendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __USB_HID_H */
/**
* @}
*/
/**
* @}
*/
component/xc6xx_drivers/Drivers/USB/Middlewares/Library/Class/HID_COMPOSITE/Inc/usbd_hid_keyboard.h
+156
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@@ -0,0 +1,156 @@
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USB_HID_KEYBOARD_H
#define __USB_HID_KEYBOARD_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "usbd_ioreq.h"
/** @defgroup USBD_HID
* @brief This file is the Header file for usbd_hid.c
* @{
*/
/** @defgroup USBD_HID_Exported_Defines
* @{
*/
#ifndef HID_KEYBOARD_EPIN_ADDR
#define HID_KEYBOARD_EPIN_ADDR 0x82U
#endif /* HID_EPIN_ADDR */
#define HID_KEYBOARD_EPIN_SIZE 0x08U
#ifndef HID_KEYBOARD_EPOUT_ADDR
#define HID_KEYBOARD_EPOUT_ADDR 0x02U
#endif /* HID_EPIN_ADDR */
#define HID_KEYBOARD_EPOUT_SIZE 0x01U
#define USB_HID_KEYBOARD_CONFIG_DESC_SIZ 41U
#define USB_HID_KEYBOARD_DESC_SIZ 9U
#define HID_KEYBOARD_REPORT_DESC_SIZE 63U
#define HID_KEYBOARD_DESCRIPTOR_TYPE 0x21U
#define HID_KEYBOARD_REPORT_DESC 0x22U
#ifndef HID_KEYBOARD_HS_BINTERVAL
#define HID_KEYBOARD_HS_BINTERVAL 0x07U
#endif /* HID_HS_BINTERVAL */
#ifndef HID_KEYBOARD_FS_BINTERVAL
#define HID_KEYBOARD_FS_BINTERVAL 0x0AU
#endif /* HID_FS_BINTERVAL */
#ifndef USBD_KEYBOARD_OUTREPORT_BUF_SIZE
#define USBD_KEYBOARD_OUTREPORT_BUF_SIZE 0x02U
#endif /* USBD_KEYBOARD_OUTREPORT_BUF_SIZE */
#define HID_KEYBOARD_REQ_SET_PROTOCOL 0x0BU
#define HID_KEYBOARD_REQ_GET_PROTOCOL 0x03U
#define HID_KEYBOARD_REQ_SET_IDLE 0x0AU
#define HID_KEYBOARD_REQ_GET_IDLE 0x02U
#define HID_KEYBOARD_REQ_SET_REPORT 0x09U
#define HID_KEYBOARD_REQ_GET_REPORT 0x01U
#ifndef HID_KEYBOARD_EP0_SET_REPORT_BUF_SIZE
#define HID_KEYBOARD_EP0_SET_REPORT_BUF_SIZE 0x10U
#endif /* HID_KEYBOARD_EP0_SET_REPORT_BUF_SIZE */
#ifndef HID_KEYBOARD_EP0_GET_REPORT_BUF_SIZE
#define HID_KEYBOARD_EP0_GET_REPORT_BUF_SIZE 0x10U
#endif /* HID_KEYBOARD_EP0_GET_REPORT_BUF_SIZE */
/**
* @}
*/
/** @defgroup USBD_CORE_Exported_TypesDefinitions
* @{
*/
typedef enum
{
KEYBOARD_HID_IDLE = 0,
KEYBOARD_HID_BUSY,
} HID_Keyboard_StateTypeDef;
typedef struct
{
uint8_t EP0_ReportBuff[HID_KEYBOARD_EP0_SET_REPORT_BUF_SIZE];
uint8_t EP0_ReportLen;
uint8_t Report_buf[USBD_KEYBOARD_OUTREPORT_BUF_SIZE];
uint32_t Protocol;
uint32_t IdleState;
uint32_t AltSetting;
HID_Keyboard_StateTypeDef state;
} USBD_HID_Keyboard_HandleTypeDef;
/*
* HID Class specification version 1.1
* 6.2.1 HID Descriptor
*/
typedef struct
{
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t bcdHID;
uint8_t bCountryCode;
uint8_t bNumDescriptors;
uint8_t bHIDDescriptorType;
uint16_t wItemLength;
} __PACKED USBD_HID_KeyboardDescTypeDef;
/**
* @}
*/
/** @defgroup USBD_CORE_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup USBD_CORE_Exported_Variables
* @{
*/
extern USBD_ClassTypeDef USBD_HID_KEYBOARD;
#define USBD_HID_KEYBOARD_CLASS &USBD_HID_KEYBOARD
/**
* @}
*/
/** @defgroup USB_CORE_Exported_Functions
* @{
*/
uint8_t USBD_HID_Keyboard_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len);
uint32_t USBD_HID_GetPollingInterval(USBD_HandleTypeDef *pdev);
uint8_t USBD_HID_Keyboard_FirstSendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __USB_HID_H */
/**
* @}
*/
/**
* @}
*/
component/xc6xx_drivers/Drivers/USB/Middlewares/Library/Class/HID_COMPOSITE/Inc/usbd_hid_mouse.h
+172
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@@ -0,0 +1,172 @@
/*!
* \file usbd_hid.h
*
* \brief This file provides the HID core functions.
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author MCD Application Team
*
* \author ( XinChip ) Alex-J
*
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USB_HID_MOUSE_H
#define __USB_HID_MOUSE_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "usbd_ioreq.h"
/** @defgroup USBD_HID
* @brief This file is the Header file for usbd_hid.c
* @{
*/
/** @defgroup USBD_HID_Exported_Defines
* @{
*/
#ifndef HID_MOUSE_EPIN_ADDR
#define HID_MOUSE_EPIN_ADDR 0x81U
#endif /* HID_EPIN_ADDR */
#define HID_MOUSE_EPIN_SIZE 0x04U
#define USB_HID_MOUSE_CONFIG_DESC_SIZ 34U
#define USB_HID_MOUSE_DESC_SIZ 9U
#define HID_MOUSE_REPORT_DESC_SIZE 74U
#define HID_MOUSE_DESCRIPTOR_TYPE 0x21U
#define HID_MOUSE_REPORT_DESC 0x22U
#ifndef HID_MOUSE_HS_BINTERVAL
#define HID_MOUSE_HS_BINTERVAL 0x07U
#endif /* HID_HS_BINTERVAL */
#ifndef HID_MOUSE_FS_BINTERVAL
#define HID_MOUSE_FS_BINTERVAL 0x01U
#endif /* HID_FS_BINTERVAL */
#define HID_MOUSE_REQ_SET_PROTOCOL 0x0BU
#define HID_MOUSE_REQ_GET_PROTOCOL 0x03U
#define HID_MOUSE_REQ_SET_IDLE 0x0AU
#define HID_MOUSE_REQ_GET_IDLE 0x02U
#define HID_MOUSE_REQ_SET_REPORT 0x09U
#define HID_MOUSE_REQ_GET_REPORT 0x01U
#ifndef HID_MOUSE_EP0_SET_REPORT_BUF_SIZE
#define HID_MOUSE_EP0_SET_REPORT_BUF_SIZE 0x10U
#endif /* HID_MOUSE_EP0_SET_REPORT_BUF_SIZE */
#ifndef HID_MOUSE_EP0_GET_REPORT_BUF_SIZE
#define HID_MOUSE_EP0_GET_REPORT_BUF_SIZE 0x10U
#endif /* HID_MOUSE_EP0_GET_REPORT_BUF_SIZE */
/**
* @}
*/
/** @defgroup USBD_CORE_Exported_TypesDefinitions
* @{
*/
typedef enum
{
MOUSE_HID_IDLE = 0,
MOUSE_HID_BUSY,
} HID_Mouse_StateTypeDef;
typedef struct
{
uint8_t EP0_ReportBuff[HID_MOUSE_EP0_SET_REPORT_BUF_SIZE];
uint8_t EP0_ReportLen;
uint32_t Protocol;
uint32_t IdleState;
uint32_t AltSetting;
HID_Mouse_StateTypeDef state;
} USBD_HID_Mouse_HandleTypeDef;
/*
* HID Class specification version 1.1
* 6.2.1 HID Descriptor
*/
typedef struct
{
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t bcdHID;
uint8_t bCountryCode;
uint8_t bNumDescriptors;
uint8_t bHIDDescriptorType;
uint16_t wItemLength;
} __PACKED USBD_HID_MouseDescTypeDef;
/**
* @}
*/
/** @defgroup USBD_CORE_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup USBD_CORE_Exported_Variables
* @{
*/
extern USBD_ClassTypeDef USBD_HID_MOUSE;
#define USBD_HID_MOUSE_CLASS &USBD_HID_MOUSE
/**
* @}
*/
/** @defgroup USB_CORE_Exported_Functions
* @{
*/
uint8_t USBD_HID_Mouse_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len);
uint32_t USBD_HID_GetPollingInterval(USBD_HandleTypeDef *pdev);
uint8_t USBD_HID_Mouse_FirstSendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __USB_HID_H */
/**
* @}
*/
/**
* @}
*/
component/xc6xx_drivers/Drivers/USB/Middlewares/Library/Class/HID_COMPOSITE/Src/usbd_hid_custom.c
+865
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@@ -0,0 +1,865 @@
/*!
* \file usbd_hid_custom.c
*
* \brief This file provides the HID core functions.
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author MCD Application Team
*
* \author ( XinChip ) Alex-J
*
* @verbatim
*
* ===================================================================
* HID Class Description
* ===================================================================
* This module manages the HID class V1.11 following the "Device Class Definition
* for Human Interface Devices (HID) Version 1.11 Jun 27, 2001".
* This driver implements the following aspects of the specification:
* - The Boot Interface Subclass
* - The Mouse protocol
* - Usage Page : Generic Desktop
* - Usage : Custom
* - Collection : Application
*
* @note In HS mode and when the DMA is used, all variables and data structures
* dealing with the DMA during the transaction process should be 32-bit aligned.
*
*
* @endverbatim
*
*/
/* Includes ------------------------------------------------------------------*/
#include "usbd_hid_custom.h"
#include "usbd_ctlreq.h"
#ifdef USE_USBD_COMPOSITE
#include "usbd_composite_builder.h"
#endif
/** @defgroup USBD_HID
* @brief usbd core module
* @{
*/
/** @defgroup USBD_HID_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup USBD_HID_Private_Defines
* @{
*/
/**
* @}
*/
/** @defgroup USBD_HID_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup USBD_HID_Private_FunctionPrototypes
* @{
*/
static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum);
static uint8_t USBD_HID_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum);
static uint8_t USBD_HID_EP0_RxReady(USBD_HandleTypeDef *pdev);
static uint8_t USBD_HID_Custom_SetReport_Setup_Stage(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *setup_data);
static uint8_t USBD_HID_Custom_SetReport_Token_Stage(USBD_HandleTypeDef *pdev);
static uint8_t USBD_HID_Custom_GetReport_Token_Stage(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *setup_data);
#ifndef USE_USBD_COMPOSITE
static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length);
static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length);
static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length);
static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length);
#endif /* USE_USBD_COMPOSITE */
/**
* @}
*/
/** @defgroup USBD_HID_Private_Variables
* @{
*/
USBD_ClassTypeDef USBD_HID_CUSTOM =
{
USBD_HID_Init,
USBD_HID_DeInit,
USBD_HID_Setup,
NULL, /* EP0_TxSent */
USBD_HID_EP0_RxReady, /* EP0_RxReady */
USBD_HID_DataIn, /* DataIn */
USBD_HID_DataOut, /* DataOut */
NULL, /* SOF */
NULL,
NULL,
#ifdef USE_USBD_COMPOSITE
NULL,
NULL,
NULL,
NULL,
#else
USBD_HID_GetHSCfgDesc,
USBD_HID_GetFSCfgDesc,
USBD_HID_GetOtherSpeedCfgDesc,
USBD_HID_GetDeviceQualifierDesc,
#endif /* USE_USBD_COMPOSITE */
};
#ifndef USE_USBD_COMPOSITE
/* USB HID device FS Configuration Descriptor */
__ALIGN_BEGIN static uint8_t USBD_HID_CUSTOM_CfgDesc[USB_HID_CUSTOM_CONFIG_DESC_SIZ] __ALIGN_END =
{
0x09, /* bLength: Configuration Descriptor size */
USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */
USB_HID_CUSTOM_CONFIG_DESC_SIZ, /* wTotalLength: Bytes returned */
0x00,
0x01, /* bNumInterfaces: 1 interface */
0x01, /* bConfigurationValue: Configuration value */
0x00, /* iConfiguration: Index of string descriptor
describing the configuration */
#if (USBD_SELF_POWERED == 1U)
0xE0, /* bmAttributes: Bus Powered according to user configuration */
#else
0xA0, /* bmAttributes: Bus Powered according to user configuration */
#endif /* USBD_SELF_POWERED */
USBD_MAX_POWER, /* MaxPower (mA) */
/************** Descriptor of Custom interface ****************/
/* 09 */
0x09, /* bLength: Interface Descriptor size */
USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */
0x00, /* bInterfaceNumber: Number of Interface */
0x00, /* bAlternateSetting: Alternate setting */
0x01, /* bNumEndpoints */
0x03, /* bInterfaceClass: HID */
0x00, /* bInterfaceSubClass : 1=BOOT, 0=no boot */
0x00, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */
0, /* iInterface: Index of string descriptor */
/******************** Descriptor of Joystick Custom HID ********************/
/* 18 */
0x09, /* bLength: HID Descriptor size */
HID_CUSTOM_DESCRIPTOR_TYPE, /* bDescriptorType: HID */
0x11, /* bcdHID: HID Class Spec release number */
0x01,
0x00, /* bCountryCode: Hardware target country */
0x01, /* bNumDescriptors: Number of HID class descriptors to follow */
0x22, /* bDescriptorType */
HID_CUSTOM_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */
0x00,
/******************** Descriptor of Custom endpoint ********************/
/* 27 */
0x07, /* bLength: Endpoint Descriptor size */
USB_DESC_TYPE_ENDPOINT, /* bDescriptorType:*/
HID_CUSTOM_EPIN_ADDR, /* bEndpointAddress: Endpoint Address (IN) */
0x03, /* bmAttributes: Interrupt endpoint */
HID_CUSTOM_EPIN_SIZE, /* wMaxPacketSize: 4 Bytes max */
0x00,
HID_CUSTOM_FS_BINTERVAL, /* bInterval: Polling Interval */
/* 34 */
};
#endif /* USE_USBD_COMPOSITE */
/* USB HID device Configuration Descriptor */
__ALIGN_BEGIN static uint8_t USBD_HID_Desc[USB_HID_CUSTOM_DESC_SIZ] __ALIGN_END =
{
/* 18 */
0x09, /* bLength: HID Descriptor size */
HID_CUSTOM_DESCRIPTOR_TYPE, /* bDescriptorType: HID */
0x11, /* bcdHID: HID Class Spec release number */
0x01,
0x00, /* bCountryCode: Hardware target country */
0x01, /* bNumDescriptors: Number of HID class descriptors to follow */
0x22, /* bDescriptorType */
HID_CUSTOM_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */
0x00,
};
#ifndef USE_USBD_COMPOSITE
/* USB Standard Device Descriptor */
__ALIGN_BEGIN static uint8_t USBD_HID_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END =
{
USB_LEN_DEV_QUALIFIER_DESC,
USB_DESC_TYPE_DEVICE_QUALIFIER,
0x00,
0x02,
0x00,
0x00,
0x00,
0x40,
0x01,
0x00,
};
#endif /* USE_USBD_COMPOSITE */
__ALIGN_BEGIN static uint8_t HID_Custom_ReportDesc[HID_CUSTOM_REPORT_DESC_SIZE] __ALIGN_END =
{
0x06, 0x00, 0xff, //USAGE_PAGE(Vendor Defined Page 1)
0x09, 0x01, //USAGE(Vendor Usage 1)
0xa1, 0x01, //COLLECTION (Application)
0x85, 0x01, //REPORT ID (0x01)
0x09, 0x01, //USAGE(Vendor Usage 1)
0x15, 0x00, //LOGICAL_MINIMUM (0)
0x26, 0xff, 0x00, //LOGICAL_MAXIMUM (255)
0x95, 0x40-0x01, //REPORT_COUNT (63)
0x75, 0x08, //REPORT_SIZE (8)
0x81, 0x02, //INPUT (Data,Var,Abs)
0x85, 0x02, //REPORT ID (0x02)
0x09, 0x01, //USAGE(Vendor Usage 1)
0x15, 0x00, //LOGICAL_MINIMUM (0)
0x26, 0xff, 0x00, //LOGICAL_MAXIMUM (255)
0x95, 0x40-0x01, //REPORT_COUNT (63)
0x75, 0x08, //REPORT_SIZE (8)
0x91, 0x02, //OUTPUT (Data,Var,Abs)
0xc0, //END_COLLECTION
USB_DFU_REPORT_MAP
};
static uint8_t HIDInEpAdd = HID_CUSTOM_EPIN_ADDR;
/**
* @}
*/
/** @defgroup USBD_HID_Private_Functions
* @{
*/
/**
* @brief USBD_HID_Init
* Initialize the HID interface
* @param pdev: device instance
* @param cfgidx: Configuration index
* @retval status
*/
static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
UNUSED(cfgidx);
USBD_HID_Custom_HandleTypeDef *hhid;
hhid = (USBD_HID_Custom_HandleTypeDef *)USBD_malloc(sizeof(USBD_HID_Custom_HandleTypeDef));
DEBUG("sizeof(USBD_HID_Custom_HandleTypeDef)=0x%x\n",sizeof(USBD_HID_Custom_HandleTypeDef));
if (hhid == NULL)
{
pdev->pClassDataCmsit[pdev->classId] = NULL;
return (uint8_t)USBD_EMEM;
}
pdev->pClassDataCmsit[pdev->classId] = (void *)hhid;
pdev->pClassData = pdev->pClassDataCmsit[pdev->classId];
#ifdef USE_USBD_COMPOSITE
/* Get the Endpoints addresses allocated for this class instance */
HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR);
#endif /* USE_USBD_COMPOSITE */
if (pdev->dev_speed == USBD_SPEED_HIGH)
{
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_CUSTOM_HS_BINTERVAL;
}
else /* LOW and FULL-speed endpoints */
{
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_CUSTOM_FS_BINTERVAL;
}
/* Open EP IN */
(void)USBD_LL_OpenEP(pdev, HIDInEpAdd, USBD_EP_TYPE_INTR, HID_CUSTOM_EPIN_SIZE);
pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 1U;
/* Open EP OUT */
(void)USBD_LL_OpenEP(pdev, HID_CUSTOM_EPOUT_ADDR, USBD_EP_TYPE_INTR, HID_CUSTOM_EPOUT_SIZE);
pdev->ep_out[HID_CUSTOM_EPOUT_ADDR & 0xFU].is_used = 1U;
/* Prepare Out endpoint to receive 1st packet */
(void)USBD_LL_PrepareReceive(pdev, HID_CUSTOM_EPOUT_ADDR, hhid->Report_buf,
HID_CUSTOM_EPOUT_SIZE);
hhid->state = CUSTOM_HID_IDLE;
return (uint8_t)USBD_OK;
}
/**
* @brief USBD_HID_DeInit
* DeInitialize the HID layer
* @param pdev: device instance
* @param cfgidx: Configuration index
* @retval status
*/
static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
UNUSED(cfgidx);
#ifdef USE_USBD_COMPOSITE
/* Get the Endpoints addresses allocated for this class instance */
HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR);
#endif /* USE_USBD_COMPOSITE */
/* Close HID EPs */
(void)USBD_LL_CloseEP(pdev, HIDInEpAdd);
pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 0U;
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = 0U;
/* Free allocated memory */
if (pdev->pClassDataCmsit[pdev->classId] != NULL)
{
(void)USBD_free(pdev->pClassDataCmsit[pdev->classId]);
pdev->pClassDataCmsit[pdev->classId] = NULL;
}
return (uint8_t)USBD_OK;
}
/**
* @brief USBD_HID_Setup
* Handle the HID specific requests
* @param pdev: instance
* @param req: usb requests
* @retval status
*/
static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
USBD_HID_Custom_HandleTypeDef *hhid = (USBD_HID_Custom_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
USBD_StatusTypeDef ret = USBD_OK;
uint16_t len;
uint8_t *pbuf;
uint16_t status_info = 0U;
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
switch (req->bmRequest & USB_REQ_TYPE_MASK)
{
case USB_REQ_TYPE_CLASS :
switch (req->bRequest)
{
case HID_CUSTOM_REQ_SET_PROTOCOL:
hhid->Protocol = (uint8_t)(req->wValue);
break;
case HID_CUSTOM_REQ_GET_PROTOCOL:
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->Protocol, 1U);
break;
case HID_CUSTOM_REQ_SET_IDLE:
hhid->IdleState = (uint8_t)(req->wValue >> 8);
break;
case HID_CUSTOM_REQ_GET_IDLE:
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->IdleState, 1U);
break;
case HID_CUSTOM_REQ_SET_REPORT:
USBD_HID_Custom_SetReport_Setup_Stage(pdev, req);
break;
case HID_CUSTOM_REQ_GET_REPORT:
USBD_HID_Custom_GetReport_Token_Stage(pdev, req);
break;
default:
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
break;
}
break;
case USB_REQ_TYPE_STANDARD:
switch (req->bRequest)
{
case USB_REQ_GET_STATUS:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
(void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U);
}
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
case USB_REQ_GET_DESCRIPTOR:
if ((req->wValue >> 8) == HID_CUSTOM_REPORT_DESC)
{
len = MIN(HID_CUSTOM_REPORT_DESC_SIZE, req->wLength);
pbuf = HID_Custom_ReportDesc;
}
else if ((req->wValue >> 8) == HID_CUSTOM_DESCRIPTOR_TYPE)
{
pbuf = USBD_HID_Desc;
len = MIN(USB_HID_CUSTOM_DESC_SIZ, req->wLength);
}
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
break;
}
(void)USBD_CtlSendData(pdev, pbuf, len);
break;
case USB_REQ_GET_INTERFACE :
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->AltSetting, 1U);
}
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
case USB_REQ_SET_INTERFACE:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
hhid->AltSetting = (uint8_t)(req->wValue);
}
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
case USB_REQ_CLEAR_FEATURE:
break;
default:
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
break;
}
break;
default:
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
break;
}
return (uint8_t)ret;
}
/**
* @brief USBD_HID_Custom_SendReport
* Send HID Report
* @param pdev: device instance
* @param buff: pointer to report
* @retval status
*/
uint8_t USBD_HID_Custom_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len)
{
#ifdef USE_USBD_COMPOSITE
uint8_t class_id;
class_id = USBD_CMPSIT_GetClassID_ByAdd(pdev, HID_CUSTOM_EPIN_ADDR, USBD_EP_TYPE_INTR);
USBD_HID_Custom_HandleTypeDef *hhid = (USBD_HID_Custom_HandleTypeDef *)pdev->pClassDataCmsit[class_id];
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
if (hhid->state == CUSTOM_HID_IDLE)
{
hhid->state = CUSTOM_HID_BUSY;
(void)USBD_LL_Transmit(pdev, HID_CUSTOM_EPIN_ADDR, report, len);
}
}
return (uint8_t)USBD_OK;
#else
USBD_HID_Custom_HandleTypeDef *hhid = (USBD_HID_Custom_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
if (hhid->state == CUSTOM_HID_IDLE)
{
hhid->state = CUSTOM_HID_BUSY;
(void)USBD_LL_Transmit(pdev, HID_CUSTOM_EPIN_ADDR, report, len);
}
}
return (uint8_t)USBD_OK;
#endif
}
extern uint8_t epnm_flag;
/**
* @brief USBD_HID_Custom_FirstSendReport
* Send HID Report
* @param pdev: device instance
* @param buff: pointer to report
* @retval status
*/
uint8_t USBD_HID_Custom_FirstSendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len)
{
#ifdef USE_USBD_COMPOSITE
uint8_t class_id;
uint8_t ep_id = HID_CUSTOM_EPIN_ADDR & 0xF;
class_id = USBD_CMPSIT_GetClassID_ByAdd(pdev, HID_CUSTOM_EPIN_ADDR, USBD_EP_TYPE_INTR);
USBD_HID_Custom_HandleTypeDef *hhid = (USBD_HID_Custom_HandleTypeDef *)pdev->pClassDataCmsit[class_id];
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
PCD_HandleTypeDef *pcd = (PCD_HandleTypeDef *)(pdev->pData);
uint32_t USBx_BASE = (uint32_t)(PCD_HandleTypeDef *)pcd->Instance;
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
if ((hhid->state == CUSTOM_HID_IDLE)||(epnm_flag == 0x01))
{
if(USBx_INEP(ep_id)->DIEPINT&USB_OTG_DIEPINT_ITTXFE)
{
USBx_INEP(ep_id)->DIEPINT |= USB_OTG_DIEPINT_ITTXFE;
hhid->state = CUSTOM_HID_BUSY;
(void)USBD_LL_Transmit(pdev, HID_CUSTOM_EPIN_ADDR, report, len);
}
else{
if(USBx_INEP(ep_id)->DIEPINT&USB_OTG_DIEPINT_NAK){
USBx_INEP(ep_id)->DIEPINT |= USB_OTG_DIEPINT_NAK;
USBx_INEP(ep_id)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
}
}
if(epnm_flag == 0x01){
epnm_flag = 0x00;
}
}
}
return (uint8_t)USBD_OK;
#else
uint8_t ep_id = HID_CUSTOM_EPIN_ADDR & 0xF;
USBD_HID_Custom_HandleTypeDef *hhid = (USBD_HID_Custom_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
PCD_HandleTypeDef *pcd = (PCD_HandleTypeDef *)(pdev->pData);
uint32_t USBx_BASE = (uint32_t)(PCD_HandleTypeDef *)pcd->Instance;
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
if ((hhid->state == CUSTOM_HID_IDLE)||(epnm_flag == 0x01))
{
if(USBx_INEP(ep_id)->DIEPINT&USB_OTG_DIEPINT_ITTXFE)
{
USBx_INEP(ep_id)->DIEPINT |= USB_OTG_DIEPINT_ITTXFE;
hhid->state = CUSTOM_HID_BUSY;
(void)USBD_LL_Transmit(pdev, HID_CUSTOM_EPIN_ADDR, report, len);
}
else{
if(USBx_INEP(ep_id)->DIEPINT&USB_OTG_DIEPINT_NAK){
USBx_INEP(ep_id)->DIEPINT |= USB_OTG_DIEPINT_NAK;
USBx_INEP(ep_id)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
}
}
if(epnm_flag == 0x01){
epnm_flag = 0x00;
}
}
}
return (uint8_t)USBD_OK;
#endif
}
/**
* @brief USBD_HID_GetPollingInterval
* return polling interval from endpoint descriptor
* @param pdev: device instance
* @retval polling interval
*/
uint32_t USBD_HID_Custom_GetPollingInterval(USBD_HandleTypeDef *pdev)
{
uint32_t polling_interval;
/* HIGH-speed endpoints */
if (pdev->dev_speed == USBD_SPEED_HIGH)
{
/* Sets the data transfer polling interval for high speed transfers.
Values between 1..16 are allowed. Values correspond to interval
of 2 ^ (bInterval-1). This option (8 ms, corresponds to HID_HS_BINTERVAL */
polling_interval = (((1U << (HID_CUSTOM_HS_BINTERVAL - 1U))) / 8U);
}
else /* LOW and FULL-speed endpoints */
{
/* Sets the data transfer polling interval for low and full
speed transfers */
polling_interval = HID_CUSTOM_FS_BINTERVAL;
}
return ((uint32_t)(polling_interval));
}
#ifndef USE_USBD_COMPOSITE
/**
* @brief USBD_HID_GetCfgFSDesc
* return FS configuration descriptor
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length)
{
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CUSTOM_CfgDesc, HID_CUSTOM_EPIN_ADDR);
if (pEpDesc != NULL)
{
pEpDesc->bInterval = HID_CUSTOM_FS_BINTERVAL;
}
*length = (uint16_t)sizeof(USBD_HID_CUSTOM_CfgDesc);
return USBD_HID_CUSTOM_CfgDesc;
}
/**
* @brief USBD_HID_GetCfgHSDesc
* return HS configuration descriptor
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length)
{
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CUSTOM_CfgDesc, HID_CUSTOM_EPIN_ADDR);
if (pEpDesc != NULL)
{
pEpDesc->bInterval = HID_CUSTOM_HS_BINTERVAL;
}
*length = (uint16_t)sizeof(USBD_HID_CUSTOM_CfgDesc);
return USBD_HID_CUSTOM_CfgDesc;
}
/**
* @brief USBD_HID_GetOtherSpeedCfgDesc
* return other speed configuration descriptor
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length)
{
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CUSTOM_CfgDesc, HID_CUSTOM_EPIN_ADDR);
if (pEpDesc != NULL)
{
pEpDesc->bInterval = HID_CUSTOM_FS_BINTERVAL;
}
*length = (uint16_t)sizeof(USBD_HID_CUSTOM_CfgDesc);
return USBD_HID_CUSTOM_CfgDesc;
}
#endif /* USE_USBD_COMPOSITE */
/**
* @brief USBD_HID_DataIn
* handle data IN Stage
* @param pdev: device instance
* @param epnum: endpoint index
* @retval status
*/
static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum)
{
UNUSED(epnum);
/* Ensure that the FIFO is empty before a new transfer, this condition could
be caused by a new transfer before the end of the previous transfer */
((USBD_HID_Custom_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId])->state = CUSTOM_HID_IDLE;
return (uint8_t)USBD_OK;
}
extern PCD_HandleTypeDef hpcd_USB_OTG_FS;
/**
* @brief USBD_HID_DataOut
* handle data OUT Stage
* @param pdev: device instance
* @param epnum: endpoint index
* @retval status
*/
static uint8_t USBD_HID_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum)
{
UNUSED(epnum);
uint8_t size_num;
USBD_HID_Custom_HandleTypeDef *hhid;
hhid = pdev->pClassData;
/* Ensure that the FIFO is empty before a new transfer, this condition could
be caused by a new transfer before the end of the previous transfer */
size_num = HAL_PCD_EP_GetRxCount(&hpcd_USB_OTG_FS,HID_CUSTOM_EPOUT_ADDR);
(void)USBD_LL_PrepareReceive(pdev, HID_CUSTOM_EPOUT_ADDR, hhid->Report_buf,HID_CUSTOM_EPOUT_SIZE);
for(int i=0;i<size_num;i++)
{
DEBUG("0x%x ", hhid->Report_buf[i]);
}
DEBUG("\n");
hhid->state = CUSTOM_HID_IDLE;
return (uint8_t)USBD_OK;
}
static uint8_t USBD_HID_EP0_RxReady(USBD_HandleTypeDef *pdev)
{
DEBUG("Custom USBD_HID_EP0_RxReady\r\n");
USBD_HID_Custom_SetReport_Token_Stage(pdev);
return (uint8_t)USBD_OK;
}
uint8_t USBD_HID_Custom_SetReport_Setup_Stage(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *setup_data)
{
uint8_t report_type;
uint8_t report_id;
#ifdef USE_USBD_COMPOSITE
uint8_t class_id;
class_id = USBD_CMPSIT_GetClassID_ByAdd(pdev, HID_CUSTOM_EPIN_ADDR, USBD_EP_TYPE_INTR);
USBD_HID_Custom_HandleTypeDef *hhid = (USBD_HID_Custom_HandleTypeDef *)pdev->pClassDataCmsit[class_id];
#else
USBD_HID_Custom_HandleTypeDef *hhid = (USBD_HID_Custom_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
#endif
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
report_type = (setup_data->wValue >> 8) & 0xFF;
report_id = setup_data->wValue & 0xFF;
hhid->EP0_ReportLen = setup_data->wLength;
DEBUG("Setup_Stage report_type=%02x, report_id=%02x, report_len=%d\r\n",report_type, report_id, hhid->EP0_ReportLen);
(void)USBD_CtlPrepareRx(pdev, hhid->EP0_ReportBuff, hhid->EP0_ReportLen);
return (uint8_t)USBD_OK;
}
uint8_t USBD_HID_Custom_SetReport_Token_Stage(USBD_HandleTypeDef *pdev)
{
#ifdef USE_USBD_COMPOSITE
uint8_t class_id;
class_id = USBD_CMPSIT_GetClassID_ByAdd(pdev, HID_CUSTOM_EPIN_ADDR, USBD_EP_TYPE_INTR);
USBD_HID_Custom_HandleTypeDef *hhid = (USBD_HID_Custom_HandleTypeDef *)pdev->pClassDataCmsit[class_id];
#else
USBD_HID_Custom_HandleTypeDef *hhid = (USBD_HID_Custom_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
#endif
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
DEBUG("Token_Stage recv len = %d\n", hhid->EP0_ReportLen);
for(int i=0;i<hhid->EP0_ReportLen;i++){
DEBUG("0x%x ", hhid->EP0_ReportBuff[i]);
}DEBUG("\n");
return (uint8_t)USBD_OK;
}
uint8_t USBD_HID_Custom_GetReport_Token_Stage(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *setup_data)
{
uint16_t report_length;
uint8_t data[HID_CUSTOM_EP0_GET_REPORT_BUF_SIZE];
DEBUG("%s,%d\n",__func__,__LINE__);
#ifdef USE_USBD_COMPOSITE
uint8_t class_id;
class_id = USBD_CMPSIT_GetClassID_ByAdd(pdev, HID_CUSTOM_EPIN_ADDR, USBD_EP_TYPE_INTR);
USBD_HID_Custom_HandleTypeDef *hhid = (USBD_HID_Custom_HandleTypeDef *)pdev->pClassDataCmsit[class_id];
#else
USBD_HID_Custom_HandleTypeDef *hhid = (USBD_HID_Custom_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
#endif
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
for(int i=0;i<HID_CUSTOM_EP0_GET_REPORT_BUF_SIZE;i++)
{
data[i] = i;
}
report_length = setup_data->wLength;
USBD_CtlSendData(pdev, data, report_length);
return (uint8_t)USBD_OK;
}
#ifndef USE_USBD_COMPOSITE
/**
* @brief DeviceQualifierDescriptor
* return Device Qualifier descriptor
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length)
{
*length = (uint16_t)sizeof(USBD_HID_DeviceQualifierDesc);
return USBD_HID_DeviceQualifierDesc;
}
#endif /* USE_USBD_COMPOSITE */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
component/xc6xx_drivers/Drivers/USB/Middlewares/Library/Class/HID_COMPOSITE/Src/usbd_hid_keyboard.c
+863
View File
@@ -0,0 +1,863 @@
/*!
* \file usbd_hid_keyboard.c
*
* \brief This file provides the HID core functions.
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author MCD Application Team
*
* \author ( XinChip ) Alex-J
*
* @verbatim
*
* ===================================================================
* HID Class Description
* ===================================================================
* This module manages the HID class V1.11 following the "Device Class Definition
* for Human Interface Devices (HID) Version 1.11 Jun 27, 2001".
* This driver implements the following aspects of the specification:
* - The Boot Interface Subclass
* - The Mouse protocol
* - Usage Page : Generic Desktop
* - Usage : Keyboard
* - Collection : Application
*
* @note In HS mode and when the DMA is used, all variables and data structures
* dealing with the DMA during the transaction process should be 32-bit aligned.
*
*
* @endverbatim
*
*/
/* Includes ------------------------------------------------------------------*/
#include "usbd_hid_keyboard.h"
#include "usbd_ctlreq.h"
#ifdef USE_USBD_COMPOSITE
#include "usbd_composite_builder.h"
#endif
/** @defgroup USBD_HID
* @brief usbd core module
* @{
*/
/** @defgroup USBD_HID_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup USBD_HID_Private_Defines
* @{
*/
/**
* @}
*/
/** @defgroup USBD_HID_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup USBD_HID_Private_FunctionPrototypes
* @{
*/
static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum);
static uint8_t USBD_HID_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum);
static uint8_t USBD_HID_EP0_RxReady(USBD_HandleTypeDef *pdev);
static uint8_t USBD_HID_Keyboard_SetReport_Setup_Stage(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *setup_data);
static uint8_t USBD_HID_Keyboard_SetReport_Token_Stage(USBD_HandleTypeDef *pdev);
static uint8_t USBD_HID_Keyboard_GetReport_Token_Stage(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *setup_data);
#ifndef USE_USBD_COMPOSITE
static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length);
static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length);
static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length);
static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length);
#endif /* USE_USBD_COMPOSITE */
/**
* @}
*/
/** @defgroup USBD_HID_Private_Variables
* @{
*/
USBD_ClassTypeDef USBD_HID_KEYBOARD =
{
USBD_HID_Init,
USBD_HID_DeInit,
USBD_HID_Setup,
NULL, /* EP0_TxSent */
USBD_HID_EP0_RxReady, /* EP0_RxReady */
USBD_HID_DataIn, /* DataIn */
USBD_HID_DataOut, /* DataOut */
NULL, /* SOF */
NULL,
NULL,
#ifdef USE_USBD_COMPOSITE
NULL,
NULL,
NULL,
NULL,
#else
USBD_HID_GetHSCfgDesc,
USBD_HID_GetFSCfgDesc,
USBD_HID_GetOtherSpeedCfgDesc,
USBD_HID_GetDeviceQualifierDesc,
#endif /* USE_USBD_COMPOSITE */
};
#ifndef USE_USBD_COMPOSITE
/* USB HID device FS Configuration Descriptor */
__ALIGN_BEGIN static uint8_t USBD_HID_CfgDesc[USB_HID_KEYBOARD_CONFIG_DESC_SIZ] __ALIGN_END =
{
0x09, /* bLength: Configuration Descriptor size */
USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */
USB_HID_KEYBOARD_CONFIG_DESC_SIZ, /* wTotalLength: Bytes returned */
0x00,
0x01, /* bNumInterfaces: 1 interface */
0x01, /* bConfigurationValue: Configuration value */
0x00, /* iConfiguration: Index of string descriptor
describing the configuration */
#if (USBD_SELF_POWERED == 1U)
0xE0, /* bmAttributes: Bus Powered according to user configuration */
#else
0xA0, /* bmAttributes: Bus Powered according to user configuration */
#endif /* USBD_SELF_POWERED */
USBD_MAX_POWER, /* MaxPower (mA) */
/************** Descriptor of Keyboard interface ****************/
/* 09 */
0x09, /* bLength: Interface Descriptor size */
USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */
0x00, /* bInterfaceNumber: Number of Interface */
0x00, /* bAlternateSetting: Alternate setting */
0x02, /* bNumEndpoints */
0x03, /* bInterfaceClass: HID */
0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */
0x01, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */
0, /* iInterface: Index of string descriptor */
/******************** Descriptor of Keyboard HID ********************/
/* 18 */
0x09, /* bLength: HID Descriptor size */
HID_KEYBOARD_DESCRIPTOR_TYPE, /* bDescriptorType: HID */
0x11, /* bcdHID: HID Class Spec release number */
0x01,
0x00, /* bCountryCode: Hardware target country */
0x01, /* bNumDescriptors: Number of HID class descriptors to follow */
0x22, /* bDescriptorType */
HID_KEYBOARD_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */
0x00,
/******************** Descriptor of Keyboard endpoint ********************/
/* 27 */
0x07, /* bLength: Endpoint Descriptor size */
USB_DESC_TYPE_ENDPOINT, /* bDescriptorType:*/
HID_KEYBOARD_EPIN_ADDR, /* bEndpointAddress: Endpoint Address (IN) */
0x03, /* bmAttributes: Interrupt endpoint */
HID_KEYBOARD_EPIN_SIZE, /* wMaxPacketSize: 4 Byte max */
0x00,
HID_KEYBOARD_FS_BINTERVAL, /* bInterval: Polling Interval */
/* 34 */
0x07, /* bLength: Endpoint Descriptor size */
USB_DESC_TYPE_ENDPOINT, /* bDescriptorType:*/
HID_KEYBOARD_EPOUT_ADDR, /* bEndpointAddress: Endpoint Address (IN) */
0x03, /* bmAttributes: Interrupt endpoint */
HID_KEYBOARD_EPOUT_SIZE, /* wMaxPacketSize: 4 Byte max */
0x00,
HID_KEYBOARD_FS_BINTERVAL, /* bInterval: Polling Interval */
/* 41 */
};
#endif /* USE_USBD_COMPOSITE */
/* USB HID device Configuration Descriptor */
__ALIGN_BEGIN static uint8_t USBD_HID_Desc[USB_HID_KEYBOARD_DESC_SIZ] __ALIGN_END =
{
/* 18 */
0x09, /* bLength: HID Descriptor size */
HID_KEYBOARD_DESCRIPTOR_TYPE, /* bDescriptorType: HID */
0x11, /* bcdHID: HID Class Spec release number */
0x01,
0x00, /* bCountryCode: Hardware target country */
0x01, /* bNumDescriptors: Number of HID class descriptors to follow */
0x22, /* bDescriptorType */
HID_KEYBOARD_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */
0x00,
};
#ifndef USE_USBD_COMPOSITE
/* USB Standard Device Descriptor */
__ALIGN_BEGIN static uint8_t USBD_HID_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END =
{
USB_LEN_DEV_QUALIFIER_DESC,
USB_DESC_TYPE_DEVICE_QUALIFIER,
0x00,
0x02,
0x00,
0x00,
0x00,
0x40,
0x01,
0x00,
};
#endif /* USE_USBD_COMPOSITE */
__ALIGN_BEGIN static uint8_t HID_Keyboard_ReportDesc[HID_KEYBOARD_REPORT_DESC_SIZE] __ALIGN_END =
{
0x05, 0x01, // Usage Page (Generic Desktop Ctrls)
0x09, 0x06, // Usage (Keyboard)
0xA1, 0x01, // Collection (Application)
0x05, 0x07, // Usage Page (Kbrd/Keypad)
0x19, 0xE0, // Usage Minimum (0xE0)
0x29, 0xE7, // Usage Maximum (0xE7)
0x15, 0x00, // Logical Minimum (0)
0x25, 0x01, // Logical Maximum (1)
0x75, 0x01, // Report Size (1)
0x95, 0x08, // Report Count (8)
0x81, 0x02, // Input (Data,Var,Abs,No Wrap,Linear,Preferred State,No Null Position)
0x95, 0x01, // Report Count (1)
0x75, 0x08, // Report Size (8)
0x81, 0x03, // Input (Const,Var,Abs,No Wrap,Linear,Preferred State,No Null Position)
0x95, 0x05, // Report Count (5)
0x75, 0x01, // Report Size (1)
0x05, 0x08, // Usage Page (LEDs)
0x19, 0x01, // Usage Minimum (Num Lock)
0x29, 0x05, // Usage Maximum (Kana)
0x91, 0x02, // Output (Data,Var,Abs,No Wrap,Linear,Preferred State,No Null Position,Non-volatile)
0x95, 0x01, // Report Count (1)
0x75, 0x03, // Report Size (3)
0x91, 0x03, // Output (Const,Var,Abs,No Wrap,Linear,Preferred State,No Null Position,Non-volatile)
0x95, 0x06, // Report Count (6)
0x75, 0x08, // Report Size (8)
0x15, 0x00, // Logical Minimum (0)
0x25, 0x65, // Logical Maximum (101)
0x05, 0x07, // Usage Page (Kbrd/Keypad)
0x19, 0x00, // Usage Minimum (Reserved (no event indicated))
0x29, 0x65, // Usage Maximum (0x65)
0x81, 0x00, // Input (Data,Array,Abs,No Wrap,Linear,Preferred State,No Null Position)
0xC0, // End Collection
};
static uint8_t HIDInEpAdd = HID_KEYBOARD_EPIN_ADDR;
/**
* @}
*/
/** @defgroup USBD_HID_Private_Functions
* @{
*/
/**
* @brief USBD_HID_Init
* Initialize the HID interface
* @param pdev: device instance
* @param cfgidx: Configuration index
* @retval status
*/
static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
UNUSED(cfgidx);
USBD_HID_Keyboard_HandleTypeDef *hhid;
hhid = (USBD_HID_Keyboard_HandleTypeDef *)USBD_malloc(sizeof(USBD_HID_Keyboard_HandleTypeDef));
DEBUG("sizeof(USBD_HID_Keyboard_HandleTypeDef)=0x%x\n",sizeof(USBD_HID_Keyboard_HandleTypeDef));
if (hhid == NULL)
{
pdev->pClassDataCmsit[pdev->classId] = NULL;
return (uint8_t)USBD_EMEM;
}
pdev->pClassDataCmsit[pdev->classId] = (void *)hhid;
pdev->pClassData = pdev->pClassDataCmsit[pdev->classId];
#ifdef USE_USBD_COMPOSITE
/* Get the Endpoints addresses allocated for this class instance */
HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR);
#endif /* USE_USBD_COMPOSITE */
if (pdev->dev_speed == USBD_SPEED_HIGH)
{
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_KEYBOARD_HS_BINTERVAL;
}
else /* LOW and FULL-speed endpoints */
{
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_KEYBOARD_FS_BINTERVAL;
}
/* Open EP IN */
(void)USBD_LL_OpenEP(pdev, HIDInEpAdd, USBD_EP_TYPE_INTR, HID_KEYBOARD_EPIN_SIZE);
pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 1U;
/* Open EP OUT */
(void)USBD_LL_OpenEP(pdev, HID_KEYBOARD_EPOUT_ADDR, USBD_EP_TYPE_INTR, HID_KEYBOARD_EPOUT_SIZE);
pdev->ep_out[HID_KEYBOARD_EPOUT_ADDR & 0xFU].is_used = 1U;
/* Prepare Out endpoint to receive 1st packet */
(void)USBD_LL_PrepareReceive(pdev, HID_KEYBOARD_EPOUT_ADDR, hhid->Report_buf,
USBD_KEYBOARD_OUTREPORT_BUF_SIZE);
hhid->state = KEYBOARD_HID_IDLE;
return (uint8_t)USBD_OK;
}
/**
* @brief USBD_HID_DeInit
* DeInitialize the HID layer
* @param pdev: device instance
* @param cfgidx: Configuration index
* @retval status
*/
static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
UNUSED(cfgidx);
#ifdef USE_USBD_COMPOSITE
/* Get the Endpoints addresses allocated for this class instance */
HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR);
#endif /* USE_USBD_COMPOSITE */
/* Close HID EPs */
(void)USBD_LL_CloseEP(pdev, HIDInEpAdd);
pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 0U;
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = 0U;
/* Free allocated memory */
if (pdev->pClassDataCmsit[pdev->classId] != NULL)
{
(void)USBD_free(pdev->pClassDataCmsit[pdev->classId]);
pdev->pClassDataCmsit[pdev->classId] = NULL;
}
return (uint8_t)USBD_OK;
}
/**
* @brief USBD_HID_Setup
* Handle the HID specific requests
* @param pdev: instance
* @param req: usb requests
* @retval status
*/
static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
USBD_HID_Keyboard_HandleTypeDef *hhid = (USBD_HID_Keyboard_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
USBD_StatusTypeDef ret = USBD_OK;
uint16_t len;
uint8_t *pbuf;
uint16_t status_info = 0U;
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
switch (req->bmRequest & USB_REQ_TYPE_MASK)
{
case USB_REQ_TYPE_CLASS :
switch (req->bRequest)
{
case HID_KEYBOARD_REQ_SET_PROTOCOL:
hhid->Protocol = (uint8_t)(req->wValue);
break;
case HID_KEYBOARD_REQ_GET_PROTOCOL:
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->Protocol, 1U);
break;
case HID_KEYBOARD_REQ_SET_IDLE:
hhid->IdleState = (uint8_t)(req->wValue >> 8);
break;
case HID_KEYBOARD_REQ_GET_IDLE:
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->IdleState, 1U);
break;
case HID_KEYBOARD_REQ_SET_REPORT:
USBD_HID_Keyboard_SetReport_Setup_Stage(pdev, req);
break;
case HID_KEYBOARD_REQ_GET_REPORT:
USBD_HID_Keyboard_GetReport_Token_Stage(pdev, req);
break;
default:
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
break;
}
break;
case USB_REQ_TYPE_STANDARD:
switch (req->bRequest)
{
case USB_REQ_GET_STATUS:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
(void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U);
}
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
case USB_REQ_GET_DESCRIPTOR:
if ((req->wValue >> 8) == HID_KEYBOARD_REPORT_DESC)
{
len = MIN(HID_KEYBOARD_REPORT_DESC_SIZE, req->wLength);
pbuf = HID_Keyboard_ReportDesc;
}
else if ((req->wValue >> 8) == HID_KEYBOARD_DESCRIPTOR_TYPE)
{
pbuf = USBD_HID_Desc;
len = MIN(USB_HID_KEYBOARD_DESC_SIZ, req->wLength);
}
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
break;
}
(void)USBD_CtlSendData(pdev, pbuf, len);
break;
case USB_REQ_GET_INTERFACE :
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->AltSetting, 1U);
}
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
case USB_REQ_SET_INTERFACE:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
hhid->AltSetting = (uint8_t)(req->wValue);
}
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
case USB_REQ_CLEAR_FEATURE:
break;
default:
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
break;
}
break;
default:
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
break;
}
return (uint8_t)ret;
}
/**
* @brief USBD_HID_Keyboard_SendReport
* Send HID Report
* @param pdev: device instance
* @param buff: pointer to report
* @retval status
*/
uint8_t USBD_HID_Keyboard_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len)
{
#ifdef USE_USBD_COMPOSITE
uint8_t class_id;
class_id = USBD_CMPSIT_GetClassID_ByAdd(pdev, HID_KEYBOARD_EPIN_ADDR, USBD_EP_TYPE_INTR);
USBD_HID_Keyboard_HandleTypeDef *hhid = (USBD_HID_Keyboard_HandleTypeDef *)pdev->pClassDataCmsit[class_id];
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
if (hhid->state == KEYBOARD_HID_IDLE)
{
hhid->state = KEYBOARD_HID_BUSY;
(void)USBD_LL_Transmit(pdev, HID_KEYBOARD_EPIN_ADDR, report, len);
}
}
#endif
return (uint8_t)USBD_OK;
}
extern uint8_t epnm_flag;
uint8_t USBD_HID_Keyboard_FirstSendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len)
{
#ifdef USE_USBD_COMPOSITE
static uint8_t first_send_flag = 0;
uint8_t class_id;
uint8_t ep_id = HID_KEYBOARD_EPIN_ADDR & 0xF;
if(first_send_flag == 1){
return (uint8_t)USBD_OK;
}
class_id = USBD_CMPSIT_GetClassID_ByAdd(pdev, HID_KEYBOARD_EPIN_ADDR, USBD_EP_TYPE_INTR);
USBD_HID_Keyboard_HandleTypeDef *hhid = (USBD_HID_Keyboard_HandleTypeDef *)pdev->pClassDataCmsit[class_id];
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
PCD_HandleTypeDef *pcd = (PCD_HandleTypeDef *)(pdev->pData);
uint32_t USBx_BASE = (uint32_t)(PCD_HandleTypeDef *)pcd->Instance;
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
if ((hhid->state == KEYBOARD_HID_IDLE)||(epnm_flag == 0x01))
{
if(USBx_INEP(ep_id)->DIEPINT&USB_OTG_DIEPINT_ITTXFE)
{
USBx_INEP(ep_id)->DIEPINT |= USB_OTG_DIEPINT_ITTXFE;
hhid->state = KEYBOARD_HID_BUSY;
(void)USBD_LL_Transmit(pdev, HID_KEYBOARD_EPIN_ADDR, report, len);
}
else{
if(USBx_INEP(ep_id)->DIEPINT&USB_OTG_DIEPINT_NAK){
USBx_INEP(ep_id)->DIEPINT |= USB_OTG_DIEPINT_NAK;
USBx_INEP(ep_id)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
}
}
if(epnm_flag == 0x01){
epnm_flag = 0x00;
}
}
}
return (uint8_t)USBD_OK;
#else
uint8_t ep_id = HID_KEYBOARD_EPIN_ADDR & 0xF;
USBD_HID_Keyboard_HandleTypeDef *hhid = (USBD_HID_Keyboard_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
PCD_HandleTypeDef *pcd = (PCD_HandleTypeDef *)(pdev->pData);
uint32_t USBx_BASE = (uint32_t)(PCD_HandleTypeDef *)pcd->Instance;
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
if ((hhid->state == KEYBOARD_HID_IDLE)||(epnm_flag == 0x01))
{
if(USBx_INEP(ep_id)->DIEPINT&SB_OTG_DIEPINT_ITTXFE)
{
USBx_INEP(ep_id)->DIEPINT |= SB_OTG_DIEPINT_ITTXFE;
hhid->state = KEYBOARD_HID_BUSY;
(void)USBD_LL_Transmit(pdev, HID_KEYBOARD_EPIN_ADDR, report, len);
}
else{
if(USBx_INEP(ep_id)->DIEPINT&USB_OTG_DIEPINT_NAK){
USBx_INEP(ep_id)->DIEPINT |= USB_OTG_DIEPINT_NAK;
USBx_INEP(ep_id)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
}
}
if(epnm_flag == 0x01){
epnm_flag = 0x00;
}
}
}
return (uint8_t)USBD_OK;
#endif
}
/**
* @brief USBD_HID_GetPollingInterval
* return polling interval from endpoint descriptor
* @param pdev: device instance
* @retval polling interval
*/
uint32_t USBD_HID_KEYBOARD_GetPollingInterval(USBD_HandleTypeDef *pdev)
{
uint32_t polling_interval;
/* HIGH-speed endpoints */
if (pdev->dev_speed == USBD_SPEED_HIGH)
{
/* Sets the data transfer polling interval for high speed transfers.
Values between 1..16 are allowed. Values correspond to interval
of 2 ^ (bInterval-1). This option (8 ms, corresponds to HID_HS_BINTERVAL */
polling_interval = (((1U << (HID_KEYBOARD_HS_BINTERVAL - 1U))) / 8U);
}
else /* LOW and FULL-speed endpoints */
{
/* Sets the data transfer polling interval for low and full
speed transfers */
polling_interval = HID_KEYBOARD_FS_BINTERVAL;
}
return ((uint32_t)(polling_interval));
}
#ifndef USE_USBD_COMPOSITE
/**
* @brief USBD_HID_GetCfgFSDesc
* return FS configuration descriptor
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length)
{
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_KEYBOARD_EPIN_ADDR);
if (pEpDesc != NULL)
{
pEpDesc->bInterval = HID_KEYBOARD_FS_BINTERVAL;
}
*length = (uint16_t)sizeof(USBD_HID_CfgDesc);
return USBD_HID_CfgDesc;
}
/**
* @brief USBD_HID_GetCfgHSDesc
* return HS configuration descriptor
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length)
{
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_KEYBOARD_EPIN_ADDR);
if (pEpDesc != NULL)
{
pEpDesc->bInterval = HID_KEYBOARD_HS_BINTERVAL;
}
*length = (uint16_t)sizeof(USBD_HID_CfgDesc);
return USBD_HID_CfgDesc;
}
/**
* @brief USBD_HID_GetOtherSpeedCfgDesc
* return other speed configuration descriptor
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length)
{
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_KEYBOARD_EPIN_ADDR);
if (pEpDesc != NULL)
{
pEpDesc->bInterval = HID_KEYBOARD_FS_BINTERVAL;
}
*length = (uint16_t)sizeof(USBD_HID_CfgDesc);
return USBD_HID_CfgDesc;
}
#endif /* USE_USBD_COMPOSITE */
/**
* @brief USBD_HID_DataIn
* handle data IN Stage
* @param pdev: device instance
* @param epnum: endpoint index
* @retval status
*/
static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum)
{
UNUSED(epnum);
/* Ensure that the FIFO is empty before a new transfer, this condition could
be caused by a new transfer before the end of the previous transfer */
((USBD_HID_Keyboard_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId])->state = KEYBOARD_HID_IDLE;
return (uint8_t)USBD_OK;
}
extern PCD_HandleTypeDef hpcd_USB_OTG_FS;
/**
* @brief USBD_CUSTOM_HID_DataOut
* handle data OUT Stage
* @param pdev: device instance
* @param epnum: endpoint index
* @retval status
*/
static uint8_t USBD_HID_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum)
{
DEBUG("line=%d,epnum=0x%x\n",__LINE__,epnum);
uint8_t size_num;
USBD_HID_Keyboard_HandleTypeDef *hhid;
hhid = pdev->pClassData;
/* Ensure that the FIFO is empty before a new transfer, this condition could
be caused by a new transfer before the end of the previous transfer */
size_num = HAL_PCD_EP_GetRxCount(&hpcd_USB_OTG_FS,HID_KEYBOARD_EPOUT_ADDR);
(void)USBD_LL_PrepareReceive(pdev, HID_KEYBOARD_EPOUT_ADDR, hhid->Report_buf,HID_KEYBOARD_EPOUT_SIZE);
for(int i=0;i<size_num;i++)
{
DEBUG("0x%x ", hhid->Report_buf[i]);
}
DEBUG("\n");
hhid->state = KEYBOARD_HID_IDLE;
return (uint8_t)USBD_OK;
}
static uint8_t USBD_HID_EP0_RxReady(USBD_HandleTypeDef *pdev)
{
DEBUG("Keyboard USBD_HID_EP0_RxReady\r\n");
USBD_HID_Keyboard_SetReport_Token_Stage(pdev);
return (uint8_t)USBD_OK;
}
uint8_t USBD_HID_Keyboard_SetReport_Setup_Stage(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *setup_data)
{
uint8_t report_type;
uint8_t report_id;
#ifdef USE_USBD_COMPOSITE
uint8_t class_id;
class_id = USBD_CMPSIT_GetClassID_ByAdd(pdev, HID_KEYBOARD_EPIN_ADDR, USBD_EP_TYPE_INTR);
USBD_HID_Keyboard_HandleTypeDef *hhid = (USBD_HID_Keyboard_HandleTypeDef *)pdev->pClassDataCmsit[class_id];
#else
USBD_HID_Keyboard_HandleTypeDef *hhid = (USBD_HID_Keyboard_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
#endif
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
report_type = (setup_data->wValue >> 8) & 0xFF;
report_id = setup_data->wValue & 0xFF;
hhid->EP0_ReportLen = setup_data->wLength;
DEBUG("Setup_Stage report_type=%02x, report_id=%02x, report_len=%d\r\n",report_type, report_id, hhid->EP0_ReportLen);
(void)USBD_CtlPrepareRx(pdev, hhid->EP0_ReportBuff, hhid->EP0_ReportLen);
return (uint8_t)USBD_OK;
}
uint8_t USBD_HID_Keyboard_SetReport_Token_Stage(USBD_HandleTypeDef *pdev)
{
#ifdef USE_USBD_COMPOSITE
uint8_t class_id;
class_id = USBD_CMPSIT_GetClassID_ByAdd(pdev, HID_KEYBOARD_EPIN_ADDR, USBD_EP_TYPE_INTR);
USBD_HID_Keyboard_HandleTypeDef *hhid = (USBD_HID_Keyboard_HandleTypeDef *)pdev->pClassDataCmsit[class_id];
#else
USBD_HID_Keyboard_HandleTypeDef *hhid = (USBD_HID_Keyboard_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
#endif
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
DEBUG("Token_Stage recv len = %d\n", hhid->EP0_ReportLen);
for(int i=0;i<hhid->EP0_ReportLen;i++){
DEBUG("0x%x ", hhid->EP0_ReportBuff[i]);
}DEBUG("\n");
return (uint8_t)USBD_OK;
}
uint8_t USBD_HID_Keyboard_GetReport_Token_Stage(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *setup_data)
{
uint16_t report_length;
uint8_t data[HID_KEYBOARD_EP0_GET_REPORT_BUF_SIZE];
DEBUG("%s,%d\n",__func__,__LINE__);
#ifdef USE_USBD_COMPOSITE
uint8_t class_id;
class_id = USBD_CMPSIT_GetClassID_ByAdd(pdev, HID_KEYBOARD_EPIN_ADDR, USBD_EP_TYPE_INTR);
USBD_HID_Keyboard_HandleTypeDef *hhid = (USBD_HID_Keyboard_HandleTypeDef *)pdev->pClassDataCmsit[class_id];
#else
USBD_HID_Keyboard_HandleTypeDef *hhid = (USBD_HID_Keyboard_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
#endif
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
for(int i=0;i<HID_KEYBOARD_EP0_GET_REPORT_BUF_SIZE;i++)
{
data[i] = i;
}
report_length = setup_data->wLength;
USBD_CtlSendData(pdev, data, report_length);
return (uint8_t)USBD_OK;
}
#ifndef USE_USBD_COMPOSITE
/**
* @brief DeviceQualifierDescriptor
* return Device Qualifier descriptor
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length)
{
*length = (uint16_t)sizeof(USBD_HID_DeviceQualifierDesc);
return USBD_HID_DeviceQualifierDesc;
}
#endif /* USE_USBD_COMPOSITE */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
component/xc6xx_drivers/Drivers/USB/Middlewares/Library/Class/HID_COMPOSITE/Src/usbd_hid_mouse.c
+841
View File
@@ -0,0 +1,841 @@
/*!
* \file usbd_hid_mouse.c
*
* \brief This file provides the HID core functions.
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author MCD Application Team
*
* \author ( XinChip ) Alex-J
*
* @verbatim
*
* ===================================================================
* HID Class Description
* ===================================================================
* This module manages the HID class V1.11 following the "Device Class Definition
* for Human Interface Devices (HID) Version 1.11 Jun 27, 2001".
* This driver implements the following aspects of the specification:
* - The Boot Interface Subclass
* - The Mouse protocol
* - Usage Page : Generic Desktop
* - Usage : Mouse
* - Collection : Application
*
* @note In HS mode and when the DMA is used, all variables and data structures
* dealing with the DMA during the transaction process should be 32-bit aligned.
*
*
* @endverbatim
*
*/
/* Includes ------------------------------------------------------------------*/
#include "usbd_hid_mouse.h"
#include "usbd_ctlreq.h"
#ifdef USE_USBD_COMPOSITE
#include "usbd_composite_builder.h"
#endif
/** @defgroup USBD_HID
* @brief usbd core module
* @{
*/
/** @defgroup USBD_HID_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup USBD_HID_Private_Defines
* @{
*/
/**
* @}
*/
/** @defgroup USBD_HID_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup USBD_HID_Private_FunctionPrototypes
* @{
*/
static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum);
static uint8_t USBD_HID_EP0_RxReady(USBD_HandleTypeDef *pdev);
static uint8_t USBD_HID_Mouse_SetReport_Setup_Stage(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *setup_data);
static uint8_t USBD_HID_Mouse_SetReport_Token_Stage(USBD_HandleTypeDef *pdev);
static uint8_t USBD_HID_Mouse_GetReport_Token_Stage(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *setup_data);
#ifndef USE_USBD_COMPOSITE
static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length);
static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length);
static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length);
static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length);
#endif /* USE_USBD_COMPOSITE */
/**
* @}
*/
/** @defgroup USBD_HID_Private_Variables
* @{
*/
USBD_ClassTypeDef USBD_HID_MOUSE =
{
USBD_HID_Init,
USBD_HID_DeInit,
USBD_HID_Setup,
NULL, /* EP0_TxSent */
USBD_HID_EP0_RxReady, /* EP0_RxReady */
USBD_HID_DataIn, /* DataIn */
NULL, /* DataOut */
NULL, /* SOF */
NULL,
NULL,
#ifdef USE_USBD_COMPOSITE
NULL,
NULL,
NULL,
NULL,
#else
USBD_HID_GetHSCfgDesc,
USBD_HID_GetFSCfgDesc,
USBD_HID_GetOtherSpeedCfgDesc,
USBD_HID_GetDeviceQualifierDesc,
#endif /* USE_USBD_COMPOSITE */
};
#ifndef USE_USBD_COMPOSITE
/* USB HID device FS Configuration Descriptor */
__ALIGN_BEGIN static uint8_t USBD_HID_CfgDesc[USB_HID_MOUSE_CONFIG_DESC_SIZ] __ALIGN_END =
{
0x09, /* bLength: Configuration Descriptor size */
USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */
USB_HID_MOUSE_CONFIG_DESC_SIZ, /* wTotalLength: Bytes returned */
0x00,
0x01, /* bNumInterfaces: 1 interface */
0x01, /* bConfigurationValue: Configuration value */
0x00, /* iConfiguration: Index of string descriptor
describing the configuration */
#if (USBD_SELF_POWERED == 1U)
0xE0, /* bmAttributes: Bus Powered according to user configuration */
#else
0xA0, /* bmAttributes: Bus Powered according to user configuration */
#endif /* USBD_SELF_POWERED */
USBD_MAX_POWER, /* MaxPower (mA) */
/************** Descriptor of Joystick Mouse interface ****************/
/* 09 */
0x09, /* bLength: Interface Descriptor size */
USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */
0x00, /* bInterfaceNumber: Number of Interface */
0x00, /* bAlternateSetting: Alternate setting */
0x01, /* bNumEndpoints */
0x03, /* bInterfaceClass: HID */
0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */
0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */
0, /* iInterface: Index of string descriptor */
/******************** Descriptor of Joystick Mouse HID ********************/
/* 18 */
0x09, /* bLength: HID Descriptor size */
HID_MOUSE_DESCRIPTOR_TYPE, /* bDescriptorType: HID */
0x11, /* bcdHID: HID Class Spec release number */
0x01,
0x00, /* bCountryCode: Hardware target country */
0x01, /* bNumDescriptors: Number of HID class descriptors to follow */
0x22, /* bDescriptorType */
HID_MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */
0x00,
/******************** Descriptor of Mouse endpoint ********************/
/* 27 */
0x07, /* bLength: Endpoint Descriptor size */
USB_DESC_TYPE_ENDPOINT, /* bDescriptorType:*/
HID_MOUSE_EPIN_ADDR, /* bEndpointAddress: Endpoint Address (IN) */
0x03, /* bmAttributes: Interrupt endpoint */
HID_MOUSE_EPIN_SIZE, /* wMaxPacketSize: 4 Bytes max */
0x00,
HID_MOUSE_FS_BINTERVAL, /* bInterval: Polling Interval */
/* 34 */
};
#endif /* USE_USBD_COMPOSITE */
/* USB HID device Configuration Descriptor */
__ALIGN_BEGIN static uint8_t USBD_HID_Desc[USB_HID_MOUSE_DESC_SIZ] __ALIGN_END =
{
/* 18 */
0x09, /* bLength: HID Descriptor size */
HID_MOUSE_DESCRIPTOR_TYPE, /* bDescriptorType: HID */
0x11, /* bcdHID: HID Class Spec release number */
0x01,
0x00, /* bCountryCode: Hardware target country */
0x01, /* bNumDescriptors: Number of HID class descriptors to follow */
0x22, /* bDescriptorType */
HID_MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */
0x00,
};
#ifndef USE_USBD_COMPOSITE
/* USB Standard Device Descriptor */
__ALIGN_BEGIN static uint8_t USBD_HID_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END =
{
USB_LEN_DEV_QUALIFIER_DESC,
USB_DESC_TYPE_DEVICE_QUALIFIER,
0x00,
0x02,
0x00,
0x00,
0x00,
0x40,
0x01,
0x00,
};
#endif /* USE_USBD_COMPOSITE */
__ALIGN_BEGIN static uint8_t HID_MOUSE_ReportDesc[HID_MOUSE_REPORT_DESC_SIZE] __ALIGN_END =
{
0x05, 0x01, /* Usage Page (Generic Desktop Ctrls) */
0x09, 0x02, /* Usage (Mouse) */
0xA1, 0x01, /* Collection (Application) */
0x09, 0x01, /* Usage (Pointer) */
0xA1, 0x00, /* Collection (Physical) */
0x05, 0x09, /* Usage Page (Button) */
0x19, 0x01, /* Usage Minimum (0x01) */
0x29, 0x03, /* Usage Maximum (0x03) */
0x15, 0x00, /* Logical Minimum (0) */
0x25, 0x01, /* Logical Maximum (1) */
0x95, 0x03, /* Report Count (3) */
0x75, 0x01, /* Report Size (1) */
0x81, 0x02, /* Input (Data,Var,Abs) */
0x95, 0x01, /* Report Count (1) */
0x75, 0x05, /* Report Size (5) */
0x81, 0x01, /* Input (Const,Array,Abs) */
0x05, 0x01, /* Usage Page (Generic Desktop Ctrls) */
0x09, 0x30, /* Usage (X) */
0x09, 0x31, /* Usage (Y) */
0x09, 0x38, /* Usage (Wheel) */
0x15, 0x81, /* Logical Minimum (-127) */
0x25, 0x7F, /* Logical Maximum (127) */
0x75, 0x08, /* Report Size (8) */
0x95, 0x03, /* Report Count (3) */
0x81, 0x06, /* Input (Data,Var,Rel) */
0xC0, /* End Collection */
0x09, 0x3C, /* Usage (Motion Wakeup) */
0x05, 0xFF, /* Usage Page (Reserved 0xFF) */
0x09, 0x01, /* Usage (0x01) */
0x15, 0x00, /* Logical Minimum (0) */
0x25, 0x01, /* Logical Maximum (1) */
0x75, 0x01, /* Report Size (1) */
0x95, 0x02, /* Report Count (2) */
0xB1, 0x22, /* Feature (Data,Var,Abs,NoWrp) */
0x75, 0x06, /* Report Size (6) */
0x95, 0x01, /* Report Count (1) */
0xB1, 0x01, /* Feature (Const,Array,Abs,NoWrp) */
0xC0 /* End Collection */
};
static uint8_t HIDInEpAdd = HID_MOUSE_EPIN_ADDR;
/**
* @}
*/
/** @defgroup USBD_HID_Private_Functions
* @{
*/
/**
* @brief USBD_HID_Init
* Initialize the HID interface
* @param pdev: device instance
* @param cfgidx: Configuration index
* @retval status
*/
static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
UNUSED(cfgidx);
USBD_HID_Mouse_HandleTypeDef *hhid;
hhid = (USBD_HID_Mouse_HandleTypeDef *)USBD_malloc(sizeof(USBD_HID_Mouse_HandleTypeDef));
printf("sizeof(USBD_HID_Mouse_HandleTypeDef)=0x%x\n",sizeof(USBD_HID_Mouse_HandleTypeDef));
if (hhid == NULL)
{
pdev->pClassDataCmsit[pdev->classId] = NULL;
return (uint8_t)USBD_EMEM;
}
pdev->pClassDataCmsit[pdev->classId] = (void *)hhid;
pdev->pClassData = pdev->pClassDataCmsit[pdev->classId];
#ifdef USE_USBD_COMPOSITE
/* Get the Endpoints addresses allocated for this class instance */
HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR);
#endif /* USE_USBD_COMPOSITE */
if (pdev->dev_speed == USBD_SPEED_HIGH)
{
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_MOUSE_HS_BINTERVAL;
}
else /* LOW and FULL-speed endpoints */
{
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_MOUSE_FS_BINTERVAL;
}
/* Open EP IN */
(void)USBD_LL_OpenEP(pdev, HIDInEpAdd, USBD_EP_TYPE_INTR, HID_MOUSE_EPIN_SIZE);
pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 1U;
hhid->state = MOUSE_HID_IDLE;
return (uint8_t)USBD_OK;
}
/**
* @brief USBD_HID_DeInit
* DeInitialize the HID layer
* @param pdev: device instance
* @param cfgidx: Configuration index
* @retval status
*/
static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
UNUSED(cfgidx);
#ifdef USE_USBD_COMPOSITE
/* Get the Endpoints addresses allocated for this class instance */
HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR);
#endif /* USE_USBD_COMPOSITE */
/* Close HID EPs */
(void)USBD_LL_CloseEP(pdev, HIDInEpAdd);
pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 0U;
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = 0U;
/* Free allocated memory */
if (pdev->pClassDataCmsit[pdev->classId] != NULL)
{
(void)USBD_free(pdev->pClassDataCmsit[pdev->classId]);
pdev->pClassDataCmsit[pdev->classId] = NULL;
}
return (uint8_t)USBD_OK;
}
/**
* @brief USBD_HID_Setup
* Handle the HID specific requests
* @param pdev: instance
* @param req: usb requests
* @retval status
*/
static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
USBD_HID_Mouse_HandleTypeDef *hhid = (USBD_HID_Mouse_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
USBD_StatusTypeDef ret = USBD_OK;
uint16_t len;
uint8_t *pbuf;
uint16_t status_info = 0U;
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
switch (req->bmRequest & USB_REQ_TYPE_MASK)
{
case USB_REQ_TYPE_CLASS :
switch (req->bRequest)
{
case HID_MOUSE_REQ_SET_PROTOCOL:
hhid->Protocol = (uint8_t)(req->wValue);
break;
case HID_MOUSE_REQ_GET_PROTOCOL:
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->Protocol, 1U);
break;
case HID_MOUSE_REQ_SET_IDLE:
hhid->IdleState = (uint8_t)(req->wValue >> 8);
break;
case HID_MOUSE_REQ_GET_IDLE:
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->IdleState, 1U);
break;
case HID_MOUSE_REQ_SET_REPORT:
USBD_HID_Mouse_SetReport_Setup_Stage(pdev, req);
break;
case HID_MOUSE_REQ_GET_REPORT:
USBD_HID_Mouse_GetReport_Token_Stage(pdev, req);
break;
default:
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
break;
}
break;
case USB_REQ_TYPE_STANDARD:
switch (req->bRequest)
{
case USB_REQ_GET_STATUS:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
(void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U);
}
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
case USB_REQ_GET_DESCRIPTOR:
if ((req->wValue >> 8) == HID_MOUSE_REPORT_DESC)
{
len = MIN(HID_MOUSE_REPORT_DESC_SIZE, req->wLength);
pbuf = HID_MOUSE_ReportDesc;
}
else if ((req->wValue >> 8) == HID_MOUSE_DESCRIPTOR_TYPE)
{
pbuf = USBD_HID_Desc;
len = MIN(USB_HID_MOUSE_DESC_SIZ, req->wLength);
}
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
break;
}
(void)USBD_CtlSendData(pdev, pbuf, len);
break;
case USB_REQ_GET_INTERFACE :
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->AltSetting, 1U);
}
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
case USB_REQ_SET_INTERFACE:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
hhid->AltSetting = (uint8_t)(req->wValue);
}
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
case USB_REQ_CLEAR_FEATURE:
break;
default:
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
break;
}
break;
default:
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
break;
}
return (uint8_t)ret;
}
/**
* @brief USBD_HID_Mouse_SendReport
* Send HID Report
* @param pdev: device instance
* @param buff: pointer to report
* @retval status
*/
uint8_t USBD_HID_Mouse_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len)
{
#ifdef USE_USBD_COMPOSITE
uint8_t class_id;
class_id = USBD_CMPSIT_GetClassID_ByAdd(pdev, HID_MOUSE_EPIN_ADDR, USBD_EP_TYPE_INTR);
USBD_HID_Mouse_HandleTypeDef *hhid = (USBD_HID_Mouse_HandleTypeDef *)pdev->pClassDataCmsit[class_id];
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
if (hhid->state == MOUSE_HID_IDLE)
{
hhid->state = MOUSE_HID_BUSY;
(void)USBD_LL_Transmit(pdev, HID_MOUSE_EPIN_ADDR, report, len);
}
}
return (uint8_t)USBD_OK;
#else
USBD_HID_Mouse_HandleTypeDef *hhid = (USBD_HID_Mouse_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
if (hhid->state == MOUSE_HID_IDLE)
{
hhid->state = MOUSE_HID_BUSY;
(void)USBD_LL_Transmit(pdev, HID_MOUSE_EPIN_ADDR, report, len);
}
}
return (uint8_t)USBD_OK;
#endif
}
extern uint8_t epnm_flag;
uint8_t USBD_HID_Mouse_FirstSendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len)
{
#ifdef USE_USBD_COMPOSITE
uint8_t class_id;
uint8_t ep_id = HID_MOUSE_EPIN_ADDR & 0xF;
class_id = USBD_CMPSIT_GetClassID_ByAdd(pdev, HID_MOUSE_EPIN_ADDR, USBD_EP_TYPE_INTR);
USBD_HID_Mouse_HandleTypeDef *hhid = (USBD_HID_Mouse_HandleTypeDef *)pdev->pClassDataCmsit[class_id];
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
PCD_HandleTypeDef *pcd = (PCD_HandleTypeDef *)(pdev->pData);
uint32_t USBx_BASE = (uint32_t)(PCD_HandleTypeDef *)pcd->Instance;
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
if ((hhid->state == MOUSE_HID_IDLE)||(epnm_flag == 0x01))
{
if(USBx_INEP(ep_id)->DIEPINT&USB_OTG_DIEPINT_ITTXFE)
{
USBx_INEP(ep_id)->DIEPINT |= USB_OTG_DIEPINT_ITTXFE;
hhid->state = MOUSE_HID_BUSY;
(void)USBD_LL_Transmit(pdev, HID_MOUSE_EPIN_ADDR, report, len);
}
else{
if(USBx_INEP(ep_id)->DIEPINT&USB_OTG_DIEPINT_NAK){
USBx_INEP(ep_id)->DIEPINT |= USB_OTG_DIEPINT_NAK;
USBx_INEP(ep_id)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
}
}
if(epnm_flag == 0x01){
epnm_flag = 0x00;
}
}
}
return (uint8_t)USBD_OK;
#else
uint8_t ep_id = HID_MOUSE_EPIN_ADDR & 0xF;
USBD_HID_Mouse_HandleTypeDef *hhid = (USBD_HID_Mouse_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
PCD_HandleTypeDef *pcd = (PCD_HandleTypeDef *)(pdev->pData);
uint32_t USBx_BASE = (uint32_t)(PCD_HandleTypeDef *)pcd->Instance;
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
if ((hhid->state == MOUSE_HID_IDLE)||(epnm_flag == 0x01))
{
if(USBx_INEP(ep_id)->DIEPINT&USB_OTG_DIEPINT_ITTXFE)
{
USBx_INEP(ep_id)->DIEPINT |= USB_OTG_DIEPINT_ITTXFE;
hhid->state = MOUSE_HID_BUSY;
(void)USBD_LL_Transmit(pdev, HID_MOUSE_EPIN_ADDR, report, len);
}
else{
if(USBx_INEP(ep_id)->DIEPINT&USB_OTG_DIEPINT_NAK){
USBx_INEP(ep_id)->DIEPINT |= USB_OTG_DIEPINT_NAK;
USBx_INEP(ep_id)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
}
}
if(epnm_flag == 0x01){
epnm_flag = 0x00;
}
}
}
return (uint8_t)USBD_OK;
#endif
}
/**
* @brief USBD_HID_GetPollingInterval
* return polling interval from endpoint descriptor
* @param pdev: device instance
* @retval polling interval
*/
uint32_t USBD_HID_GetPollingInterval(USBD_HandleTypeDef *pdev)
{
uint32_t polling_interval;
/* HIGH-speed endpoints */
if (pdev->dev_speed == USBD_SPEED_HIGH)
{
/* Sets the data transfer polling interval for high speed transfers.
Values between 1..16 are allowed. Values correspond to interval
of 2 ^ (bInterval-1). This option (8 ms, corresponds to HID_MOUSE_HS_BINTERVAL */
polling_interval = (((1U << (HID_MOUSE_HS_BINTERVAL - 1U))) / 8U);
}
else /* LOW and FULL-speed endpoints */
{
/* Sets the data transfer polling interval for low and full
speed transfers */
polling_interval = HID_MOUSE_FS_BINTERVAL;
}
return ((uint32_t)(polling_interval));
}
#ifndef USE_USBD_COMPOSITE
/**
* @brief USBD_HID_GetCfgFSDesc
* return FS configuration descriptor
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length)
{
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_MOUSE_EPIN_ADDR);
if (pEpDesc != NULL)
{
pEpDesc->bInterval = HID_MOUSE_FS_BINTERVAL;
}
*length = (uint16_t)sizeof(USBD_HID_CfgDesc);
return USBD_HID_CfgDesc;
}
/**
* @brief USBD_HID_GetCfgHSDesc
* return HS configuration descriptor
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length)
{
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_MOUSE_EPIN_ADDR);
if (pEpDesc != NULL)
{
pEpDesc->bInterval = HID_MOUSE_HS_BINTERVAL;
}
*length = (uint16_t)sizeof(USBD_HID_CfgDesc);
return USBD_HID_CfgDesc;
}
/**
* @brief USBD_HID_GetOtherSpeedCfgDesc
* return other speed configuration descriptor
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length)
{
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_MOUSE_EPIN_ADDR);
if (pEpDesc != NULL)
{
pEpDesc->bInterval = HID_MOUSE_FS_BINTERVAL;
}
*length = (uint16_t)sizeof(USBD_HID_CfgDesc);
return USBD_HID_CfgDesc;
}
#endif /* USE_USBD_COMPOSITE */
/**
* @brief USBD_HID_DataIn
* handle data IN Stage
* @param pdev: device instance
* @param epnum: endpoint index
* @retval status
*/
static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum)
{
UNUSED(epnum);
/* Ensure that the FIFO is empty before a new transfer, this condition could
be caused by a new transfer before the end of the previous transfer */
((USBD_HID_Mouse_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId])->state = MOUSE_HID_IDLE;
#ifdef APP_USB_MOUSE_FAST_SEND_DATA
extern void app_usb_mouse_fast_send_data(USBD_HandleTypeDef *pdev);
app_usb_mouse_fast_send_data(pdev);
#endif
return (uint8_t)USBD_OK;
}
static uint8_t USBD_HID_EP0_RxReady(USBD_HandleTypeDef *pdev)
{
DEBUG("Mouse USBD_HID_EP0_RxReady\r\n");
USBD_HID_Mouse_SetReport_Token_Stage(pdev);
return (uint8_t)USBD_OK;
}
uint8_t USBD_HID_Mouse_SetReport_Setup_Stage(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *setup_data)
{
uint8_t report_type;
uint8_t report_id;
#ifdef USE_USBD_COMPOSITE
uint8_t class_id;
class_id = USBD_CMPSIT_GetClassID_ByAdd(pdev, HID_MOUSE_EPIN_ADDR, USBD_EP_TYPE_INTR);
USBD_HID_Mouse_HandleTypeDef *hhid = (USBD_HID_Mouse_HandleTypeDef *)pdev->pClassDataCmsit[class_id];
#else
USBD_HID_Mouse_HandleTypeDef *hhid = (USBD_HID_Mouse_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
#endif
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
report_type = (setup_data->wValue >> 8) & 0xFF;
report_id = setup_data->wValue & 0xFF;
hhid->EP0_ReportLen = setup_data->wLength;
DEBUG("Setup_Stage report_type=%02x, report_id=%02x, report_len=%d\r\n",report_type, report_id, hhid->EP0_ReportLen);
(void)USBD_CtlPrepareRx(pdev, hhid->EP0_ReportBuff, hhid->EP0_ReportLen);
return (uint8_t)USBD_OK;
}
uint8_t USBD_HID_Mouse_SetReport_Token_Stage(USBD_HandleTypeDef *pdev)
{
#ifdef USE_USBD_COMPOSITE
uint8_t class_id;
class_id = USBD_CMPSIT_GetClassID_ByAdd(pdev, HID_MOUSE_EPIN_ADDR, USBD_EP_TYPE_INTR);
USBD_HID_Mouse_HandleTypeDef *hhid = (USBD_HID_Mouse_HandleTypeDef *)pdev->pClassDataCmsit[class_id];
#else
USBD_HID_Mouse_HandleTypeDef *hhid = (USBD_HID_Mouse_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
#endif
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
DEBUG("Token_Stage recv len = %d\n", hhid->EP0_ReportLen);
for(int i=0;i<hhid->EP0_ReportLen;i++){
DEBUG("0x%x ", hhid->EP0_ReportBuff[i]);
}DEBUG("\n");
return (uint8_t)USBD_OK;
}
uint8_t USBD_HID_Mouse_GetReport_Token_Stage(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *setup_data)
{
uint16_t report_length;
uint8_t data[HID_MOUSE_EP0_GET_REPORT_BUF_SIZE];
DEBUG("%s,%d\n",__func__,__LINE__);
#ifdef USE_USBD_COMPOSITE
uint8_t class_id;
class_id = USBD_CMPSIT_GetClassID_ByAdd(pdev, HID_MOUSE_EPIN_ADDR, USBD_EP_TYPE_INTR);
USBD_HID_Mouse_HandleTypeDef *hhid = (USBD_HID_Mouse_HandleTypeDef *)pdev->pClassDataCmsit[class_id];
#else
USBD_HID_Mouse_HandleTypeDef *hhid = (USBD_HID_Mouse_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
#endif
if (hhid == NULL)
{
return (uint8_t)USBD_FAIL;
}
for(int i=0;i<HID_MOUSE_EP0_GET_REPORT_BUF_SIZE;i++)
{
data[i] = i;
}
report_length = setup_data->wLength;
USBD_CtlSendData(pdev, data, report_length);
return (uint8_t)USBD_OK;
}
#ifndef USE_USBD_COMPOSITE
/**
* @brief DeviceQualifierDescriptor
* return Device Qualifier descriptor
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length)
{
*length = (uint16_t)sizeof(USBD_HID_DeviceQualifierDesc);
return USBD_HID_DeviceQualifierDesc;
}
#endif /* USE_USBD_COMPOSITE */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
component/xc6xx_drivers/Drivers/USB/Middlewares/Library/Class/MSC/Inc/usbd_msc.h
+136
View File
@@ -0,0 +1,136 @@
/*!
* \file usbd_msc.h
*
* \brief Header for the usbd_msc.c file
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author MCD Application Team
*
* \author ( XinChip ) Alex-J
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USBD_MSC_H
#define __USBD_MSC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "usbd_msc_bot.h"
#include "usbd_msc_scsi.h"
#include "usbd_ioreq.h"
/** @addtogroup USBD_MSC_BOT
* @{
*/
/** @defgroup USBD_MSC
* @brief This file is the Header file for usbd_msc.c
* @{
*/
/** @defgroup USBD_BOT_Exported_Defines
* @{
*/
/* MSC Class Config */
#ifndef MSC_MEDIA_PACKET
#define MSC_MEDIA_PACKET 512U
#endif /* MSC_MEDIA_PACKET */
#define MSC_MAX_FS_PACKET 0x40U
#define MSC_MAX_HS_PACKET 0x200U
#define BOT_GET_MAX_LUN 0xFE
#define BOT_RESET 0xFF
#define USB_MSC_CONFIG_DESC_SIZ 32
#ifndef MSC_EPIN_ADDR
#define MSC_EPIN_ADDR 0x81U
#endif /* MSC_EPIN_ADDR */
#ifndef MSC_EPOUT_ADDR
#define MSC_EPOUT_ADDR 0x01U
#endif /* MSC_EPOUT_ADDR */
/**
* @}
*/
/** @defgroup USB_CORE_Exported_Types
* @{
*/
typedef struct _USBD_STORAGE
{
int8_t (* Init)(uint8_t lun);
int8_t (* GetCapacity)(uint8_t lun, uint32_t *block_num, uint16_t *block_size);
int8_t (* IsReady)(uint8_t lun);
int8_t (* IsWriteProtected)(uint8_t lun);
int8_t (* Read)(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len);
int8_t (* Write)(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len);
int8_t (* GetMaxLun)(void);
int8_t *pInquiry;
} USBD_StorageTypeDef;
typedef struct
{
uint32_t max_lun;
uint32_t interface;
uint8_t bot_state;
uint8_t bot_status;
uint32_t bot_data_length;
uint8_t bot_data[MSC_MEDIA_PACKET];
USBD_MSC_BOT_CBWTypeDef cbw;
USBD_MSC_BOT_CSWTypeDef csw;
USBD_SCSI_SenseTypeDef scsi_sense [SENSE_LIST_DEEPTH];
uint8_t scsi_sense_head;
uint8_t scsi_sense_tail;
uint8_t scsi_medium_state;
uint16_t scsi_blk_size;
uint32_t scsi_blk_nbr;
uint32_t scsi_blk_addr;
uint32_t scsi_blk_len;
} USBD_MSC_BOT_HandleTypeDef;
/* Structure for MSC process */
extern USBD_ClassTypeDef USBD_MSC;
#define USBD_MSC_CLASS &USBD_MSC
uint8_t USBD_MSC_RegisterStorage(USBD_HandleTypeDef *pdev,
USBD_StorageTypeDef *fops);
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __USBD_MSC_H */
/**
* @}
*/
component/xc6xx_drivers/Drivers/USB/Middlewares/Library/Class/MSC/Inc/usbd_msc_bot.h
+150
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@@ -0,0 +1,150 @@
/*!
* \file usbd_msc_bot.h
*
* \brief Header for the usbd_msc_bot.c file.
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author MCD Application Team
*
* \author ( XinChip ) Alex-J
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USBD_MSC_BOT_H
#define __USBD_MSC_BOT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "usbd_core.h"
/** @defgroup MSC_BOT
* @brief This file is the Header file for usbd_msc_bot.c
* @{
*/
/** @defgroup USBD_CORE_Exported_Defines
* @{
*/
#define USBD_BOT_IDLE 0U /* Idle state */
#define USBD_BOT_DATA_OUT 1U /* Data Out state */
#define USBD_BOT_DATA_IN 2U /* Data In state */
#define USBD_BOT_LAST_DATA_IN 3U /* Last Data In Last */
#define USBD_BOT_SEND_DATA 4U /* Send Immediate data */
#define USBD_BOT_NO_DATA 5U /* No data Stage */
#define USBD_BOT_CBW_SIGNATURE 0x43425355U
#define USBD_BOT_CSW_SIGNATURE 0x53425355U
#define USBD_BOT_CBW_LENGTH 31U
#define USBD_BOT_CSW_LENGTH 13U
#define USBD_BOT_MAX_DATA 256U
/* CSW Status Definitions */
#define USBD_CSW_CMD_PASSED 0x00U
#define USBD_CSW_CMD_FAILED 0x01U
#define USBD_CSW_PHASE_ERROR 0x02U
/* BOT Status */
#define USBD_BOT_STATUS_NORMAL 0U
#define USBD_BOT_STATUS_RECOVERY 1U
#define USBD_BOT_STATUS_ERROR 2U
#define USBD_DIR_IN 0U
#define USBD_DIR_OUT 1U
#define USBD_BOTH_DIR 2U
/**
* @}
*/
/** @defgroup MSC_CORE_Private_TypesDefinitions
* @{
*/
typedef struct
{
uint32_t dSignature;
uint32_t dTag;
uint32_t dDataLength;
uint8_t bmFlags;
uint8_t bLUN;
uint8_t bCBLength;
uint8_t CB[16];
uint8_t ReservedForAlign;
} USBD_MSC_BOT_CBWTypeDef;
typedef struct
{
uint32_t dSignature;
uint32_t dTag;
uint32_t dDataResidue;
uint8_t bStatus;
uint8_t ReservedForAlign[3];
} USBD_MSC_BOT_CSWTypeDef;
/**
* @}
*/
/** @defgroup USBD_CORE_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup USBD_CORE_Exported_FunctionsPrototypes
* @{
*/
void MSC_BOT_Init(USBD_HandleTypeDef *pdev);
void MSC_BOT_Reset(USBD_HandleTypeDef *pdev);
void MSC_BOT_DeInit(USBD_HandleTypeDef *pdev);
void MSC_BOT_DataIn(USBD_HandleTypeDef *pdev,
uint8_t epnum);
void MSC_BOT_DataOut(USBD_HandleTypeDef *pdev,
uint8_t epnum);
void MSC_BOT_SendCSW(USBD_HandleTypeDef *pdev,
uint8_t CSW_Status);
void MSC_BOT_CplClrFeature(USBD_HandleTypeDef *pdev,
uint8_t epnum);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __USBD_MSC_BOT_H */
/**
* @}
*/
/**
* @}
*/
component/xc6xx_drivers/Drivers/USB/Middlewares/Library/Class/MSC/Inc/usbd_msc_data.h
+106
View File
@@ -0,0 +1,106 @@
/*!
* \file usbd_msc_data.h
*
* \brief Header for the usbd_msc_data.c file.
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author MCD Application Team
*
* \author ( XinChip ) Alex-J
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USBD_MSC_DATA_H
#define __USBD_MSC_DATA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "usbd_conf.h"
/** @defgroup USB_INFO
* @brief general defines for the usb device library file
* @{
*/
/** @defgroup USB_INFO_Exported_Defines
* @{
*/
#define MODE_SENSE6_LEN 0x17U
#define MODE_SENSE10_LEN 0x1BU
#define LENGTH_INQUIRY_PAGE00 0x06U
#define LENGTH_INQUIRY_PAGE80 0x08U
#define LENGTH_FORMAT_CAPACITIES 0x14U
/**
* @}
*/
/** @defgroup USBD_INFO_Exported_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup USBD_INFO_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup USBD_INFO_Exported_Variables
* @{
*/
extern uint8_t MSC_Page00_Inquiry_Data[LENGTH_INQUIRY_PAGE00];
extern uint8_t MSC_Page80_Inquiry_Data[LENGTH_INQUIRY_PAGE80];
extern uint8_t MSC_Mode_Sense6_data[MODE_SENSE6_LEN];
extern uint8_t MSC_Mode_Sense10_data[MODE_SENSE10_LEN];
/**
* @}
*/
/** @defgroup USBD_INFO_Exported_FunctionsPrototype
* @{
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __USBD_MSC_DATA_H */
/**
* @}
*/
/**
* @}
*/
component/xc6xx_drivers/Drivers/USB/Middlewares/Library/Class/MSC/Inc/usbd_msc_scsi.h
+186
View File
@@ -0,0 +1,186 @@
/*!
* \file usbd_msc_scsi.h
*
* \brief Header for the usbd_msc_scsi.c file.
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author MCD Application Team
*
* \author ( XinChip ) Alex-J
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USBD_MSC_SCSI_H
#define __USBD_MSC_SCSI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "usbd_def.h"
/** @defgroup USBD_SCSI
* @brief header file for the storage disk file
* @{
*/
/** @defgroup USBD_SCSI_Exported_Defines
* @{
*/
#define SENSE_LIST_DEEPTH 4U
/* SCSI Commands */
#define SCSI_FORMAT_UNIT 0x04U
#define SCSI_INQUIRY 0x12U
#define SCSI_MODE_SELECT6 0x15U
#define SCSI_MODE_SELECT10 0x55U
#define SCSI_MODE_SENSE6 0x1AU
#define SCSI_MODE_SENSE10 0x5AU
#define SCSI_ALLOW_MEDIUM_REMOVAL 0x1EU
#define SCSI_READ6 0x08U
#define SCSI_READ10 0x28U
#define SCSI_READ12 0xA8U
#define SCSI_READ16 0x88U
#define SCSI_READ_CAPACITY10 0x25U
#define SCSI_READ_CAPACITY16 0x9EU
#define SCSI_REQUEST_SENSE 0x03U
#define SCSI_START_STOP_UNIT 0x1BU
#define SCSI_TEST_UNIT_READY 0x00U
#define SCSI_WRITE6 0x0AU
#define SCSI_WRITE10 0x2AU
#define SCSI_WRITE12 0xAAU
#define SCSI_WRITE16 0x8AU
#define SCSI_VERIFY10 0x2FU
#define SCSI_VERIFY12 0xAFU
#define SCSI_VERIFY16 0x8FU
#define SCSI_SEND_DIAGNOSTIC 0x1DU
#define SCSI_READ_FORMAT_CAPACITIES 0x23U
#define NO_SENSE 0U
#define RECOVERED_ERROR 1U
#define NOT_READY 2U
#define MEDIUM_ERROR 3U
#define HARDWARE_ERROR 4U
#define ILLEGAL_REQUEST 5U
#define UNIT_ATTENTION 6U
#define DATA_PROTECT 7U
#define BLANK_CHECK 8U
#define VENDOR_SPECIFIC 9U
#define COPY_ABORTED 10U
#define ABORTED_COMMAND 11U
#define VOLUME_OVERFLOW 13U
#define MISCOMPARE 14U
#define INVALID_CDB 0x20U
#define INVALID_FIELED_IN_COMMAND 0x24U
#define PARAMETER_LIST_LENGTH_ERROR 0x1AU
#define INVALID_FIELD_IN_PARAMETER_LIST 0x26U
#define ADDRESS_OUT_OF_RANGE 0x21U
#define MEDIUM_NOT_PRESENT 0x3AU
#define MEDIUM_HAVE_CHANGED 0x28U
#define WRITE_PROTECTED 0x27U
#define UNRECOVERED_READ_ERROR 0x11U
#define WRITE_FAULT 0x03U
#define READ_FORMAT_CAPACITY_DATA_LEN 0x0CU
#define READ_CAPACITY10_DATA_LEN 0x08U
#define REQUEST_SENSE_DATA_LEN 0x12U
#define STANDARD_INQUIRY_DATA_LEN 0x24U
#define BLKVFY 0x04U
#define SCSI_MEDIUM_UNLOCKED 0x00U
#define SCSI_MEDIUM_LOCKED 0x01U
#define SCSI_MEDIUM_EJECTED 0x02U
/**
* @}
*/
/** @defgroup USBD_SCSI_Exported_TypesDefinitions
* @{
*/
typedef struct _SENSE_ITEM
{
uint8_t Skey;
union
{
struct _ASCs
{
uint8_t ASC;
uint8_t ASCQ;
} b;
uint8_t ASC;
uint8_t *pData;
} w;
} USBD_SCSI_SenseTypeDef;
/**
* @}
*/
/** @defgroup USBD_SCSI_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup USBD_SCSI_Exported_Variables
* @{
*/
/**
* @}
*/
/** @defgroup USBD_SCSI_Exported_FunctionsPrototype
* @{
*/
int8_t SCSI_ProcessCmd(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *cmd);
void SCSI_SenseCode(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t sKey,
uint8_t ASC);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __USBD_MSC_SCSI_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
component/xc6xx_drivers/Drivers/USB/Middlewares/Library/Class/MSC/Src/usbd_msc.c
+579
View File
@@ -0,0 +1,579 @@
/*!
* \file usbd_msc.c
*
* \brief This file provides all the MSC core functions.
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author MCD Application Team
*
* \author ( XinChip ) Alex-J
* @verbatim
*
* ===================================================================
* MSC Class Description
* ===================================================================
* This module manages the MSC class V1.0 following the "Universal
* Serial Bus Mass Storage Class (MSC) Bulk-Only Transport (BOT) Version 1.0
* Sep. 31, 1999".
* This driver implements the following aspects of the specification:
* - Bulk-Only Transport protocol
* - Subclass : SCSI transparent command set (ref. SCSI Primary Commands - 3 (SPC-3))
*
* @endverbatim
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "usbd_msc.h"
/** @defgroup MSC_CORE
* @brief Mass storage core module
* @{
*/
/** @defgroup MSC_CORE_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup MSC_CORE_Private_Defines
* @{
*/
/**
* @}
*/
/** @defgroup MSC_CORE_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup MSC_CORE_Private_FunctionPrototypes
* @{
*/
uint8_t USBD_MSC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
uint8_t USBD_MSC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
uint8_t USBD_MSC_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
uint8_t USBD_MSC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum);
uint8_t USBD_MSC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum);
#ifndef USE_USBD_COMPOSITE
uint8_t *USBD_MSC_GetHSCfgDesc(uint16_t *length);
uint8_t *USBD_MSC_GetFSCfgDesc(uint16_t *length);
uint8_t *USBD_MSC_GetOtherSpeedCfgDesc(uint16_t *length);
uint8_t *USBD_MSC_GetDeviceQualifierDescriptor(uint16_t *length);
#endif /* USE_USBD_COMPOSITE */
/**
* @}
*/
/** @defgroup MSC_CORE_Private_Variables
* @{
*/
USBD_ClassTypeDef USBD_MSC =
{
USBD_MSC_Init,
USBD_MSC_DeInit,
USBD_MSC_Setup,
NULL, /*EP0_TxSent*/
NULL, /*EP0_RxReady*/
USBD_MSC_DataIn,
USBD_MSC_DataOut,
NULL, /*SOF */
NULL,
NULL,
#ifdef USE_USBD_COMPOSITE
NULL,
NULL,
NULL,
NULL,
#else
USBD_MSC_GetHSCfgDesc,
USBD_MSC_GetFSCfgDesc,
USBD_MSC_GetOtherSpeedCfgDesc,
USBD_MSC_GetDeviceQualifierDescriptor,
#endif /* USE_USBD_COMPOSITE */
};
/* USB Mass storage device Configuration Descriptor */
#ifndef USE_USBD_COMPOSITE
/* USB Mass storage device Configuration Descriptor */
/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */
__ALIGN_BEGIN static uint8_t USBD_MSC_CfgDesc[USB_MSC_CONFIG_DESC_SIZ] __ALIGN_END =
{
0x09, /* bLength: Configuration Descriptor size */
USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */
USB_MSC_CONFIG_DESC_SIZ,
0x00,
0x01, /* bNumInterfaces: 1 interface */
0x01, /* bConfigurationValue */
0x04, /* iConfiguration */
#if (USBD_SELF_POWERED == 1U)
0xC0, /* bmAttributes: Bus Powered according to user configuration */
#else
0x80, /* bmAttributes: Bus Powered according to user configuration */
#endif /* USBD_SELF_POWERED */
USBD_MAX_POWER, /* MaxPower (mA) */
/******************** Mass Storage interface ********************/
0x09, /* bLength: Interface Descriptor size */
0x04, /* bDescriptorType: */
0x00, /* bInterfaceNumber: Number of Interface */
0x00, /* bAlternateSetting: Alternate setting */
0x02, /* bNumEndpoints */
0x08, /* bInterfaceClass: MSC Class */
0x06, /* bInterfaceSubClass : SCSI transparent*/
0x50, /* nInterfaceProtocol */
0x05, /* iInterface: */
/******************** Mass Storage Endpoints ********************/
0x07, /* Endpoint descriptor length = 7 */
0x05, /* Endpoint descriptor type */
MSC_EPIN_ADDR, /* Endpoint address (IN, address 1) */
0x02, /* Bulk endpoint type */
LOBYTE(MSC_MAX_FS_PACKET),
HIBYTE(MSC_MAX_FS_PACKET),
0x00, /* Polling interval in milliseconds */
0x07, /* Endpoint descriptor length = 7 */
0x05, /* Endpoint descriptor type */
MSC_EPOUT_ADDR, /* Endpoint address (OUT, address 1) */
0x02, /* Bulk endpoint type */
LOBYTE(MSC_MAX_FS_PACKET),
HIBYTE(MSC_MAX_FS_PACKET),
0x00 /* Polling interval in milliseconds */
};
/* USB Standard Device Descriptor */
__ALIGN_BEGIN static uint8_t USBD_MSC_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END =
{
USB_LEN_DEV_QUALIFIER_DESC,
USB_DESC_TYPE_DEVICE_QUALIFIER,
0x00,
0x02,
0x00,
0x00,
0x00,
MSC_MAX_FS_PACKET,
0x01,
0x00,
};
#endif /* USE_USBD_COMPOSITE */
uint8_t MSCInEpAdd = MSC_EPIN_ADDR;
uint8_t MSCOutEpAdd = MSC_EPOUT_ADDR;
/**
* @}
*/
/** @defgroup MSC_CORE_Private_Functions
* @{
*/
/**
* @brief USBD_MSC_Init
* Initialize the mass storage configuration
* @param pdev: device instance
* @param cfgidx: configuration index
* @retval status
*/
uint8_t USBD_MSC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
UNUSED(cfgidx);
USBD_MSC_BOT_HandleTypeDef *hmsc;
hmsc = (USBD_MSC_BOT_HandleTypeDef *)USBD_malloc(sizeof(USBD_MSC_BOT_HandleTypeDef));
DEBUG("sizeof(USBD_MSC_BOT_HandleTypeDef)=0x%x\n",sizeof(USBD_MSC_BOT_HandleTypeDef));
if (hmsc == NULL)
{
pdev->pClassDataCmsit[pdev->classId] = NULL;
return (uint8_t)USBD_EMEM;
}
pdev->pClassDataCmsit[pdev->classId] = (void *)hmsc;
pdev->pClassData = pdev->pClassDataCmsit[pdev->classId];
#ifdef USE_USBD_COMPOSITE
/* Get the Endpoints addresses allocated for this class instance */
MSCInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_BULK);
MSCOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_BULK);
#endif /* USE_USBD_COMPOSITE */
if (pdev->dev_speed == USBD_SPEED_HIGH)
{
/* Open EP OUT */
(void)USBD_LL_OpenEP(pdev, MSCOutEpAdd, USBD_EP_TYPE_BULK, MSC_MAX_HS_PACKET);
pdev->ep_out[MSCOutEpAdd & 0xFU].is_used = 1U;
/* Open EP IN */
(void)USBD_LL_OpenEP(pdev, MSCInEpAdd, USBD_EP_TYPE_BULK, MSC_MAX_HS_PACKET);
pdev->ep_in[MSCInEpAdd & 0xFU].is_used = 1U;
}
else
{
/* Open EP OUT */
(void)USBD_LL_OpenEP(pdev, MSCOutEpAdd, USBD_EP_TYPE_BULK, MSC_MAX_FS_PACKET);
pdev->ep_out[MSCOutEpAdd & 0xFU].is_used = 1U;
/* Open EP IN */
(void)USBD_LL_OpenEP(pdev, MSCInEpAdd, USBD_EP_TYPE_BULK, MSC_MAX_FS_PACKET);
pdev->ep_in[MSCInEpAdd & 0xFU].is_used = 1U;
}
/* Init the BOT layer */
MSC_BOT_Init(pdev);
return (uint8_t)USBD_OK;
}
/**
* @brief USBD_MSC_DeInit
* DeInitialize the mass storage configuration
* @param pdev: device instance
* @param cfgidx: configuration index
* @retval status
*/
uint8_t USBD_MSC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
UNUSED(cfgidx);
#ifdef USE_USBD_COMPOSITE
/* Get the Endpoints addresses allocated for this class instance */
MSCInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_BULK);
MSCOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_BULK);
#endif /* USE_USBD_COMPOSITE */
/* Close MSC EPs */
(void)USBD_LL_CloseEP(pdev, MSCOutEpAdd);
pdev->ep_out[MSCOutEpAdd & 0xFU].is_used = 0U;
/* Close EP IN */
(void)USBD_LL_CloseEP(pdev, MSCInEpAdd);
pdev->ep_in[MSCInEpAdd & 0xFU].is_used = 0U;
/* Free MSC Class Resources */
if (pdev->pClassDataCmsit[pdev->classId] != NULL)
{
/* De-Init the BOT layer */
MSC_BOT_DeInit(pdev);
(void)USBD_free(pdev->pClassDataCmsit[pdev->classId]);
pdev->pClassDataCmsit[pdev->classId] = NULL;
pdev->pClassData = NULL;
}
return (uint8_t)USBD_OK;
}
/**
* @brief USBD_MSC_Setup
* Handle the MSC specific requests
* @param pdev: device instance
* @param req: USB request
* @retval status
*/
uint8_t USBD_MSC_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
USBD_StatusTypeDef ret = USBD_OK;
uint16_t status_info = 0U;
#ifdef USE_USBD_COMPOSITE
/* Get the Endpoints addresses allocated for this class instance */
MSCInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_BULK);
MSCOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_BULK);
#endif /* USE_USBD_COMPOSITE */
if (hmsc == NULL)
{
return (uint8_t)USBD_FAIL;
}
switch (req->bmRequest & USB_REQ_TYPE_MASK)
{
/* Class request */
case USB_REQ_TYPE_CLASS:
switch (req->bRequest)
{
case BOT_GET_MAX_LUN:
if ((req->wValue == 0U) && (req->wLength == 1U) &&
((req->bmRequest & 0x80U) == 0x80U))
{
hmsc->max_lun = (uint32_t)((USBD_StorageTypeDef *)pdev->pUserData[pdev->classId])->GetMaxLun();
(void)USBD_CtlSendData(pdev, (uint8_t *)&hmsc->max_lun, 1U);
}
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
case BOT_RESET :
if ((req->wValue == 0U) && (req->wLength == 0U) &&
((req->bmRequest & 0x80U) != 0x80U))
{
MSC_BOT_Reset(pdev);
}
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
default:
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
break;
}
break;
/* Interface & Endpoint request */
case USB_REQ_TYPE_STANDARD:
switch (req->bRequest)
{
case USB_REQ_GET_STATUS:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
(void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U);
}
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
case USB_REQ_GET_INTERFACE:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
(void)USBD_CtlSendData(pdev, (uint8_t *)&hmsc->interface, 1U);
}
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
case USB_REQ_SET_INTERFACE:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
hmsc->interface = (uint8_t)(req->wValue);
}
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
case USB_REQ_CLEAR_FEATURE:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
{
if (req->wValue == USB_FEATURE_EP_HALT)
{
/* Flush the FIFO */
(void)USBD_LL_FlushEP(pdev, (uint8_t)req->wIndex);
/* Handle BOT error */
MSC_BOT_CplClrFeature(pdev, (uint8_t)req->wIndex);
}
}
break;
default:
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
break;
}
break;
default:
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
break;
}
return (uint8_t)ret;
}
/**
* @brief USBD_MSC_DataIn
* handle data IN Stage
* @param pdev: device instance
* @param epnum: endpoint index
* @retval status
*/
uint8_t USBD_MSC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum)
{
MSC_BOT_DataIn(pdev, epnum);
return (uint8_t)USBD_OK;
}
/**
* @brief USBD_MSC_DataOut
* handle data OUT Stage
* @param pdev: device instance
* @param epnum: endpoint index
* @retval status
*/
uint8_t USBD_MSC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum)
{
MSC_BOT_DataOut(pdev, epnum);
return (uint8_t)USBD_OK;
}
#ifndef USE_USBD_COMPOSITE
/**
* @brief USBD_MSC_GetHSCfgDesc
* return configuration descriptor
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
uint8_t *USBD_MSC_GetHSCfgDesc(uint16_t *length)
{
USBD_EpDescTypeDef *pEpInDesc = USBD_GetEpDesc(USBD_MSC_CfgDesc, MSC_EPIN_ADDR);
USBD_EpDescTypeDef *pEpOutDesc = USBD_GetEpDesc(USBD_MSC_CfgDesc, MSC_EPOUT_ADDR);
if (pEpInDesc != NULL)
{
pEpInDesc->wMaxPacketSize = MSC_MAX_HS_PACKET;
}
if (pEpOutDesc != NULL)
{
pEpOutDesc->wMaxPacketSize = MSC_MAX_HS_PACKET;
}
*length = (uint16_t)sizeof(USBD_MSC_CfgDesc);
return USBD_MSC_CfgDesc;
}
/**
* @brief USBD_MSC_GetFSCfgDesc
* return configuration descriptor
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
uint8_t *USBD_MSC_GetFSCfgDesc(uint16_t *length)
{
USBD_EpDescTypeDef *pEpInDesc = USBD_GetEpDesc(USBD_MSC_CfgDesc, MSC_EPIN_ADDR);
USBD_EpDescTypeDef *pEpOutDesc = USBD_GetEpDesc(USBD_MSC_CfgDesc, MSC_EPOUT_ADDR);
if (pEpInDesc != NULL)
{
pEpInDesc->wMaxPacketSize = MSC_MAX_FS_PACKET;
}
if (pEpOutDesc != NULL)
{
pEpOutDesc->wMaxPacketSize = MSC_MAX_FS_PACKET;
}
*length = (uint16_t)sizeof(USBD_MSC_CfgDesc);
return USBD_MSC_CfgDesc;
}
/**
* @brief USBD_MSC_GetOtherSpeedCfgDesc
* return other speed configuration descriptor
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
uint8_t *USBD_MSC_GetOtherSpeedCfgDesc(uint16_t *length)
{
USBD_EpDescTypeDef *pEpInDesc = USBD_GetEpDesc(USBD_MSC_CfgDesc, MSC_EPIN_ADDR);
USBD_EpDescTypeDef *pEpOutDesc = USBD_GetEpDesc(USBD_MSC_CfgDesc, MSC_EPOUT_ADDR);
if (pEpInDesc != NULL)
{
pEpInDesc->wMaxPacketSize = MSC_MAX_FS_PACKET;
}
if (pEpOutDesc != NULL)
{
pEpOutDesc->wMaxPacketSize = MSC_MAX_FS_PACKET;
}
*length = (uint16_t)sizeof(USBD_MSC_CfgDesc);
return USBD_MSC_CfgDesc;
}
/**
* @brief DeviceQualifierDescriptor
* return Device Qualifier descriptor
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
uint8_t *USBD_MSC_GetDeviceQualifierDescriptor(uint16_t *length)
{
*length = (uint16_t)sizeof(USBD_MSC_DeviceQualifierDesc);
return USBD_MSC_DeviceQualifierDesc;
}
#endif /* USE_USBD_COMPOSITE */
/**
* @brief USBD_MSC_RegisterStorage
* @param fops: storage callback
* @retval status
*/
uint8_t USBD_MSC_RegisterStorage(USBD_HandleTypeDef *pdev, USBD_StorageTypeDef *fops)
{
if (fops == NULL)
{
return (uint8_t)USBD_FAIL;
}
pdev->pUserData[pdev->classId] = fops;
return (uint8_t)USBD_OK;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
component/xc6xx_drivers/Drivers/USB/Middlewares/Library/Class/MSC/Src/usbd_msc_bot.c
+478
View File
@@ -0,0 +1,478 @@
/*!
* \file usbd_msc_bot.c
*
* \brief This file provides all the BOT protocol core functions.
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author MCD Application Team
*
* \author ( XinChip ) Alex-J
*/
/* Includes ------------------------------------------------------------------*/
#include "usbd_msc_bot.h"
#include "usbd_msc.h"
#include "usbd_msc_scsi.h"
#include "usbd_ioreq.h"
/** @defgroup MSC_BOT
* @brief BOT protocol module
* @{
*/
/** @defgroup MSC_BOT_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup MSC_BOT_Private_Defines
* @{
*/
/**
* @}
*/
/** @defgroup MSC_BOT_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup MSC_BOT_Private_Variables
* @{
*/
extern uint8_t MSCInEpAdd;
extern uint8_t MSCOutEpAdd;
/**
* @}
*/
/** @defgroup MSC_BOT_Private_FunctionPrototypes
* @{
*/
static void MSC_BOT_SendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len);
static void MSC_BOT_CBW_Decode(USBD_HandleTypeDef *pdev);
static void MSC_BOT_Abort(USBD_HandleTypeDef *pdev);
/**
* @}
*/
/** @defgroup MSC_BOT_Private_Functions
* @{
*/
/**
* @brief MSC_BOT_Init
* Initialize the BOT Process
* @param pdev: device instance
* @retval None
*/
void MSC_BOT_Init(USBD_HandleTypeDef *pdev)
{
USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
#ifdef USE_USBD_COMPOSITE
/* Get the Endpoints addresses allocated for this class instance */
MSCInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_BULK);
MSCOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_BULK);
#endif /* USE_USBD_COMPOSITE */
if (hmsc == NULL)
{
return;
}
hmsc->bot_state = USBD_BOT_IDLE;
hmsc->bot_status = USBD_BOT_STATUS_NORMAL;
hmsc->scsi_sense_tail = 0U;
hmsc->scsi_sense_head = 0U;
hmsc->scsi_medium_state = SCSI_MEDIUM_UNLOCKED;
((USBD_StorageTypeDef *)pdev->pUserData[pdev->classId])->Init(0U);
(void)USBD_LL_FlushEP(pdev, MSCOutEpAdd);
(void)USBD_LL_FlushEP(pdev, MSCInEpAdd);
/* Prepare EP to Receive First BOT Cmd */
(void)USBD_LL_PrepareReceive(pdev, MSCOutEpAdd, (uint8_t *)&hmsc->cbw,
USBD_BOT_CBW_LENGTH);
}
/**
* @brief MSC_BOT_Reset
* Reset the BOT Machine
* @param pdev: device instance
* @retval None
*/
void MSC_BOT_Reset(USBD_HandleTypeDef *pdev)
{
USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
#ifdef USE_USBD_COMPOSITE
/* Get the Endpoints addresses allocated for this class instance */
MSCInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_BULK);
MSCOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_BULK);
#endif /* USE_USBD_COMPOSITE */
if (hmsc == NULL)
{
return;
}
hmsc->bot_state = USBD_BOT_IDLE;
hmsc->bot_status = USBD_BOT_STATUS_RECOVERY;
(void)USBD_LL_ClearStallEP(pdev, MSCInEpAdd);
(void)USBD_LL_ClearStallEP(pdev, MSCOutEpAdd);
/* Prepare EP to Receive First BOT Cmd */
(void)USBD_LL_PrepareReceive(pdev, MSCOutEpAdd, (uint8_t *)&hmsc->cbw,
USBD_BOT_CBW_LENGTH);
}
/**
* @brief MSC_BOT_DeInit
* DeInitialize the BOT Machine
* @param pdev: device instance
* @retval None
*/
void MSC_BOT_DeInit(USBD_HandleTypeDef *pdev)
{
USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
if (hmsc != NULL)
{
hmsc->bot_state = USBD_BOT_IDLE;
}
}
/**
* @brief MSC_BOT_DataIn
* Handle BOT IN data stage
* @param pdev: device instance
* @param epnum: endpoint index
* @retval None
*/
void MSC_BOT_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum)
{
UNUSED(epnum);
USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
if (hmsc == NULL)
{
return;
}
switch (hmsc->bot_state)
{
case USBD_BOT_DATA_IN:
if (SCSI_ProcessCmd(pdev, hmsc->cbw.bLUN, &hmsc->cbw.CB[0]) < 0)
{
MSC_BOT_SendCSW(pdev, USBD_CSW_CMD_FAILED);
}
break;
case USBD_BOT_SEND_DATA:
case USBD_BOT_LAST_DATA_IN:
MSC_BOT_SendCSW(pdev, USBD_CSW_CMD_PASSED);
break;
default:
break;
}
}
/**
* @brief MSC_BOT_DataOut
* Process MSC OUT data
* @param pdev: device instance
* @param epnum: endpoint index
* @retval None
*/
void MSC_BOT_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum)
{
UNUSED(epnum);
USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
if (hmsc == NULL)
{
return;
}
switch (hmsc->bot_state)
{
case USBD_BOT_IDLE:
MSC_BOT_CBW_Decode(pdev);
break;
case USBD_BOT_DATA_OUT:
if (SCSI_ProcessCmd(pdev, hmsc->cbw.bLUN, &hmsc->cbw.CB[0]) < 0)
{
MSC_BOT_SendCSW(pdev, USBD_CSW_CMD_FAILED);
}
break;
default:
break;
}
}
/**
* @brief MSC_BOT_CBW_Decode
* Decode the CBW command and set the BOT state machine accordingly
* @param pdev: device instance
* @retval None
*/
static void MSC_BOT_CBW_Decode(USBD_HandleTypeDef *pdev)
{
USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
#ifdef USE_USBD_COMPOSITE
/* Get the Endpoints addresses allocated for this class instance */
MSCInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_BULK);
MSCOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_BULK);
#endif /* USE_USBD_COMPOSITE */
if (hmsc == NULL)
{
return;
}
hmsc->csw.dTag = hmsc->cbw.dTag;
hmsc->csw.dDataResidue = hmsc->cbw.dDataLength;
if ((USBD_LL_GetRxDataSize(pdev, MSCOutEpAdd) != USBD_BOT_CBW_LENGTH) ||
(hmsc->cbw.dSignature != USBD_BOT_CBW_SIGNATURE) ||
(hmsc->cbw.bLUN > 1U) || (hmsc->cbw.bCBLength < 1U) ||
(hmsc->cbw.bCBLength > 16U))
{
SCSI_SenseCode(pdev, hmsc->cbw.bLUN, ILLEGAL_REQUEST, INVALID_CDB);
hmsc->bot_status = USBD_BOT_STATUS_ERROR;
MSC_BOT_Abort(pdev);
}
else
{
if (SCSI_ProcessCmd(pdev, hmsc->cbw.bLUN, &hmsc->cbw.CB[0]) < 0)
{
if (hmsc->bot_state == USBD_BOT_NO_DATA)
{
MSC_BOT_SendCSW(pdev, USBD_CSW_CMD_FAILED);
}
else
{
MSC_BOT_Abort(pdev);
}
}
/* Burst xfer handled internally */
else if ((hmsc->bot_state != USBD_BOT_DATA_IN) &&
(hmsc->bot_state != USBD_BOT_DATA_OUT) &&
(hmsc->bot_state != USBD_BOT_LAST_DATA_IN))
{
if (hmsc->bot_data_length > 0U)
{
MSC_BOT_SendData(pdev, hmsc->bot_data, hmsc->bot_data_length);
}
else if (hmsc->bot_data_length == 0U)
{
MSC_BOT_SendCSW(pdev, USBD_CSW_CMD_PASSED);
}
else
{
MSC_BOT_Abort(pdev);
}
}
else
{
return;
}
}
}
/**
* @brief MSC_BOT_SendData
* Send the requested data
* @param pdev: device instance
* @param buf: pointer to data buffer
* @param len: Data Length
* @retval None
*/
static void MSC_BOT_SendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len)
{
USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
uint32_t length;
#ifdef USE_USBD_COMPOSITE
/* Get the Endpoints addresses allocated for this class instance */
MSCInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_BULK);
MSCOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_BULK);
#endif /* USE_USBD_COMPOSITE */
if (hmsc == NULL)
{
return;
}
length = MIN(hmsc->cbw.dDataLength, len);
hmsc->csw.dDataResidue -= len;
hmsc->csw.bStatus = USBD_CSW_CMD_PASSED;
hmsc->bot_state = USBD_BOT_SEND_DATA;
(void)USBD_LL_Transmit(pdev, MSCInEpAdd, pbuf, length);
}
/**
* @brief MSC_BOT_SendCSW
* Send the Command Status Wrapper
* @param pdev: device instance
* @param status : CSW status
* @retval None
*/
void MSC_BOT_SendCSW(USBD_HandleTypeDef *pdev, uint8_t CSW_Status)
{
USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
#ifdef USE_USBD_COMPOSITE
/* Get the Endpoints addresses allocated for this class instance */
MSCInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_BULK);
MSCOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_BULK);
#endif /* USE_USBD_COMPOSITE */
if (hmsc == NULL)
{
return;
}
hmsc->csw.dSignature = USBD_BOT_CSW_SIGNATURE;
hmsc->csw.bStatus = CSW_Status;
hmsc->bot_state = USBD_BOT_IDLE;
(void)USBD_LL_Transmit(pdev, MSCInEpAdd, (uint8_t *)&hmsc->csw,
USBD_BOT_CSW_LENGTH);
/* Prepare EP to Receive next Cmd */
(void)USBD_LL_PrepareReceive(pdev, MSCOutEpAdd, (uint8_t *)&hmsc->cbw,
USBD_BOT_CBW_LENGTH);
}
/**
* @brief MSC_BOT_Abort
* Abort the current transfer
* @param pdev: device instance
* @retval status
*/
static void MSC_BOT_Abort(USBD_HandleTypeDef *pdev)
{
USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
#ifdef USE_USBD_COMPOSITE
/* Get the Endpoints addresses allocated for this class instance */
MSCInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_BULK);
MSCOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_BULK);
#endif /* USE_USBD_COMPOSITE */
if (hmsc == NULL)
{
return;
}
if ((hmsc->cbw.bmFlags == 0U) &&
(hmsc->cbw.dDataLength != 0U) &&
(hmsc->bot_status == USBD_BOT_STATUS_NORMAL))
{
(void)USBD_LL_StallEP(pdev, MSCOutEpAdd);
}
(void)USBD_LL_StallEP(pdev, MSCInEpAdd);
if (hmsc->bot_status == USBD_BOT_STATUS_ERROR)
{
(void)USBD_LL_StallEP(pdev, MSCInEpAdd);
(void)USBD_LL_StallEP(pdev, MSCOutEpAdd);
}
}
/**
* @brief MSC_BOT_CplClrFeature
* Complete the clear feature request
* @param pdev: device instance
* @param epnum: endpoint index
* @retval None
*/
void MSC_BOT_CplClrFeature(USBD_HandleTypeDef *pdev, uint8_t epnum)
{
USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
#ifdef USE_USBD_COMPOSITE
/* Get the Endpoints addresses allocated for this class instance */
MSCInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_BULK);
MSCOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_BULK);
#endif /* USE_USBD_COMPOSITE */
if (hmsc == NULL)
{
return;
}
if (hmsc->bot_status == USBD_BOT_STATUS_ERROR) /* Bad CBW Signature */
{
(void)USBD_LL_StallEP(pdev, MSCInEpAdd);
(void)USBD_LL_StallEP(pdev, MSCOutEpAdd);
}
else if (((epnum & 0x80U) == 0x80U) && (hmsc->bot_status != USBD_BOT_STATUS_RECOVERY))
{
MSC_BOT_SendCSW(pdev, USBD_CSW_CMD_FAILED);
}
else
{
return;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
component/xc6xx_drivers/Drivers/USB/Middlewares/Library/Class/MSC/Src/usbd_msc_data.c
+161
View File
@@ -0,0 +1,161 @@
/*!
* \file usbd_msc_data.c
*
* \brief This file provides all the vital inquiry pages and sense data.
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author MCD Application Team
*
* \author ( XinChip ) Alex-J
*/
/* Includes ------------------------------------------------------------------*/
#include "usbd_msc_data.h"
/** @defgroup MSC_DATA_Private_Defines
* @{
*/
/** @defgroup MSC_DATA_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup MSC_DATA_Private_Variables
* @{
*/
/* USB Mass storage Page 0 Inquiry Data */
uint8_t MSC_Page00_Inquiry_Data[LENGTH_INQUIRY_PAGE00] =
{
0x00,
0x00,
0x00,
(LENGTH_INQUIRY_PAGE00 - 4U),
0x00,
0x80
};
/* USB Mass storage VPD Page 0x80 Inquiry Data for Unit Serial Number */
uint8_t MSC_Page80_Inquiry_Data[LENGTH_INQUIRY_PAGE80] =
{
0x00,
0x80,
0x00,
LENGTH_INQUIRY_PAGE80,
0x20, /* Put Product Serial number */
0x20,
0x20,
0x20
};
/* USB Mass storage sense 6 Data */
uint8_t MSC_Mode_Sense6_data[MODE_SENSE6_LEN] =
{
0x22,
0x00,
0x00,
0x00,
0x08,
0x12,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00
};
/* USB Mass storage sense 10 Data */
uint8_t MSC_Mode_Sense10_data[MODE_SENSE10_LEN] =
{
0x00,
0x26,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x08,
0x12,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00
};
/**
* @}
*/
/** @defgroup MSC_DATA_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup MSC_DATA_Private_Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
component/xc6xx_drivers/Drivers/USB/Middlewares/Library/Class/MSC/Src/usbd_msc_scsi.c
+1203
View File
File diff suppressed because it is too large Load Diff
component/xc6xx_drivers/Drivers/USB/Middlewares/Library/Core/Inc/usbd_core.h
+176
View File
@@ -0,0 +1,176 @@
/*!
* \file usbd_core.h
*
* \brief Header file for usbd_core.c file.
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author MCD Application Team
*
* \author ( XinChip ) Alex-J
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USBD_CORE_H
#define __USBD_CORE_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "usbd_conf.h"
#include "usbd_def.h"
#include "usbd_ioreq.h"
#include "usbd_ctlreq.h"
/** @defgroup USBD_CORE
* @brief This file is the Header file for usbd_core.c file
* @{
*/
/** @defgroup USBD_CORE_Exported_Defines
* @{
*/
#ifndef USBD_DEBUG_LEVEL
#define USBD_DEBUG_LEVEL 0U
#endif /* USBD_DEBUG_LEVEL */
/**
* @}
*/
/** @defgroup USBD_CORE_Exported_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup USBD_CORE_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup USBD_CORE_Exported_Variables
* @{
*/
#define USBD_SOF USBD_LL_SOF
/**
* @}
*/
/** @defgroup USBD_CORE_Exported_FunctionsPrototype
* @{
*/
USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id);
USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_Stop(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass);
#ifdef USE_USBD_COMPOSITE
USBD_StatusTypeDef USBD_RegisterClassComposite(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass,
USBD_CompositeClassTypeDef classtype, uint8_t *EpAddr);
USBD_StatusTypeDef USBD_UnRegisterClassComposite(USBD_HandleTypeDef *pdev);
uint8_t USBD_CoreGetEPAdd(USBD_HandleTypeDef *pdev, uint8_t ep_dir, uint8_t ep_type);
#endif /* USE_USBD_COMPOSITE */
uint8_t USBD_CoreFindIF(USBD_HandleTypeDef *pdev, uint8_t index);
uint8_t USBD_CoreFindEP(USBD_HandleTypeDef *pdev, uint8_t index);
USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup);
USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata);
USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata);
USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed);
USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum);
USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum);
USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev);
/* USBD Low Level Driver */
USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr,
uint8_t ep_type, uint16_t ep_mps);
USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr);
USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr,
uint8_t *pbuf, uint32_t size);
USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr,
uint8_t *pbuf, uint32_t size);
#ifdef USBD_HS_TESTMODE_ENABLE
USBD_StatusTypeDef USBD_LL_SetTestMode(USBD_HandleTypeDef *pdev, uint8_t testmode);
#endif /* USBD_HS_TESTMODE_ENABLE */
uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
void USBD_LL_Delay(uint32_t Delay);
void *USBD_GetEpDesc(uint8_t *pConfDesc, uint8_t EpAddr);
USBD_DescHeaderTypeDef *USBD_GetNextDesc(uint8_t *pbuf, uint16_t *ptr);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __USBD_CORE_H */
/**
* @}
*/
/**
* @}
*/
component/xc6xx_drivers/Drivers/USB/Middlewares/Library/Core/Inc/usbd_ctlreq.h
+114
View File
@@ -0,0 +1,114 @@
/*!
* \file usbd_ctlreq.h
*
* \brief Header file for the usbd_req.c file
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author MCD Application Team
*
* \author ( XinChip ) Alex-J
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USB_REQUEST_H
#define __USB_REQUEST_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "usbd_def.h"
/** @defgroup USBD_REQ
* @brief header file for the usbd_req.c file
* @{
*/
/** @defgroup USBD_REQ_Exported_Defines
* @{
*/
/**
* @}
*/
/** @defgroup USBD_REQ_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup USBD_REQ_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup USBD_REQ_Exported_Variables
* @{
*/
/**
* @}
*/
/** @defgroup USBD_REQ_Exported_FunctionsPrototype
* @{
*/
#ifdef OS_FEATURE
enum
{
OS_WIN = 0,//windows os
OS_MAC = 1,//mac os
};
#endif
USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata);
void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __USB_REQUEST_H */
/**
* @}
*/
/**
* @}
*/
component/xc6xx_drivers/Drivers/USB/Middlewares/Library/Core/Inc/usbd_def.h
+522
View File
@@ -0,0 +1,522 @@
/*!
* \file usbd_def.h
*
* \brief General defines for the usb device library
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author MCD Application Team
*
* \author ( XinChip ) Alex-J
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USBD_DEF_H
#define __USBD_DEF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "usbd_conf.h"
#include "xc_hal_pcd_np.h"
/** @defgroup USB_DEF
* @brief general defines for the usb device library file
* @{
*/
/** @defgroup USB_DEF_Exported_Defines
* @{
*/
#ifndef NULL
#define NULL 0U
#endif /* NULL */
#ifndef USBD_MAX_NUM_INTERFACES
#define USBD_MAX_NUM_INTERFACES 1U
#endif /* USBD_MAX_NUM_CONFIGURATION */
#ifndef USBD_MAX_NUM_CONFIGURATION
#define USBD_MAX_NUM_CONFIGURATION 1U
#endif /* USBD_MAX_NUM_CONFIGURATION */
#ifdef USE_USBD_COMPOSITE
#ifndef USBD_MAX_SUPPORTED_CLASS
#define USBD_MAX_SUPPORTED_CLASS 5U
#endif /* USBD_MAX_SUPPORTED_CLASS */
#else
#ifndef USBD_MAX_SUPPORTED_CLASS
#define USBD_MAX_SUPPORTED_CLASS 1U
#endif /* USBD_MAX_SUPPORTED_CLASS */
#endif /* USE_USBD_COMPOSITE */
#ifndef USBD_MAX_CLASS_ENDPOINTS
#define USBD_MAX_CLASS_ENDPOINTS 5U
#endif /* USBD_MAX_CLASS_ENDPOINTS */
#ifndef USBD_MAX_CLASS_INTERFACES
#define USBD_MAX_CLASS_INTERFACES 5U
#endif /* USBD_MAX_CLASS_INTERFACES */
#ifndef USBD_LPM_ENABLED
#define USBD_LPM_ENABLED 0U
#endif /* USBD_LPM_ENABLED */
#ifndef USBD_SELF_POWERED
#define USBD_SELF_POWERED 1U
#endif /*USBD_SELF_POWERED */
#ifndef USBD_MAX_POWER
#define USBD_MAX_POWER 0x32U /* 100 mA */
#endif /* USBD_MAX_POWER */
#ifndef USBD_SUPPORT_USER_STRING_DESC
#define USBD_SUPPORT_USER_STRING_DESC 0U
#endif /* USBD_SUPPORT_USER_STRING_DESC */
#ifndef USBD_CLASS_USER_STRING_DESC
#define USBD_CLASS_USER_STRING_DESC 0U
#endif /* USBD_CLASS_USER_STRING_DESC */
#define USB_LEN_DEV_QUALIFIER_DESC 0x0AU
#define USB_LEN_DEV_DESC 0x12U
#define USB_LEN_CFG_DESC 0x09U
#define USB_LEN_IF_DESC 0x09U
#define USB_LEN_EP_DESC 0x07U
#define USB_LEN_OTG_DESC 0x03U
#define USB_LEN_LANGID_STR_DESC 0x04U
#define USB_LEN_OTHER_SPEED_DESC_SIZ 0x09U
#define USBD_IDX_LANGID_STR 0x00U
#define USBD_IDX_MFC_STR 0x01U
#define USBD_IDX_PRODUCT_STR 0x02U
#define USBD_IDX_SERIAL_STR 0x03U
#define USBD_IDX_CONFIG_STR 0x04U
#define USBD_IDX_INTERFACE_STR 0x05U
#define USB_REQ_TYPE_STANDARD 0x00U
#define USB_REQ_TYPE_CLASS 0x20U
#define USB_REQ_TYPE_VENDOR 0x40U
#define USB_REQ_TYPE_MASK 0x60U
#define USB_REQ_RECIPIENT_DEVICE 0x00U
#define USB_REQ_RECIPIENT_INTERFACE 0x01U
#define USB_REQ_RECIPIENT_ENDPOINT 0x02U
#define USB_REQ_RECIPIENT_MASK 0x03U
#define USB_REQ_GET_STATUS 0x00U
#define USB_REQ_CLEAR_FEATURE 0x01U
#define USB_REQ_SET_FEATURE 0x03U
#define USB_REQ_SET_ADDRESS 0x05U
#define USB_REQ_GET_DESCRIPTOR 0x06U
#define USB_REQ_SET_DESCRIPTOR 0x07U
#define USB_REQ_GET_CONFIGURATION 0x08U
#define USB_REQ_SET_CONFIGURATION 0x09U
#define USB_REQ_GET_INTERFACE 0x0AU
#define USB_REQ_SET_INTERFACE 0x0BU
#define USB_REQ_SYNCH_FRAME 0x0CU
#define USB_DESC_TYPE_DEVICE 0x01U
#define USB_DESC_TYPE_CONFIGURATION 0x02U
#define USB_DESC_TYPE_STRING 0x03U
#define USB_DESC_TYPE_INTERFACE 0x04U
#define USB_DESC_TYPE_ENDPOINT 0x05U
#define USB_DESC_TYPE_DEVICE_QUALIFIER 0x06U
#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 0x07U
#define USB_DESC_TYPE_IAD 0x0BU
#define USB_DESC_TYPE_BOS 0x0FU
#define USB_CONFIG_REMOTE_WAKEUP 0x02U
#define USB_CONFIG_SELF_POWERED 0x01U
#define USB_FEATURE_EP_HALT 0x00U
#define USB_FEATURE_REMOTE_WAKEUP 0x01U
#define USB_FEATURE_TEST_MODE 0x02U
#define USB_DEVICE_CAPABITY_TYPE 0x10U
#define USB_CONF_DESC_SIZE 0x09U
#define USB_IF_DESC_SIZE 0x09U
#define USB_EP_DESC_SIZE 0x07U
#define USB_IAD_DESC_SIZE 0x08U
#define USB_HS_MAX_PACKET_SIZE 512U
#define USB_FS_MAX_PACKET_SIZE 64U
#define USB_MAX_EP0_SIZE 64U
/* Device Status */
#define USBD_STATE_DEFAULT 0x01U
#define USBD_STATE_ADDRESSED 0x02U
#define USBD_STATE_CONFIGURED 0x03U
#define USBD_STATE_SUSPENDED 0x04U
/* EP0 State */
#define USBD_EP0_IDLE 0x00U
#define USBD_EP0_SETUP 0x01U
#define USBD_EP0_DATA_IN 0x02U
#define USBD_EP0_DATA_OUT 0x03U
#define USBD_EP0_STATUS_IN 0x04U
#define USBD_EP0_STATUS_OUT 0x05U
#define USBD_EP0_STALL 0x06U
#define USBD_EP_TYPE_CTRL 0x00U
#define USBD_EP_TYPE_ISOC 0x01U
#define USBD_EP_TYPE_BULK 0x02U
#define USBD_EP_TYPE_INTR 0x03U
#ifdef USE_USBD_COMPOSITE
#define USBD_EP_IN 0x80U
#define USBD_EP_OUT 0x00U
#define USBD_FUNC_DESCRIPTOR_TYPE 0x24U
#define USBD_DESC_SUBTYPE_ACM 0x0FU
#define USBD_DESC_ECM_BCD_LOW 0x00U
#define USBD_DESC_ECM_BCD_HIGH 0x10U
#endif /* USE_USBD_COMPOSITE */
/**
* @}
*/
/** @defgroup USBD_DEF_Exported_TypesDefinitions
* @{
*/
typedef struct usb_setup_req
{
uint8_t bmRequest;
uint8_t bRequest;
uint16_t wValue;
uint16_t wIndex;
uint16_t wLength;
} USBD_SetupReqTypedef;
typedef struct
{
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t wTotalLength;
uint8_t bNumInterfaces;
uint8_t bConfigurationValue;
uint8_t iConfiguration;
uint8_t bmAttributes;
uint8_t bMaxPower;
} __PACKED USBD_ConfigDescTypeDef;
typedef struct
{
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t wTotalLength;
uint8_t bNumDeviceCaps;
} USBD_BosDescTypeDef;
typedef struct
{
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bEndpointAddress;
uint8_t bmAttributes;
uint16_t wMaxPacketSize;
uint8_t bInterval;
} __PACKED USBD_EpDescTypeDef;
typedef struct
{
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bDescriptorSubType;
} USBD_DescHeaderTypeDef;
struct _USBD_HandleTypeDef;
typedef struct _Device_cb
{
uint8_t (*Init)(struct _USBD_HandleTypeDef *pdev, uint8_t cfgidx);
uint8_t (*DeInit)(struct _USBD_HandleTypeDef *pdev, uint8_t cfgidx);
/* Control Endpoints*/
uint8_t (*Setup)(struct _USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
uint8_t (*EP0_TxSent)(struct _USBD_HandleTypeDef *pdev);
uint8_t (*EP0_RxReady)(struct _USBD_HandleTypeDef *pdev);
/* Class Specific Endpoints*/
uint8_t (*DataIn)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum);
uint8_t (*DataOut)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum);
uint8_t (*SOF)(struct _USBD_HandleTypeDef *pdev);
uint8_t (*IsoINIncomplete)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum);
uint8_t (*IsoOUTIncomplete)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum);
uint8_t *(*GetHSConfigDescriptor)(uint16_t *length);
uint8_t *(*GetFSConfigDescriptor)(uint16_t *length);
uint8_t *(*GetOtherSpeedConfigDescriptor)(uint16_t *length);
uint8_t *(*GetDeviceQualifierDescriptor)(uint16_t *length);
#if (USBD_SUPPORT_USER_STRING_DESC == 1U)
uint8_t *(*GetUsrStrDescriptor)(struct _USBD_HandleTypeDef *pdev, uint8_t index, uint16_t *length);
#endif /* USBD_SUPPORT_USER_STRING_DESC */
} USBD_ClassTypeDef;
/* Following USB Device Speed */
typedef enum
{
USBD_SPEED_HIGH = 0U,
USBD_SPEED_FULL = 1U,
USBD_SPEED_LOW = 2U,
} USBD_SpeedTypeDef;
/* Following USB Device status */
typedef enum
{
USBD_OK = 0U,
USBD_BUSY,
USBD_EMEM,
USBD_FAIL,
} USBD_StatusTypeDef;
/* USB Device descriptors structure */
typedef struct
{
uint8_t *(*GetDeviceDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t *(*GetLangIDStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t *(*GetManufacturerStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t *(*GetProductStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t *(*GetSerialStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t *(*GetConfigurationStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t *(*GetInterfaceStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
#if (USBD_CLASS_USER_STRING_DESC == 1)
uint8_t *(*GetUserStrDescriptor)(USBD_SpeedTypeDef speed, uint8_t idx, uint16_t *length);
#endif /* USBD_CLASS_USER_STRING_DESC */
#if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1))
uint8_t *(*GetBOSDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
#endif /* (USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1) */
} USBD_DescriptorsTypeDef;
/* USB Device handle structure */
typedef struct
{
uint32_t status;
uint32_t total_length;
uint32_t rem_length;
uint32_t maxpacket;
uint16_t is_used;
uint16_t bInterval;
} USBD_EndpointTypeDef;
#ifdef USE_USBD_COMPOSITE
typedef enum
{
CLASS_TYPE_NONE = 0,
CLASS_TYPE_HID_MOUSE = 1,
CLASS_TYPE_CDC = 2,
CLASS_TYPE_MSC = 3,
CLASS_TYPE_DFU = 4,
CLASS_TYPE_CHID = 5,
CLASS_TYPE_AUDIO = 6,
CLASS_TYPE_ECM = 7,
CLASS_TYPE_RNDIS = 8,
CLASS_TYPE_MTP = 9,
CLASS_TYPE_VIDEO = 10,
CLASS_TYPE_PRINTER = 11,
CLASS_TYPE_CCID = 12,
CLASS_TYPE_MICROPHONE = 13,
CLASS_TYPE_HEADPHONE = 14,
CLASS_TYPE_HID_KEYBOARD = 15,
CLASS_TYPE_HID_CUSTOM = 16,
} USBD_CompositeClassTypeDef;
/* USB Device handle structure */
typedef struct
{
uint8_t add;
uint8_t type;
uint8_t size;
uint8_t is_used;
} USBD_EPTypeDef;
/* USB Device handle structure */
typedef struct
{
USBD_CompositeClassTypeDef ClassType;
uint32_t ClassId;
uint32_t Active;
uint32_t NumEps;
USBD_EPTypeDef Eps[USBD_MAX_CLASS_ENDPOINTS];
uint8_t *EpAdd;
uint32_t NumIf;
uint8_t Ifs[USBD_MAX_CLASS_INTERFACES];
uint32_t CurrPcktSze;
} USBD_CompositeElementTypeDef;
#endif /* USE_USBD_COMPOSITE */
/* USB Device handle structure */
typedef struct _USBD_HandleTypeDef
{
uint8_t id;
uint32_t dev_config;
uint32_t dev_default_config;
uint32_t dev_config_status;
USBD_SpeedTypeDef dev_speed;
USBD_EndpointTypeDef ep_in[16];
USBD_EndpointTypeDef ep_out[16];
__IO uint32_t ep0_state;
uint32_t ep0_data_len;
__IO uint8_t dev_state;
__IO uint8_t dev_old_state;
uint8_t dev_address;
uint8_t dev_connection_status;
uint8_t dev_test_mode;
uint32_t dev_remote_wakeup;
uint8_t ConfIdx;
USBD_SetupReqTypedef request;
USBD_DescriptorsTypeDef *pDesc;
USBD_ClassTypeDef *pClass[USBD_MAX_SUPPORTED_CLASS];
void *pClassData;
void *pClassDataCmsit[USBD_MAX_SUPPORTED_CLASS];
void *pUserData[USBD_MAX_SUPPORTED_CLASS];
void *pData;
void *pBosDesc;
void *pConfDesc;
uint32_t classId;
uint32_t NumClasses;
#ifdef USE_USBD_COMPOSITE
USBD_CompositeElementTypeDef tclasslist[USBD_MAX_SUPPORTED_CLASS];
#endif /* USE_USBD_COMPOSITE */
} USBD_HandleTypeDef;
/* USB Device endpoint direction */
typedef enum
{
OUT = 0x00,
IN = 0x80,
} USBD_EPDirectionTypeDef;
typedef enum
{
NETWORK_CONNECTION = 0x00,
RESPONSE_AVAILABLE = 0x01,
CONNECTION_SPEED_CHANGE = 0x2A
} USBD_CDC_NotifCodeTypeDef;
/**
* @}
*/
/** @defgroup USBD_DEF_Exported_Macros
* @{
*/
__STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr)
{
uint16_t _SwapVal, _Byte1, _Byte2;
uint8_t *_pbuff = addr;
_Byte1 = *(uint8_t *)_pbuff;
_pbuff++;
_Byte2 = *(uint8_t *)_pbuff;
_SwapVal = (_Byte2 << 8) | _Byte1;
return _SwapVal;
}
#ifndef LOBYTE
#define LOBYTE(x) ((uint8_t)((x) & 0x00FFU))
#endif /* LOBYTE */
#ifndef HIBYTE
#define HIBYTE(x) ((uint8_t)(((x) & 0xFF00U) >> 8U))
#endif /* HIBYTE */
#ifndef MIN
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
#endif /* MIN */
#ifndef MAX
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
#endif /* MAX */
#if defined ( __GNUC__ )
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
#ifndef __packed
#define __packed __attribute__((__packed__))
#endif /* __packed */
#endif /* __GNUC__ */
/* In HS mode and when the DMA is used, all variables and data structures dealing
with the DMA during the transaction process should be 4-bytes aligned */
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4U)))
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#else
#ifndef __ALIGN_END
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler */
#define __ALIGN_BEGIN __align(4U)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
/**
* @}
*/
/** @defgroup USBD_DEF_Exported_Variables
* @{
*/
/**
* @}
*/
/** @defgroup USBD_DEF_Exported_FunctionsPrototype
* @{
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __USBD_DEF_H */
/**
* @}
*/
/**
* @}
*/
component/xc6xx_drivers/Drivers/USB/Middlewares/Library/Core/Inc/usbd_ioreq.h
+117
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@@ -0,0 +1,117 @@
/*!
* \file usbd_ioreq.h
*
* \brief Header file for the usbd_ioreq.c file.
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author MCD Application Team
*
* \author ( XinChip ) Alex-J
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USBD_IOREQ_H
#define __USBD_IOREQ_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "usbd_def.h"
#include "usbd_core.h"
/** @defgroup USBD_IOREQ
* @brief header file for the usbd_ioreq.c file
* @{
*/
/** @defgroup USBD_IOREQ_Exported_Defines
* @{
*/
/**
* @}
*/
/** @defgroup USBD_IOREQ_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup USBD_IOREQ_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup USBD_IOREQ_Exported_Variables
* @{
*/
/**
* @}
*/
/** @defgroup USBD_IOREQ_Exported_FunctionsPrototype
* @{
*/
USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint32_t len);
USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint32_t len);
USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint32_t len);
USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint32_t len);
USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev);
uint32_t USBD_GetRxCount(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __USBD_IOREQ_H */
/**
* @}
*/
/**
* @}
*/
component/xc6xx_drivers/Drivers/USB/Middlewares/Library/Core/Src/usbd_core.c
+1210
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File diff suppressed because it is too large Load Diff
component/xc6xx_drivers/Drivers/USB/Middlewares/Library/Core/Src/usbd_ctlreq.c
+1059
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File diff suppressed because it is too large Load Diff
component/xc6xx_drivers/Drivers/USB/Middlewares/Library/Core/Src/usbd_ioreq.c
+228
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@@ -0,0 +1,228 @@
/*!
* \file usbd_ioreq.c
*
* \brief This file provides the IO requests APIs for control endpoints.
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author MCD Application Team
*
* \author ( XinChip ) Alex-J
*/
/* Includes ------------------------------------------------------------------*/
#include "usbd_ioreq.h"
/** @defgroup USBD_IOREQ
* @brief control I/O requests module
* @{
*/
/** @defgroup USBD_IOREQ_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup USBD_IOREQ_Private_Defines
* @{
*/
/**
* @}
*/
/** @defgroup USBD_IOREQ_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup USBD_IOREQ_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup USBD_IOREQ_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup USBD_IOREQ_Private_Functions
* @{
*/
/**
* @brief USBD_CtlSendData
* send data on the ctl pipe
* @param pdev: device instance
* @param buff: pointer to data buffer
* @param len: length of data to be sent
* @retval status
*/
USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint32_t len)
{
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_DATA_IN;
pdev->ep_in[0].total_length = len;
#ifdef USBD_AVOID_PACKET_SPLIT_MPS
pdev->ep_in[0].rem_length = 0U;
#else
pdev->ep_in[0].rem_length = len;
#endif /* USBD_AVOID_PACKET_SPLIT_MPS */
/* Start the transfer */
(void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
return USBD_OK;
}
/**
* @brief USBD_CtlContinueSendData
* continue sending data on the ctl pipe
* @param pdev: device instance
* @param buff: pointer to data buffer
* @param len: length of data to be sent
* @retval status
*/
USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint32_t len)
{
/* Start the next transfer */
(void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
return USBD_OK;
}
/**
* @brief USBD_CtlPrepareRx
* receive data on the ctl pipe
* @param pdev: device instance
* @param buff: pointer to data buffer
* @param len: length of data to be received
* @retval status
*/
USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint32_t len)
{
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_DATA_OUT;
pdev->ep_out[0].total_length = len;
#ifdef USBD_AVOID_PACKET_SPLIT_MPS
pdev->ep_out[0].rem_length = 0U;
#else
pdev->ep_out[0].rem_length = len;
#endif /* USBD_AVOID_PACKET_SPLIT_MPS */
/* Start the transfer */
(void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
return USBD_OK;
}
/**
* @brief USBD_CtlContinueRx
* continue receive data on the ctl pipe
* @param pdev: device instance
* @param buff: pointer to data buffer
* @param len: length of data to be received
* @retval status
*/
USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint32_t len)
{
(void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
return USBD_OK;
}
/**
* @brief USBD_CtlSendStatus
* send zero lzngth packet on the ctl pipe
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev)
{
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_STATUS_IN;
/* Start the transfer */
(void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U);
return USBD_OK;
}
/**
* @brief USBD_CtlReceiveStatus
* receive zero lzngth packet on the ctl pipe
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev)
{
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_STATUS_OUT;
/* Start the transfer */
(void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
return USBD_OK;
}
/**
* @brief USBD_GetRxCount
* returns the received data length
* @param pdev: device instance
* @param ep_addr: endpoint address
* @retval Rx Data blength
*/
uint32_t USBD_GetRxCount(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
return USBD_LL_GetRxDataSize(pdev, ep_addr);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
component/xc6xx_drivers/Drivers/USB/RTC_2_Date/inc/rtc.h
+57
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@@ -0,0 +1,57 @@
/*!
* \file rtc.h
*
* \brief Target rtc implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __RTC_H__
#define __RTC_H__
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include <stdint.h>
#include "xc6xxx.h"
/*------------------------------------------------------------------------------------
Global Variables
-------------------------------------------------------------------------------------*/
extern volatile uint32_t Utc_TotalSec;
// Test val
extern uint8_t Sec_Flag;
/*------------------------------------------------------------------------------------
Exported Functions
------------------------------------------- -----------------------------------------*/
void rtc_sec_handler(void);
void RTC_Config( void );
#ifdef __cplusplus
}
#endif
#endif /* __RTC_H__ */
component/xc6xx_drivers/Drivers/USB/RTC_2_Date/inc/time_conv.h
+86
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@@ -0,0 +1,86 @@
/*!
* \file time_conv.h
*
* \brief Target time convert implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __TIME_CONV_H__
#define __TIME_CONV_H__
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include <stdint.h>
#include <time.h>
#include "rtc.h"
/*------------------------------------------------------------------------------------
Macros
------------------------------------------- -----------------------------------------*/
#define YEAR_BASE 2000U
#define TIME_ZONE (8)
#define M_JAN 1U
#define M_FEB 2U
#define M_MAR 3U
#define M_APR 4U
#define M_MAY 5U
#define M_JUN 6U
#define M_JUL 7U
#define M_AUG 8U
#define M_SEP 9U
#define M_OCT 10U
#define M_NOV 11U
#define M_DEC 12U
/*------------------------------------------------------------------------------------
Typedef
-------------------------------------------------------------------------------------*/
typedef struct tm Utc_Date_t;
typedef struct
{
uint8_t year;
uint8_t month;
uint8_t day;
uint8_t hour;
uint8_t min;
uint8_t sec;
uint8_t week;
} DateTime_t;
/*------------------------------------------------------------------------------------
Exported Functions
------------------------------------------- -----------------------------------------*/
DateTime_t UTC_SecToDate( uint32_t utc_sec );
DateTime_t UTC_DateToZoneDate(int8_t zone_num, uint16_t year_base, uint8_t u_year, uint8_t u_month,
uint8_t u_day, uint8_t u_hour, uint8_t u_min, uint8_t u_sec, uint8_t u_week);
#ifdef __cplusplus
}
#endif
#endif /* __TIME_CONV_H__ */
component/xc6xx_drivers/Drivers/USB/RTC_2_Date/src/rtc.c
+103
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@@ -0,0 +1,103 @@
/*!
* \file rtc.c
*
* \brief Target rtc implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "rtc.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------
-----------------------------------------*/
#define MANUF_UTC_SEC 1680516516 // rtc start time
/*------------------------------------------------------------------------------------
Constant
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Local Variables
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Global Variables
-------------------------------------------------------------------------------------*/
volatile uint32_t Utc_TotalSec = MANUF_UTC_SEC;
// Test val
uint8_t Sec_Flag = false;
/*------------------------------------------------------------------------------------
Functions
------------------------------------------------------------------------------------*/
/**
* @brief RTC handler func
* @param xinc_drv_rtc_int_type_t - type
* @retval void
*/
uint8_t Sec_Callback(void)
{
Utc_TotalSec += 1;
Sec_Flag = true;
return 0;
}
/**
* @brief RTC config func
* @param void
* @retval void
*/
void RTC_Config(void)
{
// Initialize RTC instance
RTC_InitCfg_t rtc_cfg = {0};
NVIC_DisableIRQ(RTC_IRQn);
// rtc_cfg.Date.Sec = 0;
// rtc_cfg.Date.Min = 0;
// rtc_cfg.Date.Hour = 18;
// rtc_cfg.Date.Day = 93;
// rtc_cfg.Date.Week = 1;
rtc_cfg.Date.Sec = 0;
rtc_cfg.Date.Min = 45;
rtc_cfg.Date.Hour = 19;
rtc_cfg.Date.Day = 340;
rtc_cfg.Date.Week = 2;
rtc_cfg.DateLimit.SecLimit = 60;
rtc_cfg.DateLimit.MinLimit = 60;
rtc_cfg.DateLimit.HourLimit = 24;
rtc_cfg.MatchTimeEnable = false;
rtc_cfg.SecIT_Enable = true;
rtc_cfg.MinIT_Enable = false;
rtc_cfg.HourIT_Enable = false;
rtc_cfg.DayIT_Enable = false;
// Rtc enable
xc_rtc_init(&rtc_cfg);
NVIC_EnableIRQ(RTC_IRQn);
xc_rtc_start();
}
component/xc6xx_drivers/Drivers/USB/RTC_2_Date/src/time_conv.c
+168
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@@ -0,0 +1,168 @@
/*!
* \file time_conv.c
*
* \brief Target time convert implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "time_conv.h"
/*------------------------------------------------------------------------------------
Functions
------------------------------------------------------------------------------------*/
/**
* @brief UTC second convert to date and time.
* @details
* @param[in] uint32_t - utc_sec
* @param[out] void
* @retval DateTime_t
* @retval void
* @par identifier
* reserve
* @par other
* void
* @par change log
* Alex created on 2022-09-09
*/
DateTime_t UTC_SecToDate(uint32_t utc_sec)
{
Utc_Date_t tmp;
DateTime_t ret;
tmp = *localtime(&utc_sec);
ret.year = tmp.tm_year;
ret.month = tmp.tm_mon;
ret.day = tmp.tm_mday;
ret.hour = tmp.tm_hour;
ret.min = tmp.tm_min;
ret.sec = tmp.tm_sec;
ret.week = tmp.tm_wday;
return ret;
}
/**
* @brief Convert the date in the UTC time zone to the date in the
* corresponding time zone.
* @details
* @param[in] int8_t - zone_num
* uint16_t - year_base
* uint8_t - u_year, u_month, u_day, u_hour, u_min, u_sec, u_week
* @param[out] void
* @retval DateTime_t
* @retval void
* @par identifier
* reserve
* @par other
* void
* @par change log
* Alex created on 2022-09-09
*/
DateTime_t UTC_DateToZoneDate(int8_t zone_num, uint16_t year_base,
uint8_t u_year, uint8_t u_month, uint8_t u_day,
uint8_t u_hour, uint8_t u_min, uint8_t u_sec,
uint8_t u_week)
{
DateTime_t zonedate;
int t_year = 0;
int lastday = 0; // last day of the month
int lastmon_lastday = 0; // last day of last month
int8_t t_hour = 0;
t_year = u_year - 100 + year_base;
zonedate.month = u_month + 1;
zonedate.day = u_day;
zonedate.hour = u_hour;
zonedate.min = u_min;
zonedate.sec = u_sec;
zonedate.week = u_week;
// Determine days by month
if (M_JAN == zonedate.month || M_MAR == zonedate.month ||
M_MAY == zonedate.month || M_JUL == zonedate.month ||
M_AUG == zonedate.month || M_OCT == zonedate.month ||
M_DEC == zonedate.month) {
lastday = 31;
if (M_MAR == zonedate.month) {
// leap year determination
if ((t_year % 400 == 0) || (t_year % 4 == 0 && t_year % 100 != 0))
lastmon_lastday = 29;
else
lastmon_lastday = 28;
}
if (M_AUG == zonedate.month)
lastmon_lastday = 31;
} else if (M_APR == zonedate.month || M_JUN == zonedate.month ||
M_SEP == zonedate.month || M_NOV == zonedate.month) {
lastday = 30;
lastmon_lastday = 31;
} else {
lastmon_lastday = 31;
// leap year determination
if ((t_year % 400 == 0) || (t_year % 4 == 0 && t_year % 100 != 0))
lastday = 29;
else
lastday = 28;
}
t_hour = (int8_t)zonedate.hour + zone_num;
if (t_hour >= 24) {
zonedate.hour = (uint8_t)t_hour - 24;
zonedate.day += 1;
if (zonedate.day > lastday) {
zonedate.day -= lastday;
zonedate.month += 1;
if (zonedate.month > M_DEC) {
zonedate.month -= M_DEC;
t_year += 1;
}
}
if (zonedate.week < 6)
zonedate.week += 1;
else
zonedate.week = 0;
} else if (t_hour < 0) {
zonedate.hour = (uint8_t)(t_hour + 24);
zonedate.day -= 1;
if (zonedate.day == 0) {
zonedate.day = lastmon_lastday;
zonedate.month -= 1;
if (zonedate.month == 0) {
zonedate.month = M_DEC;
t_year -= 1;
}
}
if ((zonedate.week > 0) && (zonedate.week <= 6))
zonedate.week -= 1;
else
zonedate.week = 6;
} else
zonedate.hour = t_hour;
zonedate.year = t_year - year_base;
return zonedate;
}
component/xc6xx_drivers/Drivers/USB/USB_DEVICE/App/cdc/usb_device.c
+95
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@@ -0,0 +1,95 @@
/*!
* \file usb_device.c
*
* \brief Target usb device implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Includes ------------------------------------------------------------------*/
#include "usb_device.h"
#include "usbd_core.h"
#include "usbd_desc.h"
#include "usbd_cdc.h"
#include "usbd_cdc_if.h"
#include "usbd_cdc.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* USER CODE BEGIN PV */
/* Private variables ---------------------------------------------------------*/
/* USER CODE END PV */
/* USER CODE BEGIN PFP */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE END PFP */
/* USB Device Core handle declaration. */
USBD_HandleTypeDef hUsbDeviceFS;
/*
* -- Insert your variables declaration here --
*/
/* USER CODE BEGIN 0 */
extern PCD_HandleTypeDef hpcd_USB_OTG_FS;
/* USER CODE END 0 */
/*
* -- Insert your external function declaration here --
*/
void USB_Handler(void) { HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS); }
/**
* Init USB device Library, add supported class and start the library
* @retval None
*/
void USB_DEVICE_Init(void)
{
/* Init Device Library, add supported class and start the library. */
if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK)
{
Error_Handler();
}
if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_CDC) != USBD_OK)
{
Error_Handler();
}
if (USBD_CDC_RegisterInterface(&hUsbDeviceFS, &USBD_CDC_Interface_fops_FS) != USBD_OK)
{
Error_Handler();
}
if (USBD_Start(&hUsbDeviceFS) != USBD_OK)
{
Error_Handler();
}
}
/**
* @}
*/
/**
* @}
*/
component/xc6xx_drivers/Drivers/USB/USB_DEVICE/App/cdc/usb_device.h
+104
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@@ -0,0 +1,104 @@
/*!
* \file usb_device.h
*
* \brief Target usb device implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USB_DEVICE_H
#define __USB_DEVICE_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "usbd_def.h"
/* USER CODE BEGIN INCLUDE */
/* USER CODE END INCLUDE */
/** @addtogroup USBD_OTG_DRIVER
* @{
*/
/** @defgroup USBD_DEVICE USBD_DEVICE
* @brief Device file for Usb otg low level driver.
* @{
*/
/** @defgroup USBD_DEVICE_Exported_Variables USBD_DEVICE_Exported_Variables
* @brief Public variables.
* @{
*/
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/*
* -- Insert your variables declaration here --
*/
/* USER CODE BEGIN VARIABLES */
/* USER CODE END VARIABLES */
/**
* @}
*/
/** @defgroup USBD_DEVICE_Exported_FunctionsPrototype USBD_DEVICE_Exported_FunctionsPrototype
* @brief Declaration of public functions for Usb device.
* @{
*/
/** USB Device initialization function. */
void USB_DEVICE_Init(void);
/*
* -- Insert functions declaration here --
*/
/* USER CODE BEGIN FD */
/* USER CODE END FD */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __USB_DEVICE_H */
component/xc6xx_drivers/Drivers/USB/USB_DEVICE/App/cdc/usbd_cdc_if.c
+367
View File
@@ -0,0 +1,367 @@
/*!
* \file usbd_cdc_if.c
*
* \brief Usb device for Virtual Com Port.
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Includes ------------------------------------------------------------------*/
#include "usbd_cdc_if.h"
/* USER CODE BEGIN INCLUDE */
/* USER CODE END INCLUDE */
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* Private variables ---------------------------------------------------------*/
/* USER CODE END PV */
/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
* @brief Usb device library.
* @{
*/
/** @addtogroup USBD_CDC_IF
* @{
*/
/** @defgroup USBD_CDC_IF_Private_TypesDefinitions USBD_CDC_IF_Private_TypesDefinitions
* @brief Private types.
* @{
*/
/* USER CODE BEGIN PRIVATE_TYPES */
/* USER CODE END PRIVATE_TYPES */
/**
* @}
*/
/** @defgroup USBD_CDC_IF_Private_Defines USBD_CDC_IF_Private_Defines
* @brief Private defines.
* @{
*/
/* USER CODE BEGIN PRIVATE_DEFINES */
/* USER CODE END PRIVATE_DEFINES */
/**
* @}
*/
/** @defgroup USBD_CDC_IF_Private_Macros USBD_CDC_IF_Private_Macros
* @brief Private macros.
* @{
*/
/* USER CODE BEGIN PRIVATE_MACRO */
/* USER CODE END PRIVATE_MACRO */
/**
* @}
*/
/** @defgroup USBD_CDC_IF_Private_Variables USBD_CDC_IF_Private_Variables
* @brief Private variables.
* @{
*/
/* Create buffer for reception and transmission */
/* It's up to user to redefine and/or remove those define */
/** Received data over USB are stored in this buffer */
uint8_t CDC_UserRxBufferFS[APP_RX_DATA_SIZE];
/** Data to send over USB CDC are stored in this buffer */
uint8_t CDC_UserTxBufferFS[APP_TX_DATA_SIZE];
/* USER CODE BEGIN PRIVATE_VARIABLES */
/* CDC Instance 0 Variables */
uint8_t UserRxBuffer0[APP_RX_DATA_SIZE];/* Received Data over USB are stored in this buffer */
uint8_t UserTxBuffer0[APP_TX_DATA_SIZE];/* Received Data over UART (CDC interface) are stored in this buffer */
uint8_t UserRxBuffer1[APP_RX_DATA_SIZE];/* Received Data over USB are stored in this buffer */
uint8_t UserTxBuffer1[APP_TX_DATA_SIZE];/* Received Data over UART (CDC interface) are stored in this buffer */
/* USER CODE END PRIVATE_VARIABLES */
/**
* @}
*/
/** @defgroup USBD_CDC_IF_Exported_Variables USBD_CDC_IF_Exported_Variables
* @brief Public variables.
* @{
*/
extern USBD_HandleTypeDef hUsbDeviceFS;
/* USER CODE BEGIN EXPORTED_VARIABLES */
/* USER CODE END EXPORTED_VARIABLES */
/**
* @}
*/
/** @defgroup USBD_CDC_IF_Private_FunctionPrototypes USBD_CDC_IF_Private_FunctionPrototypes
* @brief Private functions declaration.
* @{
*/
static int8_t CDC_Init_FS(void);
static int8_t CDC_DeInit_FS(void);
static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length);
static int8_t CDC_Receive_FS(uint8_t* pbuf, uint32_t *Len);
static int8_t CDC_TransmitCplt_FS(uint8_t *pbuf, uint32_t *Len, uint8_t epnum);
/* USER CODE BEGIN PRIVATE_FUNCTIONS_DECLARATION */
/* USER CODE END PRIVATE_FUNCTIONS_DECLARATION */
/**
* @}
*/
USBD_CDC_ItfTypeDef USBD_CDC_Interface_fops_FS =
{
CDC_Init_FS,
CDC_DeInit_FS,
CDC_Control_FS,
CDC_Receive_FS,
CDC_TransmitCplt_FS
};
/* Private functions ---------------------------------------------------------*/
/**
* @brief Initializes the CDC media low layer over the FS USB IP
* @retval USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CDC_Init_FS(void)
{
/* USER CODE BEGIN 3 */
#ifdef USE_USBD_COMPOSITE
/* Set Application Buffers */
/* Check if the class ID corresponds to instance 0 */
if (hUsbDeviceFS.classId == USBD_CMPSIT_GetClassID(&hUsbDeviceFS, CLASS_TYPE_CDC, 0))
{
USBD_CDC_SetTxBuffer(&hUsbDeviceFS, UserTxBuffer0, 0);
USBD_CDC_SetRxBuffer(&hUsbDeviceFS, UserRxBuffer0);
return (USBD_OK);
}
/* Check if the class ID corresponds to instance 1 */
else if (hUsbDeviceFS.classId == USBD_CMPSIT_GetClassID(&hUsbDeviceFS, CLASS_TYPE_CDC, 1))
{
USBD_CDC_SetTxBuffer(&hUsbDeviceFS, UserTxBuffer1, 0);
USBD_CDC_SetRxBuffer(&hUsbDeviceFS, UserRxBuffer1);
return (USBD_OK);
}
else
{
/* Error: no instancecorresponds to this class ID */
return USBD_FAIL;
}
#else
USBD_CDC_SetTxBuffer(&hUsbDeviceFS, UserTxBuffer0, 0);
USBD_CDC_SetRxBuffer(&hUsbDeviceFS, UserRxBuffer0);
return (USBD_OK);
#endif
/* USER CODE END 3 */
}
/**
* @brief DeInitializes the CDC media low layer
* @retval USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CDC_DeInit_FS(void)
{
/* USER CODE BEGIN 4 */
return (USBD_OK);
/* USER CODE END 4 */
}
/**
* @brief Manage the CDC class requests
* @param cmd: Command code
* @param pbuf: Buffer containing command data (request parameters)
* @param length: Number of data to be sent (in bytes)
* @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length)
{
/* USER CODE BEGIN 5 */
switch(cmd)
{
case CDC_SEND_ENCAPSULATED_COMMAND:
break;
case CDC_GET_ENCAPSULATED_RESPONSE:
break;
case CDC_SET_COMM_FEATURE:
break;
case CDC_GET_COMM_FEATURE:
break;
case CDC_CLEAR_COMM_FEATURE:
break;
/*******************************************************************************/
/* Line Coding Structure */
/*-----------------------------------------------------------------------------*/
/* Offset | Field | Size | Value | Description */
/* 0 | dwDTERate | 4 | Number |Data terminal rate, in bits per second*/
/* 4 | bCharFormat | 1 | Number | Stop bits */
/* 0 - 1 Stop bit */
/* 1 - 1.5 Stop bits */
/* 2 - 2 Stop bits */
/* 5 | bParityType | 1 | Number | Parity */
/* 0 - None */
/* 1 - Odd */
/* 2 - Even */
/* 3 - Mark */
/* 4 - Space */
/* 6 | bDataBits | 1 | Number Data bits (5, 6, 7, 8 or 16). */
/*******************************************************************************/
case CDC_SET_LINE_CODING:
break;
case CDC_GET_LINE_CODING:
break;
case CDC_SET_CONTROL_LINE_STATE:
break;
case CDC_SEND_BREAK:
break;
default:
break;
}
return (USBD_OK);
/* USER CODE END 5 */
}
/**
* @brief Data received over USB OUT endpoint are sent over CDC interface
* through this function.
*
* @note
* This function will issue a NAK packet on any OUT packet received on
* USB endpoint until exiting this function. If you exit this function
* before transfer is complete on CDC interface (ie. using DMA controller)
* it will result in receiving more data while previous ones are still
* not sent.
*
* @param Buf: Buffer of data to be received
* @param Len: Number of data received (in bytes)
* @param epnum: Êä³ö˵ãµØÖ·
* @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len)
{
/* USER CODE BEGIN 6 */
USBD_CDC_SetRxBuffer(&hUsbDeviceFS, &Buf[0]);
USBD_CDC_ReceivePacket(&hUsbDeviceFS);
CDC_Transmit_FS(Buf, *Len);
return (USBD_OK);
/* USER CODE END 6 */
}
/**
* @brief CDC_Transmit_FS
* Data to send over USB IN endpoint are sent over CDC interface
* through this function.
* @note
*
*
* @param Buf: Buffer of data to be sent
* @param Len: Number of data to be sent (in bytes)
* @retval USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY
*/
uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len)
{
uint8_t result = USBD_OK;
/* USER CODE BEGIN 7 */
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*)hUsbDeviceFS.pClassDataCmsit[hUsbDeviceFS.classId];
if (hcdc->TxState != 0){
hcdc->TxState = 0;
return USBD_BUSY;
}
USBD_CDC_SetTxBuffer(&hUsbDeviceFS, Buf, Len);
result = USBD_CDC_TransmitPacket(&hUsbDeviceFS);
/* USER CODE END 7 */
return result;
}
/**
* @brief CDC_TransmitCplt_FS
* Data transmitted callback
*
* @note
* This function is IN transfer complete callback used to inform user that
* the submitted Data is successfully sent over USB.
*
* @param Buf: Buffer of data to be received
* @param Len: Number of data received (in bytes)
* @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CDC_TransmitCplt_FS(uint8_t *Buf, uint32_t *Len, uint8_t epnum)
{
uint8_t result = USBD_OK;
/* USER CODE BEGIN 13 */
UNUSED(Buf);
UNUSED(Len);
UNUSED(epnum);
/* USER CODE END 13 */
return result;
}
/* USER CODE BEGIN PRIVATE_FUNCTIONS_IMPLEMENTATION */
/* USER CODE END PRIVATE_FUNCTIONS_IMPLEMENTATION */
/**
* @}
*/
/**
* @}
*/
component/xc6xx_drivers/Drivers/USB/USB_DEVICE/App/cdc/usbd_cdc_if.h
+136
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@@ -0,0 +1,136 @@
/*!
* \file usbd_cdc_if.h
*
* \brief Header for usbd_cdc_if.c file.
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USBD_CDC_IF_H
#define __USBD_CDC_IF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "usbd_cdc.h"
/* USER CODE BEGIN INCLUDE */
/* USER CODE END INCLUDE */
/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
* @brief For Usb device.
* @{
*/
/** @defgroup USBD_CDC_IF USBD_CDC_IF
* @brief Usb VCP device module
* @{
*/
/** @defgroup USBD_CDC_IF_Exported_Defines USBD_CDC_IF_Exported_Defines
* @brief Defines.
* @{
*/
/* Define size for the receive and transmit buffer over CDC */
#define APP_RX_DATA_SIZE 64
#define APP_TX_DATA_SIZE 64
/* USER CODE BEGIN EXPORTED_DEFINES */
/* USER CODE END EXPORTED_DEFINES */
/**
* @}
*/
/** @defgroup USBD_CDC_IF_Exported_Types USBD_CDC_IF_Exported_Types
* @brief Types.
* @{
*/
/* USER CODE BEGIN EXPORTED_TYPES */
/* USER CODE END EXPORTED_TYPES */
/**
* @}
*/
/** @defgroup USBD_CDC_IF_Exported_Macros USBD_CDC_IF_Exported_Macros
* @brief Aliases.
* @{
*/
/* USER CODE BEGIN EXPORTED_MACRO */
/* USER CODE END EXPORTED_MACRO */
/**
* @}
*/
/** @defgroup USBD_CDC_IF_Exported_Variables USBD_CDC_IF_Exported_Variables
* @brief Public variables.
* @{
*/
/** CDC Interface callback. */
extern USBD_CDC_ItfTypeDef USBD_CDC_Interface_fops_FS;
/* USER CODE BEGIN EXPORTED_VARIABLES */
/* USER CODE END EXPORTED_VARIABLES */
/**
* @}
*/
/** @defgroup USBD_CDC_IF_Exported_FunctionsPrototype USBD_CDC_IF_Exported_FunctionsPrototype
* @brief Public functions declaration.
* @{
*/
uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len);
/* USER CODE BEGIN EXPORTED_FUNCTIONS */
/* USER CODE END EXPORTED_FUNCTIONS */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __USBD_CDC_IF_H */
component/xc6xx_drivers/Drivers/USB/USB_DEVICE/App/cdc/usbd_desc.c
+493
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@@ -0,0 +1,493 @@
/*!
* \file usbd_desc.c
*
* \brief Target the USB device descriptors implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Includes ------------------------------------------------------------------*/
#include "usbd_core.h"
#include "usbd_desc.h"
#include "usbd_conf.h"
/* USER CODE BEGIN INCLUDE */
/* USER CODE END INCLUDE */
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* Private variables ---------------------------------------------------------*/
/* USER CODE END PV */
/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
* @{
*/
/** @addtogroup USBD_DESC
* @{
*/
/** @defgroup USBD_DESC_Private_TypesDefinitions USBD_DESC_Private_TypesDefinitions
* @brief Private types.
* @{
*/
/* USER CODE BEGIN PRIVATE_TYPES */
/* USER CODE END PRIVATE_TYPES */
/**
* @}
*/
/** @defgroup USBD_DESC_Private_Defines USBD_DESC_Private_Defines
* @brief Private defines.
* @{
*/
#define USBD_VID 0x0483
#define USBD_LANGID_STRING 0x0409
#define USBD_MANUFACTURER_STRING "XinChip"
#define USBD_PID_FS 22336
#define USBD_PRODUCT_STRING_FS "XinChip Virtual ComPort"
#define USBD_CONFIGURATION_STRING_FS "CDC Config"
#define USBD_INTERFACE_STRING_FS "CDC Interface"
#define USB_SIZ_BOS_DESC 0x0C
/* USER CODE BEGIN PRIVATE_DEFINES */
/* USER CODE END PRIVATE_DEFINES */
/**
* @}
*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/** @defgroup USBD_DESC_Private_Macros USBD_DESC_Private_Macros
* @brief Private macros.
* @{
*/
/* USER CODE BEGIN PRIVATE_MACRO */
/* USER CODE END PRIVATE_MACRO */
/**
* @}
*/
/** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes
* @brief Private functions declaration.
* @{
*/
static void Get_SerialNum(void);
static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len);
/**
* @}
*/
/** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes
* @brief Private functions declaration for FS.
* @{
*/
uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
#if (USBD_LPM_ENABLED == 1)
uint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
#endif /* (USBD_LPM_ENABLED == 1) */
/**
* @}
*/
/** @defgroup USBD_DESC_Private_Variables USBD_DESC_Private_Variables
* @brief Private variables.
* @{
*/
USBD_DescriptorsTypeDef FS_Desc =
{
USBD_FS_DeviceDescriptor
, USBD_FS_LangIDStrDescriptor
, USBD_FS_ManufacturerStrDescriptor
, USBD_FS_ProductStrDescriptor
, USBD_FS_SerialStrDescriptor
, USBD_FS_ConfigStrDescriptor
, USBD_FS_InterfaceStrDescriptor
#if (USBD_LPM_ENABLED == 1)
, USBD_FS_USR_BOSDescriptor
#endif /* (USBD_LPM_ENABLED == 1) */
};
#if defined ( __ICCARM__ ) /* IAR Compiler */
#pragma data_alignment=4
#endif /* defined ( __ICCARM__ ) */
#ifdef USE_USBD_COMPOSITE
__ALIGN_BEGIN uint8_t USBD_FS_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END =
{
0x12, /*bLength */
USB_DESC_TYPE_DEVICE, /*bDescriptorType*/
0x00, /*bcdUSB */
0x02,
#if USE_USBD_COMPOSITE /* Audio Class */
#if USBD_COMPOSITE_USE_IAD
0xEF, /*bDeviceClass*/
0x02, /*bDeviceSubClass*/
0x01, /*bDeviceProtocol*/
#else
#if USBD_CMPSIT_ACTIVATE_CDC || USBD_CMPSIT_ACTIVATE_MULTI_CDC
/* CDC 02 02 00 */
0x02,
0x02,
0x00,
#else
/* normal */
0x00, /*bDeviceClass*/
0x00, /*bDeviceSubClass*/
0x00, /*bDeviceProtocol*/
#endif
#endif
#else /* CDC 02 02 00 */
0x00, /*bDeviceClass*/
0x00, /*bDeviceSubClass*/
0x00, /*bDeviceProtocol*/
#endif
USB_MAX_EP0_SIZE, /*bMaxPacketSize*/
LOBYTE(USBD_VID), /*idVendor*/
HIBYTE(USBD_VID), /*idVendor*/
LOBYTE(USBD_PID_FS), /*idProduct*/
HIBYTE(USBD_PID_FS), /*idProduct*/
0x00, /*bcdDevice rel. 2.00*/
0x02,
USBD_IDX_MFC_STR, /*Index of manufacturer string*/
USBD_IDX_PRODUCT_STR, /*Index of product string*/
USBD_IDX_SERIAL_STR, /*Index of serial number string*/
USBD_MAX_NUM_CONFIGURATION /*bNumConfigurations*/
};
#else
/** USB standard device descriptor. */
__ALIGN_BEGIN uint8_t USBD_FS_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END =
{
0x12, /*bLength */
USB_DESC_TYPE_DEVICE, /*bDescriptorType*/
#if (USBD_LPM_ENABLED == 1)
0x01, /*bcdUSB */ /* changed to USB version 2.01
in order to support LPM L1 suspend
resume test of USBCV3.0*/
#else
0x00, /*bcdUSB */
#endif /* (USBD_LPM_ENABLED == 1) */
0x02,
0x02, /*bDeviceClass*/
0x02, /*bDeviceSubClass*/
0x00, /*bDeviceProtocol*/
USB_MAX_EP0_SIZE, /*bMaxPacketSize*/
LOBYTE(USBD_VID), /*idVendor*/
HIBYTE(USBD_VID), /*idVendor*/
LOBYTE(USBD_PID_FS), /*idProduct*/
HIBYTE(USBD_PID_FS), /*idProduct*/
0x00, /*bcdDevice rel. 2.00*/
0x02,
USBD_IDX_MFC_STR, /*Index of manufacturer string*/
USBD_IDX_PRODUCT_STR, /*Index of product string*/
USBD_IDX_SERIAL_STR, /*Index of serial number string*/
USBD_MAX_NUM_CONFIGURATION /*bNumConfigurations*/
};
#endif
/* USB_DeviceDescriptor */
/** BOS descriptor. */
#if (USBD_LPM_ENABLED == 1)
#if defined ( __ICCARM__ ) /* IAR Compiler */
#pragma data_alignment=4
#endif /* defined ( __ICCARM__ ) */
__ALIGN_BEGIN uint8_t USBD_FS_BOSDesc[USB_SIZ_BOS_DESC] __ALIGN_END =
{
0x5,
USB_DESC_TYPE_BOS,
0xC,
0x0,
0x1, /* 1 device capability*/
/* device capability*/
0x7,
USB_DEVICE_CAPABITY_TYPE,
0x2,
0x2, /* LPM capability bit set*/
0x0,
0x0,
0x0
};
#endif /* (USBD_LPM_ENABLED == 1) */
/**
* @}
*/
/** @defgroup USBD_DESC_Private_Variables USBD_DESC_Private_Variables
* @brief Private variables.
* @{
*/
#if defined ( __ICCARM__ ) /* IAR Compiler */
#pragma data_alignment=4
#endif /* defined ( __ICCARM__ ) */
/** USB lang identifier descriptor. */
__ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END =
{
USB_LEN_LANGID_STR_DESC,
USB_DESC_TYPE_STRING,
LOBYTE(USBD_LANGID_STRING),
HIBYTE(USBD_LANGID_STRING)
};
#if defined ( __ICCARM__ ) /* IAR Compiler */
#pragma data_alignment=4
#endif /* defined ( __ICCARM__ ) */
/* Internal string descriptor. */
__ALIGN_BEGIN uint8_t USBD_StrDesc[USBD_MAX_STR_DESC_SIZ] __ALIGN_END;
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
#pragma data_alignment=4
#endif
__ALIGN_BEGIN uint8_t USBD_StringSerial[USB_SIZ_STRING_SERIAL] __ALIGN_END = {
USB_SIZ_STRING_SERIAL,
USB_DESC_TYPE_STRING,
};
/**
* @}
*/
/** @defgroup USBD_DESC_Private_Functions USBD_DESC_Private_Functions
* @brief Private functions.
* @{
*/
/**
* @brief Return the device descriptor
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
UNUSED(speed);
*length = sizeof(USBD_FS_DeviceDesc);
return USBD_FS_DeviceDesc;
}
/**
* @brief Return the LangID string descriptor
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
UNUSED(speed);
*length = sizeof(USBD_LangIDDesc);
return USBD_LangIDDesc;
}
/**
* @brief Return the product string descriptor
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
if(speed == USBD_SPEED_HIGH)
{
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
}
else
{
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
}
return USBD_StrDesc;
}
/**
* @brief Return the manufacturer string descriptor
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
UNUSED(speed);
USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
return USBD_StrDesc;
}
/**
* @brief Return the serial number string descriptor
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
UNUSED(speed);
*length = USB_SIZ_STRING_SERIAL;
/* Update the serial number string descriptor with the data from the unique
* ID */
Get_SerialNum();
/* USER CODE BEGIN USBD_FS_SerialStrDescriptor */
/* USER CODE END USBD_FS_SerialStrDescriptor */
return (uint8_t *) USBD_StringSerial;
}
/**
* @brief Return the configuration string descriptor
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
if(speed == USBD_SPEED_HIGH)
{
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
}
else
{
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
}
return USBD_StrDesc;
}
/**
* @brief Return the interface string descriptor
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
if(speed == 0)
{
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
}
else
{
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
}
return USBD_StrDesc;
}
#if (USBD_LPM_ENABLED == 1)
/**
* @brief Return the BOS descriptor
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
UNUSED(speed);
*length = sizeof(USBD_FS_BOSDesc);
return (uint8_t*)USBD_FS_BOSDesc;
}
#endif /* (USBD_LPM_ENABLED == 1) */
/**
* @brief Create the serial number string descriptor
* @param None
* @retval None
*/
static void Get_SerialNum(void)
{
uint32_t deviceserial0;
uint32_t deviceserial1;
uint32_t deviceserial2;
deviceserial0 = DEVICE_ID1;
deviceserial1 = DEVICE_ID2;
deviceserial2 = DEVICE_ID3;
deviceserial0 += deviceserial2;
if (deviceserial0 != 0)
{
IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8);
IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4);
}
}
/**
* @brief Convert Hex 32Bits value into char
* @param value: value to convert
* @param pbuf: pointer to the buffer
* @param len: buffer length
* @retval None
*/
static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len)
{
uint8_t idx = 0;
for (idx = 0; idx < len; idx++)
{
if (((value >> 28)) < 0xA)
{
pbuf[2 * idx] = (value >> 28) + '0';
}
else
{
pbuf[2 * idx] = (value >> 28) + 'A' - 10;
}
value = value << 4;
pbuf[2 * idx + 1] = 0;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
component/xc6xx_drivers/Drivers/USB/USB_DEVICE/App/cdc/usbd_desc.h
+148
View File
@@ -0,0 +1,148 @@
/*!
* \file usbd_desc.h
*
* \brief Target the USB device descriptors implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USBD_DESC__C
#define __USBD_DESC__C
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "usbd_def.h"
/* USER CODE BEGIN INCLUDE */
/* USER CODE END INCLUDE */
/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
* @{
*/
/** @defgroup USBD_DESC USBD_DESC
* @brief Usb device descriptors module.
* @{
*/
/** @defgroup USBD_DESC_Exported_Constants USBD_DESC_Exported_Constants
* @brief Constants.
* @{
*/
#define DEVICE_ID1 (0x20220000)
#define DEVICE_ID2 (0x1B0000)
#define DEVICE_ID3 (0x0914)
#define USB_SIZ_STRING_SERIAL 0x1A
/* USER CODE BEGIN EXPORTED_CONSTANTS */
/* USER CODE END EXPORTED_CONSTANTS */
/**
* @}
*/
/** @defgroup USBD_DESC_Exported_Defines USBD_DESC_Exported_Defines
* @brief Defines.
* @{
*/
/* USER CODE BEGIN EXPORTED_DEFINES */
/* USER CODE END EXPORTED_DEFINES */
/**
* @}
*/
/** @defgroup USBD_DESC_Exported_TypesDefinitions USBD_DESC_Exported_TypesDefinitions
* @brief Types.
* @{
*/
/* USER CODE BEGIN EXPORTED_TYPES */
/* USER CODE END EXPORTED_TYPES */
/**
* @}
*/
/** @defgroup USBD_DESC_Exported_Macros USBD_DESC_Exported_Macros
* @brief Aliases.
* @{
*/
/* USER CODE BEGIN EXPORTED_MACRO */
/* USER CODE END EXPORTED_MACRO */
/**
* @}
*/
/** @defgroup USBD_DESC_Exported_Variables USBD_DESC_Exported_Variables
* @brief Public variables.
* @{
*/
/** Descriptor for the Usb device. */
extern USBD_DescriptorsTypeDef FS_Desc;
/* USER CODE BEGIN EXPORTED_VARIABLES */
/* USER CODE END EXPORTED_VARIABLES */
/**
* @}
*/
/** @defgroup USBD_DESC_Exported_FunctionsPrototype USBD_DESC_Exported_FunctionsPrototype
* @brief Public functions declaration.
* @{
*/
/* USER CODE BEGIN EXPORTED_FUNCTIONS */
/* USER CODE END EXPORTED_FUNCTIONS */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __USBD_DESC__C */
component/xc6xx_drivers/Drivers/USB/USB_DEVICE/App/hid_composite/usb_device.c
+119
View File
@@ -0,0 +1,119 @@
/*!
* \file usb_device.c
*
* \brief Target usb device implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Includes ------------------------------------------------------------------*/
#include "usb_device.h"
#include "usbd_core.h"
#include "usbd_desc.h"
#include "usbd_hid_mouse.h"
#include "usbd_hid_keyboard.h"
#include "usbd_hid_custom.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* USER CODE BEGIN PV */
/* Private variables ---------------------------------------------------------*/
/* USER CODE END PV */
/* USER CODE BEGIN PFP */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE END PFP */
/* USB Device Core handle declaration. */
USBD_HandleTypeDef hUsbDeviceFS;
/*
* -- Insert your variables declaration here --
*/
/* USER CODE BEGIN 0 */
extern PCD_HandleTypeDef hpcd_USB_OTG_FS;
/* USER CODE END 0 */
/*
* -- Insert your external function declaration here --
*/
void USB_Handler(void) { HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS); }
/**
* Init USB device Library, add supported class and start the library
* @retval None
*/
void USB_DEVICE_Init(void)
{
static uint8_t HID_Mouse_EP_Addr[] = {HID_MOUSE_EPIN_ADDR };
static uint8_t HID_Keyboard_EP_Addr[] = {HID_KEYBOARD_EPIN_ADDR, HID_KEYBOARD_EPOUT_ADDR };
static uint8_t HID_Custom_EP_Addr[] = {HID_CUSTOM_EPIN_ADDR, HID_CUSTOM_EPOUT_ADDR };
#ifdef USE_USBD_COMPOSITE
if(USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK)
{
Error_Handler();
}
#if USBD_CMPSIT_ACTIVATE_HID_MOUSE
/* Register HID class second instance */
if(USBD_RegisterClassComposite(&hUsbDeviceFS, USBD_HID_MOUSE_CLASS, CLASS_TYPE_HID_MOUSE, HID_Mouse_EP_Addr) != USBD_OK)
{
Error_Handler();
}
#endif
#if USBD_CMPSIT_ACTIVATE_HID_KEYBOARD
if(USBD_RegisterClassComposite(&hUsbDeviceFS, USBD_HID_KEYBOARD_CLASS, CLASS_TYPE_HID_KEYBOARD, HID_Keyboard_EP_Addr) != USBD_OK)
{
Error_Handler();
}
#endif
#if USBD_CMPSIT_ACTIVATE_HID_CUSTOM
if(USBD_RegisterClassComposite(&hUsbDeviceFS, USBD_HID_CUSTOM_CLASS, CLASS_TYPE_HID_CUSTOM, HID_Custom_EP_Addr) != USBD_OK)
{
Error_Handler();
}
#endif
if(USBD_Start(&hUsbDeviceFS) != USBD_OK)
{
Error_Handler();
}
#endif
}
/**
* @}
*/
/**
* @}
*/

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