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hpw422移植新的sdk

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xushaoxiang
2026-07-03 18:08:25 +08:00
commit 945a5a5b0b
2583 changed files with 713209 additions and 0 deletions
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project/example/2.4g/RF24_ADV/app/Startup/lora/startup_xinc.s
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;/*****************************************************************************
; * @file: startup_xinc.s
; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
; * Device xinc.
; *****************************************************************************/
Stack_Size EQU 0x00000600
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; ToDo: Add here the vectors for the device specific external interrupts handler
DCD 0 ; 0 BLE Handler
DCD DMAS_Handler ; 1
DCD CPR_Handler ; 2
DCD GPIO_Handler ; 3
DCD RTC_Handler ; 4
DCD TIMER0_Handler ; 5
DCD TIMER1_Handler
DCD TIMER2_Handler
DCD TIMER3_Handler
DCD WDT_Handler
DCD I2C_Handler
DCD UART0_Handler
DCD UART1_Handler
DCD SPI0_Handler
DCD SPI1_Handler
DCD 0
DCD 0
DCD GADC_Handler ; 17
DCD 0 ; 18
DCD 0 ; 19
DCD 0 ; 20
DCD 0 ; 21
DCD RF24G_Handler ; 22
DCD PWM_Handler ; 23
DCD BOR_Handler ; 24
DCD 0 ; 25
DCD 0 ; 26
DCD AOTIMER0_Handler ; 27
DCD AOTIMER1_Handler ; 28
DCD CMP_Handler ; 29
DCD FMC_Handler ; 30
DCD CAN_Handler ; 31
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR r0, =0x4000013C ; remap
LDR r1, =0x10000001
STR r1, [r0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
Default_Handler PROC
;EXPORT BLE_Handler [WEAK]
EXPORT DMAS_Handler [WEAK]
EXPORT CPR_Handler [WEAK]
EXPORT GPIO_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT TIMER2_Handler [WEAK]
EXPORT TIMER3_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT I2C_Handler [WEAK]
EXPORT UART0_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
EXPORT SPI0_Handler [WEAK]
EXPORT SPI1_Handler [WEAK]
;EXPORT KBS_Handler [WEAK]
;EXPORT QDEC_Handler [WEAK]
EXPORT GADC_Handler [WEAK]
EXPORT AOTIMER0_Handler [WEAK]
EXPORT AOTIMER1_Handler [WEAK]
EXPORT CMP_Handler [WEAK]
EXPORT FMC_Handler [WEAK]
EXPORT CAN_Handler [WEAK]
;EXPORT SIM_Handler [WEAK]
;EXPORT AES_Handler [WEAK]
EXPORT PendSV_Handler [WEAK]
EXPORT SysTick_Handler [WEAK]
EXPORT RF24G_Handler [WEAK]
EXPORT PWM_Handler [WEAK]
EXPORT BOR_Handler [WEAK]
PendSV_Handler
SysTick_Handler
;BLE_Handler
DMAS_Handler
CPR_Handler
GPIO_Handler
RTC_Handler
TIMER0_Handler
TIMER1_Handler
TIMER2_Handler
TIMER3_Handler
WDT_Handler
I2C_Handler
UART0_Handler
UART1_Handler
SPI0_Handler
SPI1_Handler
;KBS_Handler
;QDEC_Handler
GADC_Handler
;SIM_Handler
;AES_Handler
AOTIMER0_Handler
AOTIMER1_Handler
CMP_Handler
FMC_Handler
CAN_Handler
RF24G_Handler
PWM_Handler
BOR_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
END
project/example/2.4g/RF24_ADV/app/Startup/system_it_xinc.c
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/*!
* \file system_it_xinc.c
*
* \brief Target system interruption implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "system_it_xinc.h"
/*------------------------------------------------------------------------------------
Func Prototype
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
/**
****************************************************************************************
* @brief This function handles NMI exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void NMI_Handler(void)
{
/* USER CODE BEGIN NonMaskableInt_IRQn */
DEBUG("%s\n", __func__);
/* USER CODE END NonMaskableInt_IRQn */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles Hard Fault exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void HardFault_Handler(void)
{
/* USER CODE BEGIN HardFault_IRQn */
DEBUG("%s\n", __func__);
/* USER CODE END HardFault_IRQn */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles Memory Manage exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void MemManage_Handler(void)
{
/* USER CODE BEGIN */
DEBUG("%s\n", __func__);
/* USER CODE END */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles Bus Fault exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void BusFault_Handler(void)
{
/* USER CODE BEGIN */
DEBUG("%s\n", __func__);
/* USER CODE END */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles Usage Fault exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void UsageFault_Handler(void)
{
/* USER CODE BEGIN */
DEBUG("%s\n", __func__);
/* USER CODE END */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles SVCall exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void SVC_Handler(void)
{
/* USER CODE BEGIN SVCall_IRQn */
DEBUG("%s\n", __func__);
/* USER CODE END SVCall_IRQn */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles Debug Monitor exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void DebugMon_Handler(void)
{
/* USER CODE BEGIN */
DEBUG("%s\n", __func__);
/* USER CODE END */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles PendSVC exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void PendSV_Handler(void)
{
/* USER CODE BEGIN PendSV_IRQn */
DEBUG("%s\n", __func__);
/* USER CODE END PendSV_IRQn */
while (1)
{
}
}
/****************************** Hard Fault Handler Functions *******************************/
/*------------------------------------------------------------------------------------
Private Functions
-------------------------------------------------------------------------------------*/
void HardFault_Handler_c(unsigned int * HardFault_args)
{
/*栈帧里面内容：*/
unsigned int stack_r0; //压栈的 R0
unsigned int stack_r1; //压栈的 R1
unsigned int stack_r2; //压栈的 R2
unsigned int stack_r3; //压栈的 R3
unsigned int stack_r12; //压栈的 R12
unsigned int stack_lr; //压栈的 lr
unsigned int stack_pc; //压栈的 pc
unsigned int stack_psr; //压栈的 psr
stack_r0 = ((unsigned int)HardFault_args[0]);
stack_r1 = ((unsigned int)HardFault_args[1]);
stack_r2 = ((unsigned int)HardFault_args[2]);
stack_r3 = ((unsigned int)HardFault_args[3]);
stack_r12 = ((unsigned int)HardFault_args[4]);
stack_lr = ((unsigned int)HardFault_args[5]);
stack_pc = ((unsigned int)HardFault_args[6]);
stack_psr = ((unsigned int)HardFault_args[7]);
DEBUG("----%s----\n", __func__);
DEBUG("R0=%x\n",stack_r0);
DEBUG("R1=%x\n",stack_r1);
DEBUG("R2=%x\n",stack_r2);
DEBUG("R3=%x\n",stack_r3);
DEBUG("R12=%x\n",stack_r12);
DEBUG("LR[R14]=%x\n",stack_lr);
DEBUG("PC[R15]=%x\n",stack_pc);
DEBUG("PSR=%x\n",stack_psr);
DEBUG("SCB_SHCSR=%x\n",SCB->SHCSR);
DEBUG("---------------------------\n");
while(1);
}
/*******************************************************************************************/
project/example/2.4g/RF24_ADV/app/Startup/system_it_xinc.h
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/*!
* \file system_it_xinc.h
*
* \brief The header of system_it_xinc.c
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __SYSTEM_IT_XINC_H__
#define __SYSTEM_IT_XINC_H__
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "xc6xxx.h"
/*------------------------------------------------------------------------------------
Exported Functions
-------------------------------------------------------------------------------------*/
void NMI_Handler( void );
void HardFault_Handler( void );
void MemManage_Handler( void );
void BusFault_Handler( void );
void UsageFault_Handler( void );
void SVC_Handler( void );
void DebugMon_Handler( void );
void PendSV_Handler( void );
void HardFault_Handler_c(unsigned int * HardFault_args);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_IT_XINC_H__ */
project/example/2.4g/RF24_ADV/app/Startup/system_xinc.c
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/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system
*
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include <stdio.h>
#include "xc6xxx.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
#define __DEBUG_OUT_PORT 0
#define readl(addr) (*(volatile unsigned int *) (addr))
#define writel(addr, value) (*(volatile unsigned int *) (addr) = (value))
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
#define VECTOR_NUM 48
void set_vector(void)
{
#if (USE_XIP == 1)
GLOBAL_INT_DISABLE();
for (uint32_t i = 0, *Pvector = (uint32_t *)(0x11001000 + 0),
*_vector_table = (uint32_t *)(0x10000000);
i < VECTOR_NUM; i++) // copy vertor table
{
_vector_table[i] = *Pvector++;
}
*((volatile unsigned int *)(0x4000013C)) =
0x10000001; // inter vertor table remap
GLOBAL_INT_RESTORE();
#endif
}
static void WDT_ResetInit(void)
{
cpr_ctlapbclken_grctl__wdt_pclk_en__setf(ENABLE);
cpr_rstctl_ctlapb_sw__wdt_rstn__setf(RSTCTL_ENABLE);
cpr_rstctl_ctlapb_sw__wdt_rstn__setf(RSTCTL_DISABLE);
cpr_rstctl_wdtrst_mask_set(
(WDT_SYS_RSTN_MASK_DISABLE | WDT_M0_RSTN_MASK_ENABLE));
cpr_lp_ctl__wdt_tclk_en__setf(ENABLE);
wdt_cr__wdt_en__setf(DISABLE);
}
void SystemInit(void)
{
WDT_ResetInit();
#if (USE_XIP == 1)
set_vector();
#endif
writel(0x40000040, readl(0x40000040) | (0x01 << 4) | 0xFFFF0000);
}
__RAM_CODE int sendchar(int c)
{
unsigned int status;
#if (__DEBUG_OUT_PORT == 1)
for (;;) {
status = (*((volatile unsigned *)(0x40011000 + 0x14)));
status &= 0x20;
if (status == 0x20)
break;
}
(*((volatile unsigned *)(0x40011000 + 0x00))) = c;
return (1);
#else
for (;;) {
status = (*((volatile unsigned *)(0x40010000 + 0x14)));
status &= 0x20;
if (status == 0x20)
break;
}
(*((volatile unsigned *)(0x40010000 + 0x00))) = c;
return (1);
#endif
}
struct __FILE
{
int handle; /* Add whatever you need here */
};
FILE __stdout;
__RAM_CODE int fputc(int ch, FILE *f) { return (sendchar(ch)); }
int ferror(FILE *f)
{
/* Your implementation of ferror */
return EOF;
}
void _ttywrch(int ch) { sendchar(ch); }
void _sys_exit(int return_code)
{
label:
goto label; /* endless loop */
}
project/example/2.4g/RF24_ADV/app/Startup/xc60xx/startup_xinc.s
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;/*****************************************************************************
; * @file: startup_xinc.s
; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
; * Device xinc.
; *****************************************************************************/
Stack_Size EQU 0x00000800
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; ToDo: Add here the vectors for the device specific external interrupts handler
DCD BLE_Handler ; 0
DCD DMA_Handler ; 1
DCD CPR_Handler ; 2
DCD GPIO_Handler ; 3
DCD RTC_Handler ; 4
DCD TIMER0_Handler ; 5
DCD TIMER1_Handler ; 6
DCD TIMER2_Handler ; 7
DCD TIMER3_Handler ; 8
DCD WDT_Handler ; 9
DCD I2C_Handler ; 10
DCD UART0_Handler ; 11
DCD UART1_Handler ; 12
DCD SPI0_Handler ; 13
DCD SPI1_Handler ; 14
DCD 0 ; 15
DCD 0 ; 16
DCD GADC_Handler ; 17
DCD PWM_Handler ; 18
DCD AES_Handler ; 19
DCD USB_Handler ; 20
DCD AUDIO_Handler ; 21
DCD RF24G_Handler ; 22
DCD SPI2_Handler ; 23
DCD MPU_Handler ; 24
DCD UART2_Handler ; 25
DCD I2S_Handler ; 26
DCD AOTIMER0_Handler ; 27
DCD AOTIMER1_Handler ; 28
DCD CMP_Handler ; 29
DCD FMC_Handler ; 30
DCD CAN_Handler ; 31
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR r0, =0x4000013C ; remap
LDR r1, =0x10000001
STR r1, [r0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
IMPORT HardFault_Handler_c ;函数声明
movs r0, #4 ;判断主栈指针还是进程栈指针
mov r1, lr
tst r0, r1
beq hf_used_msp ;如果是主栈指针
mrs r0, psp ;否则是进程栈指针,把进程栈指针地址付给 R0
ldr r1, =HardFault_Handler_c ;跳转到 HardFault 中断程序
bx r1
hf_used_msp
mrs r0, msp ;把主栈指针地址赋给 R0
ldr r1, =HardFault_Handler_c
bx r1
;EXPORT HardFault_Handler [WEAK]
;B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT BLE_Handler [WEAK]
EXPORT DMA_Handler [WEAK]
EXPORT CPR_Handler [WEAK]
EXPORT GPIO_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT TIMER2_Handler [WEAK]
EXPORT TIMER3_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT I2C_Handler [WEAK]
EXPORT UART0_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
EXPORT SPI0_Handler [WEAK]
EXPORT SPI1_Handler [WEAK]
;EXPORT KBS_Handler [WEAK]
;EXPORT QDEC_Handler [WEAK]
EXPORT GADC_Handler [WEAK]
EXPORT PWM_Handler [WEAK]
EXPORT AES_Handler [WEAK]
EXPORT PendSV_Handler [WEAK]
EXPORT SysTick_Handler [WEAK]
EXPORT USB_Handler [WEAK];20
EXPORT AUDIO_Handler [WEAK];21
EXPORT RF24G_Handler [WEAK];22
EXPORT SPI2_Handler [WEAK];23
EXPORT MPU_Handler [WEAK];24
EXPORT UART2_Handler [WEAK];25
EXPORT I2S_Handler [WEAK];26
EXPORT AOTIMER0_Handler [WEAK];27
EXPORT AOTIMER1_Handler [WEAK];28
EXPORT CMP_Handler [WEAK];29
EXPORT FMC_Handler [WEAK];30
EXPORT CAN_Handler [WEAK];31
PendSV_Handler
SysTick_Handler
BLE_Handler
RF24G_Handler
DMA_Handler
CPR_Handler
GPIO_Handler
RTC_Handler
TIMER0_Handler
TIMER1_Handler
TIMER2_Handler
TIMER3_Handler
WDT_Handler
I2C_Handler
I2S_Handler
UART0_Handler
UART1_Handler
UART2_Handler
SPI0_Handler
SPI1_Handler
SPI2_Handler
MPU_Handler
;KBS_Handler
;QDEC_Handler
GADC_Handler
PWM_Handler
AUDIO_Handler
;SIM_Handler
AES_Handler
AOTIMER0_Handler
AOTIMER1_Handler
CMP_Handler
FMC_Handler
CAN_Handler
USB_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
END
project/example/2.4g/RF24_ADV/app/Startup/xc65xx/startup_xinc.s
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;/*****************************************************************************
; * @file: startup_xinc.s
; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
; * Device xinc.
; *****************************************************************************/
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; ToDo: Add here the vectors for the device specific external interrupts handler
DCD BLE_Handler ; 0
DCD DMA_Handler ; 1
DCD CPR_Handler ; 2
DCD GPIO_Handler ; 3
DCD RTC_Handler ; 4
DCD TIMER0_Handler ; 5
DCD TIMER1_Handler ; 6
DCD TIMER2_Handler ; 7
DCD TIMER3_Handler ; 8
DCD WDT_Handler ; 9
DCD I2C_Handler ; 10
DCD UART0_Handler ; 11
DCD UART1_Handler ; 12
DCD SPI0_Handler ; 13
DCD SPI1_Handler ; 14
DCD 0 ; 15
DCD 0 ; 16
DCD GADC_Handler ; 17
DCD PWM_Handler ; 18
DCD AES_Handler ; 19
DCD USB_Handler ; 20
DCD AUDIO_Handler ; 21
DCD RF24G_Handler ; 22
DCD SPI2_Handler ; 23
DCD MPU_Handler ; 24
DCD UART2_Handler ; 25
DCD I2S_Handler ; 26
DCD AOTIMER0_Handler ; 27
DCD AOTIMER1_Handler ; 28
DCD CMP_Handler ; 29
DCD FMC_Handler ; 30
DCD CAN_Handler ; 31
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR r0, =0x4000013C ; remap
LDR r1, =0x10000001
STR r1, [r0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
IMPORT HardFault_Handler_c ;函数声明
movs r0, #4 ;判断主栈指针还是进程栈指针
mov r1, lr
tst r0, r1
beq hf_used_msp ;如果是主栈指针
mrs r0, psp ;否则是进程栈指针,把进程栈指针地址付给 R0
ldr r1, =HardFault_Handler_c ;跳转到 HardFault 中断程序
bx r1
hf_used_msp
mrs r0, msp ;把主栈指针地址赋给 R0
ldr r1, =HardFault_Handler_c
bx r1
;EXPORT HardFault_Handler [WEAK]
;B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT BLE_Handler [WEAK]
EXPORT DMA_Handler [WEAK]
EXPORT CPR_Handler [WEAK]
EXPORT GPIO_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT TIMER2_Handler [WEAK]
EXPORT TIMER3_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT I2C_Handler [WEAK]
EXPORT UART0_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
EXPORT SPI0_Handler [WEAK]
EXPORT SPI1_Handler [WEAK]
;EXPORT KBS_Handler [WEAK]
;EXPORT QDEC_Handler [WEAK]
EXPORT GADC_Handler [WEAK]
EXPORT PWM_Handler [WEAK]
EXPORT AES_Handler [WEAK]
EXPORT PendSV_Handler [WEAK]
EXPORT SysTick_Handler [WEAK]
EXPORT USB_Handler [WEAK];20
EXPORT AUDIO_Handler [WEAK];21
EXPORT RF24G_Handler [WEAK];22
EXPORT SPI2_Handler [WEAK];23
EXPORT MPU_Handler [WEAK];24
EXPORT UART2_Handler [WEAK];25
EXPORT I2S_Handler [WEAK];26
EXPORT AOTIMER0_Handler [WEAK];27
EXPORT AOTIMER1_Handler [WEAK];28
EXPORT CMP_Handler [WEAK];29
EXPORT FMC_Handler [WEAK];30
EXPORT CAN_Handler [WEAK];31
PendSV_Handler
SysTick_Handler
BLE_Handler
RF24G_Handler
DMA_Handler
CPR_Handler
GPIO_Handler
RTC_Handler
TIMER0_Handler
TIMER1_Handler
TIMER2_Handler
TIMER3_Handler
WDT_Handler
I2C_Handler
I2S_Handler
UART0_Handler
UART1_Handler
UART2_Handler
SPI0_Handler
SPI1_Handler
SPI2_Handler
MPU_Handler
;KBS_Handler
;QDEC_Handler
GADC_Handler
PWM_Handler
AUDIO_Handler
;SIM_Handler
AES_Handler
AOTIMER0_Handler
AOTIMER1_Handler
CMP_Handler
FMC_Handler
CAN_Handler
USB_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
END
project/example/2.4g/RF24_ADV/app/api/app_64m.h
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#ifndef __APP_64M__
#define __APP_64M__
#include "xc6xxx_rf_2_4g.h"
#define __write_hw_reg32(reg, val) ((*reg) = (val))
#define __read_hw_reg32(reg, val) ((val) = (*reg))
#define CPR_CTLAPBCLKEN_GRCTL ((volatile unsigned *)(0x40000000 + 0x070))
#define CPR_AOCLKEN_GRCTL ((volatile unsigned *)(0x40002400 + 0x7C))
#define AO_GPIO_MODE ((volatile unsigned *)(0x40002000 + 0x0044))
#define AO_GPIO_CTL ((volatile unsigned *)(0x40002000 + 0x0048))
void use_64m_crtstal_init(void);
void rf_64M_set_rx_channel(uint16_t channel);
void rf_64M_set_tx_channel(uint16_t channel);
void testpin_64M_config(void);
void Init_rtc_gpio(uint32_t num, uint8_t inter_mode);
#endif //__APP_64M__
project/example/2.4g/RF24_ADV/app/api/main.h
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/*
* @Descripttion:
* @version:
* @Author: sueRimn
* @Date: 2023-12-12 14:23:55
* @LastEditors: sueRimn
* @LastEditTime: 2024-06-07 13:46:09
*/
/*!
* \file main.h
*
* \brief The head file of main.c
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MAIN_H__
#define __MAIN_H__
#ifdef __cplusplus
extern "C"
{
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "rf_config.h"
#include "xc6xxx.h"
#include "xc6xxx_rf_2_4g.h"
#include "xc6xxx_rf_ADV.h"
#include "rf_compatible_normal.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
#define DEBUG_LOG
#define SEND_TIMERMS_CNT 7
#define RECV_TIMERMS_OUT (7 + SEND_TIMERMS_CNT)
#define XC_SEND_NUM 1000U
#define RF_TX_TIMERx TIMER0_IDX
#define RF_RX_TIMERx TIMER0_IDX
#define RF_CONFIRMED_VALUE 5
#define GPIO_TEST 1
#define TEST_GPIO_1 GPIO_1
#if XC62XX
#define TEST_GPIO_2 GPIO_0
#else
#define TEST_GPIO_2 GPIO_21
#endif
/*------------------------------------------------------------------------------------
TypeDef
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Global Variables
-------------------------------------------------------------------------------------*/
extern bool rf_send_timer_flag;
/*------------------------------------------------------------------------------------
Exported Functions
-------------------------------------------------------------------------------------*/
void rf_buff_info(uint8_t *buff, uint16_t len);
void rf_2M_reg_info(void);
void rf_dump_log(void);
uint8_t rf_data_config(uint8_t *buff, uint16_t len);
#ifdef __cplusplus
}
#endif
#endif /* __MAIN_H__ */
project/example/2.4g/RF24_ADV/app/api/rf_compatible_normal.h
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#ifndef __RF_COMPATIBLE_NORMAL__
#define __RF_COMPATIBLE_NORMAL__
#include "rf_config.h"
#include "xc6xxx_rf_2_4g.h"
#include "xc_software_crc.h"
#include <stdint.h>
#define RF_ADDR_LEN XINCX_RF_TX_ADDR_WIDTH // 5U
#define RF_RECV_EXTEN_LEN 3U
#define RF_MAX_RECV_LEN 60U
#define RF_CRC_INIT_VALUE 0xFFFF
#define PANCHIP_WHITEN_INIT_VAL (0x7F)
extern uint16_t rf_addr_crc;
extern uint8_t panchip_addr_whiten;
extern uint8_t addr_buff[5];
void rf_addr_map(uint8_t *addr_buff);
uint16_t rf_get_addr_crc(void);
uint8_t rf_recv_addr(void);
void rf_compatible_config(void);
uint32_t rf_rx_normal_manage(void);
uint32_t rf_tx_normal_manage(uint8_t *buff, uint8_t length);
#endif //__RF_COMPATIBLE_NORMAL__
project/example/2.4g/RF24_ADV/app/api/sdk_config.h
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#ifndef SDK_DRIVER_CONFIG_H
#define SDK_DRIVER_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>\n
#ifdef USE_APP_CONFIG
#include "app_config.h"
#endif
// <h> XC_Drivers
// <e> XC_CLOCK_ENABLED
//==========================================================
#ifndef XC_CLOCK_ENABLED
#define XC_CLOCK_ENABLED 1
#endif
// </e>
// <e> XC_PWR_ENABLED
//==========================================================
#ifndef XC_PWR_ENABLED
#define XC_PWR_ENABLED 1
#endif
// </e>
// <e> XC_WDT_ENABLED
//==========================================================
#ifndef XC_WDT_ENABLED
#define XC_WDT_ENABLED 1
#endif
// </e>
// <e> XC_BOR_ENABLED
//==========================================================
#ifndef XC_BOR_ENABLED
#define XC_BOR_ENABLED 1
#endif
// </e>
// <e> XC_SYSTICK_ENABLED
//==========================================================
#ifndef XC_SYSTICK_ENABLED
#define XC_SYSTICK_ENABLED 1
#endif
// </e>
// <e> XC_TIMER_ENABLED
//==========================================================
#ifndef XC_TIMER_ENABLED
#define XC_TIMER_ENABLED 0
#endif
// </e>
// <e> XC_AOTIMER_ENABLED
//==========================================================
#ifndef XC_AOTIMER_ENABLED
#define XC_AOTIMER_ENABLED 0
#endif
// </e>
// <e> XC_GPIO_ENABLED
//==========================================================
#ifndef XC_GPIO_ENABLED
#define XC_GPIO_ENABLED 1
#endif
// </e>
// <e> XC_ADC_ENABLED
//==========================================================
#ifndef XC_ADC_ENABLED
#define XC_ADC_ENABLED 1
#endif
// </e>
// <e> XC_UART_ENABLED
//==========================================================
#ifndef XC_UART_ENABLED
#define XC_UART_ENABLED 1
#endif
// </e>
// <e> XC_PWM_ENABLED
//==========================================================
#ifndef XC_PWM_ENABLED
#define XC_PWM_ENABLED 1
#endif
// </e>
// <e> XC_FMC_SPI_ENABLED
//==========================================================
#ifndef XC_FMC_SPI_ENABLED
#define XC_FMC_SPI_ENABLED 1
#endif
// </e>
// <e> XC_SPI_ENABLED
//==========================================================
#ifndef XC_SPI_ENABLED
#define XC_SPI_ENABLED 0
#endif
// </e>
// <e> XC_IIC_ENABLED
//==========================================================
#ifndef XC_IIC_ENABLED
#define XC_IIC_ENABLED 0
#endif
// </e>
// <e> XC_RTC_ENABLED
//==========================================================
#ifndef XC_RTC_ENABLED
#define XC_RTC_ENABLED 0
#endif
//==========================================================
// <q> XC_RTC_DATE_INT_ENABLED
#ifndef XC_RTC_DATE_INT_ENABLED
#define XC_RTC_DATE_INT_ENABLED 0
#endif
// </e>
// <e> XC_DMA_ENABLED
//==========================================================
#ifndef XC_DMA_ENABLED
#define XC_DMA_ENABLED 0
#endif
// </e>
// <e> XC_PGA_ENABLED
//==========================================================
#ifndef XC_PGA_ENABLED
#define XC_PGA_ENABLED 0
#endif
// </e>
// <e> XC_QDEC_ENABLED
//==========================================================
#ifndef XC_QDEC_ENABLED
#define XC_QDEC_ENABLED 0
#endif
// </e>
// <e> XC_CALIB_ENABLED
//==========================================================
#ifndef XC_CALIB_ENABLED
#define XC_CALIB_ENABLED 0
#endif
// </e>
// <<< end of configuration section >>>
#endif //SDK_DRIVER_CONFIG_H
project/example/2.4g/RF24_ADV/app/rf_config/rf_adv_config.h
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#ifndef SDK_ADV_CONFIG_H
#define SDK_ADV_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>\n
// Xinc_ADV_config
// <o> XINCX_ADV_MODE - RF Tx or Rx Mode
// <0=> TX Mode
// <1=> RX Mode
// <2=> TRX Mode
#ifndef XINCX_ADV_MODE
#define XINCX_ADV_MODE 0
#endif
// <o> XINCX_ADV_ADDR_L - rf Address Set
#ifndef XINCX_ADV_ADDR_L
#define XINCX_ADV_ADDR_L 0x71917d6b//0xe7e7e7a4//0x71917d6b
#endif
// XINCX_ADV_ADDR_H - rf Address Set
#ifndef XINCX_ADV_ADDR_H
#define XINCX_ADV_ADDR_H 0x00
#endif
// XINCX_ADV_CHANNEL - ADV Channel Set
#ifndef XINCX_ADV_CHANNEL
#define XINCX_ADV_CHANNEL 2402
#endif
// <o> XINCX_RF_POWER - rf Power Set
// <1=> -10dbm
// <2=> -9dbm
// <4=> -4dbm
// <6=> 0dbm
// <8=> 3dbm
// <9=> 5dbm
// <12=> 7dbm
// <14=> 8dbm
// <16=> 9dbm
// <19=> 10dbm
// <24=> 11dbm
// <30=> 12dbm
// <36=> 13dbm
#ifndef XINCX_POWER
#define XINCX_POWER 0x06
#endif
// <o> XINCX_RF_NVIC_MODE - RF NVIC Mode
// <0=> Disable
// <1=> Enable
#ifndef XINCX_RF_ADV_NVIC_MODE
#define XINCX_RF_ADV_NVIC_MODE 1
#endif
// XINCX_RF_TX_ADDR_WIDTH - RF Tx Addr Width
#ifndef XINCX_RF_TX_ADDR_WIDTH
#define XINCX_RF_TX_ADDR_WIDTH 4
#endif
// XINCX_RF_TRANS_RATE - RF Transmission Rate Config
#ifndef XINCX_RF_TRANS_RATE
#define XINCX_RF_TRANS_RATE 0x02
#endif
// XINCX_RF_CRC_ENABLE - RF CRC Enable
//==========================================================
#ifndef XINCX_RF_CRC_ENABLE
#define XINCX_RF_CRC_ENABLE 0
#endif
// XINCX_2_4G_CRC_BYTE - 2.4g CRC Bytes Set
#ifndef XINCX_2_4G_CRC_BYTE
#define XINCX_2_4G_CRC_BYTE 0
#endif
// XINCX_ADV_FEATURE_PARAM - ADV Feature Parameters
//==========================================================
// XINCX_ADV_LONG_PLD - ADV Long Payload Feature
#ifndef XINCX_ADV_LONG_PLD
#define XINCX_ADV_LONG_PLD 1
#endif
// XINCX_ADV_FEC - ADV FEC&Interleave Feature
#ifndef XINCX_ADV_FEC
#define XINCX_ADV_FEC 0
#endif
// XINCX_ADV_WHITEN - ADV Whiten Feature
#ifndef XINCX_ADV_WHITEN
#define XINCX_ADV_WHITEN 0
#endif
// XINCX_ADV_DPL - ADV Dynamic Payload Length Feature
#ifndef XINCX_ADV_DPL
#define XINCX_ADV_DPL 0
#endif
// XINCX_ADV_ACK_PAY - 2.4g Payload on ACK
#ifndef XINCX_ADV_ACK_PAY
#define XINCX_ADV_ACK_PAY 0
#endif
// XINCX_ADV_DYN_ACK - 2.4g W_TX_PAYLOAD_NOACK Command
#ifndef XINCX_ADV_DYN_ACK
#define XINCX_ADV_DYN_ACK 0
#endif
// XINCX_PIPE_PIPE_RX_PAYLEN - ADV Pipe Rx Payload Len
//==========================================================
// <o> XINCX_ADV_PIPE0_LEN - ADV Pipe0 Rx Payload Len
#ifndef XINCX_ADV_PIPE0_LEN
#define XINCX_ADV_PIPE0_LEN 42
#endif
// XINCX_ADV_PIPE1_LEN - ADV Pipe1 Rx Payload Len
#ifndef XINCX_ADV_PIPE1_LEN
#define XINCX_ADV_PIPE1_LEN 0
#endif
// XINCX_ADV_PIPE2_LEN - ADV Pipe2 Rx Payload Len
#ifndef XINCX_ADV_PIPE2_LEN
#define XINCX_ADV_PIPE2_LEN 0
#endif
// XINCX_ADV_PIPE3_LEN - ADV Pipe3 Rx Payload Len
#ifndef XINCX_ADV_PIPE3_LEN
#define XINCX_ADV_PIPE3_LEN 0
#endif
// XINCX_ADV_PIPE4_LEN - ADV Pipe4 Rx Payload Len
#ifndef XINCX_ADV_PIPE4_LEN
#define XINCX_ADV_PIPE4_LEN 0
#endif
// XINCX_ADV_PIPE5_LEN - ADV Pipe5 Rx Payload Len
#ifndef XINCX_ADV_PIPE5_LEN
#define XINCX_ADV_PIPE5_LEN 0
#endif
// XINC_ADV_MAC_ADDR
// <o> XINC_ADV_MAC_ADDR_0
#ifndef XINC_ADV_MAC_ADDR_0
#define XINC_ADV_MAC_ADDR_0 0xA8
#endif
// <o> XINC_ADV_MAC_ADDR_1
#ifndef XINC_ADV_MAC_ADDR_1
#define XINC_ADV_MAC_ADDR_1 0xa5
#endif
// <o> XINC_ADV_MAC_ADDR_2
#ifndef XINC_ADV_MAC_ADDR_2
#define XINC_ADV_MAC_ADDR_2 0xa4
#endif
// <o> XINC_ADV_MAC_ADDR_3
#ifndef XINC_ADV_MAC_ADDR_3
#define XINC_ADV_MAC_ADDR_3 0xa3
#endif
// <o> XINC_ADV_MAC_ADDR_4
#ifndef XINC_ADV_MAC_ADDR_4
#define XINC_ADV_MAC_ADDR_4 0xa2
#endif
// <o> XINC_ADV_MAC_ADDR_5
#ifndef XINC_ADV_MAC_ADDR_5
#define XINC_ADV_MAC_ADDR_5 0xc1
#endif
// <<< end of configuration section >>>
#endif
project/example/2.4g/RF24_ADV/app/rf_config/rf_config.h
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#ifndef SDK_CONFIG_H
#define SDK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <e> XINCX_RF_NORMAL_PEACKET_MODE - RF normal packet mode
// <i> Configure the frame format, which is a static packet format and can only communicate in one direction.
#ifndef XINCX_RF_NORMAL_PACKET_MODE
#define XINCX_RF_NORMAL_PACKET_MODE 1
#endif
// <o>XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
//==========================================================
// <0=> Xinchip
// <1=> Panchip
// <2=> Beken
// <3=> Telink
// <4=> Huntersun
#ifndef XINCX_RF_COMPATIBILITY_MODE
#define XINCX_RF_COMPATIBILITY_MODE 0
#endif
#if (XINCX_RF_NORMAL_PACKET_MODE == 1)
// XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
//==========================================================
// <o> XINCX_RF_MODE - RF Tx or Rx Mode
// <0=> TX Mode
// <1=> RX Mode
// <2=> TRX Mode
// <3=> RTX Mode
#ifndef XINCX_RF_MODE
#define XINCX_RF_MODE 0
#endif
// <o> XINCX_RF_TRANS_RATE - RF Transmission Rate Config
// <0x02=> 1M
// <0x0A=> 2M
// <0x22=> 250k
// <0x2A=> 125k
#ifndef XINCX_RF_TRANS_RATE
#define XINCX_RF_TRANS_RATE 0x02
#endif
// <o> XINCX_2_4G_CHANNEL - 2.4g Channel Set
// <2402=> RF_ADV_CHANNEL_37
// <2426=> RF_ADV_CHANNEL_38
// <2480=> RF_ADV_CHANNEL_39
#ifndef XINCX_2_4G_CHANNEL
#define XINCX_2_4G_CHANNEL 2480
#endif
// <o> XINCX_RF_TX_ADDR_WIDTH - RF Tx Addr Width
// <3=> 3 Bytes
// <4=> 4 Bytes
// <5=> 5 Bytes
#ifndef XINCX_RF_TX_ADDR_WIDTH
#define XINCX_RF_TX_ADDR_WIDTH 5
#endif
// <o> XINCX_2_4G_ADDR_L - rf Address Set
#ifndef XINCX_2_4G_ADDR_L
#define XINCX_2_4G_ADDR_L 0xe7e7e7e7 // 0xCCDDEEDD
#endif
// <o> XINCX_2_4G_ADDR_H - rf Address Set
#ifndef XINCX_2_4G_ADDR_H
#define XINCX_2_4G_ADDR_H 0xe7 // 0xAA
#endif
// <o> XINCX_RF_POWER - rf Power Set
// <1=> -10dbm
// <2=> -9dbm
// <4=> -4dbm
// <6=> 0dbm
// <8=> 3dbm
// <9=> 5dbm
// <12=> 7dbm
// <14=> 8dbm
// <16=> 9dbm
// <19=> 10dbm
// <24=> 11dbm
// <30=> 12dbm
// <36=> 13dbm
#ifndef XINCX_POWER
#define XINCX_POWER 0x00006
#endif
// <o> XINCX_RF_NVIC_MODE - RF NVIC Mode
// <0=> Disable
// <1=> Enable
#ifndef XINCX_RF_NVIC_MODE
#define XINCX_RF_NVIC_MODE 1
#endif
// XINCX_2_4G_PIPE_RX_PAYLEN - 2.4g Pipe Rx Payload Len
// <i> Payload length. Configuration of the load length during communication.
//==========================================================
// XINCX_2_4G_PIPE0_LEN - 2.4g Pipe0 Rx Payload Len
// #ifndef XINCX_2_4G_PIPE0_LEN
// #define XINCX_2_4G_PIPE0_LEN 32
// #endif
// XINCX_2_4G_PIPE1_LEN - 2.4g Pipe1 Rx Payload Len
#ifndef XINCX_2_4G_PIPE1_LEN
#define XINCX_2_4G_PIPE1_LEN 32
#endif
// XINCX_2_4G_PIPE2_LEN - 2.4g Pipe2 Rx Payload Len
#ifndef XINCX_2_4G_PIPE2_LEN
#define XINCX_2_4G_PIPE2_LEN 32
#endif
// XINCX_2_4G_PIPE3_LEN - 2.4g Pipe3 Rx Payload Len
#ifndef XINCX_2_4G_PIPE3_LEN
#define XINCX_2_4G_PIPE3_LEN 32
#endif
// XINCX_2_4G_PIPE4_LEN - 2.4g Pipe4 Rx Payload Len
#ifndef XINCX_2_4G_PIPE4_LEN
#define XINCX_2_4G_PIPE4_LEN 32
#endif
// XINCX_2_4G_PIPE5_LEN - 2.4g Pipe5 Rx Payload Len
#ifndef XINCX_2_4G_PIPE5_LEN
#define XINCX_2_4G_PIPE5_LEN 32
#endif
//
// XINCX_RF_CRC_ENABLE - RF CRC Enable
//==========================================================
#ifndef XINCX_RF_CRC_ENABLE
#define XINCX_RF_CRC_ENABLE 1
#endif
// <o> XINCX_2_4G_CRC_BYTE - 2.4g CRC Bytes Set
// <0=> 0 Byte
// <1=> 1 Byte
// <2=> 2 Bytes
#ifndef XINCX_2_4G_CRC_BYTE
#define XINCX_2_4G_CRC_BYTE 2
#endif
// XINCX_2_4G_FEATURE_PARAM - 2.4g Feature Parameters
//==========================================================
// XINCX_2_4G_GUARD_CFG - 2.4g Long Payload Feature
#ifndef XINCX_2_4G_GUARD_CFG
#define XINCX_2_4G_GUARD_CFG 0
#endif
// XINCX_2_4G_LONG_PLD_TYPE - 2.4g Long Pld Type
#ifndef XINCX_2_4G_LONG_PLD_TYPE
#define XINCX_2_4G_LONG_PLD_TYPE 0
#endif
// XINCX_2_4G_PREAMBLE_NUM - 2.4g Preamble
#ifndef XINCX_2_4G_PREAMBLE_NUM
#define XINCX_2_4G_PREAMBLE_NUM 0
#endif
// XINCX_2_4G_PREAMBLE_TYPE - 2.4g Preamble Type
#ifndef XINCX_2_4G_PREAMBLE_TYPE
#define XINCX_2_4G_PREAMBLE_TYPE 0
#endif
// XINCX_2_4G_CRC_SCOPE_GUARD - 2.4g CRC Scope Guard
#ifndef XINCX_2_4G_CRC_SCOPE_GUARD
#define XINCX_2_4G_CRC_SCOPE_GUARD 0
#endif
// XINCX_2_4G_CRC_SCOPE_HEADER - 2.4g CRC Scope Header
#ifndef XINCX_2_4G_CRC_SCOPE_HEADER
#define XINCX_2_4G_CRC_SCOPE_HEADER 1
#endif
// XINCX_2_4G_CRC_SCOPE_ADDR - 2.4g CRC Scope Addr
#ifndef XINCX_2_4G_CRC_SCOPE_ADDR
#define XINCX_2_4G_CRC_SCOPE_ADDR 1
#endif
// <q> XINCX_2_4G_LONG_PLD - 2.4g Long Payload Feature
#ifndef XINCX_2_4G_LONG_PLD
#define XINCX_2_4G_LONG_PLD 0
#endif
// <q> XINCX_2_4G_FEC - 2.4g FEC&Interleave Feature
#ifndef XINCX_2_4G_FEC
#define XINCX_2_4G_FEC 0
#endif
// <q> XINCX_2_4G_WHITEN - 2.4g Whiten Feature
#ifndef XINCX_2_4G_WHITEN
#define XINCX_2_4G_WHITEN 0
#endif
// XINCX_2_4G_DPL - 2.4g Dynamic Payload Length Feature
#ifndef XINCX_2_4G_DPL
#define XINCX_2_4G_DPL 0
#endif
// XINCX_2_4G_ACK_PAY - 2.4g Payload on ACK
#ifndef XINCX_2_4G_ACK_PAY
#define XINCX_2_4G_ACK_PAY 0
#endif
// XINCX_2_4G_DYN_ACK - 2.4g W_TX_PAYLOAD_NOACK Command
#ifndef XINCX_2_4G_DYN_ACK
#define XINCX_2_4G_DYN_ACK 0
#endif
//
// XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
//==========================================================
// XINCX_2_4G_RETRANS_CNT - 2.4g Retransmit Count
// <i> Number of retransmissions. The maximum number of times a hardware can automatically transmit an ACK if it does
// not receive the correct ACK.
#ifndef XINCX_2_4G_RETRANS_CNT
#define XINCX_2_4G_RETRANS_CNT 0
#endif
// XINCX_2_4G_RETRANS_DELAY - 2.4g Retransmission Delay
// <i> Retransmission delay. For 32 bytes of data, the minimum configuration is 500 us for 1 Mbit/s and 1500 us for 250
// kbit/s.
#ifndef XINCX_2_4G_RETRANS_DELAY
#define XINCX_2_4G_RETRANS_DELAY 0
#endif
// XINCX_2_4G_DYNPD - 2.4g dynpd
#ifndef XINCX_2_4G_DYNPD
#define XINCX_2_4G_DYNPD 0x00
#endif
// XINCX_2_4G_AUTO_ACK - 2.4g Auto Acknowledgement
//==========================================================
// XINCX_2_4G_PIPE0_ENAA - 2.4g Pipe0 Auto Ack
#ifndef XINCX_2_4G_PIPE0_ENAA
#define XINCX_2_4G_PIPE0_ENAA 0
#endif
// XINCX_2_4G_PIPE1_ENAA - 2.4g Pipe1 Auto Ack
#ifndef XINCX_2_4G_PIPE1_ENAA
#define XINCX_2_4G_PIPE1_ENAA 0
#endif
// XINCX_2_4G_PIPE2_ENAA - 2.4g Pipe2 Auto Ack
#ifndef XINCX_2_4G_PIPE2_ENAA
#define XINCX_2_4G_PIPE2_ENAA 0
#endif
// XINCX_2_4G_PIPE3_ENAA - 2.4g Pipe3 Auto Ack
#ifndef XINCX_2_4G_PIPE3_ENAA
#define XINCX_2_4G_PIPE3_ENAA 0
#endif
// XINCX_2_4G_PIPE4_ENAA - 2.4g Pipe4 Auto Ack
#ifndef XINCX_2_4G_PIPE4_ENAA
#define XINCX_2_4G_PIPE4_ENAA 0
#endif
// XINCX_2_4G_PIPE5_ENAA - 2.4g Pipe5 Auto Ack
#ifndef XINCX_2_4G_PIPE5_ENAA
#define XINCX_2_4G_PIPE5_ENAA 0
#endif
// XINCX_RF_PIPE_ENABLE
#ifndef XINCX_RF_PIPE_ENABLE
#define XINCX_RF_PIPE_ENABLE 0
#endif
#endif
// </e> //XINCX_RF_PEACKET_MODE normal normal
// <e> XINCX_RF_EMHAMCED_PEACKET_MODE - RF enhanced packet mode
// <i> Configure the frame format, which is a dynamic packet configuration, which can communicate in both directions,and
// <i> ACK can dynamically carry data.
#ifndef XINCX_RF_EMHAMCED_PACKET_MODE
#define XINCX_RF_EMHAMCED_PACKET_MODE 0
#endif
#if (XINCX_RF_EMHAMCED_PACKET_MODE == 1)
// XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
//==========================================================
// <o> XINCX_RF_MODE - RF Tx or Rx Mode
// <0=> TX Mode
// <1=> RX Mode
#ifndef XINCX_RF_MODE
#define XINCX_RF_MODE 0
#endif
// <o> XINCX_RF_TRANS_RATE - RF Transmission Rate Config
// <0x02=> 1M
// <0x0A=> 2M
// <0x22=> 250k
// <0x2A=> 125k
#ifndef XINCX_RF_TRANS_RATE
#define XINCX_RF_TRANS_RATE 0x02
#endif
// <o> XINCX_2_4G_CHANNEL - 2.4g Channel Set
#ifndef XINCX_2_4G_CHANNEL
#define XINCX_2_4G_CHANNEL 2440
#endif
// <o> XINCX_RF_TX_ADDR_WIDTH - RF Tx Addr Width
// <3=> 3 Bytes
// <4=> 4 Bytes
// <5=> 5 Bytes
#ifndef XINCX_RF_TX_ADDR_WIDTH
#define XINCX_RF_TX_ADDR_WIDTH 5
#endif
// <o> XINCX_2_4G_ADDR_L - rf Address Set
#ifndef XINCX_2_4G_ADDR_L
#define XINCX_2_4G_ADDR_L 0xe7e7e7e7
#endif
// <o> XINCX_2_4G_ADDR_H - rf Address Set
#ifndef XINCX_2_4G_ADDR_H
#define XINCX_2_4G_ADDR_H 0xe7
#endif
// <o> XINCX_RF_POWER - rf Power Set
// <1=> -10dbm
// <2=> -9dbm
// <4=> -4dbm
// <6=> 0dbm
// <8=> 3dbm
// <9=> 5dbm
// <12=> 7dbm
// <14=> 8dbm
// <16=> 9dbm
// <19=> 10dbm
// <24=> 11dbm
// <30=> 12dbm
// <36=> 13dbm
#ifndef XINCX_POWER
#define XINCX_POWER 0x00006
#endif
// <o> XINCX_RF_NVIC_MODE - RF NVIC Mode
// <0=> Disable
// <1=> Enable
#ifndef XINCX_RF_NVIC_MODE
#define XINCX_RF_NVIC_MODE 1
#endif
// XINCX_2_4G_PIPE_RX_PAYLEN - 2.4g Pipe Rx Payload Len
// <i> Payload length. Configuration of the load length during communication.
//==========================================================
// XINCX_2_4G_PIPE0_LEN - 2.4g Pipe0 Rx Payload Len
// #ifndef XINCX_2_4G_PIPE0_LEN
// #define XINCX_2_4G_PIPE0_LEN 32
// #endif
// XINCX_2_4G_PIPE1_LEN - 2.4g Pipe1 Rx Payload Len
#ifndef XINCX_2_4G_PIPE1_LEN
#define XINCX_2_4G_PIPE1_LEN 32
#endif
// XINCX_2_4G_PIPE2_LEN - 2.4g Pipe2 Rx Payload Len
#ifndef XINCX_2_4G_PIPE2_LEN
#define XINCX_2_4G_PIPE2_LEN 32
#endif
// XINCX_2_4G_PIPE3_LEN - 2.4g Pipe3 Rx Payload Len
#ifndef XINCX_2_4G_PIPE3_LEN
#define XINCX_2_4G_PIPE3_LEN 32
#endif
// XINCX_2_4G_PIPE4_LEN - 2.4g Pipe4 Rx Payload Len
#ifndef XINCX_2_4G_PIPE4_LEN
#define XINCX_2_4G_PIPE4_LEN 32
#endif
// XINCX_2_4G_PIPE5_LEN - 2.4g Pipe5 Rx Payload Len
#ifndef XINCX_2_4G_PIPE5_LEN
#define XINCX_2_4G_PIPE5_LEN 32
#endif
// XINCX_RF_CRC_ENABLE - RF CRC Enable
//==========================================================
#ifndef XINCX_RF_CRC_ENABLE
#define XINCX_RF_CRC_ENABLE 1
#endif
// <o> XINCX_2_4G_CRC_BYTE - 2.4g CRC Bytes Set
// <0=> 0 Byte
// <1=> 1 Byte
// <2=> 2 Bytes
#ifndef XINCX_2_4G_CRC_BYTE
#define XINCX_2_4G_CRC_BYTE 2
#endif
// XINCX_2_4G_FEATURE_PARAM - 2.4g Feature Parameters
//==========================================================
// XINCX_2_4G_GUARD_CFG - 2.4g Long Payload Feature
#ifndef XINCX_2_4G_GUARD_CFG
#define XINCX_2_4G_GUARD_CFG 0
#endif
// XINCX_2_4G_LONG_PLD_TYPE - 2.4g Long Pld Type
#ifndef XINCX_2_4G_LONG_PLD_TYPE
#define XINCX_2_4G_LONG_PLD_TYPE 0
#endif
// XINCX_2_4G_PREAMBLE_NUM - 2.4g Preamble
#ifndef XINCX_2_4G_PREAMBLE_NUM
#define XINCX_2_4G_PREAMBLE_NUM 0
#endif
// XINCX_2_4G_PREAMBLE_TYPE - 2.4g Preamble Type
#ifndef XINCX_2_4G_PREAMBLE_TYPE
#define XINCX_2_4G_PREAMBLE_TYPE 0
#endif
// XINCX_2_4G_CRC_SCOPE_GUARD - 2.4g CRC Scope Guard
#ifndef XINCX_2_4G_CRC_SCOPE_GUARD
#define XINCX_2_4G_CRC_SCOPE_GUARD 0
#endif
// XINCX_2_4G_CRC_SCOPE_HEADER - 2.4g CRC Scope Header
#ifndef XINCX_2_4G_CRC_SCOPE_HEADER
#define XINCX_2_4G_CRC_SCOPE_HEADER 1
#endif
// XINCX_2_4G_CRC_SCOPE_ADDR - 2.4g CRC Scope Addr
#ifndef XINCX_2_4G_CRC_SCOPE_ADDR
#define XINCX_2_4G_CRC_SCOPE_ADDR 1
#endif
// <q> XINCX_2_4G_LONG_PLD - 2.4g Long Payload Feature
#ifndef XINCX_2_4G_LONG_PLD
#define XINCX_2_4G_LONG_PLD 1
#endif
// <q> XINCX_2_4G_FEC - 2.4g FEC&Interleave Feature
#ifndef XINCX_2_4G_FEC
#define XINCX_2_4G_FEC 1
#endif
// <q> XINCX_2_4G_WHITEN - 2.4g Whiten Feature
#ifndef XINCX_2_4G_WHITEN
#define XINCX_2_4G_WHITEN 1
#endif
// XINCX_2_4G_DPL - 2.4g Dynamic Payload Length Feature
#ifndef XINCX_2_4G_DPL
#define XINCX_2_4G_DPL 1
#endif
// XINCX_2_4G_ACK_PAY - 2.4g Payload on ACK
#ifndef XINCX_2_4G_ACK_PAY
#define XINCX_2_4G_ACK_PAY 1
#endif
// XINCX_2_4G_DYN_ACK - 2.4g W_TX_PAYLOAD_NOACK Command
#ifndef XINCX_2_4G_DYN_ACK
#define XINCX_2_4G_DYN_ACK 1
#endif
// XINCX_2_4G_DYNPD - 2.4g dynpd
#ifndef XINCX_2_4G_DYNPD
#define XINCX_2_4G_DYNPD 0x3f
#endif
// XINCX_2_4G_AUTO_ACK - 2.4g Auto Acknowledgement
//==========================================================
// XINCX_2_4G_PIPE0_ENAA - 2.4g Pipe0 Auto Ack
#ifndef XINCX_2_4G_PIPE0_ENAA
#define XINCX_2_4G_PIPE0_ENAA 1
#endif
// XINCX_2_4G_PIPE1_ENAA - 2.4g Pipe1 Auto Ack
#ifndef XINCX_2_4G_PIPE1_ENAA
#define XINCX_2_4G_PIPE1_ENAA 1
#endif
// XINCX_2_4G_PIPE2_ENAA - 2.4g Pipe2 Auto Ack
#ifndef XINCX_2_4G_PIPE2_ENAA
#define XINCX_2_4G_PIPE2_ENAA 1
#endif
// XINCX_2_4G_PIPE3_ENAA - 2.4g Pipe3 Auto Ack
#ifndef XINCX_2_4G_PIPE3_ENAA
#define XINCX_2_4G_PIPE3_ENAA 1
#endif
// XINCX_2_4G_PIPE4_ENAA - 2.4g Pipe4 Auto Ack
#ifndef XINCX_2_4G_PIPE4_ENAA
#define XINCX_2_4G_PIPE4_ENAA 1
#endif
// XINCX_2_4G_PIPE5_ENAA - 2.4g Pipe5 Auto Ack
#ifndef XINCX_2_4G_PIPE5_ENAA
#define XINCX_2_4G_PIPE5_ENAA 1
#endif
// <o.0..5> XINCX_RF_PIPE_ENABLE
#ifndef XINCX_RF_PIPE_ENABLE
#define XINCX_RF_PIPE_ENABLE 1
#endif
// XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
//==========================================================
// <o> XINCX_2_4G_RETRANS_CNT - 2.4g Retransmit Count
// <i> Number of retransmissions. The maximum number of times a hardware can automatically transmit an ACK if it does
// not receive the correct ACK.
// <0=> No retransmission
// <1=> 1 time
// <2=> 2 times
// <3=> 3 times
// <4=> 4 times
// <5=> 5 times
// <6=> 6 times
// <7=> 7 times
// <8=> 8 times
// <9=> 9 times
// <10=> 10 times
// <11=> 11 times
// <12=> 12 times
// <13=> 13 times
// <14=> 14 times
// <15=> 15 times
#ifndef XINCX_2_4G_RETRANS_CNT
#define XINCX_2_4G_RETRANS_CNT 0
#endif
// <o> XINCX_2_4G_RETRANS_DELAY - 2.4g Retransmission Delay
// <i> Retransmission delay. For 32 bytes of data, the minimum configuration is 500 us for 1 Mbit/s and 1500 us for 250
// kbit/s.
// <0=> 250us
// <1=> 500us
// <2=> 750us
// <3=> 1000us
// <4=> 1250us
// <5=> 1500us
// <6=> 1750us
// <7=> 2000us
// <8=> 2250us
// <9=> 2500us
// <10=> 2750us
// <11=> 3000us
// <12=> 3250us
// <13=> 3500us
// <14=> 3750us
// <15=> 4000us
#ifndef XINCX_2_4G_RETRANS_DELAY
#define XINCX_2_4G_RETRANS_DELAY 3
#endif
#endif
// </e> //XINCX_RF_PEACKET_MODE enhanced normal
// RF 2.4g Compatibility configuration
//==========================================================
// Compatibility configuration, when you need to be compatible with other RF chips, you don't need to configure this
// option when using our company's chips.
// XINCX_2_4G_PREAMBLE - 2.4g preamble
#ifndef XINCX_2_4G_PREAMBLE
#define XINCX_2_4G_PREAMBLE 0x710f5555
#endif
// XINCX_2_4G_GUARD - 2.4g guard
#ifndef XINCX_2_4G_GUARD
#define XINCX_2_4G_GUARD 0x8fc9
#endif
//
// XINCX_2_4G_CRY_CPT_ARRAY - 2.4g Crystal capacitor array
//==========================================================
// Crystal capacitor array, adjust to modify the frequency offset of the crystal oscillator.
// XINCX_2_4G_CRY_CPT_ARRAY - 2.4g Crystal capacitor array
#ifndef XINCX_2_4G_CRY_CPT_ARRAY
#ifdef XC62XX
#define XINCX_2_4G_CRY_CPT_ARRAY 0x38
#else
#define XINCX_2_4G_CRY_CPT_ARRAY 0x36
#endif
#endif
//
// <<< end of configuration section >>>
#endif // SDK_CONFIG_H
project/example/2.4g/RF24_ADV/app/src/app_64m.c
+99
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@@ -0,0 +1,99 @@
#include "app_64m.h"
void use_64m_crtstal_init(void)
{
testpin_64M_config();
xc_pwr_pwrkey_init();
Init_rtc_gpio(4, 0x00);
}
__RAM_CODE void rf_64M_set_rx_channel(uint16_t channel)
{
channel -= 1;
uint16_t ch = channel % 2;
XC_RF_2_4G->RF_CH &= ~(0x3fff);
switch (ch) {
case 0:
XC_RF_2_4G->RF_CH |= (channel / 2);
*((uint32_t volatile *)0x53022064) = (((channel / 2) << 16));
break;
case 1:
XC_RF_2_4G->RF_CH |= (channel / 2);
*((uint32_t volatile *)0x53022064) = (((channel / 2) << 16) | 0x80008000);
break;
default:
break;
}
(*(volatile unsigned int *)(0x53023010)) &= ~((1 << 24) | (2 << 28));
}
__RAM_CODE void rf_64M_set_tx_channel(uint16_t channel)
{
uint16_t ch = channel % 2;
XC_RF_2_4G->RF_CH &= ~(0x3fff);
switch (ch) {
case 0:
XC_RF_2_4G->RF_CH |= (channel / 2);
*((uint32_t volatile *)0x53022064) = (((channel / 2) << 16));
break;
case 1:
XC_RF_2_4G->RF_CH |= (channel / 2 + 1);
*((uint32_t volatile *)0x53022064) = (((channel / 2) << 16) | 0x80008000);
break;
default:
break;
}
(*(volatile unsigned int *)(0x53023010)) |= ((0x3 << 16) | (1 << 24) | (2 << 28));
}
void testpin_64M_config(void)
{
uint32_t val;
val = (*(volatile unsigned int *)(0x53022040));
val |= (0x7 << 4) | (0x7);
(*(volatile unsigned int *)(0x53022040)) = val; // TPORT_DATA0_SEL set
val = (*(volatile unsigned int *)(0x40000134));
(*(volatile unsigned int *)(0x40000134)) = ((val & ~(0xfu << 28)) | (1u << 28)); // testpin1_ctrl[3:0]=1
// printf("after 0x40000134=0x%x, 0x40000134=0x%x\n", *(volatile unsigned int *)(0x40000134),
// *(volatile unsigned int *)(0x40000134));
val = (*(volatile unsigned int *)(0x53023010));
val &= ~(3 << 28);
#if 1 // diag = 0xc //diag = 0x3
val |= (0x3 << 20) | (0x3 << 16 | 1 << 24 | 2 << 28); // 0xc
(*(volatile unsigned int *)(0x53023010)) = val; // diag_sel[3:0] set
#endif
// LOGI("after 0x53022040=0x%x, 0x53022010=0x%x\n", *(volatile unsigned int *)(0x53022040),
//*(volatile unsigned int *)(0x53023010));
uint32_t addr_val = 0;
xc_gpio_fun_sel(GPIO_4, GPIO_Dx);
xc_gpio_mux_ctl(GPIO_4, GPIO_Mux3); // en test_pin[1]
addr_val = 0x40000174;
*((uint32_t volatile *)addr_val) = 7;
}
void Init_rtc_gpio(uint32_t num, uint8_t inter_mode)
{
uint32_t val;
// if(!((inter_mode>=0x08) &&(inter_mode<=0x0c))) return;
__write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL, 0x20002);
__write_hw_reg32(CPR_AOCLKEN_GRCTL, 0x20002);
__read_hw_reg32(AO_GPIO_MODE, val);
val &= ~(0x0f << (num << 2));
val |= (inter_mode << (num << 2));
__write_hw_reg32(AO_GPIO_MODE, val);
__read_hw_reg32(AO_GPIO_CTL, val);
val |= (1 << (8 + num));
__write_hw_reg32(AO_GPIO_CTL, val);
// rtc_ao_gpio_mode__aogpio_debounce_en3__setf(1);
NVIC_EnableIRQ(RTC_IRQn);
}
project/example/2.4g/RF24_ADV/app/src/main.c
+411
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@@ -0,0 +1,411 @@
/*!
* \file main.c
*
* \brief Target main implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Howl-C
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "main.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
#define BLE_ADV_LEN 42
/*------------------------------------------------------------------------------------
Static Variables
-------------------------------------------------------------------------------------*/
static uint8_t rx_buf[256] = {0};
static uint16_t rx_len = 0;
static bool rf24g_rx_irq_flag = false;
static bool rf24g_tx_irq_flag = false;
/*------------------------------------------------------------------------------------
Func Prototype
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
/**
****************************************************************************************
* @brief Clock Initialization
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void clock_init(void)
{
CLOCK_InitCfg_t clock_cfg;
clock_cfg.hfclk_src = CLOCK_HFCLK_SRC_XTAL;
clock_cfg.hfclk_in = CLOCK_HFCLK_IN_32M;
#if (RC_32K)
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_RC;
#endif //(RC_32K)
#if (XTAL_32K)
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL;
#endif // (XTAL_32K)
#if (XTAL_32768K)
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL;
#endif // (XTAL_32768K)
#ifdef XC62XX
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_RC;
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32K;
#else
if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_XTAL) {
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32768;
} else if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_RC) {
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32K;
}
#endif
xc_clock_init_cfg(&clock_cfg);
SysTick_Config(xc_clock_hfclk_in_get() / 100);
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
}
#ifdef DEBUG_LOG
/**
* @brief RF 2.4g register information printing
* @param void
* @retval void
*/
void rf_2M_reg_info(void)
{
/* Register information printing */
LOGI("CFG_TOP: 0x%08x\r\n", XC_RF_2_4G->CFG_TOP);
LOGI("TXPROC_CFG: 0x%08x\r\n", XC_RF_2_4G->TXPROC_CFG);
LOGI("RXPROC_CFG_L: 0x%08x\r\n", XC_RF_2_4G->RXPROC_CFG_L);
LOGI("RF_CH: 0x%08x\r\n", XC_RF_2_4G->RF_CH);
LOGI("rccal_reg_l: 0x%08x\r\n", XC_BT_RF->rccal_reg_l);
LOGI("ana2_reg_l: 0x%08x\r\n", XC_BT_RF->ana2_reg_l);
LOGI("ana3_reg_l: 0x%08x\r\n", XC_BT_RF->ana3_reg_l);
LOGI("ana4_reg_l: 0x%08x\r\n", XC_BT_RF->ana4_reg_l);
LOGI("ana5_reg_l: 0x%08x\r\n", XC_BT_RF->ana5_reg_l);
LOGI("ana14_reg_l: 0x%08x\r\n", XC_BT_RF->ana14_reg_l);
LOGI("ana15_reg_l: 0x%08x\r\n", XC_BT_RF->ana15_reg_l);
LOGI("ana16_reg_l: 0x%08x\r\n", XC_BT_RF->ana16_reg_l);
LOGI("ana17_reg_l: 0x%08x\r\n", XC_BT_RF->ana17_reg_l);
LOGI("ana18_reg_l: 0x%08x\r\n", XC_BT_RF->ana18_reg_l);
LOGI("ana21_reg_l: 0x%08x\r\n", XC_BT_RF->ana21_reg_l);
LOGI("AON_RF_AONREG: 0x%08x\r\n", cprao_aon_rf_aonreg_get()); // 0x36
}
/**
* @brief Rf 2.4g dump log
* @param void
*
* @retval void
*/
void rf_dump_log(void)
{
LOGI("***************** 2.4G Param ******************\n");
LOGI("CFG_TOP: 0x%08x\r\n", XC_RF_2_4G->CFG_TOP);
LOGI("EN_AA: 0x%08x\r\n", XC_RF_2_4G->EN_AA);
LOGI("EN_RXADDR: 0x%08x\r\n", XC_RF_2_4G->EN_RXADDR);
LOGI("SETUP_AW: 0x%08x\r\n", XC_RF_2_4G->SETUP_AW);
LOGI("SETUP_RETR: 0x%08x\r\n", XC_RF_2_4G->SETUP_RETR);
LOGI("RF_CH: 0x%08x\r\n", XC_RF_2_4G->RF_CH);
LOGI("SETUP_RF: 0x%08x\r\n", XC_RF_2_4G->SETUP_RF);
LOGI("STATUS: 0x%08x\r\n", XC_RF_2_4G->STATUS);
LOGI("OBSERVE_TX: 0x%08x\r\n", XC_RF_2_4G->OBSERVE_TX);
LOGI("RSSI: 0x%08x\r\n", XC_RF_2_4G->RSSI);
LOGI("RX_ADDR_P0: 0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RX_ADDR_P0_H), XC_RF_2_4G->RX_ADDR_P0_L);
LOGI("RX_ADDR_P1: 0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RX_ADDR_P1_H), XC_RF_2_4G->RX_ADDR_P1_L);
LOGI("RX_ADDR_P2TOP5:0x%08x\r\n", XC_RF_2_4G->RX_ADDR_P2TOP5);
LOGI("BER_RESULT: 0x%08x%08x\r\n", XC_RF_2_4G->BER_ERR_CNT, XC_RF_2_4G->BER_RECV_CNT);
LOGI("AGC_SETTING: 0x%08x\r\n", XC_RF_2_4G->AGC_SETTING);
LOGI("PGA_SETTING: 0x%02x %08x\r\n", ((XC_RF_2_4G->TX_ADDR_H) & 0xFF00) >> 8, XC_RF_2_4G->PGA_SETTING);
LOGI("TX_ADDR: 0x%02x %08x\r\n", ((XC_RF_2_4G->TX_ADDR_H) & 0xFF), XC_RF_2_4G->TX_ADDR_L);
LOGI("RX_PW_PX: 0x%04x %08x\r\n", 0xFFFF & (XC_RF_2_4G->RX_PW_Px_H), XC_RF_2_4G->RX_PW_Px_L);
LOGI("STATUS_FIFO: 0x%08x\r\n", XC_RF_2_4G->STATUS_FIFO);
LOGI("RSSIREC: 0x%08x\r\n", XC_RF_2_4G->RSSIREC);
LOGI("TXPROC_CFG: 0x%08x\r\n", XC_RF_2_4G->TXPROC_CFG);
LOGI("RXPROC_CFG: 0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RXPROC_CFG_H), XC_RF_2_4G->RXPROC_CFG_L);
LOGI("DYNPD: 0x%08x\r\n", XC_RF_2_4G->DYNPD);
LOGI("FEATURE: 0x%08x\r\n", XC_RF_2_4G->FEATURE);
LOGI("PGA_SETTING_H: 0x%08x\r\n", XC_RF_2_4G->TX_ADDR_H);
#ifdef XC62XX
LOGI("HW_CONFIG: 0x%08x\r\n", XC_RF_2_4G->HW_CONFIG);
LOGI("PBT_CONFIG: 0x%08x\r\n", XC_RF_2_4G->PBT_CONFIG);
LOGI("PBT_TIMER: 0x%08x\r\n", XC_RF_2_4G->PBT_TIMER);
LOGI("PBT_SYNC_TIME: 0x%08x\r\n", XC_RF_2_4G->PBT_SYNC_TIME);
LOGI("PBT_TX_HEAD: 0x%08x\r\n", XC_RF_2_4G->PBT_TX_HEAD);
LOGI("PBT_RX_HEAD: 0x%08x\r\n", XC_RF_2_4G->PBT_RX_HEAD);
LOGI("PBT_AUTO_TRX_TIME: 0x%08x\r\n", XC_RF_2_4G->PBT_AUTO_TRX_TIME);
#endif
LOGI("TX_POWER 0x%08x\r\n", (XC_BT_RF->ana21_reg_l >> 6) & 0x3f);
LOGI("ana11_reg_l: 0x%08x\r\n", XC_BT_RF->ana11_reg_l);
LOGI("***********************************************\n");
LOGI("\r\n");
}
#endif // DEBUG_LOG
/**
* @brief RF 2.4g buff info
* @param uint8_t * - buff
* uint8_t len
* @retval void
*/
void rf_buff_info(uint8_t *buff, uint16_t len)
{
for (uint16_t i = 0; i < len; i++)
LOGI("%02x ", buff[i]);
LOGI("\r\n");
}
void app_uart_init(void)
{
GPIO_InitCfg_t gpio_cfg = {0};
gpio_cfg.Mux = GPIO_Mux0;
gpio_cfg.Pull = GPIO_PULLUP;
gpio_cfg.Int = NOT_INT;
gpio_cfg.FunSel = UART0_TX;
gpio_cfg.Pin = GPIO_18;
gpio_cfg.Dir = GPIO_DIR_OUTPUT;
xc_gpio_init(&gpio_cfg);
gpio_cfg.FunSel = UART0_RX;
gpio_cfg.Pin = GPIO_19;
gpio_cfg.Dir = GPIO_DIR_INPUT;
xc_gpio_init(&gpio_cfg);
UART_InitCfg_t uart_cfg = {0};
uart_cfg.Parity = UART_PARITY_DISABLE;
uart_cfg.StopBits = UART_STOP_1_BITS;
uart_cfg.WordLength = UART_DATA_8_BITS;
uart_cfg.BaudRate = UART_BAUDRATE_115200;
uart_cfg.HardwareFlowControl = UART_HWFC_DISABLE;
xc_uart_init(UART0_IDX, &uart_cfg);
}
/* switch mode and set channel */
void rf_switch_mode(uint8_t mode, uint16_t channel)
{
CE_CTL_LOW;
switch (mode) {
case TX_MODE:
case RX_MODE:
break;
default:
LOGI("The mode is set incorrectly\n");
while(1);
}
set_rf_mode(mode);
rf_set_channel(channel);
#ifdef XC62XX
XC_RF_2_4G->STATUS = ((XC_RF_2_4G->CFG_TOP >> 30) & 0x3 << 7) | ((XC_RF_2_4G->CFG_TOP >> 4) & 0x7 << 4);
#else
XC_RF_2_4G->STATUS = MASK_ALL_INTER;
#endif
rf_wr_cmd(FLUSH_RX);
rf_wr_cmd(FLUSH_TX);
if (mode) {
CE_CTL_HIGH;
}
}
/* RF发送完成回调 */
void rf_24g_tx_ds_cb(void)
{
/* set flag */
rf24g_tx_irq_flag = true;
}
/* RF接收完成回调 */
void rf_24g_rx_dr_cb(void)
{
/* stop RF */
CE_CTL_LOW;
/* set flag */
rf24g_rx_irq_flag = true;
/* recv data */
rx_len = rf_rx_packet(rx_buf);
/* start RF */
CE_CTL_HIGH;
}
uint8_t rf24g_adv_packet_generate(uint8_t *buff)
{
uint8_t l = 0;
uint8_t rf_adv_data_complete_name[26] = {"RF-ADV-TEST-123456789BLE52"};
/* hearder */
buff[l++] = 0x42;
buff[l++] = 37;
/* BLE MAC address */
buff[l++] = MAC_ADDR_0;
buff[l++] = MAC_ADDR_1;
buff[l++] = MAC_ADDR_2;
buff[l++] = MAC_ADDR_3;
buff[l++] = MAC_ADDR_4;
buff[l++] = MAC_ADDR_5;
/* Flags */
buff[l++] = 0x02;
buff[l++] = 0x01;
buff[l++] = 0x06;
/* Complete Local Name */
buff[l++] = 27;
buff[l++] = 0x09;
memcpy(&buff[l], rf_adv_data_complete_name, sizeof(rf_adv_data_complete_name));
l += sizeof(rf_adv_data_complete_name);
/* CRC */
buff[l++] = 0x55;
buff[l++] = 0x55;
buff[l++] = 0x55;
return l;
}
void rf24g_adv_tx_demo()
{
uint32_t tx_cnt = 0;
uint16_t adv_len = 0;
uint8_t adv_buff[BLE_ADV_LEN];
uint16_t adv_channel = XINCX_2_4G_CHANNEL;
/* Set the communication mode */
rf_switch_mode( TX_MODE, adv_channel);
/* genrate adv data */
adv_len = rf24g_adv_packet_generate(adv_buff);
/* CRC */
ble_crc(adv_buff, adv_len - 3, adv_buff + adv_len - 3);
/* whitening */
ble_whiten(adv_buff, adv_len, bleWhitenStart(adv_channel));
LOGI("************ADV Send Start**************\r\n");
/* main loop */
while(true)
{
/* Send data */
rf_tx_packet(adv_buff, adv_len);
tx_cnt += 1;
LOGI("tx_cnt:%d\n", tx_cnt);
delay_ms(10);
}
}
void rf24g_adv_rx_demo()
{
uint32_t rx_cnt = 0;
uint8_t adv_len = 0;
uint16_t adv_channel = XINCX_2_4G_CHANNEL;
uint32_t blecrc = 0;
uint8_t rf_adv_crc_stat = CRC_IDLE;
LOGI("************ADV Recv Start**************\r\n");
/* Set the communication mode */
rf_switch_mode( RX_MODE, adv_channel);
/* main loop */
while(true)
{
if (rf24g_rx_irq_flag)
{
rf24g_rx_irq_flag = false;
/* Whitening of packet software */
blecrc = rf_adv_unpacket( rx_buf, rx_len, &adv_len);
/* Packet software CRC judgment */
rf_adv_crc_stat = rf_adv_crc( rx_buf, &adv_len, blecrc);
if (rf_adv_crc_stat == CRC_OK)
{
//rf_buff_info( rx_buf, rx_len);
rx_cnt += 1;
LOGI("rx_cnt:%d,len:%d\n", rx_cnt, adv_len);
rf_adv_crc_stat = CRC_IDLE;
}
}
}
}
int main(void)
{
/* Clock initialization */
clock_init();
/* Serial port initialization */
app_uart_init();
/* Simulate broadcast initialization */
rf24g_adv_init();
#if (XINCX_RF_NVIC_MODE)
/* Enable RF2.4G interrupts */
NVIC_EnableIRQ(RF24G_IRQn);
/* Configure the RF2.4G interrupt priority */
NVIC_SetPriority(RF24G_IRQn, 0);
#endif // XINCX_RF_NVIC_MODE
xc_system_param_check_rf24g();
#if XINCX_RF_MODE == TX_MODE
rf24g_adv_tx_demo();
#elif XINCX_RF_MODE == RX_MODE
rf24g_adv_rx_demo();
#endif
while(true);
}
project/example/2.4g/RF24_ADV/app/src/rf_compatible_normal.c
+193
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@@ -0,0 +1,193 @@
#include "rf_compatible_normal.h"
uint16_t crc = 0;
uint8_t panchip_data_length = XINCX_2_4G_PIPE0_LEN - XINCX_2_4G_CRC_BYTE;
uint16_t rf_addr_crc = 0;
uint8_t panchip_addr_whiten;
uint8_t addr_buff[5] = {0};
uint32_t send_cnt = 0;
uint32_t recv_cnt = 0;
/**
* @brief Rf 2.4g get addr
* @param uint8_t *addr_buff
*
* @retval void
*/
void rf_addr_map(uint8_t *addr_buff)
{
uint8_t addr_xsb = (XC_RF_2_4G->CFG_TOP >> 11) & (0x1);
LOGI("addr_xsb %02x\r\n", addr_xsb);
if (!addr_xsb) {
addr_buff[0] = (XC_RF_2_4G->TX_ADDR_L >> 0) & 0xff;
addr_buff[1] = (XC_RF_2_4G->TX_ADDR_L >> 8) & 0xff;
addr_buff[2] = (XC_RF_2_4G->TX_ADDR_L >> 16) & 0xff;
addr_buff[3] = (XC_RF_2_4G->TX_ADDR_L >> 24) & 0xff;
addr_buff[4] = (XC_RF_2_4G->TX_ADDR_H >> 0) & 0xff;
} else {
addr_buff[1] = (XC_RF_2_4G->TX_ADDR_L >> 24) & 0xff;
addr_buff[2] = (XC_RF_2_4G->TX_ADDR_L >> 16) & 0xff;
addr_buff[3] = (XC_RF_2_4G->TX_ADDR_L >> 8) & 0xff;
addr_buff[4] = (XC_RF_2_4G->TX_ADDR_L >> 0) & 0xff;
addr_buff[0] = (XC_RF_2_4G->TX_ADDR_H >> 0) & 0xff;
}
}
/**
* @brief RF 2.4g get address crc
* @param void
* @retval crc data
*/
uint16_t rf_get_addr_crc(void)
{
#if (1 == XINCX_2_4G_CRC_BYTE)
return crc8_rohc(addr_buff, RF_ADDR_LEN, RF_CRC_INIT_VALUE, PACKET_NORMAL);
#elif (2 == XINCX_2_4G_CRC_BYTE)
return crc16_ccitt_false(addr_buff, RF_ADDR_LEN, RF_CRC_INIT_VALUE, PACKET_NORMAL);
#endif
}
/**
* @brief Address whitening and writing
* @param void
* @retval uint8_t whiten_addr
*/
uint8_t rf_recv_addr(void)
{
uint16_t whiten_addr = whiten_data((uint8_t *)addr_buff, RF_ADDR_LEN, PANCHIP_WHITEN_INIT_VAL);
/* Set PTX address */
set_rf_txaddr((addr_buff[0] << 0) | (addr_buff[1] << 8) | (addr_buff[2] << 16) | (addr_buff[3] << 24),
(addr_buff[4]));
/* Set PRX address */
set_rf_pipe0_rxaddr((addr_buff[0] << 0) | (addr_buff[1] << 8) | (addr_buff[2] << 16) | (addr_buff[3] << 24),
(addr_buff[4]));
return whiten_addr;
}
void rf_compatible_config(void)
{
#if (XINCX_RF_COMPATIBILITY_MODE == BELKEN_PACKET)
#if XC62XX
set_rf_retr(XINCX_2_4G_RETRANS_CNT, XINCX_2_4G_RETRANS_DELAY);
XC_RF_2_4G->FEATURE &= ~(1 << 5);
rf_set_ack_type(1);
rf_set_freq_dev(RF_FREQ_DEV);
#endif
#elif (XINCX_RF_COMPATIBILITY_MODE == PANCHIP_PACKET)
XC_RF_2_4G->FEATURE |= (1 << 11) | (2 << 12) | (1 << 14) | (1 << 18);
XC_RF_2_4G->PREAMBLE = 0x710f55;
/* 白化cc2500、同步字中断、CRC中断 */
XC_RF_2_4G->CFG_TOP |= (1 << 30) | (1 << 22);
/* get addr */
rf_addr_map(addr_buff);
/* Calculate the CRC of the address block */
rf_addr_crc = rf_get_addr_crc();
/* The address range is whitened and the whitened address is rewritten */
panchip_addr_whiten = rf_recv_addr();
#if XC62XX
rf_set_whiten_value(panchip_addr_whiten);
rf_set_fifo_len(1);
#else
XC_RF_2_4G->FEATURE |= (1 << 5);
XC_RF_2_4G->CFG_TOP &= ~(0x7f << 23);
XC_RF_2_4G->CFG_TOP |= (panchip_addr_whiten << 23);
#endif
set_rf_crc(CRC_0BYTE);
#endif
}
uint8_t rf_panchip_normal_recv_data_cfg(uint8_t *buff, uint8_t len)
{
if (len == 0) {
return 1;
}
uint16_t crc_data = 0;
/* Whiten */
whiten_data(buff, len + 2, panchip_addr_whiten);
/* CRC */
crc = ~crc16_ccitt_false(buff, len, rf_addr_crc, PACKET_NORMAL);
crc_data = ((buff[len] << 8) | (buff[len + 1]));
if (crc == crc_data) {
buff_bigandsmallend(buff, len);
} else {
len = 0;
}
return len;
}
uint8_t rf_panchip_normal_send_data_cfg(uint8_t *buff, uint8_t len)
{
if (len == 0) {
return 1;
}
buff_bigandsmallend(buff, len);
crc = ~crc16_ccitt_false(buff, panchip_data_length, rf_addr_crc, PACKET_NORMAL);
buff[panchip_data_length] = (crc >> 8) & 0xff;
buff[panchip_data_length + 1] = crc & 0xff;
/* Whiten */
whiten_data(buff, len + 2, panchip_addr_whiten);
return 0;
}
uint32_t rf_rx_normal_manage(void)
{
if (rf24g_rx_irq_flag) {
rf24g_rx_irq_flag = false;
/* Entering standby mode */
CE_CTL_LOW;
uint8_t len = recv_len;
#if (DEBUG_PIN)
xc_gpio_write_pin(TEST_PIN_2, GPIO_PIN_SET);
#endif
len = rf_panchip_normal_recv_data_cfg(recv_buf, len - 2);
if (len) {
#if (DEBUG_PIN)
xc_gpio_write_pin(TEST_PIN_1, GPIO_PIN_SET);
#endif
// rf_buff_info(recv_buf, len);
/* Receive Count */
recv_cnt++;
LOGI("recv:%d, len:%d\r\n", recv_cnt, len);
/* Receive read data buffer reset */
memset(recv_buf, 0, len);
len = 0;
}
#if (DEBUG_PIN)
xc_gpio_write_pin(TEST_PIN_1, GPIO_PIN_RESET);
xc_gpio_write_pin(TEST_PIN_2, GPIO_PIN_RESET);
#endif
/* Entering the receiver */
CE_CTL_HIGH;
}
return 0;
}
uint32_t rf_tx_normal_manage(uint8_t *buff, uint8_t length)
{
if (rf24g_tx_irq_flag) {
rf24g_tx_irq_flag = false;
buff[0] = send_cnt++;
/* Filling in software frame number */
LOGI("data len:%d, send_cnt:%d\n", length - XINCX_2_4G_CRC_BYTE, send_cnt);
// rf_buff_info(buff, length);
rf_panchip_normal_send_data_cfg(buff, length - XINCX_2_4G_CRC_BYTE);
/* data transmission */
rf_tx_packet(buff, length);
}
return 0;
}
project/example/2.4g/RF24_ADV/mdk/JLinkSettings.ini
+46
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@@ -0,0 +1,46 @@
[BREAKPOINTS]
ForceImpTypeAny = 0
ShowInfoWin = 1
EnableFlashBP = 2
BPDuringExecution = 0
[CFI]
CFISize = 0x00
CFIAddr = 0x00
[CPU]
MonModeVTableAddr = 0xFFFFFFFF
MonModeDebug = 0
MaxNumAPs = 0
LowPowerHandlingMode = 0
OverrideMemMap = 0
AllowSimulation = 1
ScriptFile=""
[FLASH]
RMWThreshold = 0x400
Loaders=""
EraseType = 0x00
CacheExcludeSize = 0x00
CacheExcludeAddr = 0x00
MinNumBytesFlashDL = 0
SkipProgOnCRCMatch = 1
VerifyDownload = 1
AllowCaching = 1
EnableFlashDL = 2
Override = 0
Device="ARM7"
[GENERAL]
WorkRAMSize = 0x00
WorkRAMAddr = 0x00
RAMUsageLimit = 0x00
[SWO]
SWOLogFile=""
[MEM]
RdOverrideOrMask = 0x00
RdOverrideAndMask = 0xFFFFFFFF
RdOverrideAddr = 0xFFFFFFFF
WrOverrideOrMask = 0x00
WrOverrideAndMask = 0xFFFFFFFF
WrOverrideAddr = 0xFFFFFFFF
[RAM]
VerifyDownload = 0x00
[DYN_MEM_MAP]
NumUserRegion = 0x00
project/example/2.4g/RF24_ADV/mdk/Linker/Initialization.ini
+12
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@@ -0,0 +1,12 @@
FUNC void Initialization(void)
{
SP = _RDWORD(0x10000000);
PC = _RDWORD(0x10000004);
}
LOAD %L INCREMENTAL
Initialization();
project/example/2.4g/RF24_ADV/mdk/Linker/XIPInitialization.ini
+84
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@@ -0,0 +1,84 @@
FUNC void InitGpio(void)
{
// Config IOMUX
/*
gpio_mux_ctl_u(33,1);//d2
gpio_mux_ctl_u(34,1);//d3
gpio_mux_ctl_u(35,2);//clk
gpio_mux_ctl_u(36,2);//cs
gpio_mux_ctl_u(37,2);//d0 rx
gpio_mux_ctl_u(38,2);//d1 tx
*/
_WDWORD(0x4000019c, 0x00002A94);
}
FUNC void InitFlash(void)
{
}
FUNC void InitXIP(void)
{
_WDWORD(0x40000104,0x040000);//reset ssi0
_WDWORD(0x40000104,0x040004);//reset ssi0
_WDWORD(0x40000050,0x110000);//close spi0 mclk
_WDWORD(0x40000070,0x1000000);//close spi0 pclk
//config fmc
_WDWORD(0x40000270, 0x0503);
_Sleep_(1);// delay about 400us
_WDWORD(0x40000270, 0x3503);
//config cache
_Sleep_(1);// delay about 400us
_WDWORD(0x52000000, 0x0);
_Sleep_(1);// delay about 400us
_WDWORD(0x52000000, 0x21);
_Sleep_(1);// delay about 400us
_Sleep_(1);// delay about 400us
_Sleep_(1);// delay about 400us
_Sleep_(1);// delay about 400us
//config xip spi
_WDWORD(0x51000008, 0); //disable spi
_WDWORD(0x5100002c,0); //close IE
_WDWORD(0x51000000,0x1F); //32bit SPI data
_WDWORD(0x51000010,0x01); //enable select slave -- SE
_WDWORD(0x51000018,0x0); //TXFTL be set 0
_WDWORD(0x5100001c,0x0); //RXFTL be set 0
_WDWORD(0x5100010c, 0x01);//enable select slave
_WDWORD(0x51000114, 0xFF);//XIP time out
_WDWORD(0x51000014, 0x2);//div 2
//quad
// _WDWORD(0x51000108, (2)|(6<<4)|(2<<9)|(1<<22)|(1<<29)|(1<<23)|(0<<24)|(8<<13));
// _WDWORD(0x51000100, 0x6b);//quad read cmd
// _WDWORD(0x51000104, 0x6b);//quad read cmd
//dual
_WDWORD(0x51000108, (1)|(6<<4)|(2<<9)|(1<<22)|(1<<29)|(1<<23)|(0)|(8<<13));
_WDWORD(0x51000100, 0x3b);//dual read cmd
_WDWORD(0x51000104, 0x3b);//dual read cmd
_WDWORD(0x51000008, 1); //enable spi
}
FUNC void Initialization(void)
{
InitGpio();
InitFlash();
InitXIP();
SP = _RDWORD(0x11001000);
PC = _RDWORD(0x11001004);
_WDWORD(0x4000013C, 0x11001001);
}
LOAD %L INCREMENTAL
Initialization();
project/example/2.4g/RF24_ADV/mdk/Linker/cpu.scat
+18
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@@ -0,0 +1,18 @@
LOAD 0x10000000
{
EXE 0x10000000
{
startup_xinc.o (RESET, +FIRST)
* (+RO)
}
RW +0000
{
* (+RW,+ZI)
}
;ScatterAssert(ImageLength(RW) < 1024 * 28)
}
project/example/2.4g/RF24_ADV/mdk/Linker/cpu_xip.scat
+25
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@@ -0,0 +1,25 @@
LOAD 0x11001000
{
EXE 0x11001000
{
startup_xinc.o (RESET, +FIRST)
* (+RO)
}
RW 0x100000C8
{
* (+RW,+ZI)
*(ram_code)
aeabi_sdiv.o(.text)
}
ScatterAssert( 0xC8 + ImageLength(RW) < 1024 * 32)
RW2 (0x53004000)
{
*(ram_em)
}
ScatterAssert( ImageLength(RW2) < 1024 * 16)
}
project/example/2.4g/RF24_ADV/mdk/Linker/cpu_xip_xc62xx.scat
+21
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@@ -0,0 +1,21 @@
LOAD 0x11001000
{
EXE 0x11001000
{
startup_xinc.o (RESET, +FIRST)
* (+RO)
}
RW 0x100000C8 0x1F38
{
* (+RW,+ZI)
*(ram_code)
aeabi_sdiv.o(.text)
}
ScatterAssert( ImageLength(RW) < 1024 * 8)
}
project/example/2.4g/RF24_ADV/mdk/Output/0_ram.bin
BIN
View File
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project/example/2.4g/RF24_ADV/mdk/Output/Rf24Demo.bin
BIN
View File
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project/example/2.4g/RF24_ADV/mdk/Output/Rf24DemoXip.bin
BIN
View File
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project/example/2.4g/RF24_ADV/mdk/Output/ram_program.bat
+1
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@@ -0,0 +1 @@
Xincboot_tool.exe 0_ram.bin 1_ram_download.bin 0 0 0 0 1
project/example/2.4g/RF24_ADV/mdk/Output/xip_dual
BIN
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project/example/2.4g/RF24_ADV/mdk/Output/xip_program.bat
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.\Tools\xinchip_xip_tool.exe .\Output\0_ram.bin .\Output\xip_dual .\Output\Rf24DemoXip.bin
project/example/2.4g/RF24_ADV/mdk/RF24_ADV.uvoptx
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project/example/2.4g/RF24_ADV/mdk/RF24_ADV_XC62XX.uvoptx
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project/example/2.4g/RF24_ADV/mdk/RF24_ADV_XC62XX.uvprojx
+679
View File
@@ -0,0 +1,679 @@
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<wLevel>0</wLevel>
<uThumb>2</uThumb>
<uSurpInc>2</uSurpInc>
<uC99>2</uC99>
<uGnu>2</uGnu>
<useXO>2</useXO>
<v6Lang>0</v6Lang>
<v6LangP>0</v6LangP>
<vShortEn>2</vShortEn>
<vShortWch>2</vShortWch>
<v6Lto>2</v6Lto>
<v6WtE>2</v6WtE>
<v6Rtti>2</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Cads>
</FileArmAds>
</FileOption>
</File>
<File>
<FileName>sdk_config.h</FileName>
<FileType>5</FileType>
<FilePath>..\app\api\sdk_config.h</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>RF_Config</GroupName>
<Files>
<File>
<FileName>rf_config.h</FileName>
<FileType>5</FileType>
<FilePath>..\app\rf_config\rf_config.h</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>RF_Drivers</GroupName>
<Files>
<File>
<FileName>xc6xxx_rf_2_4g.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\rf24\Drivers\xc6xxx_rf_2_4g\xc6xxx_rf_2_4g.c</FilePath>
</File>
<File>
<FileName>xc_software_crc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\rf24\Drivers\xc_rf24g_register\xc_software_crc.c</FilePath>
</File>
<File>
<FileName>xc6xxx_rf_ADV.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\rf24\Drivers\xc6xxx_rf_ADV\xc6xxx_rf_ADV.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Drivers</GroupName>
<Files>
<File>
<FileName>xc_drv_adc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_adc.c</FilePath>
</File>
<File>
<FileName>xc_drv_aotimer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_aotimer.c</FilePath>
</File>
<File>
<FileName>xc_drv_bor.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_bor.c</FilePath>
</File>
<File>
<FileName>xc_drv_calib.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_calib.c</FilePath>
</File>
<File>
<FileName>xc_drv_clock.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_clock.c</FilePath>
</File>
<File>
<FileName>xc_drv_dma.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_dma.c</FilePath>
</File>
<File>
<FileName>xc_drv_fmc_spi.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_fmc_spi.c</FilePath>
</File>
<File>
<FileName>xc_drv_fmc_spi_dma.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_fmc_spi_dma.c</FilePath>
</File>
<File>
<FileName>xc_drv_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_gpio.c</FilePath>
</File>
<File>
<FileName>xc_drv_i2c.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_i2c.c</FilePath>
</File>
<File>
<FileName>xc_drv_pga.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_pga.c</FilePath>
</File>
<File>
<FileName>xc_drv_pwm.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_pwm.c</FilePath>
</File>
<File>
<FileName>xc_drv_pwr.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_pwr.c</FilePath>
</File>
<File>
<FileName>xc_drv_qdec.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_qdec.c</FilePath>
</File>
<File>
<FileName>xc_drv_rtc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_rtc.c</FilePath>
</File>
<File>
<FileName>xc_drv_spi.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_spi.c</FilePath>
</File>
<File>
<FileName>xc_drv_spi_dma.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_spi_dma.c</FilePath>
</File>
<File>
<FileName>xc_drv_sw_i2c.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_sw_i2c.c</FilePath>
</File>
<File>
<FileName>xc_drv_systick.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_systick.c</FilePath>
</File>
<File>
<FileName>xc_drv_timer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_timer.c</FilePath>
</File>
<File>
<FileName>xc_drv_uart.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_uart.c</FilePath>
</File>
<File>
<FileName>xc_drv_uart_dma.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_uart_dma.c</FilePath>
</File>
<File>
<FileName>xc_drv_wdt.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_wdt.c</FilePath>
</File>
</Files>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis/>
<components/>
<files>
<file attr="config" category="linkerScript" condition="ARMCC5" name="Device\ARM\ARMCM0\Source\ARM\ARMCM0_ac5.sct" version="1.0.0">
<instance index="0" removed="1">RTE\Device\ARMCM0\ARMCM0_ac5.sct</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM0 CMSIS" isDefaultVariant="1"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.8.0"/>
<targetInfos/>
</file>
<file attr="config" category="sourceC" name="Device\ARM\ARMCM0\Source\startup_ARMCM0.c" version="2.0.3">
<instance index="0" removed="1">RTE\Device\ARMCM0\startup_ARMCM0.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM0 CMSIS" isDefaultVariant="1"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.8.0"/>
<targetInfos/>
</file>
<file attr="config" category="sourceC" name="Device\ARM\ARMCM0\Source\system_ARMCM0.c" version="1.0.0">
<instance index="0" removed="1">RTE\Device\ARMCM0\system_ARMCM0.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM0 CMSIS" isDefaultVariant="1"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.8.0"/>
<targetInfos/>
</file>
</files>
</RTE>
<LayerInfo>
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
</Layer>
</Layers>
</LayerInfo>
</Project>
project/example/2.4g/RF24_ADV/mdk/Tools/Xincboot_tool.exe
BIN
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project/example/2.4g/RF24_ADV/mdk/Tools/dump.py
+59
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@@ -0,0 +1,59 @@
#!/usr/bin/env python
#-*- coding:UTF-8 -*-
import socket
from select import select
import time
import os
import sys
import threading
import json
import struct
import binascii
import time
import re
import fileinput
def dump_addr(addr):
file_asm = "./Xinc_ble_sdk_asm"
cur_func = ""
with open(file_asm, 'r') as fd:
for line in fd:
if re.match(r" \w+", line) != None:
cur_func = line.strip()
#
if re.search("^ 0x", line) != None and re.search(addr, line) != None:
print(addr, cur_func)
break
fd.close()
if __name__ == "__main__":
file_in = "./dump.txt"
for line in fileinput.input(file_in):
# 处理 PC 指针信息
if re.search("PC = ", line) != None:
pc_addr = line.split("PC = ")[1].split(",")[0]
#print(hex(int(pc_addr, 16)))
dump_addr(hex(int(pc_addr, 16)))
# 处理 栈信息
if re.search("^[0-9]",line) != None:
#print(line)
stack = line.split('=')[1].replace('\n', '').split(' ')
for addr in stack:
if addr == ' ' or re.search("^1", addr) == None:
continue
#print(addr, hex(int(addr,16)-1))
dump_addr(hex(int(addr,16)-1))
project/example/2.4g/RF24_ADV/mdk/Tools/xinchip_xip_tool.exe
BIN
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Binary file not shown.
project/example/2.4g/RF24_ADV_Hw/app/Startup/lora/startup_xinc.s
+234
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;/*****************************************************************************
; * @file: startup_xinc.s
; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
; * Device xinc.
; *****************************************************************************/
Stack_Size EQU 0x00000600
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; ToDo: Add here the vectors for the device specific external interrupts handler
DCD 0 ; 0 BLE Handler
DCD DMAS_Handler ; 1
DCD CPR_Handler ; 2
DCD GPIO_Handler ; 3
DCD RTC_Handler ; 4
DCD TIMER0_Handler ; 5
DCD TIMER1_Handler
DCD TIMER2_Handler
DCD TIMER3_Handler
DCD WDT_Handler
DCD I2C_Handler
DCD UART0_Handler
DCD UART1_Handler
DCD SPI0_Handler
DCD SPI1_Handler
DCD 0
DCD 0
DCD GADC_Handler ; 17
DCD 0 ; 18
DCD 0 ; 19
DCD 0 ; 20
DCD 0 ; 21
DCD RF24G_Handler ; 22
DCD PWM_Handler ; 23
DCD BOR_Handler ; 24
DCD 0 ; 25
DCD 0 ; 26
DCD AOTIMER0_Handler ; 27
DCD AOTIMER1_Handler ; 28
DCD CMP_Handler ; 29
DCD FMC_Handler ; 30
DCD CAN_Handler ; 31
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR r0, =0x4000013C ; remap
LDR r1, =0x10000001
STR r1, [r0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
Default_Handler PROC
;EXPORT BLE_Handler [WEAK]
EXPORT DMAS_Handler [WEAK]
EXPORT CPR_Handler [WEAK]
EXPORT GPIO_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT TIMER2_Handler [WEAK]
EXPORT TIMER3_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT I2C_Handler [WEAK]
EXPORT UART0_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
EXPORT SPI0_Handler [WEAK]
EXPORT SPI1_Handler [WEAK]
;EXPORT KBS_Handler [WEAK]
;EXPORT QDEC_Handler [WEAK]
EXPORT GADC_Handler [WEAK]
EXPORT AOTIMER0_Handler [WEAK]
EXPORT AOTIMER1_Handler [WEAK]
EXPORT CMP_Handler [WEAK]
EXPORT FMC_Handler [WEAK]
EXPORT CAN_Handler [WEAK]
;EXPORT SIM_Handler [WEAK]
;EXPORT AES_Handler [WEAK]
EXPORT PendSV_Handler [WEAK]
EXPORT SysTick_Handler [WEAK]
EXPORT RF24G_Handler [WEAK]
EXPORT PWM_Handler [WEAK]
EXPORT BOR_Handler [WEAK]
PendSV_Handler
SysTick_Handler
;BLE_Handler
DMAS_Handler
CPR_Handler
GPIO_Handler
RTC_Handler
TIMER0_Handler
TIMER1_Handler
TIMER2_Handler
TIMER3_Handler
WDT_Handler
I2C_Handler
UART0_Handler
UART1_Handler
SPI0_Handler
SPI1_Handler
;KBS_Handler
;QDEC_Handler
GADC_Handler
;SIM_Handler
;AES_Handler
AOTIMER0_Handler
AOTIMER1_Handler
CMP_Handler
FMC_Handler
CAN_Handler
RF24G_Handler
PWM_Handler
BOR_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
END
project/example/2.4g/RF24_ADV_Hw/app/Startup/system_it_xinc.c
+232
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/*!
* \file system_it_xinc.c
*
* \brief Target system interruption implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "system_it_xinc.h"
/*------------------------------------------------------------------------------------
Func Prototype
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
/**
****************************************************************************************
* @brief This function handles NMI exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void NMI_Handler(void)
{
/* USER CODE BEGIN NonMaskableInt_IRQn */
DEBUG("%s\n", __func__);
/* USER CODE END NonMaskableInt_IRQn */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles Hard Fault exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void HardFault_Handler(void)
{
/* USER CODE BEGIN HardFault_IRQn */
DEBUG("%s\n", __func__);
/* USER CODE END HardFault_IRQn */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles Memory Manage exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void MemManage_Handler(void)
{
/* USER CODE BEGIN */
DEBUG("%s\n", __func__);
/* USER CODE END */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles Bus Fault exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void BusFault_Handler(void)
{
/* USER CODE BEGIN */
DEBUG("%s\n", __func__);
/* USER CODE END */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles Usage Fault exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void UsageFault_Handler(void)
{
/* USER CODE BEGIN */
DEBUG("%s\n", __func__);
/* USER CODE END */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles SVCall exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void SVC_Handler(void)
{
/* USER CODE BEGIN SVCall_IRQn */
DEBUG("%s\n", __func__);
/* USER CODE END SVCall_IRQn */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles Debug Monitor exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void DebugMon_Handler(void)
{
/* USER CODE BEGIN */
DEBUG("%s\n", __func__);
/* USER CODE END */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles PendSVC exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void PendSV_Handler(void)
{
/* USER CODE BEGIN PendSV_IRQn */
DEBUG("%s\n", __func__);
/* USER CODE END PendSV_IRQn */
while (1)
{
}
}
/****************************** Hard Fault Handler Functions *******************************/
/*------------------------------------------------------------------------------------
Private Functions
-------------------------------------------------------------------------------------*/
void HardFault_Handler_c(unsigned int * HardFault_args)
{
/*栈帧里面内容：*/
unsigned int stack_r0; //压栈的 R0
unsigned int stack_r1; //压栈的 R1
unsigned int stack_r2; //压栈的 R2
unsigned int stack_r3; //压栈的 R3
unsigned int stack_r12; //压栈的 R12
unsigned int stack_lr; //压栈的 lr
unsigned int stack_pc; //压栈的 pc
unsigned int stack_psr; //压栈的 psr
stack_r0 = ((unsigned int)HardFault_args[0]);
stack_r1 = ((unsigned int)HardFault_args[1]);
stack_r2 = ((unsigned int)HardFault_args[2]);
stack_r3 = ((unsigned int)HardFault_args[3]);
stack_r12 = ((unsigned int)HardFault_args[4]);
stack_lr = ((unsigned int)HardFault_args[5]);
stack_pc = ((unsigned int)HardFault_args[6]);
stack_psr = ((unsigned int)HardFault_args[7]);
DEBUG("----%s----\n", __func__);
DEBUG("R0=%x\n",stack_r0);
DEBUG("R1=%x\n",stack_r1);
DEBUG("R2=%x\n",stack_r2);
DEBUG("R3=%x\n",stack_r3);
DEBUG("R12=%x\n",stack_r12);
DEBUG("LR[R14]=%x\n",stack_lr);
DEBUG("PC[R15]=%x\n",stack_pc);
DEBUG("PSR=%x\n",stack_psr);
DEBUG("SCB_SHCSR=%x\n",SCB->SHCSR);
DEBUG("---------------------------\n");
while(1);
}
/*******************************************************************************************/
project/example/2.4g/RF24_ADV_Hw/app/Startup/system_it_xinc.h
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/*!
* \file system_it_xinc.h
*
* \brief The header of system_it_xinc.c
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __SYSTEM_IT_XINC_H__
#define __SYSTEM_IT_XINC_H__
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "xc6xxx.h"
/*------------------------------------------------------------------------------------
Exported Functions
-------------------------------------------------------------------------------------*/
void NMI_Handler( void );
void HardFault_Handler( void );
void MemManage_Handler( void );
void BusFault_Handler( void );
void UsageFault_Handler( void );
void SVC_Handler( void );
void DebugMon_Handler( void );
void PendSV_Handler( void );
void HardFault_Handler_c(unsigned int * HardFault_args);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_IT_XINC_H__ */
project/example/2.4g/RF24_ADV_Hw/app/Startup/system_xinc.c
+120
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@@ -0,0 +1,120 @@
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system
*
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include <stdio.h>
#include "xc6xxx.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
#define __DEBUG_OUT_PORT 0
#define readl(addr) (*(volatile unsigned int *) (addr))
#define writel(addr, value) (*(volatile unsigned int *) (addr) = (value))
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
#define VECTOR_NUM 48
void set_vector(void)
{
#if (USE_XIP == 1)
GLOBAL_INT_DISABLE();
for (uint32_t i = 0, *Pvector = (uint32_t *)(0x11001000 + 0),
*_vector_table = (uint32_t *)(0x10000000);
i < VECTOR_NUM; i++) // copy vertor table
{
_vector_table[i] = *Pvector++;
}
*((volatile unsigned int *)(0x4000013C)) =
0x10000001; // inter vertor table remap
GLOBAL_INT_RESTORE();
#endif
}
static void WDT_ResetInit(void)
{
cpr_ctlapbclken_grctl__wdt_pclk_en__setf(ENABLE);
cpr_rstctl_ctlapb_sw__wdt_rstn__setf(RSTCTL_ENABLE);
cpr_rstctl_ctlapb_sw__wdt_rstn__setf(RSTCTL_DISABLE);
cpr_rstctl_wdtrst_mask_set(
(WDT_SYS_RSTN_MASK_DISABLE | WDT_M0_RSTN_MASK_ENABLE));
cpr_lp_ctl__wdt_tclk_en__setf(ENABLE);
wdt_cr__wdt_en__setf(DISABLE);
}
void SystemInit(void)
{
WDT_ResetInit();
#if (USE_XIP == 1)
set_vector();
#endif
writel(0x40000040, readl(0x40000040) | (0x01 << 4) | 0xFFFF0000);
}
__RAM_CODE int sendchar(int c)
{
unsigned int status;
#if (__DEBUG_OUT_PORT == 1)
for (;;) {
status = (*((volatile unsigned *)(0x40011000 + 0x14)));
status &= 0x20;
if (status == 0x20)
break;
}
(*((volatile unsigned *)(0x40011000 + 0x00))) = c;
return (1);
#else
for (;;) {
status = (*((volatile unsigned *)(0x40010000 + 0x14)));
status &= 0x20;
if (status == 0x20)
break;
}
(*((volatile unsigned *)(0x40010000 + 0x00))) = c;
return (1);
#endif
}
struct __FILE
{
int handle; /* Add whatever you need here */
};
FILE __stdout;
__RAM_CODE int fputc(int ch, FILE *f) { return (sendchar(ch)); }
int ferror(FILE *f)
{
/* Your implementation of ferror */
return EOF;
}
void _ttywrch(int ch) { sendchar(ch); }
void _sys_exit(int return_code)
{
label:
goto label; /* endless loop */
}
project/example/2.4g/RF24_ADV_Hw/app/Startup/xc60xx/startup_xinc.s
+257
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@@ -0,0 +1,257 @@
;/*****************************************************************************
; * @file: startup_xinc.s
; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
; * Device xinc.
; *****************************************************************************/
Stack_Size EQU 0x00000800
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; ToDo: Add here the vectors for the device specific external interrupts handler
DCD BLE_Handler ; 0
DCD DMA_Handler ; 1
DCD CPR_Handler ; 2
DCD GPIO_Handler ; 3
DCD RTC_Handler ; 4
DCD TIMER0_Handler ; 5
DCD TIMER1_Handler ; 6
DCD TIMER2_Handler ; 7
DCD TIMER3_Handler ; 8
DCD WDT_Handler ; 9
DCD I2C_Handler ; 10
DCD UART0_Handler ; 11
DCD UART1_Handler ; 12
DCD SPI0_Handler ; 13
DCD SPI1_Handler ; 14
DCD 0 ; 15
DCD 0 ; 16
DCD GADC_Handler ; 17
DCD PWM_Handler ; 18
DCD AES_Handler ; 19
DCD USB_Handler ; 20
DCD AUDIO_Handler ; 21
DCD RF24G_Handler ; 22
DCD SPI2_Handler ; 23
DCD MPU_Handler ; 24
DCD UART2_Handler ; 25
DCD I2S_Handler ; 26
DCD AOTIMER0_Handler ; 27
DCD AOTIMER1_Handler ; 28
DCD CMP_Handler ; 29
DCD FMC_Handler ; 30
DCD CAN_Handler ; 31
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR r0, =0x4000013C ; remap
LDR r1, =0x10000001
STR r1, [r0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
IMPORT HardFault_Handler_c ;函数声明
movs r0, #4 ;判断主栈指针还是进程栈指针
mov r1, lr
tst r0, r1
beq hf_used_msp ;如果是主栈指针
mrs r0, psp ;否则是进程栈指针,把进程栈指针地址付给 R0
ldr r1, =HardFault_Handler_c ;跳转到 HardFault 中断程序
bx r1
hf_used_msp
mrs r0, msp ;把主栈指针地址赋给 R0
ldr r1, =HardFault_Handler_c
bx r1
;EXPORT HardFault_Handler [WEAK]
;B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT BLE_Handler [WEAK]
EXPORT DMA_Handler [WEAK]
EXPORT CPR_Handler [WEAK]
EXPORT GPIO_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT TIMER2_Handler [WEAK]
EXPORT TIMER3_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT I2C_Handler [WEAK]
EXPORT UART0_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
EXPORT SPI0_Handler [WEAK]
EXPORT SPI1_Handler [WEAK]
;EXPORT KBS_Handler [WEAK]
;EXPORT QDEC_Handler [WEAK]
EXPORT GADC_Handler [WEAK]
EXPORT PWM_Handler [WEAK]
EXPORT AES_Handler [WEAK]
EXPORT PendSV_Handler [WEAK]
EXPORT SysTick_Handler [WEAK]
EXPORT USB_Handler [WEAK];20
EXPORT AUDIO_Handler [WEAK];21
EXPORT RF24G_Handler [WEAK];22
EXPORT SPI2_Handler [WEAK];23
EXPORT MPU_Handler [WEAK];24
EXPORT UART2_Handler [WEAK];25
EXPORT I2S_Handler [WEAK];26
EXPORT AOTIMER0_Handler [WEAK];27
EXPORT AOTIMER1_Handler [WEAK];28
EXPORT CMP_Handler [WEAK];29
EXPORT FMC_Handler [WEAK];30
EXPORT CAN_Handler [WEAK];31
PendSV_Handler
SysTick_Handler
BLE_Handler
RF24G_Handler
DMA_Handler
CPR_Handler
GPIO_Handler
RTC_Handler
TIMER0_Handler
TIMER1_Handler
TIMER2_Handler
TIMER3_Handler
WDT_Handler
I2C_Handler
I2S_Handler
UART0_Handler
UART1_Handler
UART2_Handler
SPI0_Handler
SPI1_Handler
SPI2_Handler
MPU_Handler
;KBS_Handler
;QDEC_Handler
GADC_Handler
PWM_Handler
AUDIO_Handler
;SIM_Handler
AES_Handler
AOTIMER0_Handler
AOTIMER1_Handler
CMP_Handler
FMC_Handler
CAN_Handler
USB_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
END
project/example/2.4g/RF24_ADV_Hw/app/Startup/xc65xx/startup_xinc.s
+257
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@@ -0,0 +1,257 @@
;/*****************************************************************************
; * @file: startup_xinc.s
; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
; * Device xinc.
; *****************************************************************************/
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; ToDo: Add here the vectors for the device specific external interrupts handler
DCD BLE_Handler ; 0
DCD DMA_Handler ; 1
DCD CPR_Handler ; 2
DCD GPIO_Handler ; 3
DCD RTC_Handler ; 4
DCD TIMER0_Handler ; 5
DCD TIMER1_Handler ; 6
DCD TIMER2_Handler ; 7
DCD TIMER3_Handler ; 8
DCD WDT_Handler ; 9
DCD I2C_Handler ; 10
DCD UART0_Handler ; 11
DCD UART1_Handler ; 12
DCD SPI0_Handler ; 13
DCD SPI1_Handler ; 14
DCD 0 ; 15
DCD 0 ; 16
DCD GADC_Handler ; 17
DCD PWM_Handler ; 18
DCD AES_Handler ; 19
DCD USB_Handler ; 20
DCD AUDIO_Handler ; 21
DCD RF24G_Handler ; 22
DCD SPI2_Handler ; 23
DCD MPU_Handler ; 24
DCD UART2_Handler ; 25
DCD I2S_Handler ; 26
DCD AOTIMER0_Handler ; 27
DCD AOTIMER1_Handler ; 28
DCD CMP_Handler ; 29
DCD FMC_Handler ; 30
DCD CAN_Handler ; 31
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR r0, =0x4000013C ; remap
LDR r1, =0x10000001
STR r1, [r0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
IMPORT HardFault_Handler_c ;函数声明
movs r0, #4 ;判断主栈指针还是进程栈指针
mov r1, lr
tst r0, r1
beq hf_used_msp ;如果是主栈指针
mrs r0, psp ;否则是进程栈指针,把进程栈指针地址付给 R0
ldr r1, =HardFault_Handler_c ;跳转到 HardFault 中断程序
bx r1
hf_used_msp
mrs r0, msp ;把主栈指针地址赋给 R0
ldr r1, =HardFault_Handler_c
bx r1
;EXPORT HardFault_Handler [WEAK]
;B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT BLE_Handler [WEAK]
EXPORT DMA_Handler [WEAK]
EXPORT CPR_Handler [WEAK]
EXPORT GPIO_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT TIMER2_Handler [WEAK]
EXPORT TIMER3_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT I2C_Handler [WEAK]
EXPORT UART0_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
EXPORT SPI0_Handler [WEAK]
EXPORT SPI1_Handler [WEAK]
;EXPORT KBS_Handler [WEAK]
;EXPORT QDEC_Handler [WEAK]
EXPORT GADC_Handler [WEAK]
EXPORT PWM_Handler [WEAK]
EXPORT AES_Handler [WEAK]
EXPORT PendSV_Handler [WEAK]
EXPORT SysTick_Handler [WEAK]
EXPORT USB_Handler [WEAK];20
EXPORT AUDIO_Handler [WEAK];21
EXPORT RF24G_Handler [WEAK];22
EXPORT SPI2_Handler [WEAK];23
EXPORT MPU_Handler [WEAK];24
EXPORT UART2_Handler [WEAK];25
EXPORT I2S_Handler [WEAK];26
EXPORT AOTIMER0_Handler [WEAK];27
EXPORT AOTIMER1_Handler [WEAK];28
EXPORT CMP_Handler [WEAK];29
EXPORT FMC_Handler [WEAK];30
EXPORT CAN_Handler [WEAK];31
PendSV_Handler
SysTick_Handler
BLE_Handler
RF24G_Handler
DMA_Handler
CPR_Handler
GPIO_Handler
RTC_Handler
TIMER0_Handler
TIMER1_Handler
TIMER2_Handler
TIMER3_Handler
WDT_Handler
I2C_Handler
I2S_Handler
UART0_Handler
UART1_Handler
UART2_Handler
SPI0_Handler
SPI1_Handler
SPI2_Handler
MPU_Handler
;KBS_Handler
;QDEC_Handler
GADC_Handler
PWM_Handler
AUDIO_Handler
;SIM_Handler
AES_Handler
AOTIMER0_Handler
AOTIMER1_Handler
CMP_Handler
FMC_Handler
CAN_Handler
USB_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
END
project/example/2.4g/RF24_ADV_Hw/app/api/app_64m.h
+18
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@@ -0,0 +1,18 @@
#ifndef __APP_64M__
#define __APP_64M__
#include "xc6xxx_rf_2_4g.h"
#define __write_hw_reg32(reg, val) ((*reg) = (val))
#define __read_hw_reg32(reg, val) ((val) = (*reg))
#define CPR_CTLAPBCLKEN_GRCTL ((volatile unsigned *)(0x40000000 + 0x070))
#define CPR_AOCLKEN_GRCTL ((volatile unsigned *)(0x40002400 + 0x7C))
#define AO_GPIO_MODE ((volatile unsigned *)(0x40002000 + 0x0044))
#define AO_GPIO_CTL ((volatile unsigned *)(0x40002000 + 0x0048))
void use_64m_crtstal_init(void);
void rf_64M_set_rx_channel(uint16_t channel);
void rf_64M_set_tx_channel(uint16_t channel);
void testpin_64M_config(void);
void Init_rtc_gpio(uint32_t num, uint8_t inter_mode);
#endif //__APP_64M__
project/example/2.4g/RF24_ADV_Hw/app/api/main.h
+92
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@@ -0,0 +1,92 @@
/*
* @Descripttion:
* @version:
* @Author: sueRimn
* @Date: 2023-12-12 14:23:55
* @LastEditors: sueRimn
* @LastEditTime: 2024-06-07 13:46:09
*/
/*!
* \file main.h
*
* \brief The head file of main.c
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MAIN_H__
#define __MAIN_H__
#ifdef __cplusplus
extern "C"
{
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "rf_config.h"
#include "xc6xxx.h"
#include "xc6xxx_rf_2_4g.h"
#include "xc6xxx_rf_ADV.h"
#include "rf_compatible_normal.h"
#include "rf_adv_config.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
#define ADV_BUFF_LEN XINCX_ADV_PIPE0_LEN
#define DEBUG_LOG
#define RF_TX_TIMERx TIMER0_IDX
#define RF_RX_TIMERx TIMER0_IDX
#define GPIO_TEST 1
#define TEST_GPIO_1 GPIO_1
#if XC62XX
#define TEST_GPIO_2 GPIO_0
#else
#define TEST_GPIO_2 GPIO_21
#endif
/*------------------------------------------------------------------------------------
TypeDef
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Global Variables
-------------------------------------------------------------------------------------*/
extern bool rf_send_timer_flag;
/*------------------------------------------------------------------------------------
Exported Functions
-------------------------------------------------------------------------------------*/
void rf_buff_info(uint8_t *buff, uint16_t len);
void rf_2M_reg_info(void);
void rf_dump_log(void);
uint8_t rf_data_config(uint8_t *buff, uint16_t len);
#ifdef __cplusplus
}
#endif
#endif /* __MAIN_H__ */
project/example/2.4g/RF24_ADV_Hw/app/api/rf_compatible_normal.h
+25
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@@ -0,0 +1,25 @@
#ifndef __RF_COMPATIBLE_NORMAL__
#define __RF_COMPATIBLE_NORMAL__
#include "rf_config.h"
#include "xc6xxx_rf_2_4g.h"
#include "xc_software_crc.h"
#include <stdint.h>
#define RF_ADDR_LEN XINCX_RF_TX_ADDR_WIDTH // 5U
#define RF_RECV_EXTEN_LEN 3U
#define RF_MAX_RECV_LEN 60U
#define RF_CRC_INIT_VALUE 0xFFFF
#define PANCHIP_WHITEN_INIT_VAL (0x7F)
extern uint16_t rf_addr_crc;
extern uint8_t panchip_addr_whiten;
extern uint8_t addr_buff[5];
void rf_addr_map(uint8_t *addr_buff);
uint16_t rf_get_addr_crc(void);
uint8_t rf_recv_addr(void);
void rf_compatible_config(void);
uint32_t rf_rx_normal_manage(void);
uint32_t rf_tx_normal_manage(uint8_t *buff, uint8_t length);
#endif //__RF_COMPATIBLE_NORMAL__
project/example/2.4g/RF24_ADV_Hw/app/api/sdk_config.h
+152
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#ifndef SDK_DRIVER_CONFIG_H
#define SDK_DRIVER_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>\n
#ifdef USE_APP_CONFIG
#include "app_config.h"
#endif
// <h> XC_Drivers
// <e> XC_CLOCK_ENABLED
//==========================================================
#ifndef XC_CLOCK_ENABLED
#define XC_CLOCK_ENABLED 1
#endif
// </e>
// <e> XC_PWR_ENABLED
//==========================================================
#ifndef XC_PWR_ENABLED
#define XC_PWR_ENABLED 1
#endif
// </e>
// <e> XC_WDT_ENABLED
//==========================================================
#ifndef XC_WDT_ENABLED
#define XC_WDT_ENABLED 1
#endif
// </e>
// <e> XC_BOR_ENABLED
//==========================================================
#ifndef XC_BOR_ENABLED
#define XC_BOR_ENABLED 1
#endif
// </e>
// <e> XC_SYSTICK_ENABLED
//==========================================================
#ifndef XC_SYSTICK_ENABLED
#define XC_SYSTICK_ENABLED 1
#endif
// </e>
// <e> XC_TIMER_ENABLED
//==========================================================
#ifndef XC_TIMER_ENABLED
#define XC_TIMER_ENABLED 0
#endif
// </e>
// <e> XC_AOTIMER_ENABLED
//==========================================================
#ifndef XC_AOTIMER_ENABLED
#define XC_AOTIMER_ENABLED 0
#endif
// </e>
// <e> XC_GPIO_ENABLED
//==========================================================
#ifndef XC_GPIO_ENABLED
#define XC_GPIO_ENABLED 1
#endif
// </e>
// <e> XC_ADC_ENABLED
//==========================================================
#ifndef XC_ADC_ENABLED
#define XC_ADC_ENABLED 1
#endif
// </e>
// <e> XC_UART_ENABLED
//==========================================================
#ifndef XC_UART_ENABLED
#define XC_UART_ENABLED 1
#endif
// </e>
// <e> XC_PWM_ENABLED
//==========================================================
#ifndef XC_PWM_ENABLED
#define XC_PWM_ENABLED 1
#endif
// </e>
// <e> XC_FMC_SPI_ENABLED
//==========================================================
#ifndef XC_FMC_SPI_ENABLED
#define XC_FMC_SPI_ENABLED 1
#endif
// </e>
// <e> XC_SPI_ENABLED
//==========================================================
#ifndef XC_SPI_ENABLED
#define XC_SPI_ENABLED 0
#endif
// </e>
// <e> XC_IIC_ENABLED
//==========================================================
#ifndef XC_IIC_ENABLED
#define XC_IIC_ENABLED 0
#endif
// </e>
// <e> XC_RTC_ENABLED
//==========================================================
#ifndef XC_RTC_ENABLED
#define XC_RTC_ENABLED 0
#endif
//==========================================================
// <q> XC_RTC_DATE_INT_ENABLED
#ifndef XC_RTC_DATE_INT_ENABLED
#define XC_RTC_DATE_INT_ENABLED 0
#endif
// </e>
// <e> XC_DMA_ENABLED
//==========================================================
#ifndef XC_DMA_ENABLED
#define XC_DMA_ENABLED 0
#endif
// </e>
// <e> XC_PGA_ENABLED
//==========================================================
#ifndef XC_PGA_ENABLED
#define XC_PGA_ENABLED 0
#endif
// </e>
// <e> XC_QDEC_ENABLED
//==========================================================
#ifndef XC_QDEC_ENABLED
#define XC_QDEC_ENABLED 0
#endif
// </e>
// <e> XC_CALIB_ENABLED
//==========================================================
#ifndef XC_CALIB_ENABLED
#define XC_CALIB_ENABLED 0
#endif
// </e>
// <<< end of configuration section >>>
#endif //SDK_DRIVER_CONFIG_H
project/example/2.4g/RF24_ADV_Hw/app/rf_config/rf_adv_config.h
+225
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@@ -0,0 +1,225 @@
#ifndef SDK_ADV_CONFIG_H
#define SDK_ADV_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>\n
// Xinc_ADV_config
// <o> XINCX_ADV_MODE - RF Tx or Rx Mode
// <0=> TX Mode
// <1=> RX Mode
// <2=> TRX Mode
#ifndef XINCX_ADV_MODE
#define XINCX_ADV_MODE 1
#endif
// <o> XINCX_ADV_ADDR_L - rf Address Set
#ifndef XINCX_ADV_ADDR_L
#define XINCX_ADV_ADDR_L 0x71917d6b//0xe7e7e7a4//0x71917d6b
#endif
// XINCX_ADV_ADDR_H - rf Address Set
#ifndef XINCX_ADV_ADDR_H
#define XINCX_ADV_ADDR_H 0x00
#endif
// <o> XINCX_ADV_CHANNEL - ADV Channel Set
// <2402=> ADV_CHANNEL_37
// <2426=> ADV_CHANNEL_38
// <2480=> ADV_CHANNEL_39
#ifndef XINCX_ADV_CHANNEL
#define XINCX_ADV_CHANNEL 2402
#endif
// <o> XINCX_RF_POWER - rf Power Set
// <1=> -10dbm
// <2=> -9dbm
// <4=> -4dbm
// <6=> 0dbm
// <8=> 3dbm
// <9=> 5dbm
// <12=> 7dbm
// <14=> 8dbm
// <16=> 9dbm
// <19=> 10dbm
// <24=> 11dbm
// <30=> 12dbm
// <36=> 13dbm
#ifndef XINCX_POWER
#define XINCX_POWER 0x00E
#endif
// <o> XINCX_RF_NVIC_MODE - RF NVIC Mode
// <0=> Disable
// <1=> Enable
#ifndef XINCX_RF_ADV_NVIC_MODE
#define XINCX_RF_ADV_NVIC_MODE 1
#endif
// XINCX_RF_TX_ADDR_WIDTH - RF Tx Addr Width
#ifndef XINCX_RF_TX_ADDR_WIDTH
#define XINCX_RF_TX_ADDR_WIDTH 4
#endif
// XINCX_RF_TRANS_RATE - RF Transmission Rate Config
#ifndef XINCX_RF_TRANS_RATE
#define XINCX_RF_TRANS_RATE 0x02
#endif
// XINCX_RF_CRC_ENABLE - RF CRC Enable
//==========================================================
#ifndef XINCX_RF_CRC_ENABLE
#define XINCX_RF_CRC_ENABLE 0
#endif
// XINCX_2_4G_CRC_BYTE - 2.4g CRC Bytes Set
#ifndef XINCX_2_4G_CRC_BYTE
#define XINCX_2_4G_CRC_BYTE 0
#endif
// XINCX_ADV_FEATURE_PARAM - ADV Feature Parameters
//==========================================================
// XINCX_ADV_LONG_PLD - ADV Long Payload Feature
#ifndef XINCX_ADV_LONG_PLD
#define XINCX_ADV_LONG_PLD 1
#endif
// XINCX_ADV_FEC - ADV FEC&Interleave Feature
#ifndef XINCX_ADV_FEC
#define XINCX_ADV_FEC 0
#endif
// XINCX_ADV_WHITEN - ADV Whiten Feature
#ifndef XINCX_ADV_WHITEN
#define XINCX_ADV_WHITEN 0
#endif
// XINCX_ADV_DPL - ADV Dynamic Payload Length Feature
#ifndef XINCX_ADV_DPL
#define XINCX_ADV_DPL 0
#endif
// XINCX_ADV_ACK_PAY - 2.4g Payload on ACK
#ifndef XINCX_ADV_ACK_PAY
#define XINCX_ADV_ACK_PAY 0
#endif
// XINCX_ADV_DYN_ACK - 2.4g W_TX_PAYLOAD_NOACK Command
#ifndef XINCX_ADV_DYN_ACK
#define XINCX_ADV_DYN_ACK 0
#endif
// XINCX_PIPE_PIPE_RX_PAYLEN - ADV Pipe Rx Payload Len
//==========================================================
// <o> XINCX_ADV_PIPE0_LEN - ADV Pipe0 Rx Payload Len
#ifndef XINCX_ADV_PIPE0_LEN
#define XINCX_ADV_PIPE0_LEN 42
#endif
// XINCX_ADV_PIPE1_LEN - ADV Pipe1 Rx Payload Len
#ifndef XINCX_ADV_PIPE1_LEN
#define XINCX_ADV_PIPE1_LEN 0
#endif
// XINCX_ADV_PIPE2_LEN - ADV Pipe2 Rx Payload Len
#ifndef XINCX_ADV_PIPE2_LEN
#define XINCX_ADV_PIPE2_LEN 0
#endif
// XINCX_ADV_PIPE3_LEN - ADV Pipe3 Rx Payload Len
#ifndef XINCX_ADV_PIPE3_LEN
#define XINCX_ADV_PIPE3_LEN 0
#endif
// XINCX_ADV_PIPE4_LEN - ADV Pipe4 Rx Payload Len
#ifndef XINCX_ADV_PIPE4_LEN
#define XINCX_ADV_PIPE4_LEN 0
#endif
// XINCX_ADV_PIPE5_LEN - ADV Pipe5 Rx Payload Len
#ifndef XINCX_ADV_PIPE5_LEN
#define XINCX_ADV_PIPE5_LEN 0
#endif
// XINC_ADV_MAC_ADDR
// <o> XINC_ADV_MAC_ADDR_0
#ifndef XINC_ADV_MAC_ADDR_0
#define XINC_ADV_MAC_ADDR_0 0xA8
#endif
// <o> XINC_ADV_MAC_ADDR_1
#ifndef XINC_ADV_MAC_ADDR_1
#define XINC_ADV_MAC_ADDR_1 0xa5
#endif
// <o> XINC_ADV_MAC_ADDR_2
#ifndef XINC_ADV_MAC_ADDR_2
#define XINC_ADV_MAC_ADDR_2 0xa4
#endif
// <o> XINC_ADV_MAC_ADDR_3
#ifndef XINC_ADV_MAC_ADDR_3
#define XINC_ADV_MAC_ADDR_3 0xa3
#endif
// <o> XINC_ADV_MAC_ADDR_4
#ifndef XINC_ADV_MAC_ADDR_4
#define XINC_ADV_MAC_ADDR_4 0xa2
#endif
// <o> XINC_ADV_MAC_ADDR_5
#ifndef XINC_ADV_MAC_ADDR_5
#define XINC_ADV_MAC_ADDR_5 0xc1
#endif
// <o>XIMCX_2_4G_HANDLER_NUMBER -Bluetooth handler bytes
// <0=> 1 bytes
// <1=> 2 bytes
// <2=> 3 bytes
#ifndef XOMCX_2_4G_PBT_HANDLER_NUMBER
#define XOMCX_2_4G_PBT_HANDLER_NUMBER 1
#endif
// <o> XINCX_2_4G_WHITEN_VALUE - Bluetooth whitening initial value
#ifndef XINCX_2_4G_PBT_WHITEN_VALUE
// <0x53=> ADV_CHANNEL_37
// <0x33=> ADV_CHANNEL_38
// <0x73=> ADV_CHANNEL_39
#define XINCX_2_4G_PBT_WHITEN_VALUE 0x53
#endif
// <o> XINCX_2_4G_CRC_INIT_VALUE - Initial Bluetooth CRC value
#ifndef XINCX_2_4G_PBT_CRC_INIT_VALUE
#define XINCX_2_4G_PBT_CRC_INIT_VALUE 0x555555
#endif
// <o> XINCX_2_4G_PBT_HL_OFFSET
// <0=> 0 bit
// <1=> 1 bit
// <2=> 2 bits
// <3=> 3 bits
// <4=> 4 bits
// <5=> 5 bits
// <6=> 6 bits
// <7=> 7 bits
// <8=> 8 bits
// <9=> 9 bits
// <10=> 10bits
// <11=> 11bits
// <12=> 12bits
// <13=> 13bits
// <14=> 14bits
// <15=> 15bits
// <16=> 16bits
#ifndef XINCX_2_4G_PBT_HL_OFFSET
#define XINCX_2_4G_PBT_HL_OFFSET 8
#endif
// <<< end of configuration section >>>
#endif
project/example/2.4g/RF24_ADV_Hw/app/rf_config/rf_config.h
+589
View File
@@ -0,0 +1,589 @@
#ifndef SDK_CONFIG_H
#define SDK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <e> XINCX_RF_NORMAL_PEACKET_MODE - RF normal packet mode
// <i> Configure the frame format, which is a static packet format and can only communicate in one direction.
#ifndef XINCX_RF_NORMAL_PACKET_MODE
#define XINCX_RF_NORMAL_PACKET_MODE 1
#endif
// <o>XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
//==========================================================
// <0=> Xinchip
// <1=> Panchip
// <2=> Beken
// <3=> Telink
// <4=> Huntersun
#ifndef XINCX_RF_COMPATIBILITY_MODE
#define XINCX_RF_COMPATIBILITY_MODE 0
#endif
#if (XINCX_RF_NORMAL_PACKET_MODE == 1)
// XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
//==========================================================
// <o> XINCX_RF_MODE - RF Tx or Rx Mode
// <0=> TX Mode
// <1=> RX Mode
// <2=> TRX Mode
// <3=> RTX Mode
#ifndef XINCX_RF_MODE
#define XINCX_RF_MODE 0
#endif
// <o> XINCX_RF_TRANS_RATE - RF Transmission Rate Config
// <0x02=> 1M
// <0x0A=> 2M
// <0x22=> 250k
// <0x2A=> 125k
#ifndef XINCX_RF_TRANS_RATE
#define XINCX_RF_TRANS_RATE 0x02
#endif
// <o> XINCX_2_4G_CHANNEL - 2.4g Channel Set
// <2402=> RF_ADV_CHANNEL_37
// <2426=> RF_ADV_CHANNEL_38
// <2480=> RF_ADV_CHANNEL_39
#ifndef XINCX_2_4G_CHANNEL
#define XINCX_2_4G_CHANNEL 2488
#endif
// <o> XINCX_RF_TX_ADDR_WIDTH - RF Tx Addr Width
// <3=> 3 Bytes
// <4=> 4 Bytes
// <5=> 5 Bytes
#ifndef XINCX_RF_TX_ADDR_WIDTH
#define XINCX_RF_TX_ADDR_WIDTH 5
#endif
// <o> XINCX_2_4G_ADDR_L - rf Address Set
#ifndef XINCX_2_4G_ADDR_L
#define XINCX_2_4G_ADDR_L 0xe7e7e7e7 // 0xCCDDEEDD
#endif
// <o> XINCX_2_4G_ADDR_H - rf Address Set
#ifndef XINCX_2_4G_ADDR_H
#define XINCX_2_4G_ADDR_H 0xe7 // 0xAA
#endif
// <o> XINCX_RF_POWER - rf Power Set
// <1=> -10dbm
// <2=> -9dbm
// <4=> -4dbm
// <6=> 0dbm
// <8=> 3dbm
// <9=> 5dbm
// <12=> 7dbm
// <14=> 8dbm
// <16=> 9dbm
// <19=> 10dbm
// <24=> 11dbm
// <30=> 12dbm
// <36=> 13dbm
#ifndef XINCX_POWER
#define XINCX_POWER 0x00006
#endif
// <o> XINCX_RF_NVIC_MODE - RF NVIC Mode
// <0=> Disable
// <1=> Enable
#ifndef XINCX_RF_NVIC_MODE
#define XINCX_RF_NVIC_MODE 1
#endif
// XINCX_2_4G_PIPE_RX_PAYLEN - 2.4g Pipe Rx Payload Len
// <i> Payload length. Configuration of the load length during communication.
//==========================================================
// XINCX_2_4G_PIPE0_LEN - 2.4g Pipe0 Rx Payload Len
// #ifndef XINCX_2_4G_PIPE0_LEN
// #define XINCX_2_4G_PIPE0_LEN 32
// #endif
// XINCX_2_4G_PIPE1_LEN - 2.4g Pipe1 Rx Payload Len
#ifndef XINCX_2_4G_PIPE1_LEN
#define XINCX_2_4G_PIPE1_LEN 32
#endif
// XINCX_2_4G_PIPE2_LEN - 2.4g Pipe2 Rx Payload Len
#ifndef XINCX_2_4G_PIPE2_LEN
#define XINCX_2_4G_PIPE2_LEN 32
#endif
// XINCX_2_4G_PIPE3_LEN - 2.4g Pipe3 Rx Payload Len
#ifndef XINCX_2_4G_PIPE3_LEN
#define XINCX_2_4G_PIPE3_LEN 32
#endif
// XINCX_2_4G_PIPE4_LEN - 2.4g Pipe4 Rx Payload Len
#ifndef XINCX_2_4G_PIPE4_LEN
#define XINCX_2_4G_PIPE4_LEN 32
#endif
// XINCX_2_4G_PIPE5_LEN - 2.4g Pipe5 Rx Payload Len
#ifndef XINCX_2_4G_PIPE5_LEN
#define XINCX_2_4G_PIPE5_LEN 32
#endif
//
// XINCX_RF_CRC_ENABLE - RF CRC Enable
//==========================================================
#ifndef XINCX_RF_CRC_ENABLE
#define XINCX_RF_CRC_ENABLE 1
#endif
// <o> XINCX_2_4G_CRC_BYTE - 2.4g CRC Bytes Set
// <0=> 0 Byte
// <1=> 1 Byte
// <2=> 2 Bytes
#ifndef XINCX_2_4G_CRC_BYTE
#define XINCX_2_4G_CRC_BYTE 2
#endif
// XINCX_2_4G_FEATURE_PARAM - 2.4g Feature Parameters
//==========================================================
// XINCX_2_4G_GUARD_CFG - 2.4g Long Payload Feature
#ifndef XINCX_2_4G_GUARD_CFG
#define XINCX_2_4G_GUARD_CFG 0
#endif
// XINCX_2_4G_LONG_PLD_TYPE - 2.4g Long Pld Type
#ifndef XINCX_2_4G_LONG_PLD_TYPE
#define XINCX_2_4G_LONG_PLD_TYPE 0
#endif
// XINCX_2_4G_PREAMBLE_NUM - 2.4g Preamble
#ifndef XINCX_2_4G_PREAMBLE_NUM
#define XINCX_2_4G_PREAMBLE_NUM 0
#endif
// XINCX_2_4G_PREAMBLE_TYPE - 2.4g Preamble Type
#ifndef XINCX_2_4G_PREAMBLE_TYPE
#define XINCX_2_4G_PREAMBLE_TYPE 0
#endif
// XINCX_2_4G_CRC_SCOPE_GUARD - 2.4g CRC Scope Guard
#ifndef XINCX_2_4G_CRC_SCOPE_GUARD
#define XINCX_2_4G_CRC_SCOPE_GUARD 0
#endif
// XINCX_2_4G_CRC_SCOPE_HEADER - 2.4g CRC Scope Header
#ifndef XINCX_2_4G_CRC_SCOPE_HEADER
#define XINCX_2_4G_CRC_SCOPE_HEADER 1
#endif
// XINCX_2_4G_CRC_SCOPE_ADDR - 2.4g CRC Scope Addr
#ifndef XINCX_2_4G_CRC_SCOPE_ADDR
#define XINCX_2_4G_CRC_SCOPE_ADDR 1
#endif
// <q> XINCX_2_4G_LONG_PLD - 2.4g Long Payload Feature
#ifndef XINCX_2_4G_LONG_PLD
#define XINCX_2_4G_LONG_PLD 0
#endif
// <q> XINCX_2_4G_FEC - 2.4g FEC&Interleave Feature
#ifndef XINCX_2_4G_FEC
#define XINCX_2_4G_FEC 0
#endif
// <q> XINCX_2_4G_WHITEN - 2.4g Whiten Feature
#ifndef XINCX_2_4G_WHITEN
#define XINCX_2_4G_WHITEN 0
#endif
// XINCX_2_4G_DPL - 2.4g Dynamic Payload Length Feature
#ifndef XINCX_2_4G_DPL
#define XINCX_2_4G_DPL 0
#endif
// XINCX_2_4G_ACK_PAY - 2.4g Payload on ACK
#ifndef XINCX_2_4G_ACK_PAY
#define XINCX_2_4G_ACK_PAY 0
#endif
// XINCX_2_4G_DYN_ACK - 2.4g W_TX_PAYLOAD_NOACK Command
#ifndef XINCX_2_4G_DYN_ACK
#define XINCX_2_4G_DYN_ACK 0
#endif
//
// XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
//==========================================================
// XINCX_2_4G_RETRANS_CNT - 2.4g Retransmit Count
// <i> Number of retransmissions. The maximum number of times a hardware can automatically transmit an ACK if it does
// not receive the correct ACK.
#ifndef XINCX_2_4G_RETRANS_CNT
#define XINCX_2_4G_RETRANS_CNT 0
#endif
// XINCX_2_4G_RETRANS_DELAY - 2.4g Retransmission Delay
// <i> Retransmission delay. For 32 bytes of data, the minimum configuration is 500 us for 1 Mbit/s and 1500 us for 250
// kbit/s.
#ifndef XINCX_2_4G_RETRANS_DELAY
#define XINCX_2_4G_RETRANS_DELAY 0
#endif
// XINCX_2_4G_DYNPD - 2.4g dynpd
#ifndef XINCX_2_4G_DYNPD
#define XINCX_2_4G_DYNPD 0x00
#endif
// XINCX_2_4G_AUTO_ACK - 2.4g Auto Acknowledgement
//==========================================================
// XINCX_2_4G_PIPE0_ENAA - 2.4g Pipe0 Auto Ack
#ifndef XINCX_2_4G_PIPE0_ENAA
#define XINCX_2_4G_PIPE0_ENAA 0
#endif
// XINCX_2_4G_PIPE1_ENAA - 2.4g Pipe1 Auto Ack
#ifndef XINCX_2_4G_PIPE1_ENAA
#define XINCX_2_4G_PIPE1_ENAA 0
#endif
// XINCX_2_4G_PIPE2_ENAA - 2.4g Pipe2 Auto Ack
#ifndef XINCX_2_4G_PIPE2_ENAA
#define XINCX_2_4G_PIPE2_ENAA 0
#endif
// XINCX_2_4G_PIPE3_ENAA - 2.4g Pipe3 Auto Ack
#ifndef XINCX_2_4G_PIPE3_ENAA
#define XINCX_2_4G_PIPE3_ENAA 0
#endif
// XINCX_2_4G_PIPE4_ENAA - 2.4g Pipe4 Auto Ack
#ifndef XINCX_2_4G_PIPE4_ENAA
#define XINCX_2_4G_PIPE4_ENAA 0
#endif
// XINCX_2_4G_PIPE5_ENAA - 2.4g Pipe5 Auto Ack
#ifndef XINCX_2_4G_PIPE5_ENAA
#define XINCX_2_4G_PIPE5_ENAA 0
#endif
// XINCX_RF_PIPE_ENABLE
#ifndef XINCX_RF_PIPE_ENABLE
#define XINCX_RF_PIPE_ENABLE 0
#endif
#endif
// </e> //XINCX_RF_PEACKET_MODE normal normal
// <e> XINCX_RF_EMHAMCED_PEACKET_MODE - RF enhanced packet mode
// <i> Configure the frame format, which is a dynamic packet configuration, which can communicate in both directions,and
// <i> ACK can dynamically carry data.
#ifndef XINCX_RF_EMHAMCED_PACKET_MODE
#define XINCX_RF_EMHAMCED_PACKET_MODE 0
#endif
#if (XINCX_RF_EMHAMCED_PACKET_MODE == 1)
// XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
//==========================================================
// <o> XINCX_RF_MODE - RF Tx or Rx Mode
// <0=> TX Mode
// <1=> RX Mode
#ifndef XINCX_RF_MODE
#define XINCX_RF_MODE 0
#endif
// <o> XINCX_RF_TRANS_RATE - RF Transmission Rate Config
// <0x02=> 1M
// <0x0A=> 2M
// <0x22=> 250k
// <0x2A=> 125k
#ifndef XINCX_RF_TRANS_RATE
#define XINCX_RF_TRANS_RATE 0x02
#endif
// <o> XINCX_2_4G_CHANNEL - 2.4g Channel Set
#ifndef XINCX_2_4G_CHANNEL
#define XINCX_2_4G_CHANNEL 2440
#endif
// <o> XINCX_RF_TX_ADDR_WIDTH - RF Tx Addr Width
// <3=> 3 Bytes
// <4=> 4 Bytes
// <5=> 5 Bytes
#ifndef XINCX_RF_TX_ADDR_WIDTH
#define XINCX_RF_TX_ADDR_WIDTH 5
#endif
// <o> XINCX_2_4G_ADDR_L - rf Address Set
#ifndef XINCX_2_4G_ADDR_L
#define XINCX_2_4G_ADDR_L 0xe7e7e7e7
#endif
// <o> XINCX_2_4G_ADDR_H - rf Address Set
#ifndef XINCX_2_4G_ADDR_H
#define XINCX_2_4G_ADDR_H 0xe7
#endif
// <o> XINCX_RF_POWER - rf Power Set
// <1=> -10dbm
// <2=> -9dbm
// <4=> -4dbm
// <6=> 0dbm
// <8=> 3dbm
// <9=> 5dbm
// <12=> 7dbm
// <14=> 8dbm
// <16=> 9dbm
// <19=> 10dbm
// <24=> 11dbm
// <30=> 12dbm
// <36=> 13dbm
#ifndef XINCX_POWER
#define XINCX_POWER 0x00006
#endif
// <o> XINCX_RF_NVIC_MODE - RF NVIC Mode
// <0=> Disable
// <1=> Enable
#ifndef XINCX_RF_NVIC_MODE
#define XINCX_RF_NVIC_MODE 1
#endif
// XINCX_2_4G_PIPE_RX_PAYLEN - 2.4g Pipe Rx Payload Len
// <i> Payload length. Configuration of the load length during communication.
//==========================================================
// XINCX_2_4G_PIPE0_LEN - 2.4g Pipe0 Rx Payload Len
// #ifndef XINCX_2_4G_PIPE0_LEN
// #define XINCX_2_4G_PIPE0_LEN 32
// #endif
// XINCX_2_4G_PIPE1_LEN - 2.4g Pipe1 Rx Payload Len
#ifndef XINCX_2_4G_PIPE1_LEN
#define XINCX_2_4G_PIPE1_LEN 32
#endif
// XINCX_2_4G_PIPE2_LEN - 2.4g Pipe2 Rx Payload Len
#ifndef XINCX_2_4G_PIPE2_LEN
#define XINCX_2_4G_PIPE2_LEN 32
#endif
// XINCX_2_4G_PIPE3_LEN - 2.4g Pipe3 Rx Payload Len
#ifndef XINCX_2_4G_PIPE3_LEN
#define XINCX_2_4G_PIPE3_LEN 32
#endif
// XINCX_2_4G_PIPE4_LEN - 2.4g Pipe4 Rx Payload Len
#ifndef XINCX_2_4G_PIPE4_LEN
#define XINCX_2_4G_PIPE4_LEN 32
#endif
// XINCX_2_4G_PIPE5_LEN - 2.4g Pipe5 Rx Payload Len
#ifndef XINCX_2_4G_PIPE5_LEN
#define XINCX_2_4G_PIPE5_LEN 32
#endif
// XINCX_RF_CRC_ENABLE - RF CRC Enable
//==========================================================
#ifndef XINCX_RF_CRC_ENABLE
#define XINCX_RF_CRC_ENABLE 1
#endif
// <o> XINCX_2_4G_CRC_BYTE - 2.4g CRC Bytes Set
// <0=> 0 Byte
// <1=> 1 Byte
// <2=> 2 Bytes
#ifndef XINCX_2_4G_CRC_BYTE
#define XINCX_2_4G_CRC_BYTE 2
#endif
// XINCX_2_4G_FEATURE_PARAM - 2.4g Feature Parameters
//==========================================================
// XINCX_2_4G_GUARD_CFG - 2.4g Long Payload Feature
#ifndef XINCX_2_4G_GUARD_CFG
#define XINCX_2_4G_GUARD_CFG 0
#endif
// XINCX_2_4G_LONG_PLD_TYPE - 2.4g Long Pld Type
#ifndef XINCX_2_4G_LONG_PLD_TYPE
#define XINCX_2_4G_LONG_PLD_TYPE 0
#endif
// XINCX_2_4G_PREAMBLE_NUM - 2.4g Preamble
#ifndef XINCX_2_4G_PREAMBLE_NUM
#define XINCX_2_4G_PREAMBLE_NUM 0
#endif
// XINCX_2_4G_PREAMBLE_TYPE - 2.4g Preamble Type
#ifndef XINCX_2_4G_PREAMBLE_TYPE
#define XINCX_2_4G_PREAMBLE_TYPE 0
#endif
// XINCX_2_4G_CRC_SCOPE_GUARD - 2.4g CRC Scope Guard
#ifndef XINCX_2_4G_CRC_SCOPE_GUARD
#define XINCX_2_4G_CRC_SCOPE_GUARD 0
#endif
// XINCX_2_4G_CRC_SCOPE_HEADER - 2.4g CRC Scope Header
#ifndef XINCX_2_4G_CRC_SCOPE_HEADER
#define XINCX_2_4G_CRC_SCOPE_HEADER 1
#endif
// XINCX_2_4G_CRC_SCOPE_ADDR - 2.4g CRC Scope Addr
#ifndef XINCX_2_4G_CRC_SCOPE_ADDR
#define XINCX_2_4G_CRC_SCOPE_ADDR 1
#endif
// <q> XINCX_2_4G_LONG_PLD - 2.4g Long Payload Feature
#ifndef XINCX_2_4G_LONG_PLD
#define XINCX_2_4G_LONG_PLD 1
#endif
// <q> XINCX_2_4G_FEC - 2.4g FEC&Interleave Feature
#ifndef XINCX_2_4G_FEC
#define XINCX_2_4G_FEC 1
#endif
// <q> XINCX_2_4G_WHITEN - 2.4g Whiten Feature
#ifndef XINCX_2_4G_WHITEN
#define XINCX_2_4G_WHITEN 1
#endif
// XINCX_2_4G_DPL - 2.4g Dynamic Payload Length Feature
#ifndef XINCX_2_4G_DPL
#define XINCX_2_4G_DPL 1
#endif
// XINCX_2_4G_ACK_PAY - 2.4g Payload on ACK
#ifndef XINCX_2_4G_ACK_PAY
#define XINCX_2_4G_ACK_PAY 1
#endif
// XINCX_2_4G_DYN_ACK - 2.4g W_TX_PAYLOAD_NOACK Command
#ifndef XINCX_2_4G_DYN_ACK
#define XINCX_2_4G_DYN_ACK 1
#endif
// XINCX_2_4G_DYNPD - 2.4g dynpd
#ifndef XINCX_2_4G_DYNPD
#define XINCX_2_4G_DYNPD 0x3f
#endif
// XINCX_2_4G_AUTO_ACK - 2.4g Auto Acknowledgement
//==========================================================
// XINCX_2_4G_PIPE0_ENAA - 2.4g Pipe0 Auto Ack
#ifndef XINCX_2_4G_PIPE0_ENAA
#define XINCX_2_4G_PIPE0_ENAA 1
#endif
// XINCX_2_4G_PIPE1_ENAA - 2.4g Pipe1 Auto Ack
#ifndef XINCX_2_4G_PIPE1_ENAA
#define XINCX_2_4G_PIPE1_ENAA 1
#endif
// XINCX_2_4G_PIPE2_ENAA - 2.4g Pipe2 Auto Ack
#ifndef XINCX_2_4G_PIPE2_ENAA
#define XINCX_2_4G_PIPE2_ENAA 1
#endif
// XINCX_2_4G_PIPE3_ENAA - 2.4g Pipe3 Auto Ack
#ifndef XINCX_2_4G_PIPE3_ENAA
#define XINCX_2_4G_PIPE3_ENAA 1
#endif
// XINCX_2_4G_PIPE4_ENAA - 2.4g Pipe4 Auto Ack
#ifndef XINCX_2_4G_PIPE4_ENAA
#define XINCX_2_4G_PIPE4_ENAA 1
#endif
// XINCX_2_4G_PIPE5_ENAA - 2.4g Pipe5 Auto Ack
#ifndef XINCX_2_4G_PIPE5_ENAA
#define XINCX_2_4G_PIPE5_ENAA 1
#endif
// <o.0..5> XINCX_RF_PIPE_ENABLE
#ifndef XINCX_RF_PIPE_ENABLE
#define XINCX_RF_PIPE_ENABLE 1
#endif
// XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
//==========================================================
// <o> XINCX_2_4G_RETRANS_CNT - 2.4g Retransmit Count
// <i> Number of retransmissions. The maximum number of times a hardware can automatically transmit an ACK if it does
// not receive the correct ACK.
// <0=> No retransmission
// <1=> 1 time
// <2=> 2 times
// <3=> 3 times
// <4=> 4 times
// <5=> 5 times
// <6=> 6 times
// <7=> 7 times
// <8=> 8 times
// <9=> 9 times
// <10=> 10 times
// <11=> 11 times
// <12=> 12 times
// <13=> 13 times
// <14=> 14 times
// <15=> 15 times
#ifndef XINCX_2_4G_RETRANS_CNT
#define XINCX_2_4G_RETRANS_CNT 0
#endif
// <o> XINCX_2_4G_RETRANS_DELAY - 2.4g Retransmission Delay
// <i> Retransmission delay. For 32 bytes of data, the minimum configuration is 500 us for 1 Mbit/s and 1500 us for 250
// kbit/s.
// <0=> 250us
// <1=> 500us
// <2=> 750us
// <3=> 1000us
// <4=> 1250us
// <5=> 1500us
// <6=> 1750us
// <7=> 2000us
// <8=> 2250us
// <9=> 2500us
// <10=> 2750us
// <11=> 3000us
// <12=> 3250us
// <13=> 3500us
// <14=> 3750us
// <15=> 4000us
#ifndef XINCX_2_4G_RETRANS_DELAY
#define XINCX_2_4G_RETRANS_DELAY 3
#endif
#endif
// </e> //XINCX_RF_PEACKET_MODE enhanced normal
// RF 2.4g Compatibility configuration
//==========================================================
// Compatibility configuration, when you need to be compatible with other RF chips, you don't need to configure this
// option when using our company's chips.
// XINCX_2_4G_PREAMBLE - 2.4g preamble
#ifndef XINCX_2_4G_PREAMBLE
#define XINCX_2_4G_PREAMBLE 0x710f5555
#endif
// XINCX_2_4G_GUARD - 2.4g guard
#ifndef XINCX_2_4G_GUARD
#define XINCX_2_4G_GUARD 0x8fc9
#endif
//
// XINCX_2_4G_CRY_CPT_ARRAY - 2.4g Crystal capacitor array
//==========================================================
// Crystal capacitor array, adjust to modify the frequency offset of the crystal oscillator.
// XINCX_2_4G_CRY_CPT_ARRAY - 2.4g Crystal capacitor array
#ifndef XINCX_2_4G_CRY_CPT_ARRAY
#ifdef XC62XX
#define XINCX_2_4G_CRY_CPT_ARRAY 0x38
#else
#define XINCX_2_4G_CRY_CPT_ARRAY 0x36
#endif
#endif
//
// <<< end of configuration section >>>
#endif // SDK_CONFIG_H
project/example/2.4g/RF24_ADV_Hw/app/src/app_64m.c
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#include "app_64m.h"
void use_64m_crtstal_init(void)
{
testpin_64M_config();
xc_pwr_pwrkey_init();
Init_rtc_gpio(4, 0x00);
}
__RAM_CODE void rf_64M_set_rx_channel(uint16_t channel)
{
channel -= 1;
uint16_t ch = channel % 2;
XC_RF_2_4G->RF_CH &= ~(0x3fff);
switch (ch) {
case 0:
XC_RF_2_4G->RF_CH |= (channel / 2);
*((uint32_t volatile *)0x53022064) = (((channel / 2) << 16));
break;
case 1:
XC_RF_2_4G->RF_CH |= (channel / 2);
*((uint32_t volatile *)0x53022064) = (((channel / 2) << 16) | 0x80008000);
break;
default:
break;
}
(*(volatile unsigned int *)(0x53023010)) &= ~((1 << 24) | (2 << 28));
}
__RAM_CODE void rf_64M_set_tx_channel(uint16_t channel)
{
uint16_t ch = channel % 2;
XC_RF_2_4G->RF_CH &= ~(0x3fff);
switch (ch) {
case 0:
XC_RF_2_4G->RF_CH |= (channel / 2);
*((uint32_t volatile *)0x53022064) = (((channel / 2) << 16));
break;
case 1:
XC_RF_2_4G->RF_CH |= (channel / 2 + 1);
*((uint32_t volatile *)0x53022064) = (((channel / 2) << 16) | 0x80008000);
break;
default:
break;
}
(*(volatile unsigned int *)(0x53023010)) |= ((0x3 << 16) | (1 << 24) | (2 << 28));
}
void testpin_64M_config(void)
{
uint32_t val;
val = (*(volatile unsigned int *)(0x53022040));
val |= (0x7 << 4) | (0x7);
(*(volatile unsigned int *)(0x53022040)) = val; // TPORT_DATA0_SEL set
val = (*(volatile unsigned int *)(0x40000134));
(*(volatile unsigned int *)(0x40000134)) = ((val & ~(0xfu << 28)) | (1u << 28)); // testpin1_ctrl[3:0]=1
// printf("after 0x40000134=0x%x, 0x40000134=0x%x\n", *(volatile unsigned int *)(0x40000134),
// *(volatile unsigned int *)(0x40000134));
val = (*(volatile unsigned int *)(0x53023010));
val &= ~(3 << 28);
#if 1 // diag = 0xc //diag = 0x3
val |= (0x3 << 20) | (0x3 << 16 | 1 << 24 | 2 << 28); // 0xc
(*(volatile unsigned int *)(0x53023010)) = val; // diag_sel[3:0] set
#endif
// LOGI("after 0x53022040=0x%x, 0x53022010=0x%x\n", *(volatile unsigned int *)(0x53022040),
//*(volatile unsigned int *)(0x53023010));
uint32_t addr_val = 0;
xc_gpio_fun_sel(GPIO_4, GPIO_Dx);
xc_gpio_mux_ctl(GPIO_4, GPIO_Mux3); // en test_pin[1]
addr_val = 0x40000174;
*((uint32_t volatile *)addr_val) = 7;
}
void Init_rtc_gpio(uint32_t num, uint8_t inter_mode)
{
uint32_t val;
// if(!((inter_mode>=0x08) &&(inter_mode<=0x0c))) return;
__write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL, 0x20002);
__write_hw_reg32(CPR_AOCLKEN_GRCTL, 0x20002);
__read_hw_reg32(AO_GPIO_MODE, val);
val &= ~(0x0f << (num << 2));
val |= (inter_mode << (num << 2));
__write_hw_reg32(AO_GPIO_MODE, val);
__read_hw_reg32(AO_GPIO_CTL, val);
val |= (1 << (8 + num));
__write_hw_reg32(AO_GPIO_CTL, val);
// rtc_ao_gpio_mode__aogpio_debounce_en3__setf(1);
NVIC_EnableIRQ(RTC_IRQn);
}
project/example/2.4g/RF24_ADV_Hw/app/src/main.c
+394
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/*!
* \file main.c
*
* \brief Target main implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Howl-C
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "main.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Static Variables
-------------------------------------------------------------------------------------*/
uint8_t rx_buff[256] = {0};
uint16_t rx_len = 0;
bool rf24g_rx_irq_flag = false;
bool rf24g_tx_irq_flag = true;
uint8_t tx_buff[256] = {0};
/*------------------------------------------------------------------------------------
Func Prototype
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
/**
****************************************************************************************
* @brief Clock Initialization
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void clock_init(void)
{
CLOCK_InitCfg_t clock_cfg;
clock_cfg.hfclk_src = CLOCK_HFCLK_SRC_XTAL;
clock_cfg.hfclk_in = CLOCK_HFCLK_IN_32M;
#if (RC_32K)
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_RC;
#endif //(RC_32K)
#if (XTAL_32K)
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL;
#endif // (XTAL_32K)
#if (XTAL_32768K)
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL;
#endif // (XTAL_32768K)
#ifdef XC62XX
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_RC;
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32K;
#else
if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_XTAL) {
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32768;
} else if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_RC) {
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32K;
}
#endif
xc_clock_init_cfg(&clock_cfg);
SysTick_Config(xc_clock_hfclk_in_get() / 100);
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
}
#ifdef DEBUG_LOG
/**
* @brief RF 2.4g register information printing
* @param void
* @retval void
*/
void rf_2M_reg_info(void)
{
/* Register information printing */
LOGI("CFG_TOP: 0x%08x\r\n", XC_RF_2_4G->CFG_TOP);
LOGI("TXPROC_CFG: 0x%08x\r\n", XC_RF_2_4G->TXPROC_CFG);
LOGI("RXPROC_CFG_L: 0x%08x\r\n", XC_RF_2_4G->RXPROC_CFG_L);
LOGI("RF_CH: 0x%08x\r\n", XC_RF_2_4G->RF_CH);
LOGI("rccal_reg_l: 0x%08x\r\n", XC_BT_RF->rccal_reg_l);
LOGI("ana2_reg_l: 0x%08x\r\n", XC_BT_RF->ana2_reg_l);
LOGI("ana3_reg_l: 0x%08x\r\n", XC_BT_RF->ana3_reg_l);
LOGI("ana4_reg_l: 0x%08x\r\n", XC_BT_RF->ana4_reg_l);
LOGI("ana5_reg_l: 0x%08x\r\n", XC_BT_RF->ana5_reg_l);
LOGI("ana14_reg_l: 0x%08x\r\n", XC_BT_RF->ana14_reg_l);
LOGI("ana15_reg_l: 0x%08x\r\n", XC_BT_RF->ana15_reg_l);
LOGI("ana16_reg_l: 0x%08x\r\n", XC_BT_RF->ana16_reg_l);
LOGI("ana17_reg_l: 0x%08x\r\n", XC_BT_RF->ana17_reg_l);
LOGI("ana18_reg_l: 0x%08x\r\n", XC_BT_RF->ana18_reg_l);
LOGI("ana21_reg_l: 0x%08x\r\n", XC_BT_RF->ana21_reg_l);
LOGI("AON_RF_AONREG: 0x%08x\r\n", cprao_aon_rf_aonreg_get()); // 0x36
}
/**
* @brief Rf 2.4g dump log
* @param void
*
* @retval void
*/
void rf_dump_log(void)
{
LOGI("***************** 2.4G Param ******************\n");
LOGI("CFG_TOP: 0x%08x\r\n", XC_RF_2_4G->CFG_TOP);
LOGI("EN_AA: 0x%08x\r\n", XC_RF_2_4G->EN_AA);
LOGI("EN_RXADDR: 0x%08x\r\n", XC_RF_2_4G->EN_RXADDR);
LOGI("SETUP_AW: 0x%08x\r\n", XC_RF_2_4G->SETUP_AW);
LOGI("SETUP_RETR: 0x%08x\r\n", XC_RF_2_4G->SETUP_RETR);
LOGI("RF_CH: 0x%08x\r\n", XC_RF_2_4G->RF_CH);
LOGI("SETUP_RF: 0x%08x\r\n", XC_RF_2_4G->SETUP_RF);
LOGI("STATUS: 0x%08x\r\n", XC_RF_2_4G->STATUS);
LOGI("OBSERVE_TX: 0x%08x\r\n", XC_RF_2_4G->OBSERVE_TX);
LOGI("RSSI: 0x%08x\r\n", XC_RF_2_4G->RSSI);
LOGI("RX_ADDR_P0: 0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RX_ADDR_P0_H), XC_RF_2_4G->RX_ADDR_P0_L);
LOGI("RX_ADDR_P1: 0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RX_ADDR_P1_H), XC_RF_2_4G->RX_ADDR_P1_L);
LOGI("RX_ADDR_P2TOP5:0x%08x\r\n", XC_RF_2_4G->RX_ADDR_P2TOP5);
LOGI("BER_RESULT: 0x%08x%08x\r\n", XC_RF_2_4G->BER_ERR_CNT, XC_RF_2_4G->BER_RECV_CNT);
LOGI("AGC_SETTING: 0x%08x\r\n", XC_RF_2_4G->AGC_SETTING);
LOGI("PGA_SETTING: 0x%02x %08x\r\n", ((XC_RF_2_4G->TX_ADDR_H) & 0xFF00) >> 8, XC_RF_2_4G->PGA_SETTING);
LOGI("TX_ADDR: 0x%02x %08x\r\n", ((XC_RF_2_4G->TX_ADDR_H) & 0xFF), XC_RF_2_4G->TX_ADDR_L);
LOGI("RX_PW_PX: 0x%04x %08x\r\n", 0xFFFF & (XC_RF_2_4G->RX_PW_Px_H), XC_RF_2_4G->RX_PW_Px_L);
LOGI("STATUS_FIFO: 0x%08x\r\n", XC_RF_2_4G->STATUS_FIFO);
LOGI("RSSIREC: 0x%08x\r\n", XC_RF_2_4G->RSSIREC);
LOGI("TXPROC_CFG: 0x%08x\r\n", XC_RF_2_4G->TXPROC_CFG);
LOGI("RXPROC_CFG: 0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RXPROC_CFG_H), XC_RF_2_4G->RXPROC_CFG_L);
LOGI("DYNPD: 0x%08x\r\n", XC_RF_2_4G->DYNPD);
LOGI("FEATURE: 0x%08x\r\n", XC_RF_2_4G->FEATURE);
LOGI("PGA_SETTING_H: 0x%08x\r\n", XC_RF_2_4G->TX_ADDR_H);
#ifdef XC62XX
LOGI("HW_CONFIG: 0x%08x\r\n", XC_RF_2_4G->HW_CONFIG);
LOGI("PBT_CONFIG: 0x%08x\r\n", XC_RF_2_4G->PBT_CONFIG);
LOGI("PBT_TIMER: 0x%08x\r\n", XC_RF_2_4G->PBT_TIMER);
LOGI("PBT_SYNC_TIME: 0x%08x\r\n", XC_RF_2_4G->PBT_SYNC_TIME);
LOGI("PBT_TX_HEAD: 0x%08x\r\n", XC_RF_2_4G->PBT_TX_HEAD);
LOGI("PBT_RX_HEAD: 0x%08x\r\n", XC_RF_2_4G->PBT_RX_HEAD);
LOGI("PBT_AUTO_TRX_TIME: 0x%08x\r\n", XC_RF_2_4G->PBT_AUTO_TRX_TIME);
#endif
LOGI("TX_POWER 0x%08x\r\n", (XC_BT_RF->ana21_reg_l >> 6) & 0x3f);
LOGI("ana11_reg_l: 0x%08x\r\n", XC_BT_RF->ana11_reg_l);
LOGI("***********************************************\n");
LOGI("\r\n");
}
#endif // DEBUG_LOG
/**
* @brief RF 2.4g buff info
* @param uint8_t * - buff
* uint8_t len
* @retval void
*/
void rf_buff_info(uint8_t *buff, uint16_t len)
{
for (uint16_t i = 0; i < len; i++)
LOGI("%02x ", buff[i]);
LOGI("\r\n");
}
void app_uart_init(void)
{
GPIO_InitCfg_t gpio_cfg = {0};
gpio_cfg.Mux = GPIO_Mux0;
gpio_cfg.Pull = GPIO_PULLUP;
gpio_cfg.Int = NOT_INT;
gpio_cfg.FunSel = UART0_TX;
gpio_cfg.Pin = GPIO_18;
gpio_cfg.Dir = GPIO_DIR_OUTPUT;
xc_gpio_init(&gpio_cfg);
gpio_cfg.FunSel = UART0_RX;
gpio_cfg.Pin = GPIO_19;
gpio_cfg.Dir = GPIO_DIR_INPUT;
xc_gpio_init(&gpio_cfg);
UART_InitCfg_t uart_cfg = {0};
uart_cfg.Parity = UART_PARITY_DISABLE;
uart_cfg.StopBits = UART_STOP_1_BITS;
uart_cfg.WordLength = UART_DATA_8_BITS;
uart_cfg.BaudRate = UART_BAUDRATE_115200;
uart_cfg.HardwareFlowControl = UART_HWFC_DISABLE;
xc_uart_init(UART0_IDX, &uart_cfg);
}
/* switch mode and set channel */
void rf_switch_mode(uint8_t mode, uint16_t channel)
{
CE_CTL_LOW;
uint8_t rf_mode = 0;
switch (mode) {
case TRX_MODE:
case TX_MODE:
break;
case RX_MODE:
rf_mode = 1;
break;
default:
LOGI("The mode is set incorrectly\n");
return;
}
set_rf_mode(mode);
rf_set_channel(channel);
XC_RF_2_4G->STATUS = MASK_ALL_INTER;
rf_wr_cmd(FLUSH_RX);
rf_wr_cmd(FLUSH_TX);
if (rf_mode) {
CE_CTL_HIGH;
}
}
/* RF发送完成回调 */
void rf_24g_tx_ds_cb(void)
{
/* set flag */
rf24g_tx_irq_flag = true;
}
/* RF接收完成回调 */
void rf_24g_rx_dr_cb(void)
{
/* stop RF */
CE_CTL_LOW;
/* set flag */
rf24g_rx_irq_flag = true;
/* recv data */
rx_len = rf_rx_packet(rx_buff);
}
uint8_t rf24g_adv_packet(uint8_t *buff)
{
uint8_t l = 0;
uint8_t rf_adv_data_complete_name[26] = {"RF-ADV-TEST-123456789BLE52"};
/* hearder */
buff[l++] = 0x42;
buff[l++] = 37;
/* BLE MAC address */
buff[l++] = MAC_ADDR_0;
buff[l++] = MAC_ADDR_1;
buff[l++] = MAC_ADDR_2;
buff[l++] = MAC_ADDR_3;
buff[l++] = MAC_ADDR_4;
buff[l++] = MAC_ADDR_5;
/* Flags */
buff[l++] = 0x02;
buff[l++] = 0x01;
buff[l++] = 0x06;
/* Complete Local Name */
buff[l++] = 27;
buff[l++] = 0x09;
memcpy(&buff[l], rf_adv_data_complete_name, sizeof(rf_adv_data_complete_name));
l += sizeof(rf_adv_data_complete_name);
/* CRC */
buff[l++] = 0x55;
buff[l++] = 0x55;
buff[l++] = 0x55;
return l;
}
void rf24g_adv_hw_tx_demo()
{
uint8_t len = 0;
uint32_t tx_cnt = 0;
LOGI("************ADV Send Start**************\r\n");
rf_pbt_init();
/* Set the communication mode */
rf_switch_mode(TX_MODE,XINCX_ADV_CHANNEL);
while (1)
{
if (rf24g_tx_irq_flag)
{
rf24g_tx_irq_flag = false;
len = rf24g_adv_packet(tx_buff);
uint8_t tx_handler[3] = {len, tx_buff[0]};
rf_set_pbt_tx_head(tx_handler);
tx_cnt += 1;
LOGI("tx_cnt:%d,len:%d\n", tx_cnt,len);
rf_tx_packet(&tx_buff[2], len);
delay_ms(10);
}
}
}
void rf24g_adv_hw_rx_demo()
{
uint32_t rx_cnt = 0;
LOGI("************ADV Recv Start**************\r\n");
rf_pbt_init();
/* Set the communication mode */
rf_switch_mode(RX_MODE,XINCX_ADV_CHANNEL);
/* Entering the receiver */
CE_CTL_HIGH;
while (1)
{
if (rf24g_rx_irq_flag)
{
rf24g_rx_irq_flag = false;
/* Entering standby mode */
CE_CTL_LOW;
// for (int i = 0; i < rx_len; i++)
// printf("%02x "),rx_buff[i];
// printf("\r\n");
rx_cnt += 1;
LOGI("rx_cnt:%d,len:%d\n", rx_cnt,rx_len);
rx_len = 0;
/* Entering the receiver */
CE_CTL_HIGH;
}
}
}
int main(void)
{
/* Clock initialization */
clock_init();
/* Serial port initialization */
app_uart_init();
/* Simulate broadcast initialization */
rf24g_adv_init();
#if (XINCX_RF_NVIC_MODE)
/* Enable RF2.4G interrupts */
NVIC_EnableIRQ(RF24G_IRQn);
/* Configure the RF2.4G interrupt priority */
NVIC_SetPriority(RF24G_IRQn, 0);
#endif // XINCX_RF_NVIC_MODE
xc_system_param_check_rf24g();
#if XINCX_ADV_MODE == TX_MODE
rf24g_adv_hw_tx_demo();
#elif XINCX_ADV_MODE == RX_MODE
rf24g_adv_hw_rx_demo();
#endif
while(true);
}
project/example/2.4g/RF24_ADV_Hw/app/src/rf_compatible_normal.c
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#include "rf_compatible_normal.h"
uint16_t crc = 0;
uint8_t panchip_data_length = XINCX_2_4G_PIPE0_LEN - XINCX_2_4G_CRC_BYTE;
uint16_t rf_addr_crc = 0;
uint8_t panchip_addr_whiten;
uint8_t addr_buff[5] = {0};
uint32_t send_cnt = 0;
uint32_t recv_cnt = 0;
/**
* @brief Rf 2.4g get addr
* @param uint8_t *addr_buff
*
* @retval void
*/
void rf_addr_map(uint8_t *addr_buff)
{
uint8_t addr_xsb = (XC_RF_2_4G->CFG_TOP >> 11) & (0x1);
LOGI("addr_xsb %02x\r\n", addr_xsb);
if (!addr_xsb) {
addr_buff[0] = (XC_RF_2_4G->TX_ADDR_L >> 0) & 0xff;
addr_buff[1] = (XC_RF_2_4G->TX_ADDR_L >> 8) & 0xff;
addr_buff[2] = (XC_RF_2_4G->TX_ADDR_L >> 16) & 0xff;
addr_buff[3] = (XC_RF_2_4G->TX_ADDR_L >> 24) & 0xff;
addr_buff[4] = (XC_RF_2_4G->TX_ADDR_H >> 0) & 0xff;
} else {
addr_buff[1] = (XC_RF_2_4G->TX_ADDR_L >> 24) & 0xff;
addr_buff[2] = (XC_RF_2_4G->TX_ADDR_L >> 16) & 0xff;
addr_buff[3] = (XC_RF_2_4G->TX_ADDR_L >> 8) & 0xff;
addr_buff[4] = (XC_RF_2_4G->TX_ADDR_L >> 0) & 0xff;
addr_buff[0] = (XC_RF_2_4G->TX_ADDR_H >> 0) & 0xff;
}
}
/**
* @brief RF 2.4g get address crc
* @param void
* @retval crc data
*/
uint16_t rf_get_addr_crc(void)
{
#if (1 == XINCX_2_4G_CRC_BYTE)
return crc8_rohc(addr_buff, RF_ADDR_LEN, RF_CRC_INIT_VALUE, PACKET_NORMAL);
#elif (2 == XINCX_2_4G_CRC_BYTE)
return crc16_ccitt_false(addr_buff, RF_ADDR_LEN, RF_CRC_INIT_VALUE, PACKET_NORMAL);
#endif
}
/**
* @brief Address whitening and writing
* @param void
* @retval uint8_t whiten_addr
*/
uint8_t rf_recv_addr(void)
{
uint16_t whiten_addr = whiten_data((uint8_t *)addr_buff, RF_ADDR_LEN, PANCHIP_WHITEN_INIT_VAL);
/* Set PTX address */
set_rf_txaddr((addr_buff[0] << 0) | (addr_buff[1] << 8) | (addr_buff[2] << 16) | (addr_buff[3] << 24),
(addr_buff[4]));
/* Set PRX address */
set_rf_pipe0_rxaddr((addr_buff[0] << 0) | (addr_buff[1] << 8) | (addr_buff[2] << 16) | (addr_buff[3] << 24),
(addr_buff[4]));
return whiten_addr;
}
void rf_compatible_config(void)
{
#if (XINCX_RF_COMPATIBILITY_MODE == BELKEN_PACKET)
#if XC62XX
set_rf_retr(XINCX_2_4G_RETRANS_CNT, XINCX_2_4G_RETRANS_DELAY);
XC_RF_2_4G->FEATURE &= ~(1 << 5);
rf_set_ack_type(1);
rf_set_freq_dev(RF_FREQ_DEV);
#endif
#elif (XINCX_RF_COMPATIBILITY_MODE == PANCHIP_PACKET)
XC_RF_2_4G->FEATURE |= (1 << 11) | (2 << 12) | (1 << 14) | (1 << 18);
XC_RF_2_4G->PREAMBLE = 0x710f55;
/* 白化cc2500、同步字中断、CRC中断 */
XC_RF_2_4G->CFG_TOP |= (1 << 30) | (1 << 22);
/* get addr */
rf_addr_map(addr_buff);
/* Calculate the CRC of the address block */
rf_addr_crc = rf_get_addr_crc();
/* The address range is whitened and the whitened address is rewritten */
panchip_addr_whiten = rf_recv_addr();
#if XC62XX
rf_set_whiten_value(panchip_addr_whiten);
rf_set_fifo_len(1);
#else
XC_RF_2_4G->FEATURE |= (1 << 5);
XC_RF_2_4G->CFG_TOP &= ~(0x7f << 23);
XC_RF_2_4G->CFG_TOP |= (panchip_addr_whiten << 23);
#endif
set_rf_crc(CRC_0BYTE);
#endif
}
uint8_t rf_panchip_normal_recv_data_cfg(uint8_t *buff, uint8_t len)
{
if (len == 0) {
return 1;
}
uint16_t crc_data = 0;
/* Whiten */
whiten_data(buff, len + 2, panchip_addr_whiten);
/* CRC */
crc = ~crc16_ccitt_false(buff, len, rf_addr_crc, PACKET_NORMAL);
crc_data = ((buff[len] << 8) | (buff[len + 1]));
if (crc == crc_data) {
buff_bigandsmallend(buff, len);
} else {
len = 0;
}
return len;
}
uint8_t rf_panchip_normal_send_data_cfg(uint8_t *buff, uint8_t len)
{
if (len == 0) {
return 1;
}
buff_bigandsmallend(buff, len);
crc = ~crc16_ccitt_false(buff, panchip_data_length, rf_addr_crc, PACKET_NORMAL);
buff[panchip_data_length] = (crc >> 8) & 0xff;
buff[panchip_data_length + 1] = crc & 0xff;
/* Whiten */
whiten_data(buff, len + 2, panchip_addr_whiten);
return 0;
}
uint32_t rf_rx_normal_manage(void)
{
if (rf24g_rx_irq_flag) {
rf24g_rx_irq_flag = false;
/* Entering standby mode */
CE_CTL_LOW;
uint8_t len = recv_len;
#if (DEBUG_PIN)
xc_gpio_write_pin(TEST_PIN_2, GPIO_PIN_SET);
#endif
len = rf_panchip_normal_recv_data_cfg(recv_buf, len - 2);
if (len) {
#if (DEBUG_PIN)
xc_gpio_write_pin(TEST_PIN_1, GPIO_PIN_SET);
#endif
// rf_buff_info(recv_buf, len);
/* Receive Count */
recv_cnt++;
LOGI("recv:%d, len:%d\r\n", recv_cnt, len);
/* Receive read data buffer reset */
memset(recv_buf, 0, len);
len = 0;
}
#if (DEBUG_PIN)
xc_gpio_write_pin(TEST_PIN_1, GPIO_PIN_RESET);
xc_gpio_write_pin(TEST_PIN_2, GPIO_PIN_RESET);
#endif
/* Entering the receiver */
CE_CTL_HIGH;
}
return 0;
}
uint32_t rf_tx_normal_manage(uint8_t *buff, uint8_t length)
{
if (rf24g_tx_irq_flag) {
rf24g_tx_irq_flag = false;
buff[0] = send_cnt++;
/* Filling in software frame number */
LOGI("data len:%d, send_cnt:%d\n", length - XINCX_2_4G_CRC_BYTE, send_cnt);
// rf_buff_info(buff, length);
rf_panchip_normal_send_data_cfg(buff, length - XINCX_2_4G_CRC_BYTE);
/* data transmission */
rf_tx_packet(buff, length);
}
return 0;
}
project/example/2.4g/RF24_ADV_Hw/mdk/JLinkSettings.ini
+46
View File
@@ -0,0 +1,46 @@
[BREAKPOINTS]
ForceImpTypeAny = 0
ShowInfoWin = 1
EnableFlashBP = 2
BPDuringExecution = 0
[CFI]
CFISize = 0x00
CFIAddr = 0x00
[CPU]
MonModeVTableAddr = 0xFFFFFFFF
MonModeDebug = 0
MaxNumAPs = 0
LowPowerHandlingMode = 0
OverrideMemMap = 0
AllowSimulation = 1
ScriptFile=""
[FLASH]
RMWThreshold = 0x400
Loaders=""
EraseType = 0x00
CacheExcludeSize = 0x00
CacheExcludeAddr = 0x00
MinNumBytesFlashDL = 0
SkipProgOnCRCMatch = 1
VerifyDownload = 1
AllowCaching = 1
EnableFlashDL = 2
Override = 0
Device="ARM7"
[GENERAL]
WorkRAMSize = 0x00
WorkRAMAddr = 0x00
RAMUsageLimit = 0x00
[SWO]
SWOLogFile=""
[MEM]
RdOverrideOrMask = 0x00
RdOverrideAndMask = 0xFFFFFFFF
RdOverrideAddr = 0xFFFFFFFF
WrOverrideOrMask = 0x00
WrOverrideAndMask = 0xFFFFFFFF
WrOverrideAddr = 0xFFFFFFFF
[RAM]
VerifyDownload = 0x00
[DYN_MEM_MAP]
NumUserRegion = 0x00
project/example/2.4g/RF24_ADV_Hw/mdk/Linker/Initialization.ini
+12
View File
@@ -0,0 +1,12 @@
FUNC void Initialization(void)
{
SP = _RDWORD(0x10000000);
PC = _RDWORD(0x10000004);
}
LOAD %L INCREMENTAL
Initialization();
project/example/2.4g/RF24_ADV_Hw/mdk/Linker/XIPInitialization.ini
+84
View File
@@ -0,0 +1,84 @@
FUNC void InitGpio(void)
{
// Config IOMUX
/*
gpio_mux_ctl_u(33,1);//d2
gpio_mux_ctl_u(34,1);//d3
gpio_mux_ctl_u(35,2);//clk
gpio_mux_ctl_u(36,2);//cs
gpio_mux_ctl_u(37,2);//d0 rx
gpio_mux_ctl_u(38,2);//d1 tx
*/
_WDWORD(0x4000019c, 0x00002A94);
}
FUNC void InitFlash(void)
{
}
FUNC void InitXIP(void)
{
_WDWORD(0x40000104,0x040000);//reset ssi0
_WDWORD(0x40000104,0x040004);//reset ssi0
_WDWORD(0x40000050,0x110000);//close spi0 mclk
_WDWORD(0x40000070,0x1000000);//close spi0 pclk
//config fmc
_WDWORD(0x40000270, 0x0503);
_Sleep_(1);// delay about 400us
_WDWORD(0x40000270, 0x3503);
//config cache
_Sleep_(1);// delay about 400us
_WDWORD(0x52000000, 0x0);
_Sleep_(1);// delay about 400us
_WDWORD(0x52000000, 0x21);
_Sleep_(1);// delay about 400us
_Sleep_(1);// delay about 400us
_Sleep_(1);// delay about 400us
_Sleep_(1);// delay about 400us
//config xip spi
_WDWORD(0x51000008, 0); //disable spi
_WDWORD(0x5100002c,0); //close IE
_WDWORD(0x51000000,0x1F); //32bit SPI data
_WDWORD(0x51000010,0x01); //enable select slave -- SE
_WDWORD(0x51000018,0x0); //TXFTL be set 0
_WDWORD(0x5100001c,0x0); //RXFTL be set 0
_WDWORD(0x5100010c, 0x01);//enable select slave
_WDWORD(0x51000114, 0xFF);//XIP time out
_WDWORD(0x51000014, 0x2);//div 2
//quad
// _WDWORD(0x51000108, (2)|(6<<4)|(2<<9)|(1<<22)|(1<<29)|(1<<23)|(0<<24)|(8<<13));
// _WDWORD(0x51000100, 0x6b);//quad read cmd
// _WDWORD(0x51000104, 0x6b);//quad read cmd
//dual
_WDWORD(0x51000108, (1)|(6<<4)|(2<<9)|(1<<22)|(1<<29)|(1<<23)|(0)|(8<<13));
_WDWORD(0x51000100, 0x3b);//dual read cmd
_WDWORD(0x51000104, 0x3b);//dual read cmd
_WDWORD(0x51000008, 1); //enable spi
}
FUNC void Initialization(void)
{
InitGpio();
InitFlash();
InitXIP();
SP = _RDWORD(0x11001000);
PC = _RDWORD(0x11001004);
_WDWORD(0x4000013C, 0x11001001);
}
LOAD %L INCREMENTAL
Initialization();
project/example/2.4g/RF24_ADV_Hw/mdk/Linker/cpu.scat
+18
View File
@@ -0,0 +1,18 @@
LOAD 0x10000000
{
EXE 0x10000000
{
startup_xinc.o (RESET, +FIRST)
* (+RO)
}
RW +0000
{
* (+RW,+ZI)
}
;ScatterAssert(ImageLength(RW) < 1024 * 28)
}
project/example/2.4g/RF24_ADV_Hw/mdk/Linker/cpu_xip.scat
+25
View File
@@ -0,0 +1,25 @@
LOAD 0x11001000
{
EXE 0x11001000
{
startup_xinc.o (RESET, +FIRST)
* (+RO)
}
RW 0x10002000
{
* (+RW,+ZI)
*(ram_code)
aeabi_sdiv.o(.text)
}
ScatterAssert((0x10000100 )+ImageLength(RW) < 0x10000100 + 1024 * 32)
RW2 (0x53004000)
{
*(ram_em)
}
ScatterAssert((0x53004000 )+ImageLength(RW2) < 0x53004000 + 1024 * 16)
}
project/example/2.4g/RF24_ADV_Hw/mdk/Linker/cpu_xip_xc62xx.scat
+21
View File
@@ -0,0 +1,21 @@
LOAD 0x11001000
{
EXE 0x11001000
{
startup_xinc.o (RESET, +FIRST)
* (+RO)
}
RW 0x100000C8 0x1F38
{
* (+RW,+ZI)
*(ram_code)
aeabi_sdiv.o(.text)
}
ScatterAssert( ImageLength(RW) < 1024 * 8)
}
project/example/2.4g/RF24_ADV_Hw/mdk/Output/0_ram.bin
BIN
View File
Binary file not shown.
project/example/2.4g/RF24_ADV_Hw/mdk/Output/Rf24DemoXip.bin
BIN
View File
Binary file not shown.
project/example/2.4g/RF24_ADV_Hw/mdk/Output/ram_program.bat
+1
View File
@@ -0,0 +1 @@
Xincboot_tool.exe 0_ram.bin 1_ram_download.bin 0 0 0 0 1
project/example/2.4g/RF24_ADV_Hw/mdk/Output/xip_dual
BIN
View File
Binary file not shown.
project/example/2.4g/RF24_ADV_Hw/mdk/Output/xip_program.bat
+1
View File
@@ -0,0 +1 @@
.\Tools\xinchip_xip_tool.exe .\Output\0_ram.bin .\Output\xip_dual .\Output\Rf24DemoXip.bin
project/example/2.4g/RF24_ADV_Hw/mdk/RF24_ADV_XC62XX.uvoptx
+644
View File
@@ -0,0 +1,644 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp; *.cc; *.cxx</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>rf_2_4g_adv_hw_xip_demo</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>7</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>0</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>BIN\UL2CM3.DLL</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>0</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
<Group>
<GroupName>Startup</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>5</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\..\component\xc6xx_drivers\Drivers\CMSIS\core_cm0.h</PathWithFileName>
<FilenameWithoutPath>core_cm0.h</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>2</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\app\Startup\xc60xx\startup_xinc.s</PathWithFileName>
<FilenameWithoutPath>startup_xinc.s</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>3</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
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<bDave2>0</bDave2>
<PathWithFileName>..\app\Startup\system_xinc.c</PathWithFileName>
<FilenameWithoutPath>system_xinc.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
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<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\app\Startup\system_it_xinc.c</PathWithFileName>
<FilenameWithoutPath>system_it_xinc.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>Application</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>5</FileNumber>
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<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\app\src\main.c</PathWithFileName>
<FilenameWithoutPath>main.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
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</File>
<File>
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<bDave2>0</bDave2>
<PathWithFileName>..\app\src\app_64m.c</PathWithFileName>
<FilenameWithoutPath>app_64m.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>7</FileNumber>
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<bDave2>0</bDave2>
<PathWithFileName>..\app\src\rf_compatible_normal.c</PathWithFileName>
<FilenameWithoutPath>rf_compatible_normal.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
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<bDave2>0</bDave2>
<PathWithFileName>..\app\api\sdk_config.h</PathWithFileName>
<FilenameWithoutPath>sdk_config.h</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>RF_Config</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
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<File>
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<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\app\rf_config\rf_adv_config.h</PathWithFileName>
<FilenameWithoutPath>rf_adv_config.h</FilenameWithoutPath>
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<bShared>0</bShared>
</File>
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project/example/2.4g/RF24_ADV_Hw/mdk/RF24_ADV_XC62XX.uvprojx
+683
View File
@@ -0,0 +1,683 @@
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</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x20000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>1</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
<uGnu>1</uGnu>
<useXO>0</useXO>
<v6Lang>3</v6Lang>
<v6LangP>3</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls>--gnu --diag_suppress=66</MiscControls>
<Define>XC62XX DEBUG_ENABLE USE_XIP=1 RF_DEMO PBT_INIT=1 RF_ADV_INTER</Define>
<Undefine></Undefine>
<IncludePath>..\app\api;..\..\..\..\..\component\xc6xx_drivers\Drivers;..\..\..\..\..\component\xc6xx_drivers\Drivers\CMSIS\Device;..\app\Startup;..\app\Startup\xc60xx;..\..\..\..\..\component\xc6xx_drivers\Drivers\test_case\CLOCK;..\..\..\..\..\component\xc6xx_drivers\Drivers\test_case\PWR;..\..\..\..\..\component\xc6xx_drivers\Drivers\Periph_HAL_Driver\Bitfields;..\..\..\..\..\component\xc6xx_drivers\Drivers\Periph_HAL_Driver\Ringbuffer;..\..\..\..\modules\shell\api;..\..\..\..\..\component\xc6xx_drivers\Drivers\CMSIS;..\..\..\..\..\component\xc6xx_drivers\Drivers\Periph_HAL_Driver;..\..\..\..\..\component\rf24\Drivers;..\..\..\..\..\component\rf24\Drivers\xc6xxx_rf_2_4g;..\..\..\..\..\component\xc6xx_drivers\Drivers\CMSIS\Device\xc_m0_register;..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver;..\app\rf_config;..\..\..\..\..\component\rf24\Drivers\xc_rf24g_register;..\..\..\..\..\component\rf24\Drivers\xc6xxx_rf_ADV</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<ClangAsOpt>1</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>.\Linker\cpu_xip_xc62xx.scat</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>Startup</GroupName>
<Files>
<File>
<FileName>core_cm0.h</FileName>
<FileType>5</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\CMSIS\core_cm0.h</FilePath>
</File>
<File>
<FileName>startup_xinc.s</FileName>
<FileType>2</FileType>
<FilePath>..\app\Startup\xc60xx\startup_xinc.s</FilePath>
</File>
<File>
<FileName>system_xinc.c</FileName>
<FileType>1</FileType>
<FilePath>..\app\Startup\system_xinc.c</FilePath>
</File>
<File>
<FileName>system_it_xinc.c</FileName>
<FileType>1</FileType>
<FilePath>..\app\Startup\system_it_xinc.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Application</GroupName>
<Files>
<File>
<FileName>main.c</FileName>
<FileType>1</FileType>
<FilePath>..\app\src\main.c</FilePath>
</File>
<File>
<FileName>app_64m.c</FileName>
<FileType>1</FileType>
<FilePath>..\app\src\app_64m.c</FilePath>
</File>
<File>
<FileName>rf_compatible_normal.c</FileName>
<FileType>1</FileType>
<FilePath>..\app\src\rf_compatible_normal.c</FilePath>
<FileOption>
<CommonProperty>
<UseCPPCompiler>2</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>0</IncludeInBuild>
<AlwaysBuild>2</AlwaysBuild>
<GenerateAssemblyFile>2</GenerateAssemblyFile>
<AssembleAssemblyFile>2</AssembleAssemblyFile>
<PublicsOnly>2</PublicsOnly>
<StopOnExitCode>11</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<FileArmAds>
<Cads>
<interw>2</interw>
<Optim>0</Optim>
<oTime>2</oTime>
<SplitLS>2</SplitLS>
<OneElfS>2</OneElfS>
<Strict>2</Strict>
<EnumInt>2</EnumInt>
<PlainCh>2</PlainCh>
<Ropi>2</Ropi>
<Rwpi>2</Rwpi>
<wLevel>0</wLevel>
<uThumb>2</uThumb>
<uSurpInc>2</uSurpInc>
<uC99>2</uC99>
<uGnu>2</uGnu>
<useXO>2</useXO>
<v6Lang>0</v6Lang>
<v6LangP>0</v6LangP>
<vShortEn>2</vShortEn>
<vShortWch>2</vShortWch>
<v6Lto>2</v6Lto>
<v6WtE>2</v6WtE>
<v6Rtti>2</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Cads>
</FileArmAds>
</FileOption>
</File>
<File>
<FileName>sdk_config.h</FileName>
<FileType>5</FileType>
<FilePath>..\app\api\sdk_config.h</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>RF_Config</GroupName>
<Files>
<File>
<FileName>rf_adv_config.h</FileName>
<FileType>5</FileType>
<FilePath>..\app\rf_config\rf_adv_config.h</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>RF_Drivers</GroupName>
<Files>
<File>
<FileName>xc6xxx_rf_2_4g.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\rf24\Drivers\xc6xxx_rf_2_4g\xc6xxx_rf_2_4g.c</FilePath>
</File>
<File>
<FileName>xc_software_crc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\rf24\Drivers\xc_rf24g_register\xc_software_crc.c</FilePath>
</File>
<File>
<FileName>xc6xxx_rf_ADV.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\rf24\Drivers\xc6xxx_rf_ADV\xc6xxx_rf_ADV.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Drivers</GroupName>
<Files>
<File>
<FileName>ringbuffer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\ringbuffer.c</FilePath>
</File>
<File>
<FileName>xc_drv_clock.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_clock.c</FilePath>
</File>
<File>
<FileName>xc_drv_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_gpio.c</FilePath>
</File>
<File>
<FileName>xc_drv_pwr.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_pwr.c</FilePath>
</File>
<File>
<FileName>xc_drv_systick.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_systick.c</FilePath>
</File>
<File>
<FileName>xc_drv_timer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_timer.c</FilePath>
</File>
<File>
<FileName>xc_drv_uart.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_uart.c</FilePath>
</File>
<File>
<FileName>xc_drv_wdt.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_wdt.c</FilePath>
</File>
<File>
<FileName>xc_drv_fmc_spi.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_fmc_spi.c</FilePath>
</File>
<File>
<FileName>xc_drv_rtc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_rtc.c</FilePath>
</File>
<File>
<FileName>xc_drv_calib.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_calib.c</FilePath>
</File>
<File>
<FileName>xc_drv_adc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_adc.c</FilePath>
</File>
<File>
<FileName>xc_drv_aotimer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_aotimer.c</FilePath>
</File>
<File>
<FileName>xc_drv_bor.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_bor.c</FilePath>
</File>
<File>
<FileName>xc_drv_dma.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_dma.c</FilePath>
</File>
<File>
<FileName>xc_drv_fmc_spi_dma.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_fmc_spi_dma.c</FilePath>
</File>
<File>
<FileName>xc_drv_i2c.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_i2c.c</FilePath>
</File>
<File>
<FileName>xc_drv_pga.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_pga.c</FilePath>
</File>
<File>
<FileName>xc_drv_pwm.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_pwm.c</FilePath>
</File>
<File>
<FileName>xc_drv_qdec.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_qdec.c</FilePath>
</File>
<File>
<FileName>xc_drv_spi.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_spi.c</FilePath>
</File>
<File>
<FileName>xc_drv_spi_dma.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_spi_dma.c</FilePath>
</File>
<File>
<FileName>xc_drv_sw_i2c.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_sw_i2c.c</FilePath>
</File>
<File>
<FileName>xc_drv_uart_dma.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_uart_dma.c</FilePath>
</File>
</Files>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis/>
<components/>
<files>
<file attr="config" category="linkerScript" condition="ARMCC5" name="Device\ARM\ARMCM0\Source\ARM\ARMCM0_ac5.sct" version="1.0.0">
<instance index="0" removed="1">RTE\Device\ARMCM0\ARMCM0_ac5.sct</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM0 CMSIS" isDefaultVariant="1"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.8.0"/>
<targetInfos/>
</file>
<file attr="config" category="sourceC" name="Device\ARM\ARMCM0\Source\startup_ARMCM0.c" version="2.0.3">
<instance index="0" removed="1">RTE\Device\ARMCM0\startup_ARMCM0.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM0 CMSIS" isDefaultVariant="1"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.8.0"/>
<targetInfos/>
</file>
<file attr="config" category="sourceC" name="Device\ARM\ARMCM0\Source\system_ARMCM0.c" version="1.0.0">
<instance index="0" removed="1">RTE\Device\ARMCM0\system_ARMCM0.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM0 CMSIS" isDefaultVariant="1"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.8.0"/>
<targetInfos/>
</file>
</files>
</RTE>
<LayerInfo>
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
</Layer>
</Layers>
</LayerInfo>
</Project>
project/example/2.4g/RF24_ADV_Hw/mdk/Tools/Xincboot_tool.exe
BIN
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project/example/2.4g/RF24_ADV_Hw/mdk/Tools/dump.py
+59
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@@ -0,0 +1,59 @@
#!/usr/bin/env python
#-*- coding:UTF-8 -*-
import socket
from select import select
import time
import os
import sys
import threading
import json
import struct
import binascii
import time
import re
import fileinput
def dump_addr(addr):
file_asm = "./Xinc_ble_sdk_asm"
cur_func = ""
with open(file_asm, 'r') as fd:
for line in fd:
if re.match(r" \w+", line) != None:
cur_func = line.strip()
#
if re.search("^ 0x", line) != None and re.search(addr, line) != None:
print(addr, cur_func)
break
fd.close()
if __name__ == "__main__":
file_in = "./dump.txt"
for line in fileinput.input(file_in):
# 处理 PC 指针信息
if re.search("PC = ", line) != None:
pc_addr = line.split("PC = ")[1].split(",")[0]
#print(hex(int(pc_addr, 16)))
dump_addr(hex(int(pc_addr, 16)))
# 处理 栈信息
if re.search("^[0-9]",line) != None:
#print(line)
stack = line.split('=')[1].replace('\n', '').split(' ')
for addr in stack:
if addr == ' ' or re.search("^1", addr) == None:
continue
#print(addr, hex(int(addr,16)-1))
dump_addr(hex(int(addr,16)-1))
project/example/2.4g/RF24_ADV_Hw/mdk/Tools/xinchip_xip_tool.exe
BIN
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project/example/2.4g/RF24_AutoAck/app/Startup/lora/startup_xinc.s
+234
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;/*****************************************************************************
; * @file: startup_xinc.s
; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
; * Device xinc.
; *****************************************************************************/
Stack_Size EQU 0x00000600
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; ToDo: Add here the vectors for the device specific external interrupts handler
DCD 0 ; 0 BLE Handler
DCD DMAS_Handler ; 1
DCD CPR_Handler ; 2
DCD GPIO_Handler ; 3
DCD RTC_Handler ; 4
DCD TIMER0_Handler ; 5
DCD TIMER1_Handler
DCD TIMER2_Handler
DCD TIMER3_Handler
DCD WDT_Handler
DCD I2C_Handler
DCD UART0_Handler
DCD UART1_Handler
DCD SPI0_Handler
DCD SPI1_Handler
DCD 0
DCD 0
DCD GADC_Handler ; 17
DCD 0 ; 18
DCD 0 ; 19
DCD 0 ; 20
DCD 0 ; 21
DCD RF24G_Handler ; 22
DCD PWM_Handler ; 23
DCD BOR_Handler ; 24
DCD 0 ; 25
DCD 0 ; 26
DCD AOTIMER0_Handler ; 27
DCD AOTIMER1_Handler ; 28
DCD CMP_Handler ; 29
DCD FMC_Handler ; 30
DCD CAN_Handler ; 31
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR r0, =0x4000013C ; remap
LDR r1, =0x10000001
STR r1, [r0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
Default_Handler PROC
;EXPORT BLE_Handler [WEAK]
EXPORT DMAS_Handler [WEAK]
EXPORT CPR_Handler [WEAK]
EXPORT GPIO_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT TIMER2_Handler [WEAK]
EXPORT TIMER3_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT I2C_Handler [WEAK]
EXPORT UART0_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
EXPORT SPI0_Handler [WEAK]
EXPORT SPI1_Handler [WEAK]
;EXPORT KBS_Handler [WEAK]
;EXPORT QDEC_Handler [WEAK]
EXPORT GADC_Handler [WEAK]
EXPORT AOTIMER0_Handler [WEAK]
EXPORT AOTIMER1_Handler [WEAK]
EXPORT CMP_Handler [WEAK]
EXPORT FMC_Handler [WEAK]
EXPORT CAN_Handler [WEAK]
;EXPORT SIM_Handler [WEAK]
;EXPORT AES_Handler [WEAK]
EXPORT PendSV_Handler [WEAK]
EXPORT SysTick_Handler [WEAK]
EXPORT RF24G_Handler [WEAK]
EXPORT PWM_Handler [WEAK]
EXPORT BOR_Handler [WEAK]
PendSV_Handler
SysTick_Handler
;BLE_Handler
DMAS_Handler
CPR_Handler
GPIO_Handler
RTC_Handler
TIMER0_Handler
TIMER1_Handler
TIMER2_Handler
TIMER3_Handler
WDT_Handler
I2C_Handler
UART0_Handler
UART1_Handler
SPI0_Handler
SPI1_Handler
;KBS_Handler
;QDEC_Handler
GADC_Handler
;SIM_Handler
;AES_Handler
AOTIMER0_Handler
AOTIMER1_Handler
CMP_Handler
FMC_Handler
CAN_Handler
RF24G_Handler
PWM_Handler
BOR_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
END
project/example/2.4g/RF24_AutoAck/app/Startup/system_it_xinc.c
+232
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/*!
* \file system_it_xinc.c
*
* \brief Target system interruption implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "system_it_xinc.h"
/*------------------------------------------------------------------------------------
Func Prototype
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
/**
****************************************************************************************
* @brief This function handles NMI exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void NMI_Handler(void)
{
/* USER CODE BEGIN NonMaskableInt_IRQn */
DEBUG("%s\n", __func__);
/* USER CODE END NonMaskableInt_IRQn */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles Hard Fault exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void HardFault_Handler(void)
{
/* USER CODE BEGIN HardFault_IRQn */
DEBUG("%s\n", __func__);
/* USER CODE END HardFault_IRQn */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles Memory Manage exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void MemManage_Handler(void)
{
/* USER CODE BEGIN */
DEBUG("%s\n", __func__);
/* USER CODE END */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles Bus Fault exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void BusFault_Handler(void)
{
/* USER CODE BEGIN */
DEBUG("%s\n", __func__);
/* USER CODE END */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles Usage Fault exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void UsageFault_Handler(void)
{
/* USER CODE BEGIN */
DEBUG("%s\n", __func__);
/* USER CODE END */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles SVCall exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void SVC_Handler(void)
{
/* USER CODE BEGIN SVCall_IRQn */
DEBUG("%s\n", __func__);
/* USER CODE END SVCall_IRQn */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles Debug Monitor exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void DebugMon_Handler(void)
{
/* USER CODE BEGIN */
DEBUG("%s\n", __func__);
/* USER CODE END */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles PendSVC exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void PendSV_Handler(void)
{
/* USER CODE BEGIN PendSV_IRQn */
DEBUG("%s\n", __func__);
/* USER CODE END PendSV_IRQn */
while (1)
{
}
}
/****************************** Hard Fault Handler Functions *******************************/
/*------------------------------------------------------------------------------------
Private Functions
-------------------------------------------------------------------------------------*/
void HardFault_Handler_c(unsigned int * HardFault_args)
{
/*栈帧里面内容：*/
unsigned int stack_r0; //压栈的 R0
unsigned int stack_r1; //压栈的 R1
unsigned int stack_r2; //压栈的 R2
unsigned int stack_r3; //压栈的 R3
unsigned int stack_r12; //压栈的 R12
unsigned int stack_lr; //压栈的 lr
unsigned int stack_pc; //压栈的 pc
unsigned int stack_psr; //压栈的 psr
stack_r0 = ((unsigned int)HardFault_args[0]);
stack_r1 = ((unsigned int)HardFault_args[1]);
stack_r2 = ((unsigned int)HardFault_args[2]);
stack_r3 = ((unsigned int)HardFault_args[3]);
stack_r12 = ((unsigned int)HardFault_args[4]);
stack_lr = ((unsigned int)HardFault_args[5]);
stack_pc = ((unsigned int)HardFault_args[6]);
stack_psr = ((unsigned int)HardFault_args[7]);
DEBUG("----%s----\n", __func__);
DEBUG("R0=%x\n",stack_r0);
DEBUG("R1=%x\n",stack_r1);
DEBUG("R2=%x\n",stack_r2);
DEBUG("R3=%x\n",stack_r3);
DEBUG("R12=%x\n",stack_r12);
DEBUG("LR[R14]=%x\n",stack_lr);
DEBUG("PC[R15]=%x\n",stack_pc);
DEBUG("PSR=%x\n",stack_psr);
DEBUG("SCB_SHCSR=%x\n",SCB->SHCSR);
DEBUG("---------------------------\n");
while(1);
}
/*******************************************************************************************/
project/example/2.4g/RF24_AutoAck/app/Startup/system_it_xinc.h
+58
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/*!
* \file system_it_xinc.h
*
* \brief The header of system_it_xinc.c
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __SYSTEM_IT_XINC_H__
#define __SYSTEM_IT_XINC_H__
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "xc6xxx.h"
/*------------------------------------------------------------------------------------
Exported Functions
-------------------------------------------------------------------------------------*/
void NMI_Handler( void );
void HardFault_Handler( void );
void MemManage_Handler( void );
void BusFault_Handler( void );
void UsageFault_Handler( void );
void SVC_Handler( void );
void DebugMon_Handler( void );
void PendSV_Handler( void );
void HardFault_Handler_c(unsigned int * HardFault_args);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_IT_XINC_H__ */
project/example/2.4g/RF24_AutoAck/app/Startup/system_xinc.c
+120
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/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system
*
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include <stdio.h>
#include "xc6xxx.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
#define __DEBUG_OUT_PORT 0
#define readl(addr) (*(volatile unsigned int *) (addr))
#define writel(addr, value) (*(volatile unsigned int *) (addr) = (value))
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
#define VECTOR_NUM 48
void set_vector(void)
{
#if (USE_XIP == 1)
GLOBAL_INT_DISABLE();
for (uint32_t i = 0, *Pvector = (uint32_t *)(0x11001000 + 0),
*_vector_table = (uint32_t *)(0x10000000);
i < VECTOR_NUM; i++) // copy vertor table
{
_vector_table[i] = *Pvector++;
}
*((volatile unsigned int *)(0x4000013C)) =
0x10000001; // inter vertor table remap
GLOBAL_INT_RESTORE();
#endif
}
static void WDT_ResetInit(void)
{
cpr_ctlapbclken_grctl__wdt_pclk_en__setf(ENABLE);
cpr_rstctl_ctlapb_sw__wdt_rstn__setf(RSTCTL_ENABLE);
cpr_rstctl_ctlapb_sw__wdt_rstn__setf(RSTCTL_DISABLE);
cpr_rstctl_wdtrst_mask_set(
(WDT_SYS_RSTN_MASK_DISABLE | WDT_M0_RSTN_MASK_ENABLE));
cpr_lp_ctl__wdt_tclk_en__setf(ENABLE);
wdt_cr__wdt_en__setf(DISABLE);
}
void SystemInit(void)
{
WDT_ResetInit();
#if (USE_XIP == 1)
set_vector();
#endif
writel(0x40000040, readl(0x40000040) | (0x01 << 4) | 0xFFFF0000);
}
__RAM_CODE int sendchar(int c)
{
unsigned int status;
#if (__DEBUG_OUT_PORT == 1)
for (;;) {
status = (*((volatile unsigned *)(0x40011000 + 0x14)));
status &= 0x20;
if (status == 0x20)
break;
}
(*((volatile unsigned *)(0x40011000 + 0x00))) = c;
return (1);
#else
for (;;) {
status = (*((volatile unsigned *)(0x40010000 + 0x14)));
status &= 0x20;
if (status == 0x20)
break;
}
(*((volatile unsigned *)(0x40010000 + 0x00))) = c;
return (1);
#endif
}
struct __FILE
{
int handle; /* Add whatever you need here */
};
FILE __stdout;
__RAM_CODE int fputc(int ch, FILE *f) { return (sendchar(ch)); }
int ferror(FILE *f)
{
/* Your implementation of ferror */
return EOF;
}
void _ttywrch(int ch) { sendchar(ch); }
void _sys_exit(int return_code)
{
label:
goto label; /* endless loop */
}
project/example/2.4g/RF24_AutoAck/app/Startup/xc60xx/startup_xinc.s
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;/*****************************************************************************
; * @file: startup_xinc.s
; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
; * Device xinc.
; *****************************************************************************/
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; ToDo: Add here the vectors for the device specific external interrupts handler
DCD BLE_Handler ; 0
DCD DMA_Handler ; 1
DCD CPR_Handler ; 2
DCD GPIO_Handler ; 3
DCD RTC_Handler ; 4
DCD TIMER0_Handler ; 5
DCD TIMER1_Handler ; 6
DCD TIMER2_Handler ; 7
DCD TIMER3_Handler ; 8
DCD WDT_Handler ; 9
DCD I2C_Handler ; 10
DCD UART0_Handler ; 11
DCD UART1_Handler ; 12
DCD SPI0_Handler ; 13
DCD SPI1_Handler ; 14
DCD 0 ; 15
DCD 0 ; 16
DCD GADC_Handler ; 17
DCD PWM_Handler ; 18
DCD AES_Handler ; 19
DCD USB_Handler ; 20
DCD AUDIO_Handler ; 21
DCD RF24G_Handler ; 22
DCD SPI2_Handler ; 23
DCD MPU_Handler ; 24
DCD UART2_Handler ; 25
DCD I2S_Handler ; 26
DCD AOTIMER0_Handler ; 27
DCD AOTIMER1_Handler ; 28
DCD CMP_Handler ; 29
DCD FMC_Handler ; 30
DCD CAN_Handler ; 31
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR r0, =0x4000013C ; remap
LDR r1, =0x10000001
STR r1, [r0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
IMPORT HardFault_Handler_c ;函数声明
movs r0, #4 ;判断主栈指针还是进程栈指针
mov r1, lr
tst r0, r1
beq hf_used_msp ;如果是主栈指针
mrs r0, psp ;否则是进程栈指针,把进程栈指针地址付给 R0
ldr r1, =HardFault_Handler_c ;跳转到 HardFault 中断程序
bx r1
hf_used_msp
mrs r0, msp ;把主栈指针地址赋给 R0
ldr r1, =HardFault_Handler_c
bx r1
;EXPORT HardFault_Handler [WEAK]
;B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT BLE_Handler [WEAK]
EXPORT DMA_Handler [WEAK]
EXPORT CPR_Handler [WEAK]
EXPORT GPIO_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT TIMER2_Handler [WEAK]
EXPORT TIMER3_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT I2C_Handler [WEAK]
EXPORT UART0_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
EXPORT SPI0_Handler [WEAK]
EXPORT SPI1_Handler [WEAK]
;EXPORT KBS_Handler [WEAK]
;EXPORT QDEC_Handler [WEAK]
EXPORT GADC_Handler [WEAK]
EXPORT PWM_Handler [WEAK]
EXPORT AES_Handler [WEAK]
EXPORT PendSV_Handler [WEAK]
EXPORT SysTick_Handler [WEAK]
EXPORT USB_Handler [WEAK];20
EXPORT AUDIO_Handler [WEAK];21
EXPORT RF24G_Handler [WEAK];22
EXPORT SPI2_Handler [WEAK];23
EXPORT MPU_Handler [WEAK];24
EXPORT UART2_Handler [WEAK];25
EXPORT I2S_Handler [WEAK];26
EXPORT AOTIMER0_Handler [WEAK];27
EXPORT AOTIMER1_Handler [WEAK];28
EXPORT CMP_Handler [WEAK];29
EXPORT FMC_Handler [WEAK];30
EXPORT CAN_Handler [WEAK];31
PendSV_Handler
SysTick_Handler
BLE_Handler
RF24G_Handler
DMA_Handler
CPR_Handler
GPIO_Handler
RTC_Handler
TIMER0_Handler
TIMER1_Handler
TIMER2_Handler
TIMER3_Handler
WDT_Handler
I2C_Handler
I2S_Handler
UART0_Handler
UART1_Handler
UART2_Handler
SPI0_Handler
SPI1_Handler
SPI2_Handler
MPU_Handler
;KBS_Handler
;QDEC_Handler
GADC_Handler
PWM_Handler
AUDIO_Handler
;SIM_Handler
AES_Handler
AOTIMER0_Handler
AOTIMER1_Handler
CMP_Handler
FMC_Handler
CAN_Handler
USB_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
END
project/example/2.4g/RF24_AutoAck/app/Startup/xc62xx/startup_xinc.s
+257
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@@ -0,0 +1,257 @@
;/*****************************************************************************
; * @file: startup_xinc.s
; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
; * Device xinc.
; *****************************************************************************/
Stack_Size EQU 0x00000800
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; ToDo: Add here the vectors for the device specific external interrupts handler
DCD BLE_Handler ; 0
DCD DMA_Handler ; 1
DCD CPR_Handler ; 2
DCD GPIO_Handler ; 3
DCD RTC_Handler ; 4
DCD TIMER0_Handler ; 5
DCD TIMER1_Handler ; 6
DCD TIMER2_Handler ; 7
DCD TIMER3_Handler ; 8
DCD WDT_Handler ; 9
DCD I2C_Handler ; 10
DCD UART0_Handler ; 11
DCD UART1_Handler ; 12
DCD SPI0_Handler ; 13
DCD SPI1_Handler ; 14
DCD 0 ; 15
DCD 0 ; 16
DCD GADC_Handler ; 17
DCD PWM_Handler ; 18
DCD AES_Handler ; 19
DCD USB_Handler ; 20
DCD AUDIO_Handler ; 21
DCD RF24G_Handler ; 22
DCD SPI2_Handler ; 23
DCD MPU_Handler ; 24
DCD UART2_Handler ; 25
DCD I2S_Handler ; 26
DCD AOTIMER0_Handler ; 27
DCD AOTIMER1_Handler ; 28
DCD CMP_Handler ; 29
DCD FMC_Handler ; 30
DCD CAN_Handler ; 31
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR r0, =0x4000013C ; remap
LDR r1, =0x10000001
STR r1, [r0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
IMPORT HardFault_Handler_c ;函数声明
movs r0, #4 ;判断主栈指针还是进程栈指针
mov r1, lr
tst r0, r1
beq hf_used_msp ;如果是主栈指针
mrs r0, psp ;否则是进程栈指针,把进程栈指针地址付给 R0
ldr r1, =HardFault_Handler_c ;跳转到 HardFault 中断程序
bx r1
hf_used_msp
mrs r0, msp ;把主栈指针地址赋给 R0
ldr r1, =HardFault_Handler_c
bx r1
;EXPORT HardFault_Handler [WEAK]
;B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT BLE_Handler [WEAK]
EXPORT DMA_Handler [WEAK]
EXPORT CPR_Handler [WEAK]
EXPORT GPIO_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT TIMER2_Handler [WEAK]
EXPORT TIMER3_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT I2C_Handler [WEAK]
EXPORT UART0_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
EXPORT SPI0_Handler [WEAK]
EXPORT SPI1_Handler [WEAK]
;EXPORT KBS_Handler [WEAK]
;EXPORT QDEC_Handler [WEAK]
EXPORT GADC_Handler [WEAK]
EXPORT PWM_Handler [WEAK]
EXPORT AES_Handler [WEAK]
EXPORT PendSV_Handler [WEAK]
EXPORT SysTick_Handler [WEAK]
EXPORT USB_Handler [WEAK];20
EXPORT AUDIO_Handler [WEAK];21
EXPORT RF24G_Handler [WEAK];22
EXPORT SPI2_Handler [WEAK];23
EXPORT MPU_Handler [WEAK];24
EXPORT UART2_Handler [WEAK];25
EXPORT I2S_Handler [WEAK];26
EXPORT AOTIMER0_Handler [WEAK];27
EXPORT AOTIMER1_Handler [WEAK];28
EXPORT CMP_Handler [WEAK];29
EXPORT FMC_Handler [WEAK];30
EXPORT CAN_Handler [WEAK];31
PendSV_Handler
SysTick_Handler
BLE_Handler
RF24G_Handler
DMA_Handler
CPR_Handler
GPIO_Handler
RTC_Handler
TIMER0_Handler
TIMER1_Handler
TIMER2_Handler
TIMER3_Handler
WDT_Handler
I2C_Handler
I2S_Handler
UART0_Handler
UART1_Handler
UART2_Handler
SPI0_Handler
SPI1_Handler
SPI2_Handler
MPU_Handler
;KBS_Handler
;QDEC_Handler
GADC_Handler
PWM_Handler
AUDIO_Handler
;SIM_Handler
AES_Handler
AOTIMER0_Handler
AOTIMER1_Handler
CMP_Handler
FMC_Handler
CAN_Handler
USB_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
END
project/example/2.4g/RF24_AutoAck/app/Startup/xc65xx/startup_xinc.s
+257
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@@ -0,0 +1,257 @@
;/*****************************************************************************
; * @file: startup_xinc.s
; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
; * Device xinc.
; *****************************************************************************/
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; ToDo: Add here the vectors for the device specific external interrupts handler
DCD BLE_Handler ; 0
DCD DMA_Handler ; 1
DCD CPR_Handler ; 2
DCD GPIO_Handler ; 3
DCD RTC_Handler ; 4
DCD TIMER0_Handler ; 5
DCD TIMER1_Handler ; 6
DCD TIMER2_Handler ; 7
DCD TIMER3_Handler ; 8
DCD WDT_Handler ; 9
DCD I2C_Handler ; 10
DCD UART0_Handler ; 11
DCD UART1_Handler ; 12
DCD SPI0_Handler ; 13
DCD SPI1_Handler ; 14
DCD 0 ; 15
DCD 0 ; 16
DCD GADC_Handler ; 17
DCD PWM_Handler ; 18
DCD AES_Handler ; 19
DCD USB_Handler ; 20
DCD AUDIO_Handler ; 21
DCD RF24G_Handler ; 22
DCD SPI2_Handler ; 23
DCD MPU_Handler ; 24
DCD UART2_Handler ; 25
DCD I2S_Handler ; 26
DCD AOTIMER0_Handler ; 27
DCD AOTIMER1_Handler ; 28
DCD CMP_Handler ; 29
DCD FMC_Handler ; 30
DCD CAN_Handler ; 31
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR r0, =0x4000013C ; remap
LDR r1, =0x10000001
STR r1, [r0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
IMPORT HardFault_Handler_c ;函数声明
movs r0, #4 ;判断主栈指针还是进程栈指针
mov r1, lr
tst r0, r1
beq hf_used_msp ;如果是主栈指针
mrs r0, psp ;否则是进程栈指针,把进程栈指针地址付给 R0
ldr r1, =HardFault_Handler_c ;跳转到 HardFault 中断程序
bx r1
hf_used_msp
mrs r0, msp ;把主栈指针地址赋给 R0
ldr r1, =HardFault_Handler_c
bx r1
;EXPORT HardFault_Handler [WEAK]
;B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT BLE_Handler [WEAK]
EXPORT DMA_Handler [WEAK]
EXPORT CPR_Handler [WEAK]
EXPORT GPIO_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT TIMER2_Handler [WEAK]
EXPORT TIMER3_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT I2C_Handler [WEAK]
EXPORT UART0_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
EXPORT SPI0_Handler [WEAK]
EXPORT SPI1_Handler [WEAK]
;EXPORT KBS_Handler [WEAK]
;EXPORT QDEC_Handler [WEAK]
EXPORT GADC_Handler [WEAK]
EXPORT PWM_Handler [WEAK]
EXPORT AES_Handler [WEAK]
EXPORT PendSV_Handler [WEAK]
EXPORT SysTick_Handler [WEAK]
EXPORT USB_Handler [WEAK];20
EXPORT AUDIO_Handler [WEAK];21
EXPORT RF24G_Handler [WEAK];22
EXPORT SPI2_Handler [WEAK];23
EXPORT MPU_Handler [WEAK];24
EXPORT UART2_Handler [WEAK];25
EXPORT I2S_Handler [WEAK];26
EXPORT AOTIMER0_Handler [WEAK];27
EXPORT AOTIMER1_Handler [WEAK];28
EXPORT CMP_Handler [WEAK];29
EXPORT FMC_Handler [WEAK];30
EXPORT CAN_Handler [WEAK];31
PendSV_Handler
SysTick_Handler
BLE_Handler
RF24G_Handler
DMA_Handler
CPR_Handler
GPIO_Handler
RTC_Handler
TIMER0_Handler
TIMER1_Handler
TIMER2_Handler
TIMER3_Handler
WDT_Handler
I2C_Handler
I2S_Handler
UART0_Handler
UART1_Handler
UART2_Handler
SPI0_Handler
SPI1_Handler
SPI2_Handler
MPU_Handler
;KBS_Handler
;QDEC_Handler
GADC_Handler
PWM_Handler
AUDIO_Handler
;SIM_Handler
AES_Handler
AOTIMER0_Handler
AOTIMER1_Handler
CMP_Handler
FMC_Handler
CAN_Handler
USB_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
END
project/example/2.4g/RF24_AutoAck/app/api/app_data.h
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/*
* @Descripttion:
* @version:
* @Author: sueRimn
* @Date: 2024-05-09 11:45:27
* @LastEditors: sueRimn
* @LastEditTime: 2024-07-24 15:18:52
*/
#ifndef __APP_DATA_H__
#define __APP_DATA_H__
#include "rf_config.h"
#include "xc6xxx_rf_2_4g.h"
#include "xc_software_crc.h"
#include <stdint.h>
#define BEKEN (0)
#define PAN2416 (1)
#ifdef TELINK_MODE
#define COMPATILBE_MODE BEKEN
#endif
#ifdef BEKEN_MODE
#define COMPATILBE_MODE BEKEN
#endif
#ifdef PANCHIP_MODE
#define COMPATILBE_MODE PAN2416
#endif
#define RF_CONFIRMED_VALUE (5U)
/* 最大接收数据长度 */
#define BUFF_LEN_MAX (32U)
#define RF_RECV_AMX_LEN (BUFF_LEN_MAX)
#define RF_PRX_READ_RXFIFO_TIMER (RF_RECV_AMX_LEN)
#define BIT7 0x80
#define BIT6 0x40
#define BIT5 0x20
#define BIT4 0x10
#define BIT3 0x08
#define BIT2 0x04
#define BIT1 0x02
#define BIT0 0x01
/* 动态包位移长度，单位bit */
#if (BEKEN == COMPATILBE_MODE)
#define DATA_ANALYSIS_BIT_H (BIT7)
#define DATA_ANALYSIS_BIT_L (BIT0)
#define DATA_CONTROL_BIT (1U)
#define DATA_CONTROL_NOACK (1U) // 1-ack 0-noack
#elif (PAN2416 == COMPATILBE_MODE)
#define DATA_ANALYSIS_BIT_H (BIT7 | BIT6)
#define DATA_ANALYSIS_BIT_L (BIT0 | BIT1)
#define DATA_CONTROL_BIT (2U)
#define DATA_CONTROL_NOACK (0U) // 0-ack 1-noack
#endif
#define DATA_SPLICE_BIT (8U - DATA_CONTROL_BIT)
/* 地址长度 */
#define RF_ADDR_LEN XINCX_RF_TX_ADDR_WIDTH // 5U
/* 接收CRC+contorl字段长度 */
#define RF_RECV_EXTEN_LEN (3U)
/* CRC初始值 */
#if (1 == XINCX_2_4G_CRC_BYTE)
#define RF_CRC_INIT_VALUE (0xFF) // CRC8 0xFF CRC16 0xFFFF
#elif (2 == XINCX_2_4G_CRC_BYTE)
#define RF_CRC_INIT_VALUE (0xFFFF) // CRC8 0xFF CRC16 0xFFFF
#endif
/* 调制频偏 */
#if ((XINCX_RF_TRANS_RATE == DR_250K) && (PAN2416 == COMPATILBE_MODE))
#define RF_FREQ_DEV (0xb8) // 0x75
#define RF_FREQ_SEND_DEV (0x90) // 0xb8//0xa0
#define RF_FREQ_RECV_DEV (0x80) // 0x98//0xa0
#define ACK_DELAY (50) //(300)
#elif ((XINCX_RF_TRANS_RATE == DR_1M) && (PAN2416 == COMPATILBE_MODE))
#define RF_FREQ_DEV (0xd0) // 0xb8//0xa0
#define RF_FREQ_SEND_DEV (0xe0) // 0xb8//0xa0
#define RF_FREQ_RECV_DEV (0x80) // 0x98//0xa0
#define ACK_DELAY (300) //(300)
#elif ((XINCX_RF_TRANS_RATE == DR_1M) && (BEKEN == COMPATILBE_MODE))
#define RF_FREQ_DEV (0x80) // 0x75
#define RF_FREQ_SEND_DEV (0xd0) // 0xb8//0xa0
#define RF_FREQ_RECV_DEV (RF_FREQ_DEV) // 0x98//0xa0
#define ACK_DELAY (40)
#elif ((XINCX_RF_TRANS_RATE == DR_250K) && (BEKEN == COMPATILBE_MODE))
#define RF_FREQ_DEV (0x80) // 0x75
#define RF_FREQ_SEND_DEV (0xd0) // 0xb8//0xa0
#define RF_FREQ_RECV_DEV (RF_FREQ_DEV) // 0x98//0xa0
#define ACK_DELAY (0)
#endif
/* 磐启白化初始值 */
#define PANCHIP_WHITEN_INIT_VAL (0x7F)
/* ACK 长度 */
#define ACK_LEN (32U) // 32U
/* */
#define USB_TEST (1U)
/* 测试IO 使能 */
#define DEBUG_PIN (1U)
#define TEST_PIN_NO_USB (1U)
/* 测试IO */
#define TEST_PIN_1 GPIO_3
#define TEST_PIN_2 GPIO_6
#define TEST_PIN_3 GPIO_7
#define TEST_PIN_4 GPIO_8
#define TEST_PIN_5 GPIO_1
#define TEST_PIN_6 GPIO_4
#define TEST_PIN_7 GPIO_5
#define TEST_PIN_8 GPIO_0
/* ACK固定接收字节数 */
#define RF_RECV_TIMER \
(XINCX_2_4G_PREAMBLE_NUM + 1 + XINCX_RF_TX_ADDR_WIDTH + RF_PRX_READ_RXFIFO_TIMER + XINCX_2_4G_CRC_BYTE + 2 + 10)
/* 速率-bit占用时间 */
#if (XINCX_RF_TRANS_RATE == DR_2M)
#define BIT_TIMER (4U)
#elif (XINCX_RF_TRANS_RATE == DR_1M)
#define BIT_TIMER (8U)
#elif (XINCX_RF_TRANS_RATE == DR_250K)
#define BIT_TIMER (32U)
#elif (XINCX_RF_TRANS_RATE == DR_125K)
#define BIT_TIMER (64U)
#endif
extern uint8_t addr_buff[5];
extern uint8_t ack_buff[BUFF_LEN];
extern uint16_t rf_addr_crc;
extern uint8_t panchip_addr_whiten;
extern uint8_t panchip_contorl_whiten;
extern uint8_t rf_send_ack_stat;
void rf_enhanced_packet(uint8_t *buff, uint8_t buff_len);
uint16_t rf_recv_dyn_crc(uint8_t *buff, uint8_t buff_len);
uint16_t rf_enhanced_package_grouping(uint8_t *data_buff, uint8_t data_len);
uint8_t read_addr_wid(uint8_t *addr_buff);
void rf_addr_map(uint8_t *addr_buff);
uint8_t rf_enhanced_recv_data(uint8_t *buff);
#endif
project/example/2.4g/RF24_AutoAck/app/api/app_rf.h
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#ifndef __APP_RF_H__
#define __APP_RF_H__
#include "app_data.h"
#include "rf_config.h"
//#include "rtt_platform.h"
#include "xc6xxx.h"
#include "xc6xxx_rf_2_4g.h"
#include "xc_software_crc.h"
typedef enum
{
RF_SEND_TIMER_INTER = 0,
RF_RECV_TIMER_INTER = 1,
RF_FREE_TIMER_INTER = 2
} rf_timer_stat_t; // PRX 状态
#define RECV_TIMERMS_OUT 1000 // 超时接收
//#define SEND_TIMERMS_CNT 10 * 1000 // 定时发射 ms
#define RECV_TIMERMS_CNT 50
#define ACK_SEND_TIMER 50
#define XC_SEND_NUM 1000 // 发射总包数
#define RF_TX_TIMERx TIMER0_IDX // 发射定时器号
#define RF_RX_TIMERx TIMER0_IDX // 接收定时器号
#define EXTEND_LEN (5)
extern uint8_t ret;
extern uint32_t count;
extern uint32_t send_ok;
extern uint32_t send_max;
extern bool rf_send_timer_flag;
extern bool rf_recv_timer_flag;
extern bool rf_prx_ack_flag;
extern rf_timer_stat_t timer_stat;
void timer_init(uint8_t timer_id, uint32_t timer_cnt);
void gpio_test(void);
void rf_debug_pin(uint8_t gpio_id);
uint16_t rf_get_addr_crc(void);
//void rf_buff_info(uint8_t *buff, uint8_t len);
void rf_rx_ack_payload_event(uint8_t *buff, uint8_t len);
void rf_set_agc(uint8_t adc_rssi_mean, uint8_t agc_gain_delay);
void rf_pwr_down_up(void);
// uint16_t rf_send_enhanced_data_cfg(uint8_t *buff, uint8_t len, uint8_t ack);
#if (XINCX_RF_COMPATIBILITY_MODE == PANCHIP_PACKET)
uint32_t rf_tx_manage(rf_data_typedef_t *rf_data);
void timer0_callback(void *context);
#endif
void xc_rf_send_ack(uint8_t *buff, uint8_t recv_len);
void rf_set_rx_mode(uint16_t channel, uint16_t fifo_len);
void rf_recv_sf_ack_payload(uint8_t *buff, uint8_t len);
uint8_t rf_recv_enhanced_data(uint8_t *buff);
void rf_set_agc_map(uint8_t agc_gain_1th, uint8_t agc_setp);
void rf_pwm_recv_data(void);
uint8_t rf_recv_addr(void);
#endif //__APP_RF_H__
project/example/2.4g/RF24_AutoAck/app/api/main.h
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/*!
* \file main.h
*
* \brief The head file of main.c
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MAIN_H__
#define __MAIN_H__
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "xc6xxx.h"
#include "xc6xxx_rf_2_4g.h"
#include "rf_config.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
#define DEBUG_LOG
/*------------------------------------------------------------------------------------
TypeDef
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Global Variables
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Exported Functions
-------------------------------------------------------------------------------------*/
void rf_tx_manage(void);
void rf_rx_manage(void);
void rf_buff_info(uint8_t *buff, uint8_t len);
#ifdef __cplusplus
}
#endif
#endif /* __MAIN_H__ */
project/example/2.4g/RF24_AutoAck/app/api/sdk_config.h
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#ifndef SDK_DRIVER_CONFIG_H
#define SDK_DRIVER_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>\n
#ifdef USE_APP_CONFIG
#include "app_config.h"
#endif
// <h> XC_Drivers
// <e> XC_CLOCK_ENABLED
//==========================================================
#ifndef XC_CLOCK_ENABLED
#define XC_CLOCK_ENABLED 1
#endif
// </e>
// <e> XC_PWR_ENABLED
//==========================================================
#ifndef XC_PWR_ENABLED
#define XC_PWR_ENABLED 1
#endif
// </e>
// <e> XC_WDT_ENABLED
//==========================================================
#ifndef XC_WDT_ENABLED
#define XC_WDT_ENABLED 1
#endif
// </e>
// <e> XC_BOR_ENABLED
//==========================================================
#ifndef XC_BOR_ENABLED
#define XC_BOR_ENABLED 1
#endif
// </e>
// <e> XC_SYSTICK_ENABLED
//==========================================================
#ifndef XC_SYSTICK_ENABLED
#define XC_SYSTICK_ENABLED 1
#endif
// </e>
// <e> XC_TIMER_ENABLED
//==========================================================
#ifndef XC_TIMER_ENABLED
#define XC_TIMER_ENABLED 0
#endif
// </e>
// <e> XC_AOTIMER_ENABLED
//==========================================================
#ifndef XC_AOTIMER_ENABLED
#define XC_AOTIMER_ENABLED 0
#endif
// </e>
// <e> XC_GPIO_ENABLED
//==========================================================
#ifndef XC_GPIO_ENABLED
#define XC_GPIO_ENABLED 1
#endif
// </e>
// <e> XC_ADC_ENABLED
//==========================================================
#ifndef XC_ADC_ENABLED
#define XC_ADC_ENABLED 1
#endif
// </e>
// <e> XC_UART_ENABLED
//==========================================================
#ifndef XC_UART_ENABLED
#define XC_UART_ENABLED 1
#endif
// </e>
// <e> XC_PWM_ENABLED
//==========================================================
#ifndef XC_PWM_ENABLED
#define XC_PWM_ENABLED 1
#endif
// </e>
// <e> XC_FMC_SPI_ENABLED
//==========================================================
#ifndef XC_FMC_SPI_ENABLED
#define XC_FMC_SPI_ENABLED 1
#endif
// </e>
// <e> XC_SPI_ENABLED
//==========================================================
#ifndef XC_SPI_ENABLED
#define XC_SPI_ENABLED 0
#endif
// </e>
// <e> XC_IIC_ENABLED
//==========================================================
#ifndef XC_IIC_ENABLED
#define XC_IIC_ENABLED 0
#endif
// </e>
// <e> XC_RTC_ENABLED
//==========================================================
#ifndef XC_RTC_ENABLED
#define XC_RTC_ENABLED 0
#endif
//==========================================================
// <q> XC_RTC_DATE_INT_ENABLED
#ifndef XC_RTC_DATE_INT_ENABLED
#define XC_RTC_DATE_INT_ENABLED 0
#endif
// </e>
// <e> XC_DMA_ENABLED
//==========================================================
#ifndef XC_DMA_ENABLED
#define XC_DMA_ENABLED 0
#endif
// </e>
// <e> XC_PGA_ENABLED
//==========================================================
#ifndef XC_PGA_ENABLED
#define XC_PGA_ENABLED 0
#endif
// </e>
// <e> XC_QDEC_ENABLED
//==========================================================
#ifndef XC_QDEC_ENABLED
#define XC_QDEC_ENABLED 0
#endif
// </e>
// <e> XC_CALIB_ENABLED
//==========================================================
#ifndef XC_CALIB_ENABLED
#define XC_CALIB_ENABLED 0
#endif
// </e>
// <<< end of configuration section >>>
#endif //SDK_DRIVER_CONFIG_H
project/example/2.4g/RF24_AutoAck/app/rf_config/rf_config.h
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#ifndef SDK_CONFIG_H
#define SDK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// XINCX_RF_EMHAMCED_PEACKET_MODE - RF enhanced packet mode
// <i> Configure the frame format, which is a dynamic packet configuration, which can communicate in both directions,and
// <i> ACK can dynamically carry data.
#ifndef XINCX_RF_EMHAMCED_PACKET_MODE
#define XINCX_RF_EMHAMCED_PACKET_MODE 1
#endif
#if (XINCX_RF_EMHAMCED_PACKET_MODE == 1)
// <o> XINCX_RF_COMPATIBILITY_MODE - RF Compatibility mode
// <0=> Xinchip_mode
// <1=> Panchip_mode
// <2=> Beken_mode
// <3=> Telink_mode
// <4=> Huntersun_mode
#ifndef XINCX_RF_COMPATIBILITY_MODE
#define XINCX_RF_COMPATIBILITY_MODE 0
#endif
// XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
//==========================================================
// <o> XINCX_RF_MODE - RF Tx or Rx Mode
// <0=> TX Mode
// <1=> RX Mode
#ifndef XINCX_RF_MODE
#define XINCX_RF_MODE 1
#endif
// <o> XINCX_RF_TRANS_RATE - RF Transmission Rate Config
// <0x02=> 1M
// <0x0A=> 2M
// <0x22=> 250k
// <0x2A=> 125k
#ifndef XINCX_RF_TRANS_RATE
#define XINCX_RF_TRANS_RATE 0x02
#endif
// <o> XINCX_2_4G_CHANNEL - 2.4g Channel Set
#ifndef XINCX_2_4G_CHANNEL
#define XINCX_2_4G_CHANNEL 2440
#endif
// <o> XINCX_RF_TX_ADDR_WIDTH - RF Tx Addr Width
// <3=> 3 Bytes
// <4=> 4 Bytes
// <5=> 5 Bytes
#ifndef XINCX_RF_TX_ADDR_WIDTH
#define XINCX_RF_TX_ADDR_WIDTH 5
#endif
// <o> XINCX_2_4G_ADDR_L - rf Address Set
#ifndef XINCX_2_4G_ADDR_L
#define XINCX_2_4G_ADDR_L 0xe7e7e7e7
#endif
// <o> XINCX_2_4G_ADDR_H - rf Address Set
#ifndef XINCX_2_4G_ADDR_H
#define XINCX_2_4G_ADDR_H 0xe7
#endif
// <o> XINCX_RF_POWER - rf Power Set
// <1=> -10dbm
// <2=> -9dbm
// <4=> -4dbm
// <6=> 0dbm
// <8=> 3dbm
// <9=> 5dbm
// <12=> 7dbm
// <14=> 8dbm
// <16=> 9dbm
// <19=> 10dbm
// <24=> 11dbm
// <30=> 12dbm
// <36=> 13dbm
#ifndef XINCX_POWER
#define XINCX_POWER 0x00006
#endif
// <o> XINCX_RF_NVIC_MODE - RF NVIC Mode
// <0=> Disable
// <1=> Enable
#ifndef XINCX_RF_NVIC_MODE
#define XINCX_RF_NVIC_MODE 1
#endif
// XINCX_2_4G_PIPE_RX_PAYLEN - 2.4g Pipe Rx Payload Len
// <i> Payload length. Configuration of the load length during communication.
//==========================================================
// XINCX_2_4G_PIPE0_LEN - 2.4g Pipe0 Rx Payload Len
// #ifndef XINCX_2_4G_PIPE0_LEN
// #define XINCX_2_4G_PIPE0_LEN 32
// #endif
// XINCX_2_4G_PIPE1_LEN - 2.4g Pipe1 Rx Payload Len
#ifndef XINCX_2_4G_PIPE1_LEN
#define XINCX_2_4G_PIPE1_LEN 32
#endif
// XINCX_2_4G_PIPE2_LEN - 2.4g Pipe2 Rx Payload Len
#ifndef XINCX_2_4G_PIPE2_LEN
#define XINCX_2_4G_PIPE2_LEN 32
#endif
// XINCX_2_4G_PIPE3_LEN - 2.4g Pipe3 Rx Payload Len
#ifndef XINCX_2_4G_PIPE3_LEN
#define XINCX_2_4G_PIPE3_LEN 32
#endif
// XINCX_2_4G_PIPE4_LEN - 2.4g Pipe4 Rx Payload Len
#ifndef XINCX_2_4G_PIPE4_LEN
#define XINCX_2_4G_PIPE4_LEN 32
#endif
// XINCX_2_4G_PIPE5_LEN - 2.4g Pipe5 Rx Payload Len
#ifndef XINCX_2_4G_PIPE5_LEN
#define XINCX_2_4G_PIPE5_LEN 32
#endif
// XINCX_RF_CRC_ENABLE - RF CRC Enable
//==========================================================
#ifndef XINCX_RF_CRC_ENABLE
#define XINCX_RF_CRC_ENABLE 1
#endif
// <o> XINCX_2_4G_CRC_BYTE - 2.4g CRC Bytes Set
// <0=> 0 Byte
// <1=> 1 Byte
// <2=> 2 Bytes
#ifndef XINCX_2_4G_CRC_BYTE
#define XINCX_2_4G_CRC_BYTE 2
#endif
// XINCX_2_4G_FEATURE_PARAM - 2.4g Feature Parameters
//==========================================================
// XINCX_2_4G_GUARD_CFG - 2.4g Long Payload Feature
#ifndef XINCX_2_4G_GUARD_CFG
#define XINCX_2_4G_GUARD_CFG 0
#endif
// XINCX_2_4G_LONG_PLD_TYPE - 2.4g Long Pld Type
#ifndef XINCX_2_4G_LONG_PLD_TYPE
#define XINCX_2_4G_LONG_PLD_TYPE 0
#endif
// XINCX_2_4G_PREAMBLE_NUM - 2.4g Preamble
#ifndef XINCX_2_4G_PREAMBLE_NUM
#define XINCX_2_4G_PREAMBLE_NUM 0
#endif
// XINCX_2_4G_PREAMBLE_TYPE - 2.4g Preamble Type
#ifndef XINCX_2_4G_PREAMBLE_TYPE
#define XINCX_2_4G_PREAMBLE_TYPE 0
#endif
// XINCX_2_4G_CRC_SCOPE_GUARD - 2.4g CRC Scope Guard
#ifndef XINCX_2_4G_CRC_SCOPE_GUARD
#define XINCX_2_4G_CRC_SCOPE_GUARD 0
#endif
// XINCX_2_4G_CRC_SCOPE_HEADER - 2.4g CRC Scope Header
#ifndef XINCX_2_4G_CRC_SCOPE_HEADER
#define XINCX_2_4G_CRC_SCOPE_HEADER 1
#endif
// XINCX_2_4G_CRC_SCOPE_ADDR - 2.4g CRC Scope Addr
#ifndef XINCX_2_4G_CRC_SCOPE_ADDR
#define XINCX_2_4G_CRC_SCOPE_ADDR 1
#endif
// XINCX_2_4G_LONG_PLD - 2.4g Long Payload Feature
#ifndef XINCX_2_4G_LONG_PLD
#define XINCX_2_4G_LONG_PLD 1
#endif
// <q> XINCX_2_4G_FEC - 2.4g FEC&Interleave Feature
#ifndef XINCX_2_4G_FEC
#define XINCX_2_4G_FEC 0
#endif
// <q> XINCX_2_4G_WHITEN - 2.4g Whiten Feature
#ifndef XINCX_2_4G_WHITEN
#define XINCX_2_4G_WHITEN 1
#endif
// XINCX_2_4G_DPL - 2.4g Dynamic Payload Length Feature
#ifndef XINCX_2_4G_DPL
#define XINCX_2_4G_DPL 1
#endif
// XINCX_2_4G_ACK_PAY - 2.4g Payload on ACK
#ifndef XINCX_2_4G_ACK_PAY
#define XINCX_2_4G_ACK_PAY 1
#endif
// XINCX_2_4G_DYN_ACK - 2.4g W_TX_PAYLOAD_NOACK Command
#ifndef XINCX_2_4G_DYN_ACK
#define XINCX_2_4G_DYN_ACK 1
#endif
// XINCX_2_4G_DYNPD - 2.4g dynpd
#ifndef XINCX_2_4G_DYNPD
#define XINCX_2_4G_DYNPD 0x3f
#endif
// XINCX_2_4G_AUTO_ACK - 2.4g Auto Acknowledgement
//==========================================================
// XINCX_2_4G_PIPE0_ENAA - 2.4g Pipe0 Auto Ack
#ifndef XINCX_2_4G_PIPE0_ENAA
#define XINCX_2_4G_PIPE0_ENAA 1
#endif
// XINCX_2_4G_PIPE1_ENAA - 2.4g Pipe1 Auto Ack
#ifndef XINCX_2_4G_PIPE1_ENAA
#define XINCX_2_4G_PIPE1_ENAA 1
#endif
// XINCX_2_4G_PIPE2_ENAA - 2.4g Pipe2 Auto Ack
#ifndef XINCX_2_4G_PIPE2_ENAA
#define XINCX_2_4G_PIPE2_ENAA 1
#endif
// XINCX_2_4G_PIPE3_ENAA - 2.4g Pipe3 Auto Ack
#ifndef XINCX_2_4G_PIPE3_ENAA
#define XINCX_2_4G_PIPE3_ENAA 1
#endif
// XINCX_2_4G_PIPE4_ENAA - 2.4g Pipe4 Auto Ack
#ifndef XINCX_2_4G_PIPE4_ENAA
#define XINCX_2_4G_PIPE4_ENAA 1
#endif
// XINCX_2_4G_PIPE5_ENAA - 2.4g Pipe5 Auto Ack
#ifndef XINCX_2_4G_PIPE5_ENAA
#define XINCX_2_4G_PIPE5_ENAA 1
#endif
// <o.0..5> XINCX_RF_PIPE_ENABLE
#ifndef XINCX_RF_PIPE_ENABLE
#define XINCX_RF_PIPE_ENABLE 3
#endif
// XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
//==========================================================
// <o> XINCX_2_4G_RETRANS_CNT - 2.4g Retransmit Count
// <i> Number of retransmissions. The maximum number of times a hardware can automatically transmit an ACK if it does
// not receive the correct ACK.
// <0=> No retransmission
// <1=> 1 time
// <2=> 2 times
// <3=> 3 times
// <4=> 4 times
// <5=> 5 times
// <6=> 6 times
// <7=> 7 times
// <8=> 8 times
// <9=> 9 times
// <10=> 10 times
// <11=> 11 times
// <12=> 12 times
// <13=> 13 times
// <14=> 14 times
// <15=> 15 times
#ifndef XINCX_2_4G_RETRANS_CNT
#define XINCX_2_4G_RETRANS_CNT 0
#endif
// <o> XINCX_2_4G_RETRANS_DELAY - 2.4g Retransmission Delay
// <i> Retransmission delay. For 32 bytes of data, the minimum configuration is 500 us for 1 Mbit/s and 1500 us for 250
// kbit/s.
// <0=> 250us
// <1=> 500us
// <2=> 750us
// <3=> 1000us
// <4=> 1250us
// <5=> 1500us
// <6=> 1750us
// <7=> 2000us
// <8=> 2250us
// <9=> 2500us
// <10=> 2750us
// <11=> 3000us
// <12=> 3250us
// <13=> 3500us
// <14=> 3750us
// <15=> 4000us
#ifndef XINCX_2_4G_RETRANS_DELAY
#define XINCX_2_4G_RETRANS_DELAY 3
#endif
#endif
// RF 2.4g Compatibility configuration
//==========================================================
// Compatibility configuration, when you need to be compatible with other RF chips, you don't need to configure this
// option when using our company's chips.
// XINCX_2_4G_PREAMBLE - 2.4g preamble
#ifndef XINCX_2_4G_PREAMBLE
#define XINCX_2_4G_PREAMBLE 0x710f5555
#endif
// XINCX_2_4G_GUARD - 2.4g guard
#ifndef XINCX_2_4G_GUARD
#define XINCX_2_4G_GUARD 0x8fc9
#endif
//
// XINCX_2_4G_CRY_CPT_ARRAY - 2.4g Crystal capacitor array
//==========================================================
// Crystal capacitor array, adjust to modify the frequency offset of the crystal oscillator.
// XINCX_2_4G_CRY_CPT_ARRAY - 2.4g Crystal capacitor array
#ifndef XINCX_2_4G_CRY_CPT_ARRAY
#ifdef XC62XX
#define XINCX_2_4G_CRY_CPT_ARRAY 0x38
#else
#define XINCX_2_4G_CRY_CPT_ARRAY 0x36
#endif
#endif
//
// <<< end of configuration section >>>
#endif // SDK_CONFIG_H
project/example/2.4g/RF24_AutoAck/app/src/app_data.c
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#include "app_data.h"
#include "rtt_platform.h"
#include "xc_drv_gpio.h"
uint8_t addr_buff[5] = {0};
uint8_t ack_pid = 0;
uint8_t rf_send_ack_stat = TX_DATA_INVALID;
uint16_t rf_addr_crc = 0;
uint8_t ack_buff[128] = {0};
uint8_t panchip_addr_whiten;
uint8_t panchip_contorl_whiten;
/**
* @brief Rf 2.4g get addr
* @param uint8_t *addr_buff
*
* @retval void
*/
void rf_addr_map(uint8_t *addr_buff)
{
uint8_t addr_xsb = (XC_RF_2_4G->CFG_TOP >> 11) & (0x1);
LOGI("addr_xsb %02x\r\n", addr_xsb);
if (!addr_xsb) {
addr_buff[0] = (XC_RF_2_4G->TX_ADDR_L >> 0) & 0xff;
addr_buff[1] = (XC_RF_2_4G->TX_ADDR_L >> 8) & 0xff;
addr_buff[2] = (XC_RF_2_4G->TX_ADDR_L >> 16) & 0xff;
addr_buff[3] = (XC_RF_2_4G->TX_ADDR_L >> 24) & 0xff;
addr_buff[4] = (XC_RF_2_4G->TX_ADDR_H >> 0) & 0xff;
} else {
addr_buff[1] = (XC_RF_2_4G->TX_ADDR_L >> 24) & 0xff;
addr_buff[2] = (XC_RF_2_4G->TX_ADDR_L >> 16) & 0xff;
addr_buff[3] = (XC_RF_2_4G->TX_ADDR_L >> 8) & 0xff;
addr_buff[4] = (XC_RF_2_4G->TX_ADDR_L >> 0) & 0xff;
addr_buff[0] = (XC_RF_2_4G->TX_ADDR_H >> 0) & 0xff;
}
}
/**
* @brief Rf 2.4g get addr length
* @param uint8_t *addr_buff
*
* @retval void
*/
uint8_t read_addr_wid(uint8_t *addr_buff)
{
uint8_t addr_wid = 0;
switch (XC_RF_2_4G->SETUP_AW & 0xff) {
case 0xa5:
addr_wid = 3;
#ifdef BEKEN_MODE
addr_wid = 5;
addr_buff[3] = 0xe7;
addr_buff[4] = 0xe7;
#endif
break;
case 0xaa:
addr_wid = 4;
#ifdef BEKEN_MODE
addr_wid = 4;
addr_buff[4] = 0xe7;
#endif
break;
case 0xaf:
addr_wid = 5;
break;
default:
addr_wid = 0;
break;
}
return addr_wid;
}
/**
* @brief Rf 2.4g panchip ack data config
* @param uint8_t *addr_buff
* @param uint8_t *ack_buff_cfg
* @param uint8_t ack_payload_len
* @retval uint16_t ack_crc_data
*/
__RAM_CODE uint16_t rf_enhanced_package_grouping(uint8_t *data_buff, uint8_t data_len)
{
uint16_t ack_control = (data_len << RF_RECV_EXTEN_LEN);
// uint8_t ack_crc_buff[64] = {0};
uint16_t ack_crc_data = 0;
uint8_t temp_buff[64] = {0};
ack_pid += 1;
#if (COMPATILBE_MODE == PAN2416)
if (ack_pid > 1)
#else
if (ack_pid > 3)
#endif
ack_pid = 0;
ack_control = (ack_control & ~(0x3 << 1)) | (ack_pid << DATA_CONTROL_BIT) | DATA_CONTROL_NOACK;
#if (COMPATILBE_MODE == PAN2416)
/* 数据反序 */
buff_bigandsmallend(data_buff, data_len);
#endif
temp_buff[0] = ack_control >> DATA_CONTROL_BIT;
temp_buff[1] = ((ack_control & DATA_ANALYSIS_BIT_L) << DATA_SPLICE_BIT) |
((data_buff[0] >> DATA_CONTROL_BIT) & (~DATA_ANALYSIS_BIT_H));
if (data_len == 0) {
temp_buff[1] &= DATA_ANALYSIS_BIT_H;
}
/* 数据填入 */
for (uint8_t i = 0; i < data_len; i++) {
if (i == (data_len - 1)) {
temp_buff[i + 2] = (data_buff[data_len - 1] & DATA_ANALYSIS_BIT_L) << DATA_SPLICE_BIT;
} else {
temp_buff[i + 2] =
((data_buff[i] & DATA_ANALYSIS_BIT_L) << DATA_SPLICE_BIT) | (data_buff[i + 1] >> DATA_CONTROL_BIT);
}
}
for (uint8_t i = 0; i < data_len + RF_RECV_EXTEN_LEN; i++) {
data_buff[i] = temp_buff[i];
}
#if (1 == XINCX_2_4G_CRC_BYTE)
ack_crc_data = crc8_rohc(ack_crc_buff, data_len + RF_RECV_EXTEN_LEN - 1, RF_CRC_INIT_VALUE, PACKET_ENHANCED);
data_buff[data_len + 1] =
(data_buff[data_len + 1] & DATA_ANALYSIS_BIT_H) | ((ack_crc_data >> DATA_CONTROL_BIT) & (~DATA_ANALYSIS_BIT_H));
data_buff[data_len + 2] = (ack_crc_data << DATA_SPLICE_BIT) & (DATA_ANALYSIS_BIT_H);
memset(&ack_buff[0], 0, sizeof(ack_buff));
whiten_data(&ack_crc_buff[addr_len], data_len, PANCHIP_WHITEN_INIT_VAL);
if (data_len < sizeof(ack_buff))
memcpy(&ack_buff[0], &ack_crc_buff[0], data_len);
else
LOGI("err %s,%d\r\n", __func__, __LINE__);
#elif (2 == XINCX_2_4G_CRC_BYTE)
/* 计算CRC */
ack_crc_data = crc16_ccitt_false(data_buff, data_len + RF_RECV_EXTEN_LEN - 1, rf_addr_crc, PACKET_ENHANCED);
#if (COMPATILBE_MODE == PAN2416)
/* CRC 取反 */
ack_crc_data = ~ack_crc_data;
#endif
/* CRC 放入数据包 */
data_buff[data_len + 1] = (data_buff[data_len + 1] & DATA_ANALYSIS_BIT_H) |
((ack_crc_data >> (DATA_CONTROL_BIT + BIT3)) & (~DATA_ANALYSIS_BIT_H));
data_buff[data_len + 2] = (ack_crc_data >> DATA_CONTROL_BIT) & 0xff;
data_buff[data_len + 3] =
((ack_crc_data & DATA_ANALYSIS_BIT_L) << DATA_SPLICE_BIT) | (SUPPLEMENTARY_DATA >> DATA_CONTROL_BIT);
#if (COMPATILBE_MODE == PAN2416)
/* 白化数据 */
whiten_data(&data_buff[0], data_len + 5, panchip_addr_whiten);
data_buff[data_len + 3] = (data_buff[data_len + 3] & 0xf0) | 0x04;
#endif
if (data_len + 1 < sizeof(ack_buff)) {
for (uint8_t i = 0; i < data_len + 5; i++) {
ack_buff[i] = data_buff[i];
}
} else
LOGI("err %s,%d\r\n", __func__, __LINE__);
#endif
return ack_crc_data;
}
/**
* @brief Rf 2.4g recv enhanced crc
* @param uint8_t *buff
* @param uint8_t buff_len
* @retval uint16_t crc data
*/
__RAM_CODE uint16_t rf_recv_dyn_crc(uint8_t *buff, uint8_t buff_len)
{
uint8_t ack_crc_buff[64] = {0};
for (uint8_t i = 0; i < buff_len; i++) {
ack_crc_buff[i] = buff[i];
}
ack_crc_buff[buff_len - 1] &= DATA_ANALYSIS_BIT_H;
#if (1 == XINCX_2_4G_CRC_BYTE)
return crc8_rohc(ack_crc_buff, buff_len, rf_addr_crc, PACKET_ENHANCED);
#elif (2 == XINCX_2_4G_CRC_BYTE)
return crc16_ccitt_false(ack_crc_buff, buff_len, rf_addr_crc, PACKET_ENHANCED);
#endif
}
/**
* @brief Rf 2.4g recv enhanced packet data parsing
* @param uint8_t *buff
* @param uint8_t buff_len
*/
__RAM_CODE void rf_enhanced_packet(uint8_t *buff, uint8_t buff_len)
{
uint8_t temp_buff[128] = {0};
if (buff_len < sizeof(temp_buff))
memcpy((char *)&temp_buff, (char *)buff, buff_len);
else
LOGI("err %s,%d\r\n", __func__, __LINE__);
for (uint8_t i = 0; i < buff_len; i++) {
buff[i] = ((temp_buff[i + 1] & (~DATA_ANALYSIS_BIT_H)) << DATA_CONTROL_BIT) |
((temp_buff[i + 2] & DATA_ANALYSIS_BIT_H) >> DATA_SPLICE_BIT);
}
}
/**
* @brief Rf 2.4g recv enhanced packet data acquisition and parsing
* @param uint8_t *buff
* @retval uint8_t len
*/
__RAM_CODE uint8_t rf_enhanced_recv_data(uint8_t *buff)
{
uint16_t calc_crc_data = 0;
uint16_t recv_crc_data = 0;
uint8_t len = 0;
if ((XC_RF_2_4G->STATUS & MASK_RX_DR) == MASK_RX_DR) {
CE_CTL_LOW;
rf_wr_cmd(R_RX_PLOAD);
/* Get control field */
buff[0] = XC_RF_2_4G->RX_FIFO_DATA;
#if (COMPATILBE_MODE == PAN2416)
panchip_contorl_whiten = whiten_data(&buff[0], 1, panchip_addr_whiten);
len = ((buff[0] & 0xfe) >> 1);
#elif (COMPATILBE_MODE == BEKEN)
len = ((buff[0] & 0xfe) >> 2);
#endif
/* Get complete data */
if (len > RF_RECV_AMX_LEN) {
len = RF_RECV_AMX_LEN;
}
for (uint8_t i = 1; i < len + RF_RECV_EXTEN_LEN + 2; i++) {
buff[i] = XC_RF_2_4G->RX_FIFO_DATA;
}
/* Clear FIFO and STATUS */
rf_wr_cmd(FLUSH_RX);
XC_RF_2_4G->STATUS = MASK_RX_DR;
#if (COMPATILBE_MODE == PAN2416)
/* Bleaching */
whiten_data(&buff[1], len + 5, panchip_contorl_whiten);
#endif
/* CRC veify */
calc_crc_data = rf_recv_dyn_crc(buff, len + RF_RECV_EXTEN_LEN - 1);
recv_crc_data = ((buff[len + 1] & (~DATA_ANALYSIS_BIT_H)) << (DATA_CONTROL_BIT + BIT3)) |
((buff[len + 2] & 0xff) << DATA_CONTROL_BIT) |
((buff[len + 3] & DATA_ANALYSIS_BIT_H) >> DATA_SPLICE_BIT);
#if (COMPATILBE_MODE == PAN2416)
recv_crc_data = ~recv_crc_data;
#endif
if (recv_crc_data == calc_crc_data) {
/* Verify correctly and parse the data */
rf_enhanced_packet(buff, len + RF_RECV_EXTEN_LEN + 1);
#if (COMPATILBE_MODE == PAN2416)
buff_bigandsmallend(buff, len + RF_RECV_EXTEN_LEN + 1);
#endif
rf_send_ack_stat = TX_DATA_OK;
} else {
/* The verification failed and data was discarded. Procedure */
memset(buff, 0, len);
len = 0;
}
} else {
rf_send_ack_stat = TX_RETRANS_MAX;
}
return len;
}
project/example/2.4g/RF24_AutoAck/app/src/app_rf.c
+830
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#include "app_rf.h"
rf_timer_stat_t timer_stat = RF_FREE_TIMER_INTER;
#define TEST_PIN_USB 1
uint8_t ret = TX_DATA_INVALID;
uint32_t count = 0;
uint32_t send_ok = 0;
uint32_t send_max = 0;
uint8_t rf_ack_len = ACK_LEN;
uint16_t recv_crc_data = 0;
uint16_t calc_crc_data = 0;
bool rf_send_timer_flag = false;
bool rf_recv_timer_flag = false;
bool rf_prx_ack_flag = false;
uint8_t data_len = 0;
rf_data_typedef_t rf_data_t;
uint8_t send_buff[35] = {0};
uint32_t send_cnt = 0;
uint32_t recv_timer_cnt = 0;
uint32_t recv_crc_err = 0;
uint32_t recv_crc_ok = 0;
uint32_t recv_cnt = 0;
extern uint8_t rf_send_ack_stat;
Timer_InitCfg_t timer_cfg = {
.timer_src_clk = TIMER_CLK_SRC_32M_DIV,
.timer_div_clk = TIMER_DIV_CLK_16MHzOr16K,
};
// #if DEBUG_PIN
/**
* @brief Test pin config
* @param void
* @retval void
*/
void gpio_test(void)
{
// LOGI("gpio\r\n");
GPIO_InitCfg_t gpio_cfg;
gpio_cfg.Mux = GPIO_Mux0;
gpio_cfg.FunSel = GPIO_Dx;
gpio_cfg.Pull = GPIO_PULLDOWN;
gpio_cfg.Int = NOT_INT;
gpio_cfg.Dir = GPIO_DIR_OUTPUT;
// #if TEST_PIN_NO_USB
gpio_cfg.Pin = TEST_PIN_1;
xc_gpio_init(&gpio_cfg);
gpio_cfg.Pin = TEST_PIN_2;
xc_gpio_init(&gpio_cfg);
gpio_cfg.Pin = TEST_PIN_3;
xc_gpio_init(&gpio_cfg);
gpio_cfg.Pin = TEST_PIN_5;
xc_gpio_init(&gpio_cfg);
// #endif
gpio_cfg.Pin = TEST_PIN_4;
xc_gpio_init(&gpio_cfg);
gpio_cfg.Pin = TEST_PIN_6;
xc_gpio_init(&gpio_cfg);
// #if TEST_PIN_NO_USB
gpio_cfg.Pin = TEST_PIN_7;
xc_gpio_init(&gpio_cfg);
gpio_cfg.Pin = TEST_PIN_8;
xc_gpio_init(&gpio_cfg);
// #endif
xc_gpio_write_pin(TEST_PIN_1, GPIO_PIN_RESET);
xc_gpio_write_pin(TEST_PIN_2, GPIO_PIN_RESET);
xc_gpio_write_pin(TEST_PIN_3, GPIO_PIN_RESET);
// xc_gpio_write_pin(GPIO_9, GPIO_PIN_RESET);
xc_gpio_write_pin(TEST_PIN_4, GPIO_PIN_RESET);
xc_gpio_write_pin(TEST_PIN_5, GPIO_PIN_RESET);
xc_gpio_write_pin(TEST_PIN_6, GPIO_PIN_RESET);
xc_gpio_write_pin(TEST_PIN_7, GPIO_PIN_RESET);
xc_gpio_write_pin(TEST_PIN_8, GPIO_PIN_RESET);
gpio_cfg.Pull = GPIO_PULLDOWN;
gpio_cfg.Dir = GPIO_DIR_INPUT;
gpio_cfg.Pin = GPIO_4;
xc_gpio_init(&gpio_cfg);
}
// #endif // DEBUG_PIN
/**
* @brief RF 2.4g DEBUG PIN config
* @param uint8_t gpio_id - The parameters can be GPIO 2 ~ 9, GPIO 18 ~ 25, and GPIO 14
* @retval void
*/
void rf_debug_pin(uint8_t gpio_id)
{
uint32_t val;
val = (*(volatile unsigned int *)(0x53022040));
val |= 0x7 << 4;
(*(volatile unsigned int *)(0x53022040)) = val; // TPORT_DATA0_SEL set
val = (*(volatile unsigned int *)(0x53023010));
val &= ~(3 << 28);
val |= (0xa << 16 | 1 << 24 | 2 << 28); // 0xc
(*(volatile unsigned int *)(0x53023010)) = val; // diag_sel[3:0] set
LOGI("after 0x53022040=0x%x, 0x53022010=0x%x\n", *(volatile unsigned int *)(0x53022040),
*(volatile unsigned int *)(0x53023010));
uint32_t addr_val = 0;
switch (gpio_id) {
case GPIO_3:
xc_gpio_fun_sel(gpio_id, GPIO_Dx);
xc_gpio_mux_ctl(gpio_id, GPIO_Mux3); // en test_pin[8]
addr_val = 0x40000170;
break;
case GPIO_4:
xc_gpio_fun_sel(gpio_id, GPIO_Dx);
xc_gpio_mux_ctl(gpio_id, GPIO_Mux3); // en test_pin[8]
addr_val = 0x40000174;
break;
case GPIO_2:
xc_gpio_fun_sel(gpio_id, GPIO_Dx);
xc_gpio_mux_ctl(gpio_id, GPIO_Mux2); // en test_pin[8]
addr_val = 0x40000178;
break;
case GPIO_6:
xc_gpio_fun_sel(gpio_id, GPIO_Dx);
xc_gpio_mux_ctl(gpio_id, GPIO_Mux3); // en test_pin[8]
addr_val = 0x4000017c;
break;
case GPIO_7:
case GPIO_20:
xc_gpio_fun_sel(gpio_id, GPIO_Dx);
xc_gpio_mux_ctl(gpio_id, GPIO_Mux3); // en test_pin[8]
addr_val = 0x40000180;
break;
case GPIO_8:
case GPIO_21:
xc_gpio_fun_sel(gpio_id, GPIO_Dx);
xc_gpio_mux_ctl(gpio_id, GPIO_Mux3); // en test_pin[8]
addr_val = 0x40000184;
break;
case GPIO_9:
case GPIO_14:
case GPIO_22:
xc_gpio_fun_sel(gpio_id, GPIO_Dx);
xc_gpio_mux_ctl(gpio_id, GPIO_Mux3); // en test_pin[8]
addr_val = 0x40000188;
break;
case GPIO_18:
case GPIO_23:
xc_gpio_fun_sel(gpio_id, GPIO_Dx);
xc_gpio_mux_ctl(gpio_id, GPIO_Mux3); // en test_pin[8]
addr_val = 0x4000018c;
break;
case GPIO_19:
case GPIO_24:
xc_gpio_fun_sel(gpio_id, GPIO_Dx);
xc_gpio_mux_ctl(gpio_id, GPIO_Mux3); // en test_pin[8]
addr_val = 0x40000190;
break;
case GPIO_12:
case GPIO_25:
xc_gpio_fun_sel(gpio_id, GPIO_Dx);
xc_gpio_mux_ctl(gpio_id, GPIO_Mux3); // en test_pin[8]
addr_val = 0x40000194;
break;
default:
LOGI("test pin id error\n");
break;
}
*((uint32_t volatile *)addr_val) = 7;
}
/**
* @brief RF 2.4g get address crc
* @param void
* @retval crc data
*/
uint16_t rf_get_addr_crc(void)
{
#if (1 == XINCX_2_4G_CRC_BYTE)
return crc8_rohc(addr_buff, RF_ADDR_LEN, RF_CRC_INIT_VALUE, PACKET_NORMAL);
#elif (2 == XINCX_2_4G_CRC_BYTE)
return crc16_ccitt_false(addr_buff, RF_ADDR_LEN, RF_CRC_INIT_VALUE, PACKET_NORMAL);
#endif
}
///**
// * @brief RF 2.4g buff info
// * @param uint8_t * - buff
// * uint8_t len
// * @retval void
// */
// void rf_buff_info(uint8_t *buff, uint8_t len)
//{
// for (uint8_t i = 0; i < len; i++)
// LOGI("%02x ", buff[i]);
// LOGI("\r\n");
//}
/**
* @brief RF 2.4g panchip tx data config
* @param uint8_t *buff
* @param uint8_t *data_buff
* @param uint8_t data_len
* @retval uint16_t crc data
*/
__RAM_CODE void rf_rx_ack_payload_event(uint8_t *buff, uint8_t len)
{
// /* ACK data filling */
// rf_data_config(ack_buff, len);
/* Dynamic packet grouping */
rf_enhanced_package_grouping(buff, len);
/* ACK pyaload data fill FIFO */
rf_recv_sf_ack_payload(buff, len);
}
/**
* @brief RF 2.4g setting agc
* @param uint8_t adc_rssi_mean
* @param uint8_t agc_gain_delay
* @retval void
*/
void rf_set_agc(uint8_t adc_rssi_mean, uint8_t agc_gain_delay)
{
XC_RF_2_4G->AGC_SETTING &= ~(0xf << 16);
XC_RF_2_4G->AGC_SETTING |= (adc_rssi_mean << 16) | (agc_gain_delay << 18);
}
/**
* @brief RF 2.4g pwr down and up
* @param void
* @retval void
*/
void rf_pwr_down_up(void)
{
XC_RF_2_4G->CFG_TOP &= ~(1 << 1);
XC_RF_2_4G->CFG_TOP |= (1 << 1);
}
__RAM_CODE uint8_t rf_tx2rx_payload_event(rf_data_typedef_t *rf_data, uint8_t *ack_buff)
{
uint8_t send_len = rf_data->data_length + 5;
/* Modulation frequency offset */
XC_RF_2_4G->TXPROC_CFG = ((XC_RF_2_4G->TXPROC_CFG & (~0x1FF)) | RF_FREQ_SEND_DEV);
/* Set receive length */
set_rf_pipe_rx_payLen(send_len, send_len, send_len, send_len, send_len, send_len);
/* Set send mode */
set_rf_mode(TX_MODE);
/* Set the sending frequency */
set_rf_channel(XINCX_2_4G_CHANNEL);
/* data transmission */
rf_enhanced_package_grouping(send_buff, rf_data->data_length);
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_2, GPIO_PIN_SET);
#endif
ret = rf_tx_event(send_buff, send_len);
CE_CTL_LOW;
/* txlo spi en,1=work,默认0 */
XC_BT_RF->ana31_reg_l &= ~(1 << 5);
XC_BT_RF->ana31_reg_l &= ~(1 << 4);
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_2, GPIO_PIN_RESET);
#endif
#if 1
/* Modulation frequency offset */
XC_RF_2_4G->TXPROC_CFG = ((XC_RF_2_4G->TXPROC_CFG & (~0x1FF)) | RF_FREQ_RECV_DEV);
/* 切换到接收模式 */
rf_set_rx_mode(XINCX_2_4G_CHANNEL, XINCX_2_4G_PIPE0_LEN + 5);
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_3, GPIO_PIN_SET);
#endif
/* 等待接收ACK数据 */
#if (COMPATILBE_MODE == PANCHIP_PACKET)
delay_ms(3);
#else
delay_ms(2);
#endif
do {
if (recv_timer_cnt >= (RF_RECV_TIMER + 5)) {
rf_send_ack_stat = TX_RETRANS_MAX;
break;
}
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_4, GPIO_PIN_SET);
#endif // DEBUG_PIN
delay_us(BIT_TIMER);
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_4, GPIO_PIN_RESET);
#endif // DEBUG_PIN
recv_len = rf_enhanced_recv_data(ack_buff);
if (rf_send_ack_stat == TX_DATA_OK) {
recv_cnt += 1;
break;
} else if (rf_send_ack_stat == TX_RETRANS_MAX) {
break;
}
recv_timer_cnt += 1;
} while (!recv_len);
CE_CTL_LOW;
rf_send_ack_stat = TX_DATA_INVALID;
rf_wr_cmd(FLUSH_RX);
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_3, GPIO_PIN_RESET);
#endif // DEBUG_PIN
#endif
recv_timer_cnt = 0;
return recv_len;
}
#if (XINCX_RF_COMPATIBILITY_MODE == PANCHIP_PACKET)
/**
* @brief Timer initialize
* @param uint8_t timer_id
* @param uint32_t timer_cnt
* @retval void
*/
void timer_init(uint8_t timer_id, uint32_t timer_cnt)
{
#if !XINCX_RF_MODE
timer_cfg.timer_mode = TIMER_MODE_CYCLE; // TIMER_MODE_CYCLE//TIMER_MODE_SINGLE
#else
timer_cfg.timer_mode = TIMER_MODE_CYCLE; // TIMER_MODE_CYCLE//TIMER_MODE_SINGLE
#endif
xc_timer_init(timer_id, &timer_cfg);
xc_timer_set_value(timer_id, timer_cnt);
}
/**
* @brief RF 2.4g tx maage
* @param rf_data_typedef_t *rf_data,
* @retval uint32_t rf_data->cnt
*/
__RAM_CODE uint32_t rf_tx_manage(rf_data_typedef_t *rf_data)
{
uint8_t ack_buff[64] = {0};
static uint32_t send_cnt = 0;
if (send_cnt < XC_SEND_NUM) {
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_1, GPIO_PIN_SET);
#endif
rf_send_timer_flag = false;
rf_data->cnt += 1;
/* Filling in software frame number */
rf_data->data_length = 32;
rf_data_config(send_buff, rf_data->data_length);
uint8_t ack_len = rf_tx2rx_payload_event(rf_data, ack_buff);
send_cnt += 1;
LOGI("send_cnt:%d, recv_cnt:%d, recv_len:%d\r\n", send_cnt, recv_cnt, ack_len);
LOGI("ack data(len:%d):%02x\n\n", ack_len, ack_buff[0]);
// rf_buff_info(ack_buff, ack_len);
memset(rf_data->buff, 0, sizeof(rf_data->buff));
memset(ack_buff, 0xff, sizeof(ack_buff));
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_1, GPIO_PIN_RESET);
#endif
rf_send_ack_stat = TX_DATA_INVALID;
}
if (send_cnt == XC_SEND_NUM) {
rf_data->cnt += 1;
send_cnt += 1;
/* Turn off the send timer */
xc_timer_stop(RF_TX_TIMERx);
}
return rf_data->cnt;
}
/**
* @brief timer0 callback
* @param void *context
* @retval void
*/
__RAM_CODE void timer0_callback(void *context)
{
#if XINCX_RF_MODE
xc_timer_stop(RF_RX_TIMERx);
switch (timer_stat) {
case RF_SEND_TIMER_INTER /* 动态 ACk 发射完成 */:
/* code */
timer_stat = RF_FREE_TIMER_INTER;
#if DEBUG_PIN
// xc_gpio_write_pin(TEST_PIN_4, GPIO_PIN_SET);
#endif // DEBUG_PIN
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_5, GPIO_PIN_RESET);
#endif
CE_CTL_LOW;
/* txlo spi en,1=work,默认0 */
XC_BT_RF->ana31_reg_l &= ~(1 << 5);
XC_BT_RF->ana31_reg_l &= ~(1 << 4);
rf_prx_ack_flag = true;
if (recv_len <= BUFF_LEN_MAX) {
} else {
LOGI("err %s,%d\r\n", __func__, __LINE__);
}
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_4, GPIO_PIN_RESET);
#endif // DEBUG_PIN
break;
case RF_RECV_TIMER_INTER /* 动态收包完成 */:
/* code */
xc_timer_stop(RF_RX_TIMERx);
timer_stat = RF_FREE_TIMER_INTER;
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_2, GPIO_PIN_RESET);
#endif // DEBUG_PIN
for (uint8_t i = 1; i < recv_len + RF_RECV_EXTEN_LEN + 1; i++) {
rf_data_t.buff[i] = XC_RF_2_4G->RX_FIFO_DATA;
}
CE_CTL_LOW;
rf_wr_cmd(FLUSH_RX);
XC_RF_2_4G->STATUS |= MASK_RX_DR | MASK_RX_SYNC;
NVIC_EnableIRQ(RF24G_IRQn);
// rf_buff_info(rf_data_t.buff, recv_len+10);
xc_rf_send_ack(rf_data_t.buff, recv_len);
recv_cnt += 1;
break;
case RF_FREE_TIMER_INTER /* 其他状态 */:
rf_set_rx_mode(XINCX_2_4G_CHANNEL, XINCX_2_4G_PIPE0_LEN);
/* code */
break;
default:
break;
}
#else
rf_send_timer_flag = true;
#endif
}
#endif
/**
* @brief RF 2.4g software send ack packet
* @param uint8_t *buff
* @param uint8_t recv_len
* @retval void
*/
__RAM_CODE void xc_rf_send_ack(uint8_t *buff, uint8_t recv_len)
{
#if (1 == XINCX_2_4G_CRC_BYTE)
/* Set the length of the data to be sent */
set_rf_pipe_rx_payLen(rf_ack_len + RF_RECV_EXTEN_LEN, rf_ack_len + RF_RECV_EXTEN_LEN,
rf_ack_len + RF_RECV_EXTEN_LEN, rf_ack_len + RF_RECV_EXTEN_LEN,
rf_ack_len + RF_RECV_EXTEN_LEN, rf_ack_len + RF_RECV_EXTEN_LEN);
/* Set send mode */
set_rf_mode(TX_MODE);
/* Set the transmission frequency */
set_rf_channel(XINCX_2_4G_CHANNEL);
CE_CTL_HIGH;
/* txlo spi en,1=work,默认0 */
XC_BT_RF->ana31_reg_l |= (1 << 5);
/* Theoretical CRC calculation of received data */
calc_crc_data = rf_recv_dyn_crc(rf_data_t.buff, recv_len + RF_RECV_EXTEN_LEN - 1);
/* Get the actual CRC for receiving data */
recv_crc_data = ((rf_data_t.buff[recv_len + 1] & (~BIT7)) << DATA_CONTROL_BIT) |
((rf_data_t.buff[recv_len + 2] & BIT7) >> DATA_SPLICE_BIT);
/* txlo spi en,1=work,默认0 */
XC_BT_RF->ana31_reg_l |= (1 << 4);
/* CRC check */
if (calc_crc_data == recv_crc_data) {
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_4, GPIO_PIN_SET);
#endif // DEBUG_PIN
/* Wait for sending to complete */
xc_timer_set_value(RF_RX_TIMERx, 10 + (rf_ack_len + 9) * BIT_TIMER);
xc_timer_start(RF_RX_TIMERx);
/* Data parsing */
rf_enhanced_packet(rf_data_t.buff, recv_len + RF_RECV_EXTEN_LEN - 1);
#elif (2 == XINCX_2_4G_CRC_BYTE)
set_rf_pipe_rx_payLen(rf_ack_len + RF_RECV_EXTEN_LEN + 2, rf_ack_len + RF_RECV_EXTEN_LEN + 2,
rf_ack_len + RF_RECV_EXTEN_LEN + 2, rf_ack_len + RF_RECV_EXTEN_LEN + 2,
rf_ack_len + RF_RECV_EXTEN_LEN + 2, rf_ack_len + RF_RECV_EXTEN_LEN + 2);
set_rf_mode(TX_MODE);
/* 调制频偏 */
XC_RF_2_4G->TXPROC_CFG = ((XC_RF_2_4G->TXPROC_CFG & (~0x1FF)) | RF_FREQ_SEND_DEV);
set_rf_channel(XINCX_2_4G_CHANNEL);
/* 发射 ACk */
CE_CTL_HIGH;
/* txlo spi en,1=work,默认0 */
XC_BT_RF->ana31_reg_l |= (1 << 5);
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_5, GPIO_PIN_SET);
#endif // DEBUG_PIN
#if (COMPATILBE_MODE == PANCHIP_PACKET)
whiten_data(&rf_data_t.buff[1], recv_len + RF_RECV_EXTEN_LEN, panchip_contorl_whiten);
#endif //(COMPATILBE_MODE == PAN2416)
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_5, GPIO_PIN_RESET);
xc_gpio_write_pin(TEST_PIN_6, GPIO_PIN_SET);
#endif // DEBUG_PIN
calc_crc_data = rf_recv_dyn_crc(rf_data_t.buff, recv_len + RF_RECV_EXTEN_LEN - 1);
recv_crc_data = ((rf_data_t.buff[recv_len + 1] & (~DATA_ANALYSIS_BIT_H)) << (DATA_CONTROL_BIT + BIT3)) |
((rf_data_t.buff[recv_len + 2] & 0xff) << DATA_CONTROL_BIT) |
((rf_data_t.buff[recv_len + 3] & DATA_ANALYSIS_BIT_H) >> DATA_SPLICE_BIT);
// rf_enhanced_packet(rf_data_t.buff, recv_len + RF_RECV_EXTEN_LEN - 1);
// rf_buff_info(rf_data_t.buff, recv_len + 3);
/* txlo spi en,1=work,默认0 */
XC_BT_RF->ana31_reg_l |= (1 << 4);
#if (COMPATILBE_MODE == PANCHIP_PACKET)
recv_crc_data = ~recv_crc_data;
#endif //(COMPATILBE_MODE == PANCHIP_PACKET)
// LOGI("calc_crc_data:0x%02x,recv_crc_data:0x%02x\nrecv_len:%d\n panchip_addr_whiten:%02x\n", calc_crc_data,
// recv_crc_data, recv_len, panchip_addr_whiten);
if (calc_crc_data == recv_crc_data) { /* CRC正确，继续发射ACK*/
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_4, GPIO_PIN_SET);
#endif // DEBUG_PIN
#if (BEKEN_PACKET == COMPATILBE_MODE)
rf_enhanced_packet(rf_data_t.buff, recv_len + RF_RECV_EXTEN_LEN - 1);
/* Wait for sending to complete */
xc_timer_stop(RF_RX_TIMERx);
xc_timer_set_value(RF_RX_TIMERx, (rf_ack_len + 10) * BIT_TIMER);
#elif (COMPATILBE_MODE == PANCHIP_PACKET)
/* Wait for sending to complete */
xc_timer_set_value(RF_RX_TIMERx, 120 + (rf_ack_len + 3 + 5 + 4) * BIT_TIMER);
/* Albino data is parsed into valid data */
rf_enhanced_packet(rf_data_t.buff, recv_len + RF_RECV_EXTEN_LEN + 1);
buff_bigandsmallend(rf_data_t.buff, recv_len + RF_RECV_EXTEN_LEN + 1);
#endif
xc_timer_start(RF_RX_TIMERx);
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_5, GPIO_PIN_SET);
#endif
timer_stat = RF_SEND_TIMER_INTER;
recv_crc_ok += 1;
#endif
} else { /* CRC错误，停止发射ACK并重新填入ACK数据，转接收模式 */
CE_CTL_LOW;
/* txlo spi en,1=work,默认0 */
XC_BT_RF->ana31_reg_l &= ~(1 << 5);
XC_BT_RF->ana31_reg_l &= ~(1 << 4);
memset(rf_data_t.buff, 0, recv_len);
recv_len = 0;
rf_wr_cmd(FLUSH_RX);
rf_data_config(ack_buff, rf_ack_len);
/* ACK data config */
rf_rx_ack_payload_event(ack_buff, rf_ack_len); // 96MHz 32bytes 402us
rf_set_rx_mode(XINCX_2_4G_CHANNEL, XINCX_2_4G_PIPE0_LEN);
timer_stat = RF_FREE_TIMER_INTER;
recv_crc_err += 1;
}
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_6, GPIO_PIN_RESET);
#endif
#if DEBUG_PIN
// xc_gpio_write_pin(TEST_PIN_3, GPIO_PIN_RESET);
#endif // DEBUG_PIN
}
/**
* @brief Set rf 2.4g rx mode
* @param uint16_t channel
* @retval void
*/
__RAM_CODE void rf_set_rx_mode(uint16_t channel, uint16_t fifo_len)
{
CE_CTL_LOW;
#if DEBUG_PIN
// xc_gpio_write_pin(TEST_PIN_7, GPIO_PIN_SET);
#endif // DEBUG_PIN
/* 调制频偏 */
XC_RF_2_4G->TXPROC_CFG = ((XC_RF_2_4G->TXPROC_CFG & (~0x1FF)) | RF_FREQ_RECV_DEV);
/* Set receive length */
set_rf_pipe_rx_payLen(fifo_len, fifo_len, fifo_len, fifo_len, fifo_len, fifo_len);
/* Set recv mode */
set_rf_mode(RX_MODE);
/* Set the receiving frequency */
set_rf_channel(channel);
/* AFC manual configuration */
set_rf_afc();
rf_wr_cmd(FLUSH_RX);
XC_RF_2_4G->STATUS |= MASK_RX_DR;
#if DEBUG_PIN
// xc_gpio_write_pin(TEST_PIN_7, GPIO_PIN_RESET);
#endif
CE_CTL_HIGH;
}
/**
* @brief rf 2.4g enhanced pack data loading fifo
* @param uint8_t *buff
* @param uint8_t len
* @retval void
*/
__RAM_CODE void rf_recv_sf_ack_payload(uint8_t *buff, uint8_t len)
{
rf_wr_cmd(FLUSH_TX);
XC_RF_2_4G->STATUS = MASK_TX_DS | MASK_MAX_RT;
rf_wr_cmd(W_TX_PLOAD);
#if (1 == XINCX_2_4G_CRC_BYTE)
for (uint8_t i = 0; i < rf_ack_len + RF_RECV_EXTEN_LEN; i++)
XC_RF_2_4G->TX_FIFO_DATA = ack_buff[i];
#elif (2 == XINCX_2_4G_CRC_BYTE)
for (uint8_t i = 0; i < rf_ack_len + RF_RECV_EXTEN_LEN + 1; i++) {
XC_RF_2_4G->TX_FIFO_DATA = ack_buff[i];
}
#endif
}
/**
* @brief rf 2.4g enhanced pack data loading fifo
* @param uint8_t *buff
* @param uint8_t len
* @retval void
*/
__RAM_CODE uint8_t rf_recv_enhanced_data(uint8_t *buff)
{
#if (XINCX_RF_TRANS_RATE == RATE_250K)
delay_us(60);
#endif
rf_wr_cmd(R_RX_PLOAD);
delay_us(BIT_TIMER * 3); // 接收第1字节
rf_data_t.buff[0] = XC_RF_2_4G->RX_FIFO_DATA;
/* 获取动态包长度 */
#if (COMPATILBE_MODE == PANCHIP_PACKET)
panchip_contorl_whiten = whiten_data(&rf_data_t.buff[0], 1, panchip_addr_whiten);
recv_len = rf_data_t.buff[0] >> 1;
#else
recv_len = rf_data_t.buff[0] >> 2;
#endif
if (recv_len > RF_RECV_AMX_LEN) {
recv_len = RF_RECV_AMX_LEN;
XC_RF_2_4G->RX_PW_Px_L =
(recv_len + RF_RECV_EXTEN_LEN + EXTEND_LEN) | ((recv_len + RF_RECV_EXTEN_LEN + EXTEND_LEN) << 8);
}
if (!recv_len) {
CE_CTL_LOW;
rf_wr_cmd(FLUSH_RX);
rf_data_config(ack_buff, rf_ack_len);
/* ACK data config */
rf_rx_ack_payload_event(ack_buff, rf_ack_len); // 96MHz 32bytes 402us
CE_CTL_HIGH;
return 0;
}
XC_RF_2_4G->RX_PW_Px_L =
(recv_len + RF_RECV_EXTEN_LEN + EXTEND_LEN) | ((recv_len + RF_RECV_EXTEN_LEN + EXTEND_LEN) << 8);
/* timer 定时退出接收 */
#if (COMPATILBE_MODE == PANCHIP_PACKET)
xc_timer_set_value(RF_RX_TIMERx, (recv_len + 1 + RF_RECV_EXTEN_LEN) * BIT_TIMER + ACK_DELAY);
xc_timer_start(RF_RX_TIMERx);
#else
xc_timer_set_value(RF_RX_TIMERx, (recv_len + 2) * BIT_TIMER + ACK_DELAY);
xc_timer_start(RF_RX_TIMERx);
#endif
timer_stat = RF_RECV_TIMER_INTER;
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_2, GPIO_PIN_SET);
#endif // DEBUG_PIN
return recv_len;
}
/**
* @brief Receive data processing and start replying ACK
* @param void
* @retval void
*/
__RAM_CODE void rf_pwm_recv_data(void)
{
NVIC_DisableIRQ(RF24G_IRQn); //
xc_timer_stop(RF_RX_TIMERx);
rf_prx_ack_flag = false;
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_1, GPIO_PIN_SET);
#endif // DEBUG_PIN
rf_recv_enhanced_data(rf_data_t.buff);
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_1, GPIO_PIN_RESET);
#endif // DEBUG_PIN
}
#if (XINCX_RF_COMPATIBILITY_MODE == PANCHIP_PACKET)
void rf_24g_callback(void *context)
{
uint16_t rf_stat = XC_RF_2_4G->STATUS;
#ifdef XC62XX
if (rf_stat & MASK_RX_SYNC) {
// XC_RF_2_4G->STATUS |= MASK_RX_SYNC;
// printf("-----------------------------1\n");
XC_RF_2_4G->STATUS |= MASK_RX_SYNC;
rf_pwm_recv_data();
}
if (rf_stat & MASK_PBT_CRC_FAIL) {
XC_RF_2_4G->STATUS |= MASK_PBT_CRC_FAIL;
}
#endif
// /* Reception is interrupted when it completes */
// if (rf_stat & MASK_RX_DR) {
// rf24g_rx_irq_flag = true;
// CE_CTL_LOW;
// #if (1 == XINCX_RF_ADV_NVIC_MODE)
// recv_len = rf_rx_event(recv_adv_buf);
// #endif // XINCX_RF_ADV_NVIC_MODE
// #if (1 == XINCX_RF_NVIC_MODE)
// recv_len = rf_rx_event(recv_buf);
// #endif // XINCX_RF_NVIC_MODE
// XC_RF_2_4G->STATUS |= MASK_RX_DR;
// #ifdef XC62XX
// XC_RF_2_4G->STATUS |= MASK_RX_SYNC;
// #endif
// }
/* The sending is interrupted when it completes */
if (rf_stat & MASK_TX_DS) {
rf24g_tx_irq_flag = true;
tx_stat = TX_DATA_OK;
XC_RF_2_4G->STATUS |= MASK_TX_DS;
}
/* The launch timeout is interrupted */
if (rf_stat & MASK_MAX_RT) {
rf24g_tx_irq_flag = true;
tx_stat = TX_RETRANS_MAX;
XC_RF_2_4G->STATUS |= MASK_MAX_RT;
}
}
#endif
/**
* @brief PWM 0 Capture the callback function
* @param void *context
* @retval uint8_t 0
*/
__RAM_CODE uint8_t pwm_capture_ch0_callback(void *context)
{
rf_pwm_recv_data();
return 0;
}
/**
* @brief PWM 1 Capture the callback function
* @param void *context
* @retval uint8_t 0
*/
__RAM_CODE uint8_t pwm_capture_ch1_callback(void *context)
{
rf_pwm_recv_data();
return 0;
}
/**
* @brief PWM 2 Capture the callback function
* @param void *context
* @retval uint8_t 0
*/
__RAM_CODE uint8_t pwm_capture_ch2_callback(void *context)
{
rf_pwm_recv_data();
return 0;
}
/**
* @brief Address whitening and writing
* @param void
* @retval uint8_t whiten_addr
*/
uint8_t rf_recv_addr(void)
{
uint16_t whiten_addr = whiten_data((uint8_t *)addr_buff, RF_ADDR_LEN, PANCHIP_WHITEN_INIT_VAL);
/* Set PTX address */
set_rf_txaddr((addr_buff[0] << 0) | (addr_buff[1] << 8) | (addr_buff[2] << 16) | (addr_buff[3] << 24),
(addr_buff[4]));
/* Set PRX address */
set_rf_pipe0_rxaddr((addr_buff[0] << 0) | (addr_buff[1] << 8) | (addr_buff[2] << 16) | (addr_buff[3] << 24),
(addr_buff[4]));
return whiten_addr;
}
void rf_set_agc_map(uint8_t agc_gain_1th, uint8_t agc_setp)
{
uint8_t agc_map[5] = {0};
for (uint8_t i = 0; i < sizeof(agc_map); i++) {
agc_map[i] = agc_gain_1th - i * agc_setp;
}
XC_RF_2_4G->PGA_SETTING = agc_map[0] | (agc_map[1] << 8) | (agc_map[2] << 16) | (agc_map[3] << 24);
XC_RF_2_4G->TX_ADDR_H &= ~(0xFF << 8);
XC_RF_2_4G->TX_ADDR_H |= (agc_map[4] << 8);
}
project/example/2.4g/RF24_AutoAck/app/src/main.c
+425
View File
@@ -0,0 +1,425 @@
/*!
* \file main.c
*
* \brief Target main implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "main.h"
#include "xc6xxx_rf_2_4g.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Global Variables
-------------------------------------------------------------------------------------*/
volatile bool rf24g_rx_irq_flag = false;
volatile bool rf24g_tx_irq_flag = false;
volatile bool rf24g_rx_to_irq_flag = false;
/*------------------------------------------------------------------------------------
Func Prototype
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
/**
****************************************************************************************
* @brief Clock Initialization
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void clock_init(void)
{
CLOCK_InitCfg_t clock_cfg;
clock_cfg.hfclk_src = CLOCK_HFCLK_SRC_XTAL;
clock_cfg.hfclk_in = CLOCK_HFCLK_IN_32M;
#if (RC_32K)
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_RC;
#endif //(RC_32K)
#if (XTAL_32K)
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL;
#endif // (XTAL_32K)
#if (XTAL_32768K)
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL;
#endif // (XTAL_32768K)
#ifdef XC62XX
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_RC;
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32K;
#else
if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_XTAL) {
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32768;
} else if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_RC) {
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32K;
}
#endif
xc_clock_init_cfg(&clock_cfg);
SysTick_Config(xc_clock_hfclk_in_get() / 100);
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
}
/**
* @brief Rf 2.4g dump log
* @param void
*
* @retval void
*/
#ifdef DEBUG_LOG
void rf_dump_log(void)
{
LOGI("***************** 2.4G Param ******************\n");
LOGI("CFG_TOP: 0x%08x\r\n", XC_RF_2_4G->CFG_TOP);
LOGI("EN_AA: 0x%08x\r\n", XC_RF_2_4G->EN_AA);
LOGI("EN_RXADDR: 0x%08x\r\n", XC_RF_2_4G->EN_RXADDR);
LOGI("SETUP_AW: 0x%08x\r\n", XC_RF_2_4G->SETUP_AW);
LOGI("SETUP_RETR: 0x%08x\r\n", XC_RF_2_4G->SETUP_RETR);
LOGI("RF_CH: 0x%08x\r\n", XC_RF_2_4G->RF_CH);
LOGI("SETUP_RF: 0x%08x\r\n", XC_RF_2_4G->SETUP_RF);
LOGI("STATUS: 0x%08x\r\n", XC_RF_2_4G->STATUS);
LOGI("OBSERVE_TX: 0x%08x\r\n", XC_RF_2_4G->OBSERVE_TX);
LOGI("RSSI: 0x%08x\r\n", XC_RF_2_4G->RSSI);
LOGI("RX_ADDR_P0: 0x%02x%08x\r\n", 0xFF & (XC_RF_2_4G->RX_ADDR_P0_H), XC_RF_2_4G->RX_ADDR_P0_L);
LOGI("RX_ADDR_P1: 0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RX_ADDR_P1_H), XC_RF_2_4G->RX_ADDR_P1_L);
LOGI("RX_ADDR_P2TOP5:0x%08x\r\n", XC_RF_2_4G->RX_ADDR_P2TOP5);
LOGI("BER_RESULT: 0x%08x%08x\r\n", XC_RF_2_4G->BER_ERR_CNT, XC_RF_2_4G->BER_RECV_CNT);
LOGI("AGC_SETTING: 0x%08x\r\n", XC_RF_2_4G->AGC_SETTING);
LOGI("PGA_SETTING: 0x%02x%08x\r\n", ((XC_RF_2_4G->TX_ADDR_H) & 0xFF00) >> 8, XC_RF_2_4G->PGA_SETTING);
LOGI("TX_ADDR: 0x%02x%08x\r\n", ((XC_RF_2_4G->TX_ADDR_H) & 0xFF), XC_RF_2_4G->TX_ADDR_L);
LOGI("RX_PW_PX: 0x%04x %08x\r\n", 0xFFFF & (XC_RF_2_4G->RX_PW_Px_H), XC_RF_2_4G->RX_PW_Px_L);
LOGI("STATUS_FIFO: 0x%08x\r\n", XC_RF_2_4G->STATUS_FIFO);
LOGI("RSSIREC: 0x%08x\r\n", XC_RF_2_4G->RSSIREC);
LOGI("TXPROC_CFG: 0x%08x\r\n", XC_RF_2_4G->TXPROC_CFG);
LOGI("RXPROC_CFG: 0x%02x%08x\r\n", 0xFF & (XC_RF_2_4G->RXPROC_CFG_H), XC_RF_2_4G->RXPROC_CFG_L);
LOGI("DYNPD: 0x%08x\r\n", XC_RF_2_4G->DYNPD);
LOGI("FEATURE: 0x%08x\r\n", XC_RF_2_4G->FEATURE);
LOGI("PGA_SETTING_H: 0x%08x\r\n", XC_RF_2_4G->TX_ADDR_H);
#ifdef XC62XX
LOGI("HW_CONFIG: 0x%08x\r\n", XC_RF_2_4G->HW_CONFIG);
LOGI("PBT_CONFIG: 0x%08x\r\n", XC_RF_2_4G->PBT_CONFIG);
LOGI("PBT_TIMER: 0x%08x\r\n", XC_RF_2_4G->PBT_TIMER);
LOGI("PBT_SYNC_TIME: 0x%08x\r\n", XC_RF_2_4G->PBT_SYNC_TIME);
LOGI("PBT_TX_HEAD: 0x%08x\r\n", XC_RF_2_4G->PBT_TX_HEAD);
LOGI("PBT_RX_HEAD: 0x%08x\r\n", XC_RF_2_4G->PBT_RX_HEAD);
LOGI("PBT_AUTO_TRX_TIME: 0x%08x\r\n", XC_RF_2_4G->PBT_AUTO_TRX_TIME);
#endif
LOGI("TX_POWER 0x%08x\r\n", (XC_BT_RF->ana21_reg_l >> 6) & 0x3f);
LOGI("ana11_reg_l: 0x%08x\r\n", XC_BT_RF->ana11_reg_l);
LOGI("***********************************************\n");
LOGI("\r\n");
}
#endif
/**
* @brief RF 2.4g buff info
* @param uint8_t * - buff
* uint8_t len
* @retval void
*/
void rf_buff_info(uint8_t *buff, uint8_t len)
{
for (uint8_t i = 0; i < len; i++)
LOGI("%02x ", buff[i]);
LOGI("\r\n");
}
void app_uart_init(void)
{
GPIO_InitCfg_t gpio_cfg = {0};
gpio_cfg.Mux = GPIO_Mux0;
gpio_cfg.Pull = GPIO_PULLUP;
gpio_cfg.Int = NOT_INT;
gpio_cfg.FunSel = UART0_TX;
gpio_cfg.Pin = GPIO_18;
gpio_cfg.Dir = GPIO_DIR_OUTPUT;
xc_gpio_init(&gpio_cfg);
gpio_cfg.FunSel = UART0_RX;
gpio_cfg.Pin = GPIO_19;
gpio_cfg.Dir = GPIO_DIR_INPUT;
xc_gpio_init(&gpio_cfg);
UART_InitCfg_t uart_cfg = {0};
uart_cfg.Parity = UART_PARITY_DISABLE;
uart_cfg.StopBits = UART_STOP_1_BITS;
uart_cfg.WordLength = UART_DATA_8_BITS;
uart_cfg.BaudRate = UART_BAUDRATE_115200;
uart_cfg.HardwareFlowControl = UART_HWFC_DISABLE;
xc_uart_init(UART0_IDX, &uart_cfg);
}
/* switch mode and set channel */
void rf_switch_mode(uint8_t mode, uint16_t channel)
{
CE_CTL_LOW;
switch (mode) {
case TX_MODE:
case RX_MODE:
break;
default:
LOGI("The mode is set incorrectly\n");
while(1);
}
set_rf_mode(mode);
rf_set_channel(channel);
#ifdef XC62XX
XC_RF_2_4G->STATUS = ((XC_RF_2_4G->CFG_TOP >> 30) & 0x3 << 7) | ((XC_RF_2_4G->CFG_TOP >> 4) & 0x7 << 4);
#else
XC_RF_2_4G->STATUS = MASK_ALL_INTER;
#endif
rf_wr_cmd(FLUSH_RX);
rf_wr_cmd(FLUSH_TX);
if (mode) {
CE_CTL_HIGH;
}
}
/* RF接收完成回调 */
void rf_24g_rx_dr_cb(void)
{
/* set flag */
rf24g_rx_irq_flag = true;
}
/* RF发送完成回调 */
void rf_24g_tx_ds_cb(void)
{
rf24g_tx_irq_flag = true;
}
/* RF接收超时回调 */
void rf_24g_max_rt_cb(void)
{
rf24g_rx_to_irq_flag = true;
}
/* RF 发送数据（自动应答） */
__RAM_CODE eRF_Tx_Status rf_tx_autoack(uint8_t *buff, uint16_t len)
{
eRF_Tx_Status ret = TX_DATA_INVALID;
/* len can't be 0 */
if (len == 0)
{
return ret;
}
/* rf_off_and_on */
rf_off_and_on();
rf24g_tx_irq_flag = false;
rf24g_rx_to_irq_flag = false;
/* send data */
rf_tx_packet(buff, len);
/* wait for ack */
while(1)
{
/* recv ack */
if(rf24g_tx_irq_flag)
{
ret = TX_DATA_OK;
break;
}
/* time out */
else if(rf24g_rx_to_irq_flag)
{
ret = TX_RETRANS_MAX;
break;
}
}
return ret;
}
__RAM_CODE void rf24g_AckPayload_tx_demo(void)
{
uint8_t ack_status = TX_DATA_INVALID;
uint8_t ack_buff[BUFF_LEN] = {0};
uint8_t tx_buff[BUFF_LEN] = {0};
uint8_t ack_len = 0;
uint32_t ack_cnt = 0;
uint32_t tx_cnt = 0;
/* Set testing frequency points */
rf_switch_mode( TX_MODE, XINCX_2_4G_CHANNEL);
/* fill data */
for (uint8_t i = 0; i < BUFF_LEN; i++)
{
tx_buff[i] = i;
}
LOGI( "AutoAck Tx Demo start!\r\n");
/* main loop */
while(true)
{
/* data transmission */
tx_cnt ++;
LOGI( "\r\ntx_cnt = %d\r\n",tx_cnt);
ack_status = rf_tx_autoack(tx_buff, BUFF_LEN);
/* recv ack */
if(ack_status == TX_DATA_OK)
{
ack_cnt += 1;
/* read ack payload */
ack_len = rf_read_ack_packet(ack_buff);
LOGI( "ack_cnt:%d,len=%d\r\n", ack_cnt, ack_len);
if(ack_len)
{
/* print ack data */
rf_buff_info( ack_buff, ack_len);
}
}
else
{
LOGI( "No ack,ack_cnt=%d\r\n",ack_cnt);
}
delay_ms(10);
}
}
__RAM_CODE void rf24g_AckPayload_rx_demo(void)
{
uint8_t ack_buff[BUFF_LEN] = {0};
uint8_t rx_buff[BUFF_LEN] = {0};
uint8_t rx_len;
uint32_t rx_cnt = 0;
/* fill data */
for (uint8_t i = 0; i < BUFF_LEN; i++)
{
ack_buff[i] = BUFF_LEN - i;
}
/* Fill ack pyaload of next packet */
rf_fill_ack_packet(ack_buff, BUFF_LEN);
/* Set the communication mode */
rf_switch_mode( RX_MODE, XINCX_2_4G_CHANNEL);
LOGI( "AutoAck Rx Demo start!\r\n");
while(true)
{
if (rf24g_rx_irq_flag)
{
rf24g_rx_irq_flag = false;
/* Entering standby mode */
CE_CTL_LOW;
/* Read rf data */
rx_len = rf_rx_packet(rx_buff);
/* Receive Count */
rx_cnt += 1;
LOGI("recv:%d\r\n", rx_cnt);
/* Print the received data. */
//rf_buff_info(rx_buff, rx_len);
delay_us(200);
/* rf_off_and_on */
rf_off_and_on();
/* Fill ack pyaload of next packet */
rf_fill_ack_packet(ack_buff, BUFF_LEN);
/* Start recv */
CE_CTL_HIGH;
}
}
}
int main(void)
{
/* Clock initialization */
clock_init();
/* Serial port initialization */
app_uart_init();
/* rf 2.4g initialization configuration */
rf24g_init();
#if (XINCX_RF_TRANS_RATE == DR_250K)
rf_ack_payload_config();
#elif (XINCX_RF_TRANS_RATE == DR_2M)
/* Set 2M mode register configuration */
/* Don't move this function interface */
rf_2M_config();
#endif
#if (XINCX_RF_NVIC_MODE)
/* Enable RF2.4G interrupts */
NVIC_EnableIRQ(RF24G_IRQn);
/* Configure the RF2.4G interrupt priority */
NVIC_SetPriority(RF24G_IRQn, 0);
#endif // XINCX_RF_NVIC_MODE
xc_system_param_check_rf24g();
#if XINCX_RF_MODE == TX_MODE
rf24g_AckPayload_tx_demo();
#elif XINCX_RF_MODE == RX_MODE
rf24g_AckPayload_rx_demo();
#endif
while(true);
}
project/example/2.4g/RF24_AutoAck/mdk/JLinkSettings.ini
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[BREAKPOINTS]
ForceImpTypeAny = 0
ShowInfoWin = 1
EnableFlashBP = 2
BPDuringExecution = 0
[CFI]
CFISize = 0x00
CFIAddr = 0x00
[CPU]
MonModeVTableAddr = 0xFFFFFFFF
MonModeDebug = 0
MaxNumAPs = 0
LowPowerHandlingMode = 0
OverrideMemMap = 0
AllowSimulation = 1
ScriptFile=""
[FLASH]
RMWThreshold = 0x400
Loaders=""
EraseType = 0x00
CacheExcludeSize = 0x00
CacheExcludeAddr = 0x00
MinNumBytesFlashDL = 0
SkipProgOnCRCMatch = 1
VerifyDownload = 1
AllowCaching = 1
EnableFlashDL = 2
Override = 0
Device="ARM7"
[GENERAL]
WorkRAMSize = 0x00
WorkRAMAddr = 0x00
RAMUsageLimit = 0x00
[SWO]
SWOLogFile=""
[MEM]
RdOverrideOrMask = 0x00
RdOverrideAndMask = 0xFFFFFFFF
RdOverrideAddr = 0xFFFFFFFF
WrOverrideOrMask = 0x00
WrOverrideAndMask = 0xFFFFFFFF
WrOverrideAddr = 0xFFFFFFFF
[RAM]
VerifyDownload = 0x00
[DYN_MEM_MAP]
NumUserRegion = 0x00
project/example/2.4g/RF24_AutoAck/mdk/Linker/Initialization.ini
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FUNC void Initialization(void)
{
SP = _RDWORD(0x10000000);
PC = _RDWORD(0x10000004);
}
LOAD %L INCREMENTAL
Initialization();
project/example/2.4g/RF24_AutoAck/mdk/Linker/XIPInitialization.ini
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FUNC void InitGpio(void)
{
// Config IOMUX
/*
gpio_mux_ctl_u(33,1);//d2
gpio_mux_ctl_u(34,1);//d3
gpio_mux_ctl_u(35,2);//clk
gpio_mux_ctl_u(36,2);//cs
gpio_mux_ctl_u(37,2);//d0 rx
gpio_mux_ctl_u(38,2);//d1 tx
*/
_WDWORD(0x4000019c, 0x00002A94);
}
FUNC void InitFlash(void)
{
}
FUNC void InitXIP(void)
{
_WDWORD(0x40000104,0x040000);//reset ssi0
_WDWORD(0x40000104,0x040004);//reset ssi0
_WDWORD(0x40000050,0x110000);//close spi0 mclk
_WDWORD(0x40000070,0x1000000);//close spi0 pclk
//config fmc
_WDWORD(0x40000270, 0x0503);
_Sleep_(1);// delay about 400us
_WDWORD(0x40000270, 0x3503);
//config cache
_Sleep_(1);// delay about 400us
_WDWORD(0x52000000, 0x0);
_Sleep_(1);// delay about 400us
_WDWORD(0x52000000, 0x21);
_Sleep_(1);// delay about 400us
_Sleep_(1);// delay about 400us
_Sleep_(1);// delay about 400us
_Sleep_(1);// delay about 400us
//config xip spi
_WDWORD(0x51000008, 0); //disable spi
_WDWORD(0x5100002c,0); //close IE
_WDWORD(0x51000000,0x1F); //32bit SPI data
_WDWORD(0x51000010,0x01); //enable select slave -- SE
_WDWORD(0x51000018,0x0); //TXFTL be set 0
_WDWORD(0x5100001c,0x0); //RXFTL be set 0
_WDWORD(0x5100010c, 0x01);//enable select slave
_WDWORD(0x51000114, 0xFF);//XIP time out
_WDWORD(0x51000014, 0x2);//div 2
//quad
// _WDWORD(0x51000108, (2)|(6<<4)|(2<<9)|(1<<22)|(1<<29)|(1<<23)|(0<<24)|(8<<13));
// _WDWORD(0x51000100, 0x6b);//quad read cmd
// _WDWORD(0x51000104, 0x6b);//quad read cmd
//dual
_WDWORD(0x51000108, (1)|(6<<4)|(2<<9)|(1<<22)|(1<<29)|(1<<23)|(0)|(8<<13));
_WDWORD(0x51000100, 0x3b);//dual read cmd
_WDWORD(0x51000104, 0x3b);//dual read cmd
_WDWORD(0x51000008, 1); //enable spi
}
FUNC void Initialization(void)
{
InitGpio();
InitFlash();
InitXIP();
SP = _RDWORD(0x11001000);
PC = _RDWORD(0x11001004);
_WDWORD(0x4000013C, 0x11001001);
}
LOAD %L INCREMENTAL
Initialization();
project/example/2.4g/RF24_AutoAck/mdk/Linker/cpu.scat
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LOAD 0x10000000
{
EXE 0x10000000
{
startup_xinc.o (RESET, +FIRST)
* (+RO)
}
RW +0000
{
* (+RW,+ZI)
}
ScatterAssert(ImageLength(RW) < 1024 * 28)
}
project/example/2.4g/RF24_AutoAck/mdk/Linker/cpu_xip.scat
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LOAD 0x11001000
{
EXE 0x11001000
{
startup_xinc.o (RESET, +FIRST)
* (+RO)
}
RW 0x100000C8
{
* (+RW,+ZI)
*(ram_code)
aeabi_sdiv.o(.text)
rt_memclr.o(.text)
}
ScatterAssert( (0xC8)+ImageLength(RW) < 1024 * 32)
RW2 (0x53004000)
{
*(ram_em)
}
ScatterAssert( ImageLength(RW2) < 1024 * 16)
}
project/example/2.4g/RF24_AutoAck/mdk/Linker/cpu_xip_xc62xx.scat
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LOAD 0x11001000
{
EXE 0x11001000
{
startup_xinc.o (RESET, +FIRST)
* (+RO)
}
RW 0x100000C8 0x1F38
{
* (+RW,+ZI)
*(ram_code)
aeabi_sdiv.o(.text)
}
ScatterAssert((0x10000100 )+ImageLength(RW) < 0x10000100 + 1024 * 8)
}
project/example/2.4g/RF24_AutoAck/mdk/Output/0_ram.bin
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project/example/2.4g/RF24_AutoAck/mdk/Output/ram_program.bat
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Xincboot_tool.exe 0_ram.bin 1_ram_download.bin 0 0 0 0 1
project/example/2.4g/RF24_AutoAck/mdk/Output/rf24_AutoAck.bin
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project/example/2.4g/RF24_AutoAck/mdk/Output/rf24_AutoAck_xip.bin
BIN
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project/example/2.4g/RF24_AutoAck/mdk/Output/xip_dual
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project/example/2.4g/RF24_AutoAck/mdk/Output/xip_program.bat
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.\Tools\xinchip_xip_tool.exe .\Output\0_ram.bin .\Output\xip_dual .\Output\rf24_AutoAck_xip.bin
project/example/2.4g/RF24_AutoAck/mdk/Tools/Xincboot_tool.exe
BIN
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project/example/2.4g/RF24_AutoAck/mdk/Tools/dump.py
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#!/usr/bin/env python
#-*- coding:UTF-8 -*-
import socket
from select import select
import time
import os
import sys
import threading
import json
import struct
import binascii
import time
import re
import fileinput
def dump_addr(addr):
file_asm = "./Xinc_ble_sdk_asm"
cur_func = ""
with open(file_asm, 'r') as fd:
for line in fd:
if re.match(r" \w+", line) != None:
cur_func = line.strip()
#
if re.search("^ 0x", line) != None and re.search(addr, line) != None:
print(addr, cur_func)
break
fd.close()
if __name__ == "__main__":
file_in = "./dump.txt"
for line in fileinput.input(file_in):
# 处理 PC 指针信息
if re.search("PC = ", line) != None:
pc_addr = line.split("PC = ")[1].split(",")[0]
#print(hex(int(pc_addr, 16)))
dump_addr(hex(int(pc_addr, 16)))
# 处理 栈信息
if re.search("^[0-9]",line) != None:
#print(line)
stack = line.split('=')[1].replace('\n', '').split(' ')
for addr in stack:
if addr == ' ' or re.search("^1", addr) == None:
continue
#print(addr, hex(int(addr,16)-1))
dump_addr(hex(int(addr,16)-1))
project/example/2.4g/RF24_AutoAck/mdk/Tools/xinchip_xip_tool.exe
BIN
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project/example/2.4g/RF24_AutoAck/mdk/rf24_AutoAck.uvoptx
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp; *.cc; *.cxx</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>rf24_AutoAck</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
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<LGenerateSymbols>1</LGenerateSymbols>
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project/example/2.4g/RF24_AutoAck/mdk/rf24_AutoAck.uvprojx
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File diff suppressed because it is too large Load Diff
project/example/2.4g/RF24_AutoAck/mdk/rf24_AutoAck_XC62XX.uvoptx
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project/example/2.4g/RF24_AutoAck/mdk/rf24_AutoAck_XC62XX.uvprojx
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<TargetName>rf24_AutoAck_XC62XX</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060960::V5.06 update 7 (build 960)::.\arm506_update7_960</pCCUsed>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>ARMCM0</Device>
<Vendor>ARM</Vendor>
<PackID>ARM.CMSIS.5.7.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:ARMCM0$Device\ARM\ARMCM0\Include\ARMCM0.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:ARMCM0$Device\ARM\SVD\ARMCM0.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\Objects\</OutputDirectory>
<OutputName>RF24_AutoAck</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\Listings\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name>fromelf --bin --output=.\Output\0_ram.bin !L</UserProg1Name>
<UserProg2Name>.\Output\xip_program.bat</UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name>fromelf --text -a -c --output=.\Tools\@L_asm !L</UserProg1Name>
<UserProg2Name>.\tools\Xincboot_tool .\Output\0_ram.bin .\Output\1_ram_download.bin</UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>1</RunUserProg1>
<RunUserProg2>1</RunUserProg2>
<UserProg1Name>fromelf --bin --output=.\Output\0_ram.bin !L</UserProg1Name>
<UserProg2Name>.\Output\xip_program.bat</UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> </SimDllArguments>
<SimDlgDll>DARMCM1.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM0</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> </TargetDllArguments>
<TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4096</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3>"" ()</Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M0"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<RvdsMve>0</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>0</useUlib>
<EndSel>1</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>0</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>0</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x20000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x40000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x40000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x20000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
<uGnu>1</uGnu>
<useXO>0</useXO>
<v6Lang>3</v6Lang>
<v6LangP>3</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls>--gnu --diag_suppress=66</MiscControls>
<Define>XC62XX DEBUG_ENABLE USE_XIP=1 RF_DEMO</Define>
<Undefine></Undefine>
<IncludePath>..\app\api;..\..\..\..\..\component\xc6xx_drivers\Drivers;..\..\..\..\..\component\xc6xx_drivers\Drivers\CMSIS\Device;..\app\Startup;..\app\Startup\xc60xx;..\..\..\..\..\component\xc6xx_drivers\Drivers\test_case\CLOCK;..\..\..\..\..\component\xc6xx_drivers\Drivers\test_case\PWR;..\..\..\..\..\component\xc6xx_drivers\Drivers\Periph_HAL_Driver\Bitfields;..\..\..\..\..\component\xc6xx_drivers\Drivers\Periph_HAL_Driver\Ringbuffer;..\..\..\..\modules\shell\api;..\..\..\..\..\component\xc6xx_drivers\Drivers\CMSIS;..\..\..\..\..\component\xc6xx_drivers\Drivers\Periph_HAL_Driver;..\..\..\..\..\component\rf24\Drivers;..\..\..\..\..\component\rf24\Drivers\xc6xxx_rf_2_4g;..\..\..\..\..\component\rf24\Drivers\xc_rf24g_register;..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver;..\app\rf_config;..\..\..\..\..\component\xc6xx_drivers\Drivers\CMSIS\Device\xc_m0_register</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<ClangAsOpt>1</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>.\Linker\cpu_xip_xc62xx.scat</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>Startup</GroupName>
<Files>
<File>
<FileName>core_cm0.h</FileName>
<FileType>5</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\CMSIS\core_cm0.h</FilePath>
</File>
<File>
<FileName>startup_xinc.s</FileName>
<FileType>2</FileType>
<FilePath>..\app\Startup\xc60xx\startup_xinc.s</FilePath>
</File>
<File>
<FileName>system_xinc.c</FileName>
<FileType>1</FileType>
<FilePath>..\app\Startup\system_xinc.c</FilePath>
</File>
<File>
<FileName>system_it_xinc.c</FileName>
<FileType>1</FileType>
<FilePath>..\app\Startup\system_it_xinc.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Application</GroupName>
<Files>
<File>
<FileName>main.c</FileName>
<FileType>1</FileType>
<FilePath>..\app\src\main.c</FilePath>
</File>
<File>
<FileName>sdk_config.h</FileName>
<FileType>5</FileType>
<FilePath>..\app\api\sdk_config.h</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>RF_Config</GroupName>
<Files>
<File>
<FileName>rf_config.h</FileName>
<FileType>5</FileType>
<FilePath>..\app\rf_config\rf_config.h</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>RF_Drivers</GroupName>
<Files>
<File>
<FileName>xc6xxx_rf_2_4g.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\rf24\Drivers\xc6xxx_rf_2_4g\xc6xxx_rf_2_4g.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Drivers</GroupName>
<Files>
<File>
<FileName>xc_drv_adc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_adc.c</FilePath>
</File>
<File>
<FileName>xc_drv_aotimer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_aotimer.c</FilePath>
</File>
<File>
<FileName>xc_drv_bor.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_bor.c</FilePath>
</File>
<File>
<FileName>xc_drv_calib.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_calib.c</FilePath>
</File>
<File>
<FileName>xc_drv_clock.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_clock.c</FilePath>
</File>
<File>
<FileName>xc_drv_dma.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_dma.c</FilePath>
</File>
<File>
<FileName>xc_drv_fmc_spi.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_fmc_spi.c</FilePath>
</File>
<File>
<FileName>xc_drv_fmc_spi_dma.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_fmc_spi_dma.c</FilePath>
</File>
<File>
<FileName>xc_drv_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_gpio.c</FilePath>
</File>
<File>
<FileName>xc_drv_i2c.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_i2c.c</FilePath>
</File>
<File>
<FileName>xc_drv_pga.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_pga.c</FilePath>
</File>
<File>
<FileName>xc_drv_pwm.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_pwm.c</FilePath>
</File>
<File>
<FileName>xc_drv_pwr.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_pwr.c</FilePath>
</File>
<File>
<FileName>xc_drv_qdec.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_qdec.c</FilePath>
</File>
<File>
<FileName>xc_drv_rtc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_rtc.c</FilePath>
</File>
<File>
<FileName>xc_drv_spi.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_spi.c</FilePath>
</File>
<File>
<FileName>xc_drv_spi_dma.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_spi_dma.c</FilePath>
</File>
<File>
<FileName>xc_drv_sw_i2c.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_sw_i2c.c</FilePath>
</File>
<File>
<FileName>xc_drv_systick.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_systick.c</FilePath>
</File>
<File>
<FileName>xc_drv_timer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_timer.c</FilePath>
</File>
<File>
<FileName>xc_drv_uart.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_uart.c</FilePath>
</File>
<File>
<FileName>xc_drv_uart_dma.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_uart_dma.c</FilePath>
</File>
<File>
<FileName>xc_drv_wdt.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_wdt.c</FilePath>
</File>
</Files>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis/>
<components/>
<files>
<file attr="config" category="linkerScript" condition="ARMCC5" name="Device\ARM\ARMCM0\Source\ARM\ARMCM0_ac5.sct" version="1.0.0">
<instance index="0" removed="1">RTE\Device\ARMCM0\ARMCM0_ac5.sct</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM0 CMSIS" isDefaultVariant="1"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.8.0"/>
<targetInfos/>
</file>
<file attr="config" category="sourceC" name="Device\ARM\ARMCM0\Source\startup_ARMCM0.c" version="2.0.3">
<instance index="0" removed="1">RTE\Device\ARMCM0\startup_ARMCM0.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM0 CMSIS" isDefaultVariant="1"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.8.0"/>
<targetInfos/>
</file>
<file attr="config" category="sourceC" name="Device\ARM\ARMCM0\Source\system_ARMCM0.c" version="1.0.0">
<instance index="0" removed="1">RTE\Device\ARMCM0\system_ARMCM0.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM0 CMSIS" isDefaultVariant="1"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.8.0"/>
<targetInfos/>
</file>
</files>
</RTE>
<LayerInfo>
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
</Layer>
</Layers>
</LayerInfo>
</Project>
project/example/2.4g/RF24_AutoAckSw/app/Startup/lora/startup_xinc.s
+234
View File
@@ -0,0 +1,234 @@
;/*****************************************************************************
; * @file: startup_xinc.s
; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
; * Device xinc.
; *****************************************************************************/
Stack_Size EQU 0x00000600
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; ToDo: Add here the vectors for the device specific external interrupts handler
DCD 0 ; 0 BLE Handler
DCD DMAS_Handler ; 1
DCD CPR_Handler ; 2
DCD GPIO_Handler ; 3
DCD RTC_Handler ; 4
DCD TIMER0_Handler ; 5
DCD TIMER1_Handler
DCD TIMER2_Handler
DCD TIMER3_Handler
DCD WDT_Handler
DCD I2C_Handler
DCD UART0_Handler
DCD UART1_Handler
DCD SPI0_Handler
DCD SPI1_Handler
DCD 0
DCD 0
DCD GADC_Handler ; 17
DCD 0 ; 18
DCD 0 ; 19
DCD 0 ; 20
DCD 0 ; 21
DCD RF24G_Handler ; 22
DCD PWM_Handler ; 23
DCD BOR_Handler ; 24
DCD 0 ; 25
DCD 0 ; 26
DCD AOTIMER0_Handler ; 27
DCD AOTIMER1_Handler ; 28
DCD CMP_Handler ; 29
DCD FMC_Handler ; 30
DCD CAN_Handler ; 31
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR r0, =0x4000013C ; remap
LDR r1, =0x10000001
STR r1, [r0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
Default_Handler PROC
;EXPORT BLE_Handler [WEAK]
EXPORT DMAS_Handler [WEAK]
EXPORT CPR_Handler [WEAK]
EXPORT GPIO_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT TIMER2_Handler [WEAK]
EXPORT TIMER3_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT I2C_Handler [WEAK]
EXPORT UART0_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
EXPORT SPI0_Handler [WEAK]
EXPORT SPI1_Handler [WEAK]
;EXPORT KBS_Handler [WEAK]
;EXPORT QDEC_Handler [WEAK]
EXPORT GADC_Handler [WEAK]
EXPORT AOTIMER0_Handler [WEAK]
EXPORT AOTIMER1_Handler [WEAK]
EXPORT CMP_Handler [WEAK]
EXPORT FMC_Handler [WEAK]
EXPORT CAN_Handler [WEAK]
;EXPORT SIM_Handler [WEAK]
;EXPORT AES_Handler [WEAK]
EXPORT PendSV_Handler [WEAK]
EXPORT SysTick_Handler [WEAK]
EXPORT RF24G_Handler [WEAK]
EXPORT PWM_Handler [WEAK]
EXPORT BOR_Handler [WEAK]
PendSV_Handler
SysTick_Handler
;BLE_Handler
DMAS_Handler
CPR_Handler
GPIO_Handler
RTC_Handler
TIMER0_Handler
TIMER1_Handler
TIMER2_Handler
TIMER3_Handler
WDT_Handler
I2C_Handler
UART0_Handler
UART1_Handler
SPI0_Handler
SPI1_Handler
;KBS_Handler
;QDEC_Handler
GADC_Handler
;SIM_Handler
;AES_Handler
AOTIMER0_Handler
AOTIMER1_Handler
CMP_Handler
FMC_Handler
CAN_Handler
RF24G_Handler
PWM_Handler
BOR_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
END

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