xushaoxiang
151 lines
4.5 KiB
C
151 lines
4.5 KiB
C
/*
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* @Descripttion:
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* @version:
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* @Author: sueRimn
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* @Date: 2024-05-09 11:45:27
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* @LastEditors: sueRimn
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* @LastEditTime: 2024-07-24 15:18:52
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*/
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#ifndef __APP_DATA_H__
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#define __APP_DATA_H__
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#include "rf_config.h"
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#include "xc6xxx_rf_2_4g.h"
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#include "xc_software_crc.h"
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#include <stdint.h>
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#define BEKEN (0)
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#define PAN2416 (1)
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#ifdef TELINK_MODE
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#define COMPATILBE_MODE BEKEN
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#endif
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#ifdef BEKEN_MODE
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#define COMPATILBE_MODE BEKEN
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#endif
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#ifdef PANCHIP_MODE
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#define COMPATILBE_MODE PAN2416
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#endif
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#define RF_CONFIRMED_VALUE (5U)
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/* 最大接收数据长度 */
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#define BUFF_LEN_MAX (32U)
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#define RF_RECV_AMX_LEN (BUFF_LEN_MAX)
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#define RF_PRX_READ_RXFIFO_TIMER (RF_RECV_AMX_LEN)
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#define BIT7 0x80
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#define BIT6 0x40
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#define BIT5 0x20
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#define BIT4 0x10
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#define BIT3 0x08
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#define BIT2 0x04
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#define BIT1 0x02
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#define BIT0 0x01
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/* 动态包位移长度，单位bit */
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#if (BEKEN == COMPATILBE_MODE)
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#define DATA_ANALYSIS_BIT_H (BIT7)
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#define DATA_ANALYSIS_BIT_L (BIT0)
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#define DATA_CONTROL_BIT (1U)
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#define DATA_CONTROL_NOACK (1U) // 1-ack 0-noack
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#elif (PAN2416 == COMPATILBE_MODE)
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#define DATA_ANALYSIS_BIT_H (BIT7 | BIT6)
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#define DATA_ANALYSIS_BIT_L (BIT0 | BIT1)
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#define DATA_CONTROL_BIT (2U)
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#define DATA_CONTROL_NOACK (0U) // 0-ack 1-noack
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#endif
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#define DATA_SPLICE_BIT (8U - DATA_CONTROL_BIT)
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/* 地址长度 */
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#define RF_ADDR_LEN XINCX_RF_TX_ADDR_WIDTH // 5U
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/* 接收CRC+contorl字段长度 */
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#define RF_RECV_EXTEN_LEN (3U)
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/* CRC初始值 */
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#if (1 == XINCX_2_4G_CRC_BYTE)
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#define RF_CRC_INIT_VALUE (0xFF) // CRC8 0xFF CRC16 0xFFFF
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#elif (2 == XINCX_2_4G_CRC_BYTE)
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#define RF_CRC_INIT_VALUE (0xFFFF) // CRC8 0xFF CRC16 0xFFFF
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#endif
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/* 调制频偏 */
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#if ((XINCX_RF_TRANS_RATE == DR_250K) && (PAN2416 == COMPATILBE_MODE))
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#define RF_FREQ_DEV (0xb8) // 0x75
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#define RF_FREQ_SEND_DEV (0x90) // 0xb8//0xa0
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#define RF_FREQ_RECV_DEV (0x80) // 0x98//0xa0
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#define ACK_DELAY (50) //(300)
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#elif ((XINCX_RF_TRANS_RATE == DR_1M) && (PAN2416 == COMPATILBE_MODE))
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#define RF_FREQ_DEV (0xd0) // 0xb8//0xa0
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#define RF_FREQ_SEND_DEV (0xe0) // 0xb8//0xa0
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#define RF_FREQ_RECV_DEV (0x80) // 0x98//0xa0
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#define ACK_DELAY (300) //(300)
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#elif ((XINCX_RF_TRANS_RATE == DR_1M) && (BEKEN == COMPATILBE_MODE))
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#define RF_FREQ_DEV (0x80) // 0x75
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#define RF_FREQ_SEND_DEV (0xd0) // 0xb8//0xa0
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#define RF_FREQ_RECV_DEV (RF_FREQ_DEV) // 0x98//0xa0
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#define ACK_DELAY (40)
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#elif ((XINCX_RF_TRANS_RATE == DR_250K) && (BEKEN == COMPATILBE_MODE))
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#define RF_FREQ_DEV (0x80) // 0x75
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#define RF_FREQ_SEND_DEV (0xd0) // 0xb8//0xa0
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#define RF_FREQ_RECV_DEV (RF_FREQ_DEV) // 0x98//0xa0
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#define ACK_DELAY (0)
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#endif
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/* 磐启白化初始值 */
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#define PANCHIP_WHITEN_INIT_VAL (0x7F)
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/* ACK 长度 */
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#define ACK_LEN (32U) // 32U
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/* */
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#define USB_TEST (1U)
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/* 测试IO 使能 */
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#define DEBUG_PIN (1U)
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#define TEST_PIN_NO_USB (1U)
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/* 测试IO */
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#define TEST_PIN_1 GPIO_3
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#define TEST_PIN_2 GPIO_6
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#define TEST_PIN_3 GPIO_7
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#define TEST_PIN_4 GPIO_8
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#define TEST_PIN_5 GPIO_1
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#define TEST_PIN_6 GPIO_4
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#define TEST_PIN_7 GPIO_5
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#define TEST_PIN_8 GPIO_0
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/* ACK固定接收字节数 */
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#define RF_RECV_TIMER \
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(XINCX_2_4G_PREAMBLE_NUM + 1 + XINCX_RF_TX_ADDR_WIDTH + RF_PRX_READ_RXFIFO_TIMER + XINCX_2_4G_CRC_BYTE + 2 + 10)
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/* 速率-bit占用时间 */
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#if (XINCX_RF_TRANS_RATE == DR_2M)
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#define BIT_TIMER (4U)
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#elif (XINCX_RF_TRANS_RATE == DR_1M)
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#define BIT_TIMER (8U)
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#elif (XINCX_RF_TRANS_RATE == DR_250K)
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#define BIT_TIMER (32U)
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#elif (XINCX_RF_TRANS_RATE == DR_125K)
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#define BIT_TIMER (64U)
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#endif
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extern uint8_t addr_buff[5];
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extern uint8_t ack_buff[BUFF_LEN];
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extern uint16_t rf_addr_crc;
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extern uint8_t panchip_addr_whiten;
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extern uint8_t panchip_contorl_whiten;
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extern uint8_t rf_send_ack_stat;
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void rf_enhanced_packet(uint8_t *buff, uint8_t buff_len);
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uint16_t rf_recv_dyn_crc(uint8_t *buff, uint8_t buff_len);
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uint16_t rf_enhanced_package_grouping(uint8_t *data_buff, uint8_t data_len);
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uint8_t read_addr_wid(uint8_t *addr_buff);
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void rf_addr_map(uint8_t *addr_buff);
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uint8_t rf_enhanced_recv_data(uint8_t *buff);
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#endif
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