hpw422移植新的sdk
This commit is contained in:
xushaoxiang
@@ -0,0 +1,234 @@
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;/*****************************************************************************
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; * @file: startup_xinc.s
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; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
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; * Device xinc.
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; *****************************************************************************/
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Stack_Size EQU 0x00000600
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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Heap_Size EQU 0x00000000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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; ToDo: Add here the vectors for the device specific external interrupts handler
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DCD 0 ; 0 BLE Handler
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DCD DMAS_Handler ; 1
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DCD CPR_Handler ; 2
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DCD GPIO_Handler ; 3
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DCD RTC_Handler ; 4
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DCD TIMER0_Handler ; 5
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DCD TIMER1_Handler
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DCD TIMER2_Handler
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DCD TIMER3_Handler
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DCD WDT_Handler
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DCD I2C_Handler
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DCD UART0_Handler
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DCD UART1_Handler
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DCD SPI0_Handler
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DCD SPI1_Handler
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DCD 0
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DCD 0
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DCD GADC_Handler ; 17
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DCD 0 ; 18
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DCD 0 ; 19
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DCD 0 ; 20
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DCD 0 ; 21
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DCD RF24G_Handler ; 22
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DCD PWM_Handler ; 23
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DCD BOR_Handler ; 24
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DCD 0 ; 25
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DCD 0 ; 26
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DCD AOTIMER0_Handler ; 27
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DCD AOTIMER1_Handler ; 28
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DCD CMP_Handler ; 29
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DCD FMC_Handler ; 30
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DCD CAN_Handler ; 31
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR r0, =0x4000013C ; remap
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LDR r1, =0x10000001
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STR r1, [r0]
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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;EXPORT BLE_Handler [WEAK]
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EXPORT DMAS_Handler [WEAK]
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EXPORT CPR_Handler [WEAK]
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EXPORT GPIO_Handler [WEAK]
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EXPORT RTC_Handler [WEAK]
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EXPORT TIMER0_Handler [WEAK]
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EXPORT TIMER1_Handler [WEAK]
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EXPORT TIMER2_Handler [WEAK]
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EXPORT TIMER3_Handler [WEAK]
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EXPORT WDT_Handler [WEAK]
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EXPORT I2C_Handler [WEAK]
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EXPORT UART0_Handler [WEAK]
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EXPORT UART1_Handler [WEAK]
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EXPORT SPI0_Handler [WEAK]
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EXPORT SPI1_Handler [WEAK]
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;EXPORT KBS_Handler [WEAK]
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;EXPORT QDEC_Handler [WEAK]
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EXPORT GADC_Handler [WEAK]
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EXPORT AOTIMER0_Handler [WEAK]
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EXPORT AOTIMER1_Handler [WEAK]
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EXPORT CMP_Handler [WEAK]
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EXPORT FMC_Handler [WEAK]
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EXPORT CAN_Handler [WEAK]
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;EXPORT SIM_Handler [WEAK]
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;EXPORT AES_Handler [WEAK]
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EXPORT PendSV_Handler [WEAK]
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EXPORT SysTick_Handler [WEAK]
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EXPORT RF24G_Handler [WEAK]
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EXPORT PWM_Handler [WEAK]
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EXPORT BOR_Handler [WEAK]
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PendSV_Handler
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SysTick_Handler
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;BLE_Handler
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DMAS_Handler
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CPR_Handler
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GPIO_Handler
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RTC_Handler
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TIMER0_Handler
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TIMER1_Handler
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TIMER2_Handler
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TIMER3_Handler
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WDT_Handler
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I2C_Handler
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UART0_Handler
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UART1_Handler
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SPI0_Handler
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SPI1_Handler
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;KBS_Handler
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;QDEC_Handler
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GADC_Handler
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;SIM_Handler
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;AES_Handler
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AOTIMER0_Handler
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AOTIMER1_Handler
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CMP_Handler
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FMC_Handler
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CAN_Handler
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RF24G_Handler
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PWM_Handler
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BOR_Handler
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B .
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ENDP
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ALIGN
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; User Initial Stack & Heap
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap
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LDR R0, = Heap_Mem
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LDR R1, = (Stack_Mem + Stack_Size)
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LDR R2, = (Heap_Mem + Heap_Size)
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LDR R3, = Stack_Mem
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BX LR
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ALIGN
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END
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@@ -0,0 +1,232 @@
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/*!
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* \file system_it_xinc.c
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*
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* \brief Target system interruption implementation
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*
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* \copyright Revised BSD License, see section \ref LICENSE.
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*
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* \code
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*
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* _ __ _ ________ _
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* | |/ /(_)___ / ____/ /_ (_)___
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* | // / __ \/ / / __ \/ / __ \
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* / |/ / / / / /___/ / / / / /_/ /
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* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
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* /_/
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* (C) 2022-2025 XinChip
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*
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* \endcode
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*
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* \author ( XinChip ) Alex-J
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*
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* \author ( XinChip )
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*/
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/*-----------------------------------------------------------------------------------
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INCLUDE HEADE FILES
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------------------------------------------------------------------------------------*/
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#include "system_it_xinc.h"
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/*------------------------------------------------------------------------------------
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Func Prototype
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-------------------------------------------------------------------------------------*/
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/*------------------------------------------------------------------------------------
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Functions
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-------------------------------------------------------------------------------------*/
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/**
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****************************************************************************************
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* @brief This function handles NMI exception.
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*
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* @param[in]
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* @param[in]
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****************************************************************************************
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*/
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void NMI_Handler(void)
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{
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/* USER CODE BEGIN NonMaskableInt_IRQn */
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DEBUG("%s\n", __func__);
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/* USER CODE END NonMaskableInt_IRQn */
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while (1)
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{
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}
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}
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/**
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****************************************************************************************
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* @brief This function handles Hard Fault exception.
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*
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* @param[in]
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* @param[in]
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****************************************************************************************
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*/
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void HardFault_Handler(void)
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{
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/* USER CODE BEGIN HardFault_IRQn */
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DEBUG("%s\n", __func__);
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/* USER CODE END HardFault_IRQn */
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while (1)
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{
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}
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}
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/**
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****************************************************************************************
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* @brief This function handles Memory Manage exception.
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*
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* @param[in]
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* @param[in]
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****************************************************************************************
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*/
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void MemManage_Handler(void)
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{
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/* USER CODE BEGIN */
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DEBUG("%s\n", __func__);
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/* USER CODE END */
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while (1)
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{
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}
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}
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/**
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****************************************************************************************
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* @brief This function handles Bus Fault exception.
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*
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* @param[in]
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* @param[in]
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****************************************************************************************
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*/
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void BusFault_Handler(void)
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{
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/* USER CODE BEGIN */
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DEBUG("%s\n", __func__);
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/* USER CODE END */
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while (1)
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{
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}
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}
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|
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/**
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****************************************************************************************
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* @brief This function handles Usage Fault exception.
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*
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* @param[in]
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* @param[in]
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||||
****************************************************************************************
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*/
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void UsageFault_Handler(void)
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{
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/* USER CODE BEGIN */
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DEBUG("%s\n", __func__);
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||||
/* USER CODE END */
|
||||
while (1)
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||||
{
|
||||
|
||||
}
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}
|
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|
||||
/**
|
||||
****************************************************************************************
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* @brief This function handles SVCall exception.
|
||||
*
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||||
* @param[in]
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* @param[in]
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||||
****************************************************************************************
|
||||
*/
|
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void SVC_Handler(void)
|
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{
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/* USER CODE BEGIN SVCall_IRQn */
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DEBUG("%s\n", __func__);
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||||
/* USER CODE END SVCall_IRQn */
|
||||
while (1)
|
||||
{
|
||||
|
||||
}
|
||||
}
|
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|
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/**
|
||||
****************************************************************************************
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* @brief This function handles Debug Monitor exception.
|
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*
|
||||
* @param[in]
|
||||
* @param[in]
|
||||
****************************************************************************************
|
||||
*/
|
||||
void DebugMon_Handler(void)
|
||||
{
|
||||
/* USER CODE BEGIN */
|
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DEBUG("%s\n", __func__);
|
||||
/* USER CODE END */
|
||||
while (1)
|
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{
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
****************************************************************************************
|
||||
* @brief This function handles PendSVC exception.
|
||||
*
|
||||
* @param[in]
|
||||
* @param[in]
|
||||
****************************************************************************************
|
||||
*/
|
||||
void PendSV_Handler(void)
|
||||
{
|
||||
/* USER CODE BEGIN PendSV_IRQn */
|
||||
DEBUG("%s\n", __func__);
|
||||
/* USER CODE END PendSV_IRQn */
|
||||
while (1)
|
||||
{
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
/****************************** Hard Fault Handler Functions *******************************/
|
||||
/*------------------------------------------------------------------------------------
|
||||
Private Functions
|
||||
-------------------------------------------------------------------------------------*/
|
||||
|
||||
void HardFault_Handler_c(unsigned int * HardFault_args)
|
||||
{
|
||||
/*栈帧里面内容：*/
|
||||
unsigned int stack_r0; //压栈的 R0
|
||||
unsigned int stack_r1; //压栈的 R1
|
||||
unsigned int stack_r2; //压栈的 R2
|
||||
unsigned int stack_r3; //压栈的 R3
|
||||
unsigned int stack_r12; //压栈的 R12
|
||||
unsigned int stack_lr; //压栈的 lr
|
||||
unsigned int stack_pc; //压栈的 pc
|
||||
unsigned int stack_psr; //压栈的 psr
|
||||
|
||||
stack_r0 = ((unsigned int)HardFault_args[0]);
|
||||
stack_r1 = ((unsigned int)HardFault_args[1]);
|
||||
stack_r2 = ((unsigned int)HardFault_args[2]);
|
||||
stack_r3 = ((unsigned int)HardFault_args[3]);
|
||||
stack_r12 = ((unsigned int)HardFault_args[4]);
|
||||
stack_lr = ((unsigned int)HardFault_args[5]);
|
||||
stack_pc = ((unsigned int)HardFault_args[6]);
|
||||
stack_psr = ((unsigned int)HardFault_args[7]);
|
||||
|
||||
DEBUG("----%s----\n", __func__);
|
||||
DEBUG("R0=%x\n",stack_r0);
|
||||
DEBUG("R1=%x\n",stack_r1);
|
||||
DEBUG("R2=%x\n",stack_r2);
|
||||
DEBUG("R3=%x\n",stack_r3);
|
||||
DEBUG("R12=%x\n",stack_r12);
|
||||
DEBUG("LR[R14]=%x\n",stack_lr);
|
||||
DEBUG("PC[R15]=%x\n",stack_pc);
|
||||
DEBUG("PSR=%x\n",stack_psr);
|
||||
DEBUG("SCB_SHCSR=%x\n",SCB->SHCSR);
|
||||
DEBUG("---------------------------\n");
|
||||
|
||||
while(1);
|
||||
}
|
||||
|
||||
/*******************************************************************************************/
|
||||
|
||||
@@ -0,0 +1,58 @@
|
||||
/*!
|
||||
* \file system_it_xinc.h
|
||||
*
|
||||
* \brief The header of system_it_xinc.c
|
||||
*
|
||||
* \copyright Revised BSD License, see section \ref LICENSE.
|
||||
*
|
||||
* \code
|
||||
*
|
||||
* _ __ _ ________ _
|
||||
* | |/ /(_)___ / ____/ /_ (_)___
|
||||
* | // / __ \/ / / __ \/ / __ \
|
||||
* / |/ / / / / /___/ / / / / /_/ /
|
||||
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
|
||||
* /_/
|
||||
* (C) 2022-2025 XinChip
|
||||
*
|
||||
* \endcode
|
||||
*
|
||||
* \author ( XinChip ) Alex-J
|
||||
*
|
||||
* \author ( XinChip )
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __SYSTEM_IT_XINC_H__
|
||||
#define __SYSTEM_IT_XINC_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------------------
|
||||
INCLUDE HEADE FILES
|
||||
------------------------------------------------------------------------------------*/
|
||||
#include "xc6xxx.h"
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Exported Functions
|
||||
-------------------------------------------------------------------------------------*/
|
||||
void NMI_Handler( void );
|
||||
void HardFault_Handler( void );
|
||||
void MemManage_Handler( void );
|
||||
void BusFault_Handler( void );
|
||||
void UsageFault_Handler( void );
|
||||
void SVC_Handler( void );
|
||||
void DebugMon_Handler( void );
|
||||
void PendSV_Handler( void );
|
||||
|
||||
void HardFault_Handler_c(unsigned int * HardFault_args);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_IT_XINC_H__ */
|
||||
|
||||
@@ -0,0 +1,120 @@
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system
|
||||
*
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------------------------------
|
||||
INCLUDE HEADE FILES
|
||||
------------------------------------------------------------------------------------*/
|
||||
#include <stdio.h>
|
||||
|
||||
#include "xc6xxx.h"
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Macros
|
||||
-------------------------------------------------------------------------------------*/
|
||||
#define __DEBUG_OUT_PORT 0
|
||||
#define readl(addr) (*(volatile unsigned int *) (addr))
|
||||
#define writel(addr, value) (*(volatile unsigned int *) (addr) = (value))
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Functions
|
||||
-------------------------------------------------------------------------------------*/
|
||||
|
||||
#define VECTOR_NUM 48
|
||||
|
||||
void set_vector(void)
|
||||
{
|
||||
#if (USE_XIP == 1)
|
||||
GLOBAL_INT_DISABLE();
|
||||
for (uint32_t i = 0, *Pvector = (uint32_t *)(0x11001000 + 0),
|
||||
*_vector_table = (uint32_t *)(0x10000000);
|
||||
i < VECTOR_NUM; i++) // copy vertor table
|
||||
{
|
||||
_vector_table[i] = *Pvector++;
|
||||
}
|
||||
|
||||
*((volatile unsigned int *)(0x4000013C)) =
|
||||
0x10000001; // inter vertor table remap
|
||||
GLOBAL_INT_RESTORE();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
static void WDT_ResetInit(void)
|
||||
{
|
||||
cpr_ctlapbclken_grctl__wdt_pclk_en__setf(ENABLE);
|
||||
|
||||
cpr_rstctl_ctlapb_sw__wdt_rstn__setf(RSTCTL_ENABLE);
|
||||
cpr_rstctl_ctlapb_sw__wdt_rstn__setf(RSTCTL_DISABLE);
|
||||
|
||||
cpr_rstctl_wdtrst_mask_set(
|
||||
(WDT_SYS_RSTN_MASK_DISABLE | WDT_M0_RSTN_MASK_ENABLE));
|
||||
|
||||
cpr_lp_ctl__wdt_tclk_en__setf(ENABLE);
|
||||
wdt_cr__wdt_en__setf(DISABLE);
|
||||
}
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
|
||||
WDT_ResetInit();
|
||||
|
||||
#if (USE_XIP == 1)
|
||||
|
||||
set_vector();
|
||||
#endif
|
||||
writel(0x40000040, readl(0x40000040) | (0x01 << 4) | 0xFFFF0000);
|
||||
|
||||
}
|
||||
|
||||
__RAM_CODE int sendchar(int c)
|
||||
{
|
||||
unsigned int status;
|
||||
#if (__DEBUG_OUT_PORT == 1)
|
||||
for (;;) {
|
||||
status = (*((volatile unsigned *)(0x40011000 + 0x14)));
|
||||
status &= 0x20;
|
||||
if (status == 0x20)
|
||||
break;
|
||||
}
|
||||
(*((volatile unsigned *)(0x40011000 + 0x00))) = c;
|
||||
return (1);
|
||||
#else
|
||||
for (;;) {
|
||||
status = (*((volatile unsigned *)(0x40010000 + 0x14)));
|
||||
status &= 0x20;
|
||||
if (status == 0x20)
|
||||
break;
|
||||
}
|
||||
(*((volatile unsigned *)(0x40010000 + 0x00))) = c;
|
||||
return (1);
|
||||
#endif
|
||||
}
|
||||
|
||||
struct __FILE
|
||||
{
|
||||
int handle; /* Add whatever you need here */
|
||||
};
|
||||
|
||||
FILE __stdout;
|
||||
__RAM_CODE int fputc(int ch, FILE *f) { return (sendchar(ch)); }
|
||||
|
||||
int ferror(FILE *f)
|
||||
{
|
||||
/* Your implementation of ferror */
|
||||
return EOF;
|
||||
}
|
||||
|
||||
void _ttywrch(int ch) { sendchar(ch); }
|
||||
|
||||
void _sys_exit(int return_code)
|
||||
{
|
||||
label:
|
||||
goto label; /* endless loop */
|
||||
}
|
||||
@@ -0,0 +1,257 @@
|
||||
|
||||
;/*****************************************************************************
|
||||
; * @file: startup_xinc.s
|
||||
; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
|
||||
; * Device xinc.
|
||||
; *****************************************************************************/
|
||||
|
||||
Stack_Size EQU 0x00000200
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
; ToDo: Add here the vectors for the device specific external interrupts handler
|
||||
DCD BLE_Handler ; 0
|
||||
DCD DMA_Handler ; 1
|
||||
DCD CPR_Handler ; 2
|
||||
DCD GPIO_Handler ; 3
|
||||
DCD RTC_Handler ; 4
|
||||
DCD TIMER0_Handler ; 5
|
||||
DCD TIMER1_Handler ; 6
|
||||
DCD TIMER2_Handler ; 7
|
||||
DCD TIMER3_Handler ; 8
|
||||
DCD WDT_Handler ; 9
|
||||
DCD I2C_Handler ; 10
|
||||
DCD UART0_Handler ; 11
|
||||
DCD UART1_Handler ; 12
|
||||
DCD SPI0_Handler ; 13
|
||||
DCD SPI1_Handler ; 14
|
||||
DCD 0 ; 15
|
||||
DCD 0 ; 16
|
||||
DCD GADC_Handler ; 17
|
||||
DCD PWM_Handler ; 18
|
||||
DCD AES_Handler ; 19
|
||||
DCD USB_Handler ; 20
|
||||
DCD AUDIO_Handler ; 21
|
||||
DCD RF24G_Handler ; 22
|
||||
DCD SPI2_Handler ; 23
|
||||
DCD MPU_Handler ; 24
|
||||
DCD UART2_Handler ; 25
|
||||
DCD I2S_Handler ; 26
|
||||
DCD AOTIMER0_Handler ; 27
|
||||
DCD AOTIMER1_Handler ; 28
|
||||
DCD CMP_Handler ; 29
|
||||
DCD FMC_Handler ; 30
|
||||
DCD CAN_Handler ; 31
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR r0, =0x4000013C ; remap
|
||||
LDR r1, =0x10000001
|
||||
STR r1, [r0]
|
||||
|
||||
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
IMPORT HardFault_Handler_c ;函数声明
|
||||
movs r0, #4 ;判断主栈指针还是进程栈指针
|
||||
mov r1, lr
|
||||
tst r0, r1
|
||||
beq hf_used_msp ;如果是主栈指针
|
||||
mrs r0, psp ;否则是进程栈指针,把进程栈指针地址付给 R0
|
||||
ldr r1, =HardFault_Handler_c ;跳转到 HardFault 中断程序
|
||||
bx r1
|
||||
hf_used_msp
|
||||
mrs r0, msp ;把主栈指针地址赋给 R0
|
||||
ldr r1, =HardFault_Handler_c
|
||||
bx r1
|
||||
;EXPORT HardFault_Handler [WEAK]
|
||||
;B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT BLE_Handler [WEAK]
|
||||
EXPORT DMA_Handler [WEAK]
|
||||
EXPORT CPR_Handler [WEAK]
|
||||
EXPORT GPIO_Handler [WEAK]
|
||||
EXPORT RTC_Handler [WEAK]
|
||||
EXPORT TIMER0_Handler [WEAK]
|
||||
EXPORT TIMER1_Handler [WEAK]
|
||||
EXPORT TIMER2_Handler [WEAK]
|
||||
EXPORT TIMER3_Handler [WEAK]
|
||||
EXPORT WDT_Handler [WEAK]
|
||||
EXPORT I2C_Handler [WEAK]
|
||||
EXPORT UART0_Handler [WEAK]
|
||||
EXPORT UART1_Handler [WEAK]
|
||||
EXPORT SPI0_Handler [WEAK]
|
||||
EXPORT SPI1_Handler [WEAK]
|
||||
;EXPORT KBS_Handler [WEAK]
|
||||
;EXPORT QDEC_Handler [WEAK]
|
||||
EXPORT GADC_Handler [WEAK]
|
||||
EXPORT PWM_Handler [WEAK]
|
||||
EXPORT AES_Handler [WEAK]
|
||||
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
|
||||
EXPORT USB_Handler [WEAK];20
|
||||
EXPORT AUDIO_Handler [WEAK];21
|
||||
EXPORT RF24G_Handler [WEAK];22
|
||||
EXPORT SPI2_Handler [WEAK];23
|
||||
EXPORT MPU_Handler [WEAK];24
|
||||
EXPORT UART2_Handler [WEAK];25
|
||||
EXPORT I2S_Handler [WEAK];26
|
||||
EXPORT AOTIMER0_Handler [WEAK];27
|
||||
EXPORT AOTIMER1_Handler [WEAK];28
|
||||
EXPORT CMP_Handler [WEAK];29
|
||||
EXPORT FMC_Handler [WEAK];30
|
||||
EXPORT CAN_Handler [WEAK];31
|
||||
|
||||
PendSV_Handler
|
||||
SysTick_Handler
|
||||
BLE_Handler
|
||||
RF24G_Handler
|
||||
DMA_Handler
|
||||
CPR_Handler
|
||||
GPIO_Handler
|
||||
RTC_Handler
|
||||
TIMER0_Handler
|
||||
TIMER1_Handler
|
||||
TIMER2_Handler
|
||||
TIMER3_Handler
|
||||
WDT_Handler
|
||||
I2C_Handler
|
||||
I2S_Handler
|
||||
UART0_Handler
|
||||
UART1_Handler
|
||||
UART2_Handler
|
||||
SPI0_Handler
|
||||
SPI1_Handler
|
||||
SPI2_Handler
|
||||
MPU_Handler
|
||||
;KBS_Handler
|
||||
;QDEC_Handler
|
||||
GADC_Handler
|
||||
PWM_Handler
|
||||
AUDIO_Handler
|
||||
;SIM_Handler
|
||||
AES_Handler
|
||||
AOTIMER0_Handler
|
||||
AOTIMER1_Handler
|
||||
CMP_Handler
|
||||
FMC_Handler
|
||||
CAN_Handler
|
||||
USB_Handler
|
||||
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, = (Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
END
|
||||
@@ -0,0 +1,257 @@
|
||||
|
||||
;/*****************************************************************************
|
||||
; * @file: startup_xinc.s
|
||||
; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
|
||||
; * Device xinc.
|
||||
; *****************************************************************************/
|
||||
|
||||
Stack_Size EQU 0x00000800
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
; ToDo: Add here the vectors for the device specific external interrupts handler
|
||||
DCD BLE_Handler ; 0
|
||||
DCD DMA_Handler ; 1
|
||||
DCD CPR_Handler ; 2
|
||||
DCD GPIO_Handler ; 3
|
||||
DCD RTC_Handler ; 4
|
||||
DCD TIMER0_Handler ; 5
|
||||
DCD TIMER1_Handler ; 6
|
||||
DCD TIMER2_Handler ; 7
|
||||
DCD TIMER3_Handler ; 8
|
||||
DCD WDT_Handler ; 9
|
||||
DCD I2C_Handler ; 10
|
||||
DCD UART0_Handler ; 11
|
||||
DCD UART1_Handler ; 12
|
||||
DCD SPI0_Handler ; 13
|
||||
DCD SPI1_Handler ; 14
|
||||
DCD 0 ; 15
|
||||
DCD 0 ; 16
|
||||
DCD GADC_Handler ; 17
|
||||
DCD PWM_Handler ; 18
|
||||
DCD AES_Handler ; 19
|
||||
DCD USB_Handler ; 20
|
||||
DCD AUDIO_Handler ; 21
|
||||
DCD RF24G_Handler ; 22
|
||||
DCD SPI2_Handler ; 23
|
||||
DCD MPU_Handler ; 24
|
||||
DCD UART2_Handler ; 25
|
||||
DCD I2S_Handler ; 26
|
||||
DCD AOTIMER0_Handler ; 27
|
||||
DCD AOTIMER1_Handler ; 28
|
||||
DCD CMP_Handler ; 29
|
||||
DCD FMC_Handler ; 30
|
||||
DCD CAN_Handler ; 31
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR r0, =0x4000013C ; remap
|
||||
LDR r1, =0x10000001
|
||||
STR r1, [r0]
|
||||
|
||||
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
IMPORT HardFault_Handler_c ;函数声明
|
||||
movs r0, #4 ;判断主栈指针还是进程栈指针
|
||||
mov r1, lr
|
||||
tst r0, r1
|
||||
beq hf_used_msp ;如果是主栈指针
|
||||
mrs r0, psp ;否则是进程栈指针,把进程栈指针地址付给 R0
|
||||
ldr r1, =HardFault_Handler_c ;跳转到 HardFault 中断程序
|
||||
bx r1
|
||||
hf_used_msp
|
||||
mrs r0, msp ;把主栈指针地址赋给 R0
|
||||
ldr r1, =HardFault_Handler_c
|
||||
bx r1
|
||||
;EXPORT HardFault_Handler [WEAK]
|
||||
;B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT BLE_Handler [WEAK]
|
||||
EXPORT DMA_Handler [WEAK]
|
||||
EXPORT CPR_Handler [WEAK]
|
||||
EXPORT GPIO_Handler [WEAK]
|
||||
EXPORT RTC_Handler [WEAK]
|
||||
EXPORT TIMER0_Handler [WEAK]
|
||||
EXPORT TIMER1_Handler [WEAK]
|
||||
EXPORT TIMER2_Handler [WEAK]
|
||||
EXPORT TIMER3_Handler [WEAK]
|
||||
EXPORT WDT_Handler [WEAK]
|
||||
EXPORT I2C_Handler [WEAK]
|
||||
EXPORT UART0_Handler [WEAK]
|
||||
EXPORT UART1_Handler [WEAK]
|
||||
EXPORT SPI0_Handler [WEAK]
|
||||
EXPORT SPI1_Handler [WEAK]
|
||||
;EXPORT KBS_Handler [WEAK]
|
||||
;EXPORT QDEC_Handler [WEAK]
|
||||
EXPORT GADC_Handler [WEAK]
|
||||
EXPORT PWM_Handler [WEAK]
|
||||
EXPORT AES_Handler [WEAK]
|
||||
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
|
||||
EXPORT USB_Handler [WEAK];20
|
||||
EXPORT AUDIO_Handler [WEAK];21
|
||||
EXPORT RF24G_Handler [WEAK];22
|
||||
EXPORT SPI2_Handler [WEAK];23
|
||||
EXPORT MPU_Handler [WEAK];24
|
||||
EXPORT UART2_Handler [WEAK];25
|
||||
EXPORT I2S_Handler [WEAK];26
|
||||
EXPORT AOTIMER0_Handler [WEAK];27
|
||||
EXPORT AOTIMER1_Handler [WEAK];28
|
||||
EXPORT CMP_Handler [WEAK];29
|
||||
EXPORT FMC_Handler [WEAK];30
|
||||
EXPORT CAN_Handler [WEAK];31
|
||||
|
||||
PendSV_Handler
|
||||
SysTick_Handler
|
||||
BLE_Handler
|
||||
RF24G_Handler
|
||||
DMA_Handler
|
||||
CPR_Handler
|
||||
GPIO_Handler
|
||||
RTC_Handler
|
||||
TIMER0_Handler
|
||||
TIMER1_Handler
|
||||
TIMER2_Handler
|
||||
TIMER3_Handler
|
||||
WDT_Handler
|
||||
I2C_Handler
|
||||
I2S_Handler
|
||||
UART0_Handler
|
||||
UART1_Handler
|
||||
UART2_Handler
|
||||
SPI0_Handler
|
||||
SPI1_Handler
|
||||
SPI2_Handler
|
||||
MPU_Handler
|
||||
;KBS_Handler
|
||||
;QDEC_Handler
|
||||
GADC_Handler
|
||||
PWM_Handler
|
||||
AUDIO_Handler
|
||||
;SIM_Handler
|
||||
AES_Handler
|
||||
AOTIMER0_Handler
|
||||
AOTIMER1_Handler
|
||||
CMP_Handler
|
||||
FMC_Handler
|
||||
CAN_Handler
|
||||
USB_Handler
|
||||
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, = (Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
END
|
||||
@@ -0,0 +1,257 @@
|
||||
|
||||
;/*****************************************************************************
|
||||
; * @file: startup_xinc.s
|
||||
; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
|
||||
; * Device xinc.
|
||||
; *****************************************************************************/
|
||||
|
||||
Stack_Size EQU 0x00000200
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
; ToDo: Add here the vectors for the device specific external interrupts handler
|
||||
DCD BLE_Handler ; 0
|
||||
DCD DMA_Handler ; 1
|
||||
DCD CPR_Handler ; 2
|
||||
DCD GPIO_Handler ; 3
|
||||
DCD RTC_Handler ; 4
|
||||
DCD TIMER0_Handler ; 5
|
||||
DCD TIMER1_Handler ; 6
|
||||
DCD TIMER2_Handler ; 7
|
||||
DCD TIMER3_Handler ; 8
|
||||
DCD WDT_Handler ; 9
|
||||
DCD I2C_Handler ; 10
|
||||
DCD UART0_Handler ; 11
|
||||
DCD UART1_Handler ; 12
|
||||
DCD SPI0_Handler ; 13
|
||||
DCD SPI1_Handler ; 14
|
||||
DCD 0 ; 15
|
||||
DCD 0 ; 16
|
||||
DCD GADC_Handler ; 17
|
||||
DCD PWM_Handler ; 18
|
||||
DCD AES_Handler ; 19
|
||||
DCD USB_Handler ; 20
|
||||
DCD AUDIO_Handler ; 21
|
||||
DCD RF24G_Handler ; 22
|
||||
DCD SPI2_Handler ; 23
|
||||
DCD MPU_Handler ; 24
|
||||
DCD UART2_Handler ; 25
|
||||
DCD I2S_Handler ; 26
|
||||
DCD AOTIMER0_Handler ; 27
|
||||
DCD AOTIMER1_Handler ; 28
|
||||
DCD CMP_Handler ; 29
|
||||
DCD FMC_Handler ; 30
|
||||
DCD CAN_Handler ; 31
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR r0, =0x4000013C ; remap
|
||||
LDR r1, =0x10000001
|
||||
STR r1, [r0]
|
||||
|
||||
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
IMPORT HardFault_Handler_c ;函数声明
|
||||
movs r0, #4 ;判断主栈指针还是进程栈指针
|
||||
mov r1, lr
|
||||
tst r0, r1
|
||||
beq hf_used_msp ;如果是主栈指针
|
||||
mrs r0, psp ;否则是进程栈指针,把进程栈指针地址付给 R0
|
||||
ldr r1, =HardFault_Handler_c ;跳转到 HardFault 中断程序
|
||||
bx r1
|
||||
hf_used_msp
|
||||
mrs r0, msp ;把主栈指针地址赋给 R0
|
||||
ldr r1, =HardFault_Handler_c
|
||||
bx r1
|
||||
;EXPORT HardFault_Handler [WEAK]
|
||||
;B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT BLE_Handler [WEAK]
|
||||
EXPORT DMA_Handler [WEAK]
|
||||
EXPORT CPR_Handler [WEAK]
|
||||
EXPORT GPIO_Handler [WEAK]
|
||||
EXPORT RTC_Handler [WEAK]
|
||||
EXPORT TIMER0_Handler [WEAK]
|
||||
EXPORT TIMER1_Handler [WEAK]
|
||||
EXPORT TIMER2_Handler [WEAK]
|
||||
EXPORT TIMER3_Handler [WEAK]
|
||||
EXPORT WDT_Handler [WEAK]
|
||||
EXPORT I2C_Handler [WEAK]
|
||||
EXPORT UART0_Handler [WEAK]
|
||||
EXPORT UART1_Handler [WEAK]
|
||||
EXPORT SPI0_Handler [WEAK]
|
||||
EXPORT SPI1_Handler [WEAK]
|
||||
;EXPORT KBS_Handler [WEAK]
|
||||
;EXPORT QDEC_Handler [WEAK]
|
||||
EXPORT GADC_Handler [WEAK]
|
||||
EXPORT PWM_Handler [WEAK]
|
||||
EXPORT AES_Handler [WEAK]
|
||||
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
|
||||
EXPORT USB_Handler [WEAK];20
|
||||
EXPORT AUDIO_Handler [WEAK];21
|
||||
EXPORT RF24G_Handler [WEAK];22
|
||||
EXPORT SPI2_Handler [WEAK];23
|
||||
EXPORT MPU_Handler [WEAK];24
|
||||
EXPORT UART2_Handler [WEAK];25
|
||||
EXPORT I2S_Handler [WEAK];26
|
||||
EXPORT AOTIMER0_Handler [WEAK];27
|
||||
EXPORT AOTIMER1_Handler [WEAK];28
|
||||
EXPORT CMP_Handler [WEAK];29
|
||||
EXPORT FMC_Handler [WEAK];30
|
||||
EXPORT CAN_Handler [WEAK];31
|
||||
|
||||
PendSV_Handler
|
||||
SysTick_Handler
|
||||
BLE_Handler
|
||||
RF24G_Handler
|
||||
DMA_Handler
|
||||
CPR_Handler
|
||||
GPIO_Handler
|
||||
RTC_Handler
|
||||
TIMER0_Handler
|
||||
TIMER1_Handler
|
||||
TIMER2_Handler
|
||||
TIMER3_Handler
|
||||
WDT_Handler
|
||||
I2C_Handler
|
||||
I2S_Handler
|
||||
UART0_Handler
|
||||
UART1_Handler
|
||||
UART2_Handler
|
||||
SPI0_Handler
|
||||
SPI1_Handler
|
||||
SPI2_Handler
|
||||
MPU_Handler
|
||||
;KBS_Handler
|
||||
;QDEC_Handler
|
||||
GADC_Handler
|
||||
PWM_Handler
|
||||
AUDIO_Handler
|
||||
;SIM_Handler
|
||||
AES_Handler
|
||||
AOTIMER0_Handler
|
||||
AOTIMER1_Handler
|
||||
CMP_Handler
|
||||
FMC_Handler
|
||||
CAN_Handler
|
||||
USB_Handler
|
||||
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, = (Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
END
|
||||
@@ -0,0 +1,150 @@
|
||||
/*
|
||||
* @Descripttion:
|
||||
* @version:
|
||||
* @Author: sueRimn
|
||||
* @Date: 2024-05-09 11:45:27
|
||||
* @LastEditors: sueRimn
|
||||
* @LastEditTime: 2024-07-24 15:18:52
|
||||
*/
|
||||
#ifndef __APP_DATA_H__
|
||||
#define __APP_DATA_H__
|
||||
|
||||
#include "rf_config.h"
|
||||
#include "xc6xxx_rf_2_4g.h"
|
||||
#include "xc_software_crc.h"
|
||||
#include <stdint.h>
|
||||
|
||||
#define BEKEN (0)
|
||||
#define PAN2416 (1)
|
||||
|
||||
#ifdef TELINK_MODE
|
||||
#define COMPATILBE_MODE BEKEN
|
||||
#endif
|
||||
|
||||
#ifdef BEKEN_MODE
|
||||
#define COMPATILBE_MODE BEKEN
|
||||
#endif
|
||||
|
||||
#ifdef PANCHIP_MODE
|
||||
#define COMPATILBE_MODE PAN2416
|
||||
#endif
|
||||
|
||||
#define RF_CONFIRMED_VALUE (5U)
|
||||
|
||||
/* 最大接收数据长度 */
|
||||
#define BUFF_LEN_MAX (32U)
|
||||
#define RF_RECV_AMX_LEN (BUFF_LEN_MAX)
|
||||
#define RF_PRX_READ_RXFIFO_TIMER (RF_RECV_AMX_LEN)
|
||||
|
||||
#define BIT7 0x80
|
||||
#define BIT6 0x40
|
||||
#define BIT5 0x20
|
||||
#define BIT4 0x10
|
||||
#define BIT3 0x08
|
||||
#define BIT2 0x04
|
||||
#define BIT1 0x02
|
||||
#define BIT0 0x01
|
||||
|
||||
/* 动态包位移长度，单位bit */
|
||||
#if (BEKEN == COMPATILBE_MODE)
|
||||
#define DATA_ANALYSIS_BIT_H (BIT7)
|
||||
#define DATA_ANALYSIS_BIT_L (BIT0)
|
||||
#define DATA_CONTROL_BIT (1U)
|
||||
#define DATA_CONTROL_NOACK (1U) // 1-ack 0-noack
|
||||
#elif (PAN2416 == COMPATILBE_MODE)
|
||||
#define DATA_ANALYSIS_BIT_H (BIT7 | BIT6)
|
||||
#define DATA_ANALYSIS_BIT_L (BIT0 | BIT1)
|
||||
#define DATA_CONTROL_BIT (2U)
|
||||
#define DATA_CONTROL_NOACK (0U) // 0-ack 1-noack
|
||||
#endif
|
||||
#define DATA_SPLICE_BIT (8U - DATA_CONTROL_BIT)
|
||||
|
||||
/* 地址长度 */
|
||||
#define RF_ADDR_LEN XINCX_RF_TX_ADDR_WIDTH // 5U
|
||||
|
||||
/* 接收CRC+contorl字段长度 */
|
||||
#define RF_RECV_EXTEN_LEN (3U)
|
||||
|
||||
/* CRC初始值 */
|
||||
#if (1 == XINCX_2_4G_CRC_BYTE)
|
||||
#define RF_CRC_INIT_VALUE (0xFF) // CRC8 0xFF CRC16 0xFFFF
|
||||
#elif (2 == XINCX_2_4G_CRC_BYTE)
|
||||
#define RF_CRC_INIT_VALUE (0xFFFF) // CRC8 0xFF CRC16 0xFFFF
|
||||
#endif
|
||||
|
||||
/* 调制频偏 */
|
||||
#if ((XINCX_RF_TRANS_RATE == DR_250K) && (PAN2416 == COMPATILBE_MODE))
|
||||
#define RF_FREQ_DEV (0xb8) // 0x75
|
||||
#define RF_FREQ_SEND_DEV (0x90) // 0xb8//0xa0
|
||||
#define RF_FREQ_RECV_DEV (0x80) // 0x98//0xa0
|
||||
#define ACK_DELAY (50) //(300)
|
||||
#elif ((XINCX_RF_TRANS_RATE == DR_1M) && (PAN2416 == COMPATILBE_MODE))
|
||||
#define RF_FREQ_DEV (0xd0) // 0xb8//0xa0
|
||||
#define RF_FREQ_SEND_DEV (0xe0) // 0xb8//0xa0
|
||||
#define RF_FREQ_RECV_DEV (0x80) // 0x98//0xa0
|
||||
#define ACK_DELAY (300) //(300)
|
||||
#elif ((XINCX_RF_TRANS_RATE == DR_1M) && (BEKEN == COMPATILBE_MODE))
|
||||
#define RF_FREQ_DEV (0x80) // 0x75
|
||||
#define RF_FREQ_SEND_DEV (0xd0) // 0xb8//0xa0
|
||||
#define RF_FREQ_RECV_DEV (RF_FREQ_DEV) // 0x98//0xa0
|
||||
#define ACK_DELAY (40)
|
||||
#elif ((XINCX_RF_TRANS_RATE == DR_250K) && (BEKEN == COMPATILBE_MODE))
|
||||
#define RF_FREQ_DEV (0x80) // 0x75
|
||||
#define RF_FREQ_SEND_DEV (0xd0) // 0xb8//0xa0
|
||||
#define RF_FREQ_RECV_DEV (RF_FREQ_DEV) // 0x98//0xa0
|
||||
#define ACK_DELAY (0)
|
||||
#endif
|
||||
|
||||
/* 磐启白化初始值 */
|
||||
#define PANCHIP_WHITEN_INIT_VAL (0x7F)
|
||||
|
||||
/* ACK 长度 */
|
||||
#define ACK_LEN (32U) // 32U
|
||||
|
||||
/* */
|
||||
#define USB_TEST (1U)
|
||||
|
||||
/* 测试IO 使能 */
|
||||
#define DEBUG_PIN (1U)
|
||||
#define TEST_PIN_NO_USB (1U)
|
||||
|
||||
/* 测试IO */
|
||||
#define TEST_PIN_1 GPIO_3
|
||||
#define TEST_PIN_2 GPIO_6
|
||||
#define TEST_PIN_3 GPIO_7
|
||||
#define TEST_PIN_4 GPIO_8
|
||||
#define TEST_PIN_5 GPIO_1
|
||||
#define TEST_PIN_6 GPIO_4
|
||||
#define TEST_PIN_7 GPIO_5
|
||||
#define TEST_PIN_8 GPIO_0
|
||||
|
||||
/* ACK固定接收字节数 */
|
||||
#define RF_RECV_TIMER \
|
||||
(XINCX_2_4G_PREAMBLE_NUM + 1 + XINCX_RF_TX_ADDR_WIDTH + RF_PRX_READ_RXFIFO_TIMER + XINCX_2_4G_CRC_BYTE + 2 + 10)
|
||||
|
||||
/* 速率-bit占用时间 */
|
||||
#if (XINCX_RF_TRANS_RATE == DR_2M)
|
||||
#define BIT_TIMER (4U)
|
||||
#elif (XINCX_RF_TRANS_RATE == DR_1M)
|
||||
#define BIT_TIMER (8U)
|
||||
#elif (XINCX_RF_TRANS_RATE == DR_250K)
|
||||
#define BIT_TIMER (32U)
|
||||
#elif (XINCX_RF_TRANS_RATE == DR_125K)
|
||||
#define BIT_TIMER (64U)
|
||||
#endif
|
||||
|
||||
extern uint8_t addr_buff[5];
|
||||
extern uint8_t ack_buff[BUFF_LEN];
|
||||
extern uint16_t rf_addr_crc;
|
||||
extern uint8_t panchip_addr_whiten;
|
||||
extern uint8_t panchip_contorl_whiten;
|
||||
extern uint8_t rf_send_ack_stat;
|
||||
|
||||
void rf_enhanced_packet(uint8_t *buff, uint8_t buff_len);
|
||||
uint16_t rf_recv_dyn_crc(uint8_t *buff, uint8_t buff_len);
|
||||
uint16_t rf_enhanced_package_grouping(uint8_t *data_buff, uint8_t data_len);
|
||||
uint8_t read_addr_wid(uint8_t *addr_buff);
|
||||
void rf_addr_map(uint8_t *addr_buff);
|
||||
|
||||
uint8_t rf_enhanced_recv_data(uint8_t *buff);
|
||||
#endif
|
||||
@@ -0,0 +1,61 @@
|
||||
#ifndef __APP_RF_H__
|
||||
#define __APP_RF_H__
|
||||
|
||||
#include "app_data.h"
|
||||
#include "rf_config.h"
|
||||
//#include "rtt_platform.h"
|
||||
#include "xc6xxx.h"
|
||||
#include "xc6xxx_rf_2_4g.h"
|
||||
#include "xc_software_crc.h"
|
||||
|
||||
typedef enum
|
||||
{
|
||||
RF_SEND_TIMER_INTER = 0,
|
||||
RF_RECV_TIMER_INTER = 1,
|
||||
RF_FREE_TIMER_INTER = 2
|
||||
} rf_timer_stat_t; // PRX 状态
|
||||
|
||||
#define RECV_TIMERMS_OUT 1000 // 超时接收
|
||||
//#define SEND_TIMERMS_CNT 10 * 1000 // 定时发射 ms
|
||||
#define RECV_TIMERMS_CNT 50
|
||||
#define ACK_SEND_TIMER 50
|
||||
|
||||
#define XC_SEND_NUM 1000 // 发射总包数
|
||||
|
||||
#define RF_TX_TIMERx TIMER0_IDX // 发射定时器号
|
||||
#define RF_RX_TIMERx TIMER0_IDX // 接收定时器号
|
||||
|
||||
#define EXTEND_LEN (5)
|
||||
|
||||
extern uint8_t ret;
|
||||
extern uint32_t count;
|
||||
extern uint32_t send_ok;
|
||||
extern uint32_t send_max;
|
||||
extern bool rf_send_timer_flag;
|
||||
extern bool rf_recv_timer_flag;
|
||||
extern bool rf_prx_ack_flag;
|
||||
extern rf_timer_stat_t timer_stat;
|
||||
|
||||
void timer_init(uint8_t timer_id, uint32_t timer_cnt);
|
||||
void gpio_test(void);
|
||||
void rf_debug_pin(uint8_t gpio_id);
|
||||
uint16_t rf_get_addr_crc(void);
|
||||
//void rf_buff_info(uint8_t *buff, uint8_t len);
|
||||
void rf_rx_ack_payload_event(uint8_t *buff, uint8_t len);
|
||||
void rf_set_agc(uint8_t adc_rssi_mean, uint8_t agc_gain_delay);
|
||||
void rf_pwr_down_up(void);
|
||||
// uint16_t rf_send_enhanced_data_cfg(uint8_t *buff, uint8_t len, uint8_t ack);
|
||||
#if (XINCX_RF_COMPATIBILITY_MODE == PANCHIP_PACKET)
|
||||
uint32_t rf_tx_manage(rf_data_typedef_t *rf_data);
|
||||
void timer0_callback(void *context);
|
||||
#endif
|
||||
void xc_rf_send_ack(uint8_t *buff, uint8_t recv_len);
|
||||
void rf_set_rx_mode(uint16_t channel, uint16_t fifo_len);
|
||||
void rf_recv_sf_ack_payload(uint8_t *buff, uint8_t len);
|
||||
uint8_t rf_recv_enhanced_data(uint8_t *buff);
|
||||
void rf_set_agc_map(uint8_t agc_gain_1th, uint8_t agc_setp);
|
||||
|
||||
void rf_pwm_recv_data(void);
|
||||
uint8_t rf_recv_addr(void);
|
||||
|
||||
#endif //__APP_RF_H__
|
||||
@@ -0,0 +1,68 @@
|
||||
/*!
|
||||
* \file main.h
|
||||
*
|
||||
* \brief The head file of main.c
|
||||
*
|
||||
* \copyright Revised BSD License, see section \ref LICENSE.
|
||||
*
|
||||
* \code
|
||||
*
|
||||
* _ __ _ ________ _
|
||||
* | |/ /(_)___ / ____/ /_ (_)___
|
||||
* | // / __ \/ / / __ \/ / __ \
|
||||
* / |/ / / / / /___/ / / / / /_/ /
|
||||
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
|
||||
* /_/
|
||||
* (C) 2022-2025 XinChip
|
||||
*
|
||||
* \endcode
|
||||
*
|
||||
* \author ( XinChip ) Alex-J
|
||||
*
|
||||
* \author ( XinChip )
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __MAIN_H__
|
||||
#define __MAIN_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------------------
|
||||
INCLUDE HEADE FILES
|
||||
------------------------------------------------------------------------------------*/
|
||||
#include "xc6xxx.h"
|
||||
#include "xc6xxx_rf_2_4g.h"
|
||||
#include "rf_config.h"
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Macros
|
||||
-------------------------------------------------------------------------------------*/
|
||||
#define DEBUG_LOG
|
||||
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
TypeDef
|
||||
-------------------------------------------------------------------------------------*/
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Global Variables
|
||||
-------------------------------------------------------------------------------------*/
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Exported Functions
|
||||
-------------------------------------------------------------------------------------*/
|
||||
|
||||
void rf_tx_manage(void);
|
||||
void rf_rx_manage(void);
|
||||
void rf_buff_info(uint8_t *buff, uint8_t len);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MAIN_H__ */
|
||||
|
||||
@@ -0,0 +1,152 @@
|
||||
|
||||
#ifndef SDK_DRIVER_CONFIG_H
|
||||
#define SDK_DRIVER_CONFIG_H
|
||||
// <<< Use Configuration Wizard in Context Menu >>>\n
|
||||
#ifdef USE_APP_CONFIG
|
||||
#include "app_config.h"
|
||||
#endif
|
||||
// <h> XC_Drivers
|
||||
|
||||
// <e> XC_CLOCK_ENABLED
|
||||
//==========================================================
|
||||
#ifndef XC_CLOCK_ENABLED
|
||||
#define XC_CLOCK_ENABLED 1
|
||||
#endif
|
||||
// </e>
|
||||
|
||||
// <e> XC_PWR_ENABLED
|
||||
//==========================================================
|
||||
#ifndef XC_PWR_ENABLED
|
||||
#define XC_PWR_ENABLED 1
|
||||
#endif
|
||||
// </e>
|
||||
|
||||
// <e> XC_WDT_ENABLED
|
||||
//==========================================================
|
||||
#ifndef XC_WDT_ENABLED
|
||||
#define XC_WDT_ENABLED 1
|
||||
#endif
|
||||
// </e>
|
||||
|
||||
// <e> XC_BOR_ENABLED
|
||||
//==========================================================
|
||||
#ifndef XC_BOR_ENABLED
|
||||
#define XC_BOR_ENABLED 1
|
||||
#endif
|
||||
// </e>
|
||||
|
||||
// <e> XC_SYSTICK_ENABLED
|
||||
//==========================================================
|
||||
#ifndef XC_SYSTICK_ENABLED
|
||||
#define XC_SYSTICK_ENABLED 1
|
||||
#endif
|
||||
// </e>
|
||||
|
||||
// <e> XC_TIMER_ENABLED
|
||||
//==========================================================
|
||||
#ifndef XC_TIMER_ENABLED
|
||||
#define XC_TIMER_ENABLED 0
|
||||
#endif
|
||||
// </e>
|
||||
|
||||
// <e> XC_AOTIMER_ENABLED
|
||||
//==========================================================
|
||||
#ifndef XC_AOTIMER_ENABLED
|
||||
#define XC_AOTIMER_ENABLED 0
|
||||
#endif
|
||||
// </e>
|
||||
|
||||
// <e> XC_GPIO_ENABLED
|
||||
//==========================================================
|
||||
#ifndef XC_GPIO_ENABLED
|
||||
#define XC_GPIO_ENABLED 1
|
||||
#endif
|
||||
// </e>
|
||||
|
||||
// <e> XC_ADC_ENABLED
|
||||
//==========================================================
|
||||
#ifndef XC_ADC_ENABLED
|
||||
#define XC_ADC_ENABLED 1
|
||||
#endif
|
||||
// </e>
|
||||
|
||||
// <e> XC_UART_ENABLED
|
||||
//==========================================================
|
||||
#ifndef XC_UART_ENABLED
|
||||
#define XC_UART_ENABLED 1
|
||||
#endif
|
||||
// </e>
|
||||
|
||||
// <e> XC_PWM_ENABLED
|
||||
//==========================================================
|
||||
#ifndef XC_PWM_ENABLED
|
||||
#define XC_PWM_ENABLED 1
|
||||
#endif
|
||||
// </e>
|
||||
|
||||
// <e> XC_FMC_SPI_ENABLED
|
||||
//==========================================================
|
||||
#ifndef XC_FMC_SPI_ENABLED
|
||||
#define XC_FMC_SPI_ENABLED 1
|
||||
#endif
|
||||
// </e>
|
||||
|
||||
// <e> XC_SPI_ENABLED
|
||||
//==========================================================
|
||||
#ifndef XC_SPI_ENABLED
|
||||
#define XC_SPI_ENABLED 0
|
||||
#endif
|
||||
// </e>
|
||||
|
||||
// <e> XC_IIC_ENABLED
|
||||
//==========================================================
|
||||
#ifndef XC_IIC_ENABLED
|
||||
#define XC_IIC_ENABLED 0
|
||||
#endif
|
||||
// </e>
|
||||
|
||||
// <e> XC_RTC_ENABLED
|
||||
//==========================================================
|
||||
#ifndef XC_RTC_ENABLED
|
||||
#define XC_RTC_ENABLED 0
|
||||
#endif
|
||||
|
||||
//==========================================================
|
||||
// <q> XC_RTC_DATE_INT_ENABLED
|
||||
|
||||
#ifndef XC_RTC_DATE_INT_ENABLED
|
||||
#define XC_RTC_DATE_INT_ENABLED 0
|
||||
#endif
|
||||
// </e>
|
||||
|
||||
// <e> XC_DMA_ENABLED
|
||||
//==========================================================
|
||||
#ifndef XC_DMA_ENABLED
|
||||
#define XC_DMA_ENABLED 0
|
||||
#endif
|
||||
// </e>
|
||||
|
||||
// <e> XC_PGA_ENABLED
|
||||
//==========================================================
|
||||
#ifndef XC_PGA_ENABLED
|
||||
#define XC_PGA_ENABLED 0
|
||||
#endif
|
||||
// </e>
|
||||
|
||||
// <e> XC_QDEC_ENABLED
|
||||
//==========================================================
|
||||
#ifndef XC_QDEC_ENABLED
|
||||
#define XC_QDEC_ENABLED 0
|
||||
#endif
|
||||
// </e>
|
||||
|
||||
// <e> XC_CALIB_ENABLED
|
||||
//==========================================================
|
||||
#ifndef XC_CALIB_ENABLED
|
||||
#define XC_CALIB_ENABLED 0
|
||||
#endif
|
||||
// </e>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
#endif //SDK_DRIVER_CONFIG_H
|
||||
|
||||
@@ -0,0 +1,329 @@
|
||||
#ifndef SDK_CONFIG_H
|
||||
#define SDK_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// XINCX_RF_EMHAMCED_PEACKET_MODE - RF enhanced packet mode
|
||||
// <i> Configure the frame format, which is a dynamic packet configuration, which can communicate in both directions,and
|
||||
// <i> ACK can dynamically carry data.
|
||||
#ifndef XINCX_RF_EMHAMCED_PACKET_MODE
|
||||
#define XINCX_RF_EMHAMCED_PACKET_MODE 1
|
||||
#endif
|
||||
|
||||
#if (XINCX_RF_EMHAMCED_PACKET_MODE == 1)
|
||||
// <o> XINCX_RF_COMPATIBILITY_MODE - RF Compatibility mode
|
||||
// <0=> Xinchip_mode
|
||||
// <1=> Panchip_mode
|
||||
// <2=> Beken_mode
|
||||
// <3=> Telink_mode
|
||||
// <4=> Huntersun_mode
|
||||
#ifndef XINCX_RF_COMPATIBILITY_MODE
|
||||
#define XINCX_RF_COMPATIBILITY_MODE 0
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
|
||||
//==========================================================
|
||||
|
||||
// <o> XINCX_RF_MODE - RF Tx or Rx Mode
|
||||
// <0=> TX Mode
|
||||
// <1=> RX Mode
|
||||
#ifndef XINCX_RF_MODE
|
||||
#define XINCX_RF_MODE 1
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
// <o> XINCX_RF_TRANS_RATE - RF Transmission Rate Config
|
||||
// <0x02=> 1M
|
||||
// <0x0A=> 2M
|
||||
// <0x22=> 250k
|
||||
// <0x2A=> 125k
|
||||
#ifndef XINCX_RF_TRANS_RATE
|
||||
#define XINCX_RF_TRANS_RATE 0x02
|
||||
#endif
|
||||
|
||||
// <o> XINCX_2_4G_CHANNEL - 2.4g Channel Set
|
||||
#ifndef XINCX_2_4G_CHANNEL
|
||||
#define XINCX_2_4G_CHANNEL 2440
|
||||
#endif
|
||||
|
||||
// <o> XINCX_RF_TX_ADDR_WIDTH - RF Tx Addr Width
|
||||
// <3=> 3 Bytes
|
||||
// <4=> 4 Bytes
|
||||
// <5=> 5 Bytes
|
||||
#ifndef XINCX_RF_TX_ADDR_WIDTH
|
||||
#define XINCX_RF_TX_ADDR_WIDTH 5
|
||||
#endif
|
||||
|
||||
// <o> XINCX_2_4G_ADDR_L - rf Address Set
|
||||
#ifndef XINCX_2_4G_ADDR_L
|
||||
#define XINCX_2_4G_ADDR_L 0xe7e7e7e7
|
||||
#endif
|
||||
|
||||
// <o> XINCX_2_4G_ADDR_H - rf Address Set
|
||||
#ifndef XINCX_2_4G_ADDR_H
|
||||
#define XINCX_2_4G_ADDR_H 0xe7
|
||||
#endif
|
||||
|
||||
// <o> XINCX_RF_POWER - rf Power Set
|
||||
// <1=> -10dbm
|
||||
// <2=> -9dbm
|
||||
// <4=> -4dbm
|
||||
// <6=> 0dbm
|
||||
// <8=> 3dbm
|
||||
// <9=> 5dbm
|
||||
// <12=> 7dbm
|
||||
// <14=> 8dbm
|
||||
// <16=> 9dbm
|
||||
// <19=> 10dbm
|
||||
// <24=> 11dbm
|
||||
// <30=> 12dbm
|
||||
// <36=> 13dbm
|
||||
#ifndef XINCX_POWER
|
||||
#define XINCX_POWER 0x00006
|
||||
#endif
|
||||
|
||||
// <o> XINCX_RF_NVIC_MODE - RF NVIC Mode
|
||||
// <0=> Disable
|
||||
// <1=> Enable
|
||||
#ifndef XINCX_RF_NVIC_MODE
|
||||
#define XINCX_RF_NVIC_MODE 1
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PIPE_RX_PAYLEN - 2.4g Pipe Rx Payload Len
|
||||
// <i> Payload length. Configuration of the load length during communication.
|
||||
//==========================================================
|
||||
// XINCX_2_4G_PIPE0_LEN - 2.4g Pipe0 Rx Payload Len
|
||||
// #ifndef XINCX_2_4G_PIPE0_LEN
|
||||
// #define XINCX_2_4G_PIPE0_LEN 32
|
||||
// #endif
|
||||
|
||||
// XINCX_2_4G_PIPE1_LEN - 2.4g Pipe1 Rx Payload Len
|
||||
#ifndef XINCX_2_4G_PIPE1_LEN
|
||||
#define XINCX_2_4G_PIPE1_LEN 32
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PIPE2_LEN - 2.4g Pipe2 Rx Payload Len
|
||||
#ifndef XINCX_2_4G_PIPE2_LEN
|
||||
#define XINCX_2_4G_PIPE2_LEN 32
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PIPE3_LEN - 2.4g Pipe3 Rx Payload Len
|
||||
#ifndef XINCX_2_4G_PIPE3_LEN
|
||||
#define XINCX_2_4G_PIPE3_LEN 32
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PIPE4_LEN - 2.4g Pipe4 Rx Payload Len
|
||||
#ifndef XINCX_2_4G_PIPE4_LEN
|
||||
#define XINCX_2_4G_PIPE4_LEN 32
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PIPE5_LEN - 2.4g Pipe5 Rx Payload Len
|
||||
#ifndef XINCX_2_4G_PIPE5_LEN
|
||||
#define XINCX_2_4G_PIPE5_LEN 32
|
||||
#endif
|
||||
|
||||
// XINCX_RF_CRC_ENABLE - RF CRC Enable
|
||||
//==========================================================
|
||||
#ifndef XINCX_RF_CRC_ENABLE
|
||||
#define XINCX_RF_CRC_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <o> XINCX_2_4G_CRC_BYTE - 2.4g CRC Bytes Set
|
||||
// <0=> 0 Byte
|
||||
// <1=> 1 Byte
|
||||
// <2=> 2 Bytes
|
||||
#ifndef XINCX_2_4G_CRC_BYTE
|
||||
#define XINCX_2_4G_CRC_BYTE 2
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_FEATURE_PARAM - 2.4g Feature Parameters
|
||||
//==========================================================
|
||||
|
||||
// XINCX_2_4G_GUARD_CFG - 2.4g Long Payload Feature
|
||||
#ifndef XINCX_2_4G_GUARD_CFG
|
||||
#define XINCX_2_4G_GUARD_CFG 0
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_LONG_PLD_TYPE - 2.4g Long Pld Type
|
||||
#ifndef XINCX_2_4G_LONG_PLD_TYPE
|
||||
#define XINCX_2_4G_LONG_PLD_TYPE 0
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PREAMBLE_NUM - 2.4g Preamble
|
||||
#ifndef XINCX_2_4G_PREAMBLE_NUM
|
||||
#define XINCX_2_4G_PREAMBLE_NUM 0
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PREAMBLE_TYPE - 2.4g Preamble Type
|
||||
#ifndef XINCX_2_4G_PREAMBLE_TYPE
|
||||
#define XINCX_2_4G_PREAMBLE_TYPE 0
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_CRC_SCOPE_GUARD - 2.4g CRC Scope Guard
|
||||
#ifndef XINCX_2_4G_CRC_SCOPE_GUARD
|
||||
#define XINCX_2_4G_CRC_SCOPE_GUARD 0
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_CRC_SCOPE_HEADER - 2.4g CRC Scope Header
|
||||
#ifndef XINCX_2_4G_CRC_SCOPE_HEADER
|
||||
#define XINCX_2_4G_CRC_SCOPE_HEADER 1
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_CRC_SCOPE_ADDR - 2.4g CRC Scope Addr
|
||||
#ifndef XINCX_2_4G_CRC_SCOPE_ADDR
|
||||
#define XINCX_2_4G_CRC_SCOPE_ADDR 1
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_LONG_PLD - 2.4g Long Payload Feature
|
||||
#ifndef XINCX_2_4G_LONG_PLD
|
||||
#define XINCX_2_4G_LONG_PLD 1
|
||||
#endif
|
||||
|
||||
// <q> XINCX_2_4G_FEC - 2.4g FEC&Interleave Feature
|
||||
#ifndef XINCX_2_4G_FEC
|
||||
#define XINCX_2_4G_FEC 0
|
||||
#endif
|
||||
|
||||
// <q> XINCX_2_4G_WHITEN - 2.4g Whiten Feature
|
||||
#ifndef XINCX_2_4G_WHITEN
|
||||
#define XINCX_2_4G_WHITEN 1
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_DPL - 2.4g Dynamic Payload Length Feature
|
||||
#ifndef XINCX_2_4G_DPL
|
||||
#define XINCX_2_4G_DPL 1
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_ACK_PAY - 2.4g Payload on ACK
|
||||
#ifndef XINCX_2_4G_ACK_PAY
|
||||
#define XINCX_2_4G_ACK_PAY 1
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_DYN_ACK - 2.4g W_TX_PAYLOAD_NOACK Command
|
||||
#ifndef XINCX_2_4G_DYN_ACK
|
||||
#define XINCX_2_4G_DYN_ACK 1
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_DYNPD - 2.4g dynpd
|
||||
#ifndef XINCX_2_4G_DYNPD
|
||||
#define XINCX_2_4G_DYNPD 0x3f
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_AUTO_ACK - 2.4g Auto Acknowledgement
|
||||
//==========================================================
|
||||
// XINCX_2_4G_PIPE0_ENAA - 2.4g Pipe0 Auto Ack
|
||||
#ifndef XINCX_2_4G_PIPE0_ENAA
|
||||
#define XINCX_2_4G_PIPE0_ENAA 1
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PIPE1_ENAA - 2.4g Pipe1 Auto Ack
|
||||
#ifndef XINCX_2_4G_PIPE1_ENAA
|
||||
#define XINCX_2_4G_PIPE1_ENAA 1
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PIPE2_ENAA - 2.4g Pipe2 Auto Ack
|
||||
#ifndef XINCX_2_4G_PIPE2_ENAA
|
||||
#define XINCX_2_4G_PIPE2_ENAA 1
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PIPE3_ENAA - 2.4g Pipe3 Auto Ack
|
||||
#ifndef XINCX_2_4G_PIPE3_ENAA
|
||||
#define XINCX_2_4G_PIPE3_ENAA 1
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PIPE4_ENAA - 2.4g Pipe4 Auto Ack
|
||||
#ifndef XINCX_2_4G_PIPE4_ENAA
|
||||
#define XINCX_2_4G_PIPE4_ENAA 1
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PIPE5_ENAA - 2.4g Pipe5 Auto Ack
|
||||
#ifndef XINCX_2_4G_PIPE5_ENAA
|
||||
#define XINCX_2_4G_PIPE5_ENAA 1
|
||||
#endif
|
||||
// <o.0..5> XINCX_RF_PIPE_ENABLE
|
||||
#ifndef XINCX_RF_PIPE_ENABLE
|
||||
#define XINCX_RF_PIPE_ENABLE 3
|
||||
#endif
|
||||
// XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
|
||||
//==========================================================
|
||||
|
||||
// <o> XINCX_2_4G_RETRANS_CNT - 2.4g Retransmit Count
|
||||
// <i> Number of retransmissions. The maximum number of times a hardware can automatically transmit an ACK if it does
|
||||
// not receive the correct ACK.
|
||||
// <0=> No retransmission
|
||||
// <1=> 1 time
|
||||
// <2=> 2 times
|
||||
// <3=> 3 times
|
||||
// <4=> 4 times
|
||||
// <5=> 5 times
|
||||
// <6=> 6 times
|
||||
// <7=> 7 times
|
||||
// <8=> 8 times
|
||||
// <9=> 9 times
|
||||
// <10=> 10 times
|
||||
// <11=> 11 times
|
||||
// <12=> 12 times
|
||||
// <13=> 13 times
|
||||
// <14=> 14 times
|
||||
// <15=> 15 times
|
||||
#ifndef XINCX_2_4G_RETRANS_CNT
|
||||
#define XINCX_2_4G_RETRANS_CNT 0
|
||||
#endif
|
||||
|
||||
// <o> XINCX_2_4G_RETRANS_DELAY - 2.4g Retransmission Delay
|
||||
// <i> Retransmission delay. For 32 bytes of data, the minimum configuration is 500 us for 1 Mbit/s and 1500 us for 250
|
||||
// kbit/s.
|
||||
// <0=> 250us
|
||||
// <1=> 500us
|
||||
// <2=> 750us
|
||||
// <3=> 1000us
|
||||
// <4=> 1250us
|
||||
// <5=> 1500us
|
||||
// <6=> 1750us
|
||||
// <7=> 2000us
|
||||
// <8=> 2250us
|
||||
// <9=> 2500us
|
||||
// <10=> 2750us
|
||||
// <11=> 3000us
|
||||
// <12=> 3250us
|
||||
// <13=> 3500us
|
||||
// <14=> 3750us
|
||||
// <15=> 4000us
|
||||
#ifndef XINCX_2_4G_RETRANS_DELAY
|
||||
#define XINCX_2_4G_RETRANS_DELAY 3
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
// RF 2.4g Compatibility configuration
|
||||
//==========================================================
|
||||
// Compatibility configuration, when you need to be compatible with other RF chips, you don't need to configure this
|
||||
// option when using our company's chips.
|
||||
// XINCX_2_4G_PREAMBLE - 2.4g preamble
|
||||
#ifndef XINCX_2_4G_PREAMBLE
|
||||
#define XINCX_2_4G_PREAMBLE 0x710f5555
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_GUARD - 2.4g guard
|
||||
#ifndef XINCX_2_4G_GUARD
|
||||
#define XINCX_2_4G_GUARD 0x8fc9
|
||||
#endif
|
||||
//
|
||||
|
||||
// XINCX_2_4G_CRY_CPT_ARRAY - 2.4g Crystal capacitor array
|
||||
//==========================================================
|
||||
// Crystal capacitor array, adjust to modify the frequency offset of the crystal oscillator.
|
||||
// XINCX_2_4G_CRY_CPT_ARRAY - 2.4g Crystal capacitor array
|
||||
#ifndef XINCX_2_4G_CRY_CPT_ARRAY
|
||||
#ifdef XC62XX
|
||||
#define XINCX_2_4G_CRY_CPT_ARRAY 0x38
|
||||
#else
|
||||
#define XINCX_2_4G_CRY_CPT_ARRAY 0x36
|
||||
#endif
|
||||
#endif
|
||||
//
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // SDK_CONFIG_H
|
||||
@@ -0,0 +1,276 @@
|
||||
|
||||
|
||||
#include "app_data.h"
|
||||
#include "rtt_platform.h"
|
||||
#include "xc_drv_gpio.h"
|
||||
|
||||
uint8_t addr_buff[5] = {0};
|
||||
uint8_t ack_pid = 0;
|
||||
uint8_t rf_send_ack_stat = TX_DATA_INVALID;
|
||||
uint16_t rf_addr_crc = 0;
|
||||
uint8_t ack_buff[128] = {0};
|
||||
uint8_t panchip_addr_whiten;
|
||||
uint8_t panchip_contorl_whiten;
|
||||
|
||||
/**
|
||||
* @brief Rf 2.4g get addr
|
||||
* @param uint8_t *addr_buff
|
||||
*
|
||||
* @retval void
|
||||
*/
|
||||
void rf_addr_map(uint8_t *addr_buff)
|
||||
{
|
||||
uint8_t addr_xsb = (XC_RF_2_4G->CFG_TOP >> 11) & (0x1);
|
||||
LOGI("addr_xsb %02x\r\n", addr_xsb);
|
||||
if (!addr_xsb) {
|
||||
addr_buff[0] = (XC_RF_2_4G->TX_ADDR_L >> 0) & 0xff;
|
||||
addr_buff[1] = (XC_RF_2_4G->TX_ADDR_L >> 8) & 0xff;
|
||||
addr_buff[2] = (XC_RF_2_4G->TX_ADDR_L >> 16) & 0xff;
|
||||
addr_buff[3] = (XC_RF_2_4G->TX_ADDR_L >> 24) & 0xff;
|
||||
addr_buff[4] = (XC_RF_2_4G->TX_ADDR_H >> 0) & 0xff;
|
||||
} else {
|
||||
addr_buff[1] = (XC_RF_2_4G->TX_ADDR_L >> 24) & 0xff;
|
||||
addr_buff[2] = (XC_RF_2_4G->TX_ADDR_L >> 16) & 0xff;
|
||||
addr_buff[3] = (XC_RF_2_4G->TX_ADDR_L >> 8) & 0xff;
|
||||
addr_buff[4] = (XC_RF_2_4G->TX_ADDR_L >> 0) & 0xff;
|
||||
addr_buff[0] = (XC_RF_2_4G->TX_ADDR_H >> 0) & 0xff;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Rf 2.4g get addr length
|
||||
* @param uint8_t *addr_buff
|
||||
*
|
||||
* @retval void
|
||||
*/
|
||||
uint8_t read_addr_wid(uint8_t *addr_buff)
|
||||
{
|
||||
uint8_t addr_wid = 0;
|
||||
switch (XC_RF_2_4G->SETUP_AW & 0xff) {
|
||||
case 0xa5:
|
||||
addr_wid = 3;
|
||||
#ifdef BEKEN_MODE
|
||||
addr_wid = 5;
|
||||
addr_buff[3] = 0xe7;
|
||||
addr_buff[4] = 0xe7;
|
||||
#endif
|
||||
break;
|
||||
|
||||
case 0xaa:
|
||||
addr_wid = 4;
|
||||
#ifdef BEKEN_MODE
|
||||
addr_wid = 4;
|
||||
addr_buff[4] = 0xe7;
|
||||
#endif
|
||||
break;
|
||||
|
||||
case 0xaf:
|
||||
addr_wid = 5;
|
||||
break;
|
||||
|
||||
default:
|
||||
addr_wid = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
return addr_wid;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Rf 2.4g panchip ack data config
|
||||
* @param uint8_t *addr_buff
|
||||
* @param uint8_t *ack_buff_cfg
|
||||
* @param uint8_t ack_payload_len
|
||||
* @retval uint16_t ack_crc_data
|
||||
*/
|
||||
__RAM_CODE uint16_t rf_enhanced_package_grouping(uint8_t *data_buff, uint8_t data_len)
|
||||
{
|
||||
uint16_t ack_control = (data_len << RF_RECV_EXTEN_LEN);
|
||||
// uint8_t ack_crc_buff[64] = {0};
|
||||
uint16_t ack_crc_data = 0;
|
||||
uint8_t temp_buff[64] = {0};
|
||||
ack_pid += 1;
|
||||
#if (COMPATILBE_MODE == PAN2416)
|
||||
if (ack_pid > 1)
|
||||
#else
|
||||
if (ack_pid > 3)
|
||||
#endif
|
||||
ack_pid = 0;
|
||||
ack_control = (ack_control & ~(0x3 << 1)) | (ack_pid << DATA_CONTROL_BIT) | DATA_CONTROL_NOACK;
|
||||
|
||||
#if (COMPATILBE_MODE == PAN2416)
|
||||
/* 数据反序 */
|
||||
buff_bigandsmallend(data_buff, data_len);
|
||||
#endif
|
||||
temp_buff[0] = ack_control >> DATA_CONTROL_BIT;
|
||||
temp_buff[1] = ((ack_control & DATA_ANALYSIS_BIT_L) << DATA_SPLICE_BIT) |
|
||||
((data_buff[0] >> DATA_CONTROL_BIT) & (~DATA_ANALYSIS_BIT_H));
|
||||
|
||||
if (data_len == 0) {
|
||||
temp_buff[1] &= DATA_ANALYSIS_BIT_H;
|
||||
}
|
||||
|
||||
/* 数据填入 */
|
||||
for (uint8_t i = 0; i < data_len; i++) {
|
||||
if (i == (data_len - 1)) {
|
||||
|
||||
temp_buff[i + 2] = (data_buff[data_len - 1] & DATA_ANALYSIS_BIT_L) << DATA_SPLICE_BIT;
|
||||
} else {
|
||||
temp_buff[i + 2] =
|
||||
((data_buff[i] & DATA_ANALYSIS_BIT_L) << DATA_SPLICE_BIT) | (data_buff[i + 1] >> DATA_CONTROL_BIT);
|
||||
}
|
||||
}
|
||||
|
||||
for (uint8_t i = 0; i < data_len + RF_RECV_EXTEN_LEN; i++) {
|
||||
data_buff[i] = temp_buff[i];
|
||||
}
|
||||
|
||||
#if (1 == XINCX_2_4G_CRC_BYTE)
|
||||
ack_crc_data = crc8_rohc(ack_crc_buff, data_len + RF_RECV_EXTEN_LEN - 1, RF_CRC_INIT_VALUE, PACKET_ENHANCED);
|
||||
|
||||
data_buff[data_len + 1] =
|
||||
(data_buff[data_len + 1] & DATA_ANALYSIS_BIT_H) | ((ack_crc_data >> DATA_CONTROL_BIT) & (~DATA_ANALYSIS_BIT_H));
|
||||
data_buff[data_len + 2] = (ack_crc_data << DATA_SPLICE_BIT) & (DATA_ANALYSIS_BIT_H);
|
||||
|
||||
memset(&ack_buff[0], 0, sizeof(ack_buff));
|
||||
whiten_data(&ack_crc_buff[addr_len], data_len, PANCHIP_WHITEN_INIT_VAL);
|
||||
if (data_len < sizeof(ack_buff))
|
||||
memcpy(&ack_buff[0], &ack_crc_buff[0], data_len);
|
||||
else
|
||||
LOGI("err %s,%d\r\n", __func__, __LINE__);
|
||||
|
||||
#elif (2 == XINCX_2_4G_CRC_BYTE)
|
||||
/* 计算CRC */
|
||||
ack_crc_data = crc16_ccitt_false(data_buff, data_len + RF_RECV_EXTEN_LEN - 1, rf_addr_crc, PACKET_ENHANCED);
|
||||
|
||||
#if (COMPATILBE_MODE == PAN2416)
|
||||
/* CRC 取反 */
|
||||
ack_crc_data = ~ack_crc_data;
|
||||
#endif
|
||||
/* CRC 放入数据包 */
|
||||
data_buff[data_len + 1] = (data_buff[data_len + 1] & DATA_ANALYSIS_BIT_H) |
|
||||
((ack_crc_data >> (DATA_CONTROL_BIT + BIT3)) & (~DATA_ANALYSIS_BIT_H));
|
||||
data_buff[data_len + 2] = (ack_crc_data >> DATA_CONTROL_BIT) & 0xff;
|
||||
data_buff[data_len + 3] =
|
||||
((ack_crc_data & DATA_ANALYSIS_BIT_L) << DATA_SPLICE_BIT) | (SUPPLEMENTARY_DATA >> DATA_CONTROL_BIT);
|
||||
|
||||
#if (COMPATILBE_MODE == PAN2416)
|
||||
/* 白化数据 */
|
||||
whiten_data(&data_buff[0], data_len + 5, panchip_addr_whiten);
|
||||
data_buff[data_len + 3] = (data_buff[data_len + 3] & 0xf0) | 0x04;
|
||||
#endif
|
||||
if (data_len + 1 < sizeof(ack_buff)) {
|
||||
for (uint8_t i = 0; i < data_len + 5; i++) {
|
||||
ack_buff[i] = data_buff[i];
|
||||
}
|
||||
} else
|
||||
LOGI("err %s,%d\r\n", __func__, __LINE__);
|
||||
|
||||
#endif
|
||||
return ack_crc_data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Rf 2.4g recv enhanced crc
|
||||
* @param uint8_t *buff
|
||||
* @param uint8_t buff_len
|
||||
* @retval uint16_t crc data
|
||||
*/
|
||||
__RAM_CODE uint16_t rf_recv_dyn_crc(uint8_t *buff, uint8_t buff_len)
|
||||
{
|
||||
uint8_t ack_crc_buff[64] = {0};
|
||||
for (uint8_t i = 0; i < buff_len; i++) {
|
||||
ack_crc_buff[i] = buff[i];
|
||||
}
|
||||
ack_crc_buff[buff_len - 1] &= DATA_ANALYSIS_BIT_H;
|
||||
#if (1 == XINCX_2_4G_CRC_BYTE)
|
||||
return crc8_rohc(ack_crc_buff, buff_len, rf_addr_crc, PACKET_ENHANCED);
|
||||
#elif (2 == XINCX_2_4G_CRC_BYTE)
|
||||
return crc16_ccitt_false(ack_crc_buff, buff_len, rf_addr_crc, PACKET_ENHANCED);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Rf 2.4g recv enhanced packet data parsing
|
||||
* @param uint8_t *buff
|
||||
* @param uint8_t buff_len
|
||||
*/
|
||||
__RAM_CODE void rf_enhanced_packet(uint8_t *buff, uint8_t buff_len)
|
||||
{
|
||||
uint8_t temp_buff[128] = {0};
|
||||
if (buff_len < sizeof(temp_buff))
|
||||
memcpy((char *)&temp_buff, (char *)buff, buff_len);
|
||||
else
|
||||
LOGI("err %s,%d\r\n", __func__, __LINE__);
|
||||
|
||||
for (uint8_t i = 0; i < buff_len; i++) {
|
||||
buff[i] = ((temp_buff[i + 1] & (~DATA_ANALYSIS_BIT_H)) << DATA_CONTROL_BIT) |
|
||||
((temp_buff[i + 2] & DATA_ANALYSIS_BIT_H) >> DATA_SPLICE_BIT);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Rf 2.4g recv enhanced packet data acquisition and parsing
|
||||
* @param uint8_t *buff
|
||||
* @retval uint8_t len
|
||||
*/
|
||||
__RAM_CODE uint8_t rf_enhanced_recv_data(uint8_t *buff)
|
||||
{
|
||||
uint16_t calc_crc_data = 0;
|
||||
uint16_t recv_crc_data = 0;
|
||||
uint8_t len = 0;
|
||||
if ((XC_RF_2_4G->STATUS & MASK_RX_DR) == MASK_RX_DR) {
|
||||
CE_CTL_LOW;
|
||||
rf_wr_cmd(R_RX_PLOAD);
|
||||
/* Get control field */
|
||||
buff[0] = XC_RF_2_4G->RX_FIFO_DATA;
|
||||
#if (COMPATILBE_MODE == PAN2416)
|
||||
panchip_contorl_whiten = whiten_data(&buff[0], 1, panchip_addr_whiten);
|
||||
len = ((buff[0] & 0xfe) >> 1);
|
||||
#elif (COMPATILBE_MODE == BEKEN)
|
||||
len = ((buff[0] & 0xfe) >> 2);
|
||||
#endif
|
||||
/* Get complete data */
|
||||
if (len > RF_RECV_AMX_LEN) {
|
||||
len = RF_RECV_AMX_LEN;
|
||||
}
|
||||
for (uint8_t i = 1; i < len + RF_RECV_EXTEN_LEN + 2; i++) {
|
||||
buff[i] = XC_RF_2_4G->RX_FIFO_DATA;
|
||||
}
|
||||
|
||||
/* Clear FIFO and STATUS */
|
||||
rf_wr_cmd(FLUSH_RX);
|
||||
XC_RF_2_4G->STATUS = MASK_RX_DR;
|
||||
|
||||
#if (COMPATILBE_MODE == PAN2416)
|
||||
/* Bleaching */
|
||||
whiten_data(&buff[1], len + 5, panchip_contorl_whiten);
|
||||
#endif
|
||||
/* CRC veify */
|
||||
calc_crc_data = rf_recv_dyn_crc(buff, len + RF_RECV_EXTEN_LEN - 1);
|
||||
recv_crc_data = ((buff[len + 1] & (~DATA_ANALYSIS_BIT_H)) << (DATA_CONTROL_BIT + BIT3)) |
|
||||
((buff[len + 2] & 0xff) << DATA_CONTROL_BIT) |
|
||||
((buff[len + 3] & DATA_ANALYSIS_BIT_H) >> DATA_SPLICE_BIT);
|
||||
|
||||
#if (COMPATILBE_MODE == PAN2416)
|
||||
recv_crc_data = ~recv_crc_data;
|
||||
#endif
|
||||
if (recv_crc_data == calc_crc_data) {
|
||||
/* Verify correctly and parse the data */
|
||||
rf_enhanced_packet(buff, len + RF_RECV_EXTEN_LEN + 1);
|
||||
|
||||
#if (COMPATILBE_MODE == PAN2416)
|
||||
buff_bigandsmallend(buff, len + RF_RECV_EXTEN_LEN + 1);
|
||||
#endif
|
||||
rf_send_ack_stat = TX_DATA_OK;
|
||||
} else {
|
||||
/* The verification failed and data was discarded. Procedure */
|
||||
memset(buff, 0, len);
|
||||
len = 0;
|
||||
}
|
||||
} else {
|
||||
rf_send_ack_stat = TX_RETRANS_MAX;
|
||||
}
|
||||
|
||||
return len;
|
||||
}
|
||||
@@ -0,0 +1,830 @@
|
||||
|
||||
#include "app_rf.h"
|
||||
rf_timer_stat_t timer_stat = RF_FREE_TIMER_INTER;
|
||||
#define TEST_PIN_USB 1
|
||||
|
||||
uint8_t ret = TX_DATA_INVALID;
|
||||
uint32_t count = 0;
|
||||
uint32_t send_ok = 0;
|
||||
uint32_t send_max = 0;
|
||||
|
||||
uint8_t rf_ack_len = ACK_LEN;
|
||||
uint16_t recv_crc_data = 0;
|
||||
uint16_t calc_crc_data = 0;
|
||||
|
||||
bool rf_send_timer_flag = false;
|
||||
bool rf_recv_timer_flag = false;
|
||||
|
||||
bool rf_prx_ack_flag = false;
|
||||
|
||||
uint8_t data_len = 0;
|
||||
|
||||
rf_data_typedef_t rf_data_t;
|
||||
|
||||
uint8_t send_buff[35] = {0};
|
||||
uint32_t send_cnt = 0;
|
||||
uint32_t recv_timer_cnt = 0;
|
||||
uint32_t recv_crc_err = 0;
|
||||
uint32_t recv_crc_ok = 0;
|
||||
uint32_t recv_cnt = 0;
|
||||
extern uint8_t rf_send_ack_stat;
|
||||
|
||||
Timer_InitCfg_t timer_cfg = {
|
||||
.timer_src_clk = TIMER_CLK_SRC_32M_DIV,
|
||||
.timer_div_clk = TIMER_DIV_CLK_16MHzOr16K,
|
||||
};
|
||||
|
||||
// #if DEBUG_PIN
|
||||
|
||||
/**
|
||||
* @brief Test pin config
|
||||
* @param void
|
||||
* @retval void
|
||||
*/
|
||||
void gpio_test(void)
|
||||
{
|
||||
// LOGI("gpio\r\n");
|
||||
GPIO_InitCfg_t gpio_cfg;
|
||||
gpio_cfg.Mux = GPIO_Mux0;
|
||||
gpio_cfg.FunSel = GPIO_Dx;
|
||||
gpio_cfg.Pull = GPIO_PULLDOWN;
|
||||
gpio_cfg.Int = NOT_INT;
|
||||
gpio_cfg.Dir = GPIO_DIR_OUTPUT;
|
||||
// #if TEST_PIN_NO_USB
|
||||
gpio_cfg.Pin = TEST_PIN_1;
|
||||
xc_gpio_init(&gpio_cfg);
|
||||
|
||||
gpio_cfg.Pin = TEST_PIN_2;
|
||||
xc_gpio_init(&gpio_cfg);
|
||||
|
||||
gpio_cfg.Pin = TEST_PIN_3;
|
||||
xc_gpio_init(&gpio_cfg);
|
||||
|
||||
gpio_cfg.Pin = TEST_PIN_5;
|
||||
xc_gpio_init(&gpio_cfg);
|
||||
// #endif
|
||||
|
||||
gpio_cfg.Pin = TEST_PIN_4;
|
||||
xc_gpio_init(&gpio_cfg);
|
||||
|
||||
gpio_cfg.Pin = TEST_PIN_6;
|
||||
xc_gpio_init(&gpio_cfg);
|
||||
// #if TEST_PIN_NO_USB
|
||||
gpio_cfg.Pin = TEST_PIN_7;
|
||||
xc_gpio_init(&gpio_cfg);
|
||||
|
||||
gpio_cfg.Pin = TEST_PIN_8;
|
||||
xc_gpio_init(&gpio_cfg);
|
||||
// #endif
|
||||
xc_gpio_write_pin(TEST_PIN_1, GPIO_PIN_RESET);
|
||||
xc_gpio_write_pin(TEST_PIN_2, GPIO_PIN_RESET);
|
||||
xc_gpio_write_pin(TEST_PIN_3, GPIO_PIN_RESET);
|
||||
// xc_gpio_write_pin(GPIO_9, GPIO_PIN_RESET);
|
||||
xc_gpio_write_pin(TEST_PIN_4, GPIO_PIN_RESET);
|
||||
xc_gpio_write_pin(TEST_PIN_5, GPIO_PIN_RESET);
|
||||
xc_gpio_write_pin(TEST_PIN_6, GPIO_PIN_RESET);
|
||||
xc_gpio_write_pin(TEST_PIN_7, GPIO_PIN_RESET);
|
||||
|
||||
xc_gpio_write_pin(TEST_PIN_8, GPIO_PIN_RESET);
|
||||
|
||||
gpio_cfg.Pull = GPIO_PULLDOWN;
|
||||
gpio_cfg.Dir = GPIO_DIR_INPUT;
|
||||
gpio_cfg.Pin = GPIO_4;
|
||||
xc_gpio_init(&gpio_cfg);
|
||||
}
|
||||
// #endif // DEBUG_PIN
|
||||
|
||||
/**
|
||||
* @brief RF 2.4g DEBUG PIN config
|
||||
* @param uint8_t gpio_id - The parameters can be GPIO 2 ~ 9, GPIO 18 ~ 25, and GPIO 14
|
||||
* @retval void
|
||||
*/
|
||||
void rf_debug_pin(uint8_t gpio_id)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
val = (*(volatile unsigned int *)(0x53022040));
|
||||
val |= 0x7 << 4;
|
||||
(*(volatile unsigned int *)(0x53022040)) = val; // TPORT_DATA0_SEL set
|
||||
|
||||
val = (*(volatile unsigned int *)(0x53023010));
|
||||
val &= ~(3 << 28);
|
||||
|
||||
val |= (0xa << 16 | 1 << 24 | 2 << 28); // 0xc
|
||||
(*(volatile unsigned int *)(0x53023010)) = val; // diag_sel[3:0] set
|
||||
|
||||
LOGI("after 0x53022040=0x%x, 0x53022010=0x%x\n", *(volatile unsigned int *)(0x53022040),
|
||||
*(volatile unsigned int *)(0x53023010));
|
||||
|
||||
uint32_t addr_val = 0;
|
||||
switch (gpio_id) {
|
||||
case GPIO_3:
|
||||
xc_gpio_fun_sel(gpio_id, GPIO_Dx);
|
||||
xc_gpio_mux_ctl(gpio_id, GPIO_Mux3); // en test_pin[8]
|
||||
addr_val = 0x40000170;
|
||||
break;
|
||||
case GPIO_4:
|
||||
xc_gpio_fun_sel(gpio_id, GPIO_Dx);
|
||||
xc_gpio_mux_ctl(gpio_id, GPIO_Mux3); // en test_pin[8]
|
||||
addr_val = 0x40000174;
|
||||
break;
|
||||
case GPIO_2:
|
||||
xc_gpio_fun_sel(gpio_id, GPIO_Dx);
|
||||
xc_gpio_mux_ctl(gpio_id, GPIO_Mux2); // en test_pin[8]
|
||||
addr_val = 0x40000178;
|
||||
break;
|
||||
case GPIO_6:
|
||||
xc_gpio_fun_sel(gpio_id, GPIO_Dx);
|
||||
xc_gpio_mux_ctl(gpio_id, GPIO_Mux3); // en test_pin[8]
|
||||
addr_val = 0x4000017c;
|
||||
break;
|
||||
case GPIO_7:
|
||||
case GPIO_20:
|
||||
xc_gpio_fun_sel(gpio_id, GPIO_Dx);
|
||||
xc_gpio_mux_ctl(gpio_id, GPIO_Mux3); // en test_pin[8]
|
||||
addr_val = 0x40000180;
|
||||
break;
|
||||
case GPIO_8:
|
||||
case GPIO_21:
|
||||
xc_gpio_fun_sel(gpio_id, GPIO_Dx);
|
||||
xc_gpio_mux_ctl(gpio_id, GPIO_Mux3); // en test_pin[8]
|
||||
addr_val = 0x40000184;
|
||||
break;
|
||||
case GPIO_9:
|
||||
case GPIO_14:
|
||||
case GPIO_22:
|
||||
xc_gpio_fun_sel(gpio_id, GPIO_Dx);
|
||||
xc_gpio_mux_ctl(gpio_id, GPIO_Mux3); // en test_pin[8]
|
||||
addr_val = 0x40000188;
|
||||
break;
|
||||
case GPIO_18:
|
||||
case GPIO_23:
|
||||
xc_gpio_fun_sel(gpio_id, GPIO_Dx);
|
||||
xc_gpio_mux_ctl(gpio_id, GPIO_Mux3); // en test_pin[8]
|
||||
addr_val = 0x4000018c;
|
||||
break;
|
||||
case GPIO_19:
|
||||
case GPIO_24:
|
||||
xc_gpio_fun_sel(gpio_id, GPIO_Dx);
|
||||
xc_gpio_mux_ctl(gpio_id, GPIO_Mux3); // en test_pin[8]
|
||||
addr_val = 0x40000190;
|
||||
break;
|
||||
case GPIO_12:
|
||||
case GPIO_25:
|
||||
xc_gpio_fun_sel(gpio_id, GPIO_Dx);
|
||||
xc_gpio_mux_ctl(gpio_id, GPIO_Mux3); // en test_pin[8]
|
||||
addr_val = 0x40000194;
|
||||
break;
|
||||
default:
|
||||
LOGI("test pin id error\n");
|
||||
break;
|
||||
}
|
||||
*((uint32_t volatile *)addr_val) = 7;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief RF 2.4g get address crc
|
||||
* @param void
|
||||
* @retval crc data
|
||||
*/
|
||||
uint16_t rf_get_addr_crc(void)
|
||||
{
|
||||
#if (1 == XINCX_2_4G_CRC_BYTE)
|
||||
return crc8_rohc(addr_buff, RF_ADDR_LEN, RF_CRC_INIT_VALUE, PACKET_NORMAL);
|
||||
#elif (2 == XINCX_2_4G_CRC_BYTE)
|
||||
return crc16_ccitt_false(addr_buff, RF_ADDR_LEN, RF_CRC_INIT_VALUE, PACKET_NORMAL);
|
||||
#endif
|
||||
}
|
||||
|
||||
///**
|
||||
// * @brief RF 2.4g buff info
|
||||
// * @param uint8_t * - buff
|
||||
// * uint8_t len
|
||||
// * @retval void
|
||||
// */
|
||||
// void rf_buff_info(uint8_t *buff, uint8_t len)
|
||||
//{
|
||||
// for (uint8_t i = 0; i < len; i++)
|
||||
// LOGI("%02x ", buff[i]);
|
||||
// LOGI("\r\n");
|
||||
//}
|
||||
|
||||
/**
|
||||
* @brief RF 2.4g panchip tx data config
|
||||
* @param uint8_t *buff
|
||||
* @param uint8_t *data_buff
|
||||
* @param uint8_t data_len
|
||||
* @retval uint16_t crc data
|
||||
*/
|
||||
__RAM_CODE void rf_rx_ack_payload_event(uint8_t *buff, uint8_t len)
|
||||
{
|
||||
// /* ACK data filling */
|
||||
// rf_data_config(ack_buff, len);
|
||||
/* Dynamic packet grouping */
|
||||
rf_enhanced_package_grouping(buff, len);
|
||||
/* ACK pyaload data fill FIFO */
|
||||
rf_recv_sf_ack_payload(buff, len);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief RF 2.4g setting agc
|
||||
* @param uint8_t adc_rssi_mean
|
||||
* @param uint8_t agc_gain_delay
|
||||
* @retval void
|
||||
*/
|
||||
void rf_set_agc(uint8_t adc_rssi_mean, uint8_t agc_gain_delay)
|
||||
{
|
||||
XC_RF_2_4G->AGC_SETTING &= ~(0xf << 16);
|
||||
XC_RF_2_4G->AGC_SETTING |= (adc_rssi_mean << 16) | (agc_gain_delay << 18);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief RF 2.4g pwr down and up
|
||||
* @param void
|
||||
* @retval void
|
||||
*/
|
||||
void rf_pwr_down_up(void)
|
||||
{
|
||||
XC_RF_2_4G->CFG_TOP &= ~(1 << 1);
|
||||
XC_RF_2_4G->CFG_TOP |= (1 << 1);
|
||||
}
|
||||
|
||||
__RAM_CODE uint8_t rf_tx2rx_payload_event(rf_data_typedef_t *rf_data, uint8_t *ack_buff)
|
||||
{
|
||||
|
||||
uint8_t send_len = rf_data->data_length + 5;
|
||||
/* Modulation frequency offset */
|
||||
XC_RF_2_4G->TXPROC_CFG = ((XC_RF_2_4G->TXPROC_CFG & (~0x1FF)) | RF_FREQ_SEND_DEV);
|
||||
/* Set receive length */
|
||||
set_rf_pipe_rx_payLen(send_len, send_len, send_len, send_len, send_len, send_len);
|
||||
/* Set send mode */
|
||||
set_rf_mode(TX_MODE);
|
||||
/* Set the sending frequency */
|
||||
set_rf_channel(XINCX_2_4G_CHANNEL);
|
||||
/* data transmission */
|
||||
rf_enhanced_package_grouping(send_buff, rf_data->data_length);
|
||||
#if DEBUG_PIN
|
||||
xc_gpio_write_pin(TEST_PIN_2, GPIO_PIN_SET);
|
||||
#endif
|
||||
ret = rf_tx_event(send_buff, send_len);
|
||||
CE_CTL_LOW;
|
||||
/* txlo spi en,1=work,默认0 */
|
||||
XC_BT_RF->ana31_reg_l &= ~(1 << 5);
|
||||
XC_BT_RF->ana31_reg_l &= ~(1 << 4);
|
||||
|
||||
#if DEBUG_PIN
|
||||
xc_gpio_write_pin(TEST_PIN_2, GPIO_PIN_RESET);
|
||||
#endif
|
||||
#if 1
|
||||
/* Modulation frequency offset */
|
||||
XC_RF_2_4G->TXPROC_CFG = ((XC_RF_2_4G->TXPROC_CFG & (~0x1FF)) | RF_FREQ_RECV_DEV);
|
||||
/* 切换到接收模式 */
|
||||
rf_set_rx_mode(XINCX_2_4G_CHANNEL, XINCX_2_4G_PIPE0_LEN + 5);
|
||||
#if DEBUG_PIN
|
||||
xc_gpio_write_pin(TEST_PIN_3, GPIO_PIN_SET);
|
||||
#endif
|
||||
|
||||
/* 等待接收ACK数据 */
|
||||
#if (COMPATILBE_MODE == PANCHIP_PACKET)
|
||||
delay_ms(3);
|
||||
#else
|
||||
delay_ms(2);
|
||||
#endif
|
||||
do {
|
||||
if (recv_timer_cnt >= (RF_RECV_TIMER + 5)) {
|
||||
rf_send_ack_stat = TX_RETRANS_MAX;
|
||||
break;
|
||||
}
|
||||
#if DEBUG_PIN
|
||||
xc_gpio_write_pin(TEST_PIN_4, GPIO_PIN_SET);
|
||||
#endif // DEBUG_PIN
|
||||
delay_us(BIT_TIMER);
|
||||
#if DEBUG_PIN
|
||||
xc_gpio_write_pin(TEST_PIN_4, GPIO_PIN_RESET);
|
||||
#endif // DEBUG_PIN
|
||||
|
||||
recv_len = rf_enhanced_recv_data(ack_buff);
|
||||
|
||||
if (rf_send_ack_stat == TX_DATA_OK) {
|
||||
recv_cnt += 1;
|
||||
break;
|
||||
} else if (rf_send_ack_stat == TX_RETRANS_MAX) {
|
||||
break;
|
||||
}
|
||||
recv_timer_cnt += 1;
|
||||
} while (!recv_len);
|
||||
CE_CTL_LOW;
|
||||
rf_send_ack_stat = TX_DATA_INVALID;
|
||||
rf_wr_cmd(FLUSH_RX);
|
||||
#if DEBUG_PIN
|
||||
xc_gpio_write_pin(TEST_PIN_3, GPIO_PIN_RESET);
|
||||
#endif // DEBUG_PIN
|
||||
|
||||
#endif
|
||||
recv_timer_cnt = 0;
|
||||
return recv_len;
|
||||
}
|
||||
#if (XINCX_RF_COMPATIBILITY_MODE == PANCHIP_PACKET)
|
||||
/**
|
||||
* @brief Timer initialize
|
||||
* @param uint8_t timer_id
|
||||
* @param uint32_t timer_cnt
|
||||
* @retval void
|
||||
*/
|
||||
void timer_init(uint8_t timer_id, uint32_t timer_cnt)
|
||||
{
|
||||
|
||||
#if !XINCX_RF_MODE
|
||||
timer_cfg.timer_mode = TIMER_MODE_CYCLE; // TIMER_MODE_CYCLE//TIMER_MODE_SINGLE
|
||||
#else
|
||||
timer_cfg.timer_mode = TIMER_MODE_CYCLE; // TIMER_MODE_CYCLE//TIMER_MODE_SINGLE
|
||||
#endif
|
||||
xc_timer_init(timer_id, &timer_cfg);
|
||||
xc_timer_set_value(timer_id, timer_cnt);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief RF 2.4g tx maage
|
||||
* @param rf_data_typedef_t *rf_data,
|
||||
* @retval uint32_t rf_data->cnt
|
||||
*/
|
||||
__RAM_CODE uint32_t rf_tx_manage(rf_data_typedef_t *rf_data)
|
||||
{
|
||||
uint8_t ack_buff[64] = {0};
|
||||
|
||||
static uint32_t send_cnt = 0;
|
||||
if (send_cnt < XC_SEND_NUM) {
|
||||
#if DEBUG_PIN
|
||||
xc_gpio_write_pin(TEST_PIN_1, GPIO_PIN_SET);
|
||||
#endif
|
||||
rf_send_timer_flag = false;
|
||||
|
||||
rf_data->cnt += 1;
|
||||
/* Filling in software frame number */
|
||||
rf_data->data_length = 32;
|
||||
|
||||
rf_data_config(send_buff, rf_data->data_length);
|
||||
|
||||
uint8_t ack_len = rf_tx2rx_payload_event(rf_data, ack_buff);
|
||||
|
||||
send_cnt += 1;
|
||||
|
||||
LOGI("send_cnt:%d, recv_cnt:%d, recv_len:%d\r\n", send_cnt, recv_cnt, ack_len);
|
||||
LOGI("ack data(len:%d):%02x\n\n", ack_len, ack_buff[0]);
|
||||
// rf_buff_info(ack_buff, ack_len);
|
||||
memset(rf_data->buff, 0, sizeof(rf_data->buff));
|
||||
memset(ack_buff, 0xff, sizeof(ack_buff));
|
||||
#if DEBUG_PIN
|
||||
xc_gpio_write_pin(TEST_PIN_1, GPIO_PIN_RESET);
|
||||
#endif
|
||||
rf_send_ack_stat = TX_DATA_INVALID;
|
||||
}
|
||||
if (send_cnt == XC_SEND_NUM) {
|
||||
rf_data->cnt += 1;
|
||||
send_cnt += 1;
|
||||
/* Turn off the send timer */
|
||||
xc_timer_stop(RF_TX_TIMERx);
|
||||
}
|
||||
|
||||
return rf_data->cnt;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief timer0 callback
|
||||
* @param void *context
|
||||
* @retval void
|
||||
*/
|
||||
__RAM_CODE void timer0_callback(void *context)
|
||||
{
|
||||
#if XINCX_RF_MODE
|
||||
xc_timer_stop(RF_RX_TIMERx);
|
||||
switch (timer_stat) {
|
||||
case RF_SEND_TIMER_INTER /* 动态 ACk 发射完成 */:
|
||||
/* code */
|
||||
timer_stat = RF_FREE_TIMER_INTER;
|
||||
#if DEBUG_PIN
|
||||
// xc_gpio_write_pin(TEST_PIN_4, GPIO_PIN_SET);
|
||||
#endif // DEBUG_PIN
|
||||
#if DEBUG_PIN
|
||||
xc_gpio_write_pin(TEST_PIN_5, GPIO_PIN_RESET);
|
||||
#endif
|
||||
CE_CTL_LOW;
|
||||
/* txlo spi en,1=work,默认0 */
|
||||
XC_BT_RF->ana31_reg_l &= ~(1 << 5);
|
||||
XC_BT_RF->ana31_reg_l &= ~(1 << 4);
|
||||
rf_prx_ack_flag = true;
|
||||
|
||||
if (recv_len <= BUFF_LEN_MAX) {
|
||||
} else {
|
||||
LOGI("err %s,%d\r\n", __func__, __LINE__);
|
||||
}
|
||||
|
||||
#if DEBUG_PIN
|
||||
xc_gpio_write_pin(TEST_PIN_4, GPIO_PIN_RESET);
|
||||
#endif // DEBUG_PIN
|
||||
break;
|
||||
|
||||
case RF_RECV_TIMER_INTER /* 动态收包完成 */:
|
||||
/* code */
|
||||
xc_timer_stop(RF_RX_TIMERx);
|
||||
timer_stat = RF_FREE_TIMER_INTER;
|
||||
#if DEBUG_PIN
|
||||
xc_gpio_write_pin(TEST_PIN_2, GPIO_PIN_RESET);
|
||||
#endif // DEBUG_PIN
|
||||
|
||||
for (uint8_t i = 1; i < recv_len + RF_RECV_EXTEN_LEN + 1; i++) {
|
||||
rf_data_t.buff[i] = XC_RF_2_4G->RX_FIFO_DATA;
|
||||
}
|
||||
CE_CTL_LOW;
|
||||
rf_wr_cmd(FLUSH_RX);
|
||||
XC_RF_2_4G->STATUS |= MASK_RX_DR | MASK_RX_SYNC;
|
||||
|
||||
NVIC_EnableIRQ(RF24G_IRQn);
|
||||
// rf_buff_info(rf_data_t.buff, recv_len+10);
|
||||
xc_rf_send_ack(rf_data_t.buff, recv_len);
|
||||
recv_cnt += 1;
|
||||
break;
|
||||
case RF_FREE_TIMER_INTER /* 其他状态 */:
|
||||
rf_set_rx_mode(XINCX_2_4G_CHANNEL, XINCX_2_4G_PIPE0_LEN);
|
||||
/* code */
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
#else
|
||||
rf_send_timer_flag = true;
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
/**
|
||||
* @brief RF 2.4g software send ack packet
|
||||
* @param uint8_t *buff
|
||||
* @param uint8_t recv_len
|
||||
* @retval void
|
||||
*/
|
||||
__RAM_CODE void xc_rf_send_ack(uint8_t *buff, uint8_t recv_len)
|
||||
{
|
||||
#if (1 == XINCX_2_4G_CRC_BYTE)
|
||||
/* Set the length of the data to be sent */
|
||||
set_rf_pipe_rx_payLen(rf_ack_len + RF_RECV_EXTEN_LEN, rf_ack_len + RF_RECV_EXTEN_LEN,
|
||||
rf_ack_len + RF_RECV_EXTEN_LEN, rf_ack_len + RF_RECV_EXTEN_LEN,
|
||||
rf_ack_len + RF_RECV_EXTEN_LEN, rf_ack_len + RF_RECV_EXTEN_LEN);
|
||||
/* Set send mode */
|
||||
set_rf_mode(TX_MODE);
|
||||
/* Set the transmission frequency */
|
||||
set_rf_channel(XINCX_2_4G_CHANNEL);
|
||||
CE_CTL_HIGH;
|
||||
/* txlo spi en,1=work,默认0 */
|
||||
XC_BT_RF->ana31_reg_l |= (1 << 5);
|
||||
/* Theoretical CRC calculation of received data */
|
||||
calc_crc_data = rf_recv_dyn_crc(rf_data_t.buff, recv_len + RF_RECV_EXTEN_LEN - 1);
|
||||
/* Get the actual CRC for receiving data */
|
||||
recv_crc_data = ((rf_data_t.buff[recv_len + 1] & (~BIT7)) << DATA_CONTROL_BIT) |
|
||||
((rf_data_t.buff[recv_len + 2] & BIT7) >> DATA_SPLICE_BIT);
|
||||
/* txlo spi en,1=work,默认0 */
|
||||
XC_BT_RF->ana31_reg_l |= (1 << 4);
|
||||
/* CRC check */
|
||||
if (calc_crc_data == recv_crc_data) {
|
||||
#if DEBUG_PIN
|
||||
xc_gpio_write_pin(TEST_PIN_4, GPIO_PIN_SET);
|
||||
#endif // DEBUG_PIN
|
||||
/* Wait for sending to complete */
|
||||
xc_timer_set_value(RF_RX_TIMERx, 10 + (rf_ack_len + 9) * BIT_TIMER);
|
||||
xc_timer_start(RF_RX_TIMERx);
|
||||
/* Data parsing */
|
||||
rf_enhanced_packet(rf_data_t.buff, recv_len + RF_RECV_EXTEN_LEN - 1);
|
||||
|
||||
#elif (2 == XINCX_2_4G_CRC_BYTE)
|
||||
|
||||
set_rf_pipe_rx_payLen(rf_ack_len + RF_RECV_EXTEN_LEN + 2, rf_ack_len + RF_RECV_EXTEN_LEN + 2,
|
||||
rf_ack_len + RF_RECV_EXTEN_LEN + 2, rf_ack_len + RF_RECV_EXTEN_LEN + 2,
|
||||
rf_ack_len + RF_RECV_EXTEN_LEN + 2, rf_ack_len + RF_RECV_EXTEN_LEN + 2);
|
||||
set_rf_mode(TX_MODE);
|
||||
|
||||
/* 调制频偏 */
|
||||
XC_RF_2_4G->TXPROC_CFG = ((XC_RF_2_4G->TXPROC_CFG & (~0x1FF)) | RF_FREQ_SEND_DEV);
|
||||
set_rf_channel(XINCX_2_4G_CHANNEL);
|
||||
/* 发射 ACk */
|
||||
CE_CTL_HIGH;
|
||||
/* txlo spi en,1=work,默认0 */
|
||||
XC_BT_RF->ana31_reg_l |= (1 << 5);
|
||||
|
||||
#if DEBUG_PIN
|
||||
xc_gpio_write_pin(TEST_PIN_5, GPIO_PIN_SET);
|
||||
#endif // DEBUG_PIN
|
||||
|
||||
#if (COMPATILBE_MODE == PANCHIP_PACKET)
|
||||
whiten_data(&rf_data_t.buff[1], recv_len + RF_RECV_EXTEN_LEN, panchip_contorl_whiten);
|
||||
#endif //(COMPATILBE_MODE == PAN2416)
|
||||
|
||||
#if DEBUG_PIN
|
||||
xc_gpio_write_pin(TEST_PIN_5, GPIO_PIN_RESET);
|
||||
|
||||
xc_gpio_write_pin(TEST_PIN_6, GPIO_PIN_SET);
|
||||
#endif // DEBUG_PIN
|
||||
calc_crc_data = rf_recv_dyn_crc(rf_data_t.buff, recv_len + RF_RECV_EXTEN_LEN - 1);
|
||||
recv_crc_data = ((rf_data_t.buff[recv_len + 1] & (~DATA_ANALYSIS_BIT_H)) << (DATA_CONTROL_BIT + BIT3)) |
|
||||
((rf_data_t.buff[recv_len + 2] & 0xff) << DATA_CONTROL_BIT) |
|
||||
((rf_data_t.buff[recv_len + 3] & DATA_ANALYSIS_BIT_H) >> DATA_SPLICE_BIT);
|
||||
// rf_enhanced_packet(rf_data_t.buff, recv_len + RF_RECV_EXTEN_LEN - 1);
|
||||
// rf_buff_info(rf_data_t.buff, recv_len + 3);
|
||||
/* txlo spi en,1=work,默认0 */
|
||||
XC_BT_RF->ana31_reg_l |= (1 << 4);
|
||||
#if (COMPATILBE_MODE == PANCHIP_PACKET)
|
||||
recv_crc_data = ~recv_crc_data;
|
||||
#endif //(COMPATILBE_MODE == PANCHIP_PACKET)
|
||||
// LOGI("calc_crc_data:0x%02x,recv_crc_data:0x%02x\nrecv_len:%d\n panchip_addr_whiten:%02x\n", calc_crc_data,
|
||||
// recv_crc_data, recv_len, panchip_addr_whiten);
|
||||
if (calc_crc_data == recv_crc_data) { /* CRC正确，继续发射ACK*/
|
||||
#if DEBUG_PIN
|
||||
xc_gpio_write_pin(TEST_PIN_4, GPIO_PIN_SET);
|
||||
#endif // DEBUG_PIN
|
||||
|
||||
#if (BEKEN_PACKET == COMPATILBE_MODE)
|
||||
|
||||
rf_enhanced_packet(rf_data_t.buff, recv_len + RF_RECV_EXTEN_LEN - 1);
|
||||
/* Wait for sending to complete */
|
||||
xc_timer_stop(RF_RX_TIMERx);
|
||||
xc_timer_set_value(RF_RX_TIMERx, (rf_ack_len + 10) * BIT_TIMER);
|
||||
|
||||
#elif (COMPATILBE_MODE == PANCHIP_PACKET)
|
||||
/* Wait for sending to complete */
|
||||
xc_timer_set_value(RF_RX_TIMERx, 120 + (rf_ack_len + 3 + 5 + 4) * BIT_TIMER);
|
||||
/* Albino data is parsed into valid data */
|
||||
rf_enhanced_packet(rf_data_t.buff, recv_len + RF_RECV_EXTEN_LEN + 1);
|
||||
buff_bigandsmallend(rf_data_t.buff, recv_len + RF_RECV_EXTEN_LEN + 1);
|
||||
#endif
|
||||
|
||||
xc_timer_start(RF_RX_TIMERx);
|
||||
#if DEBUG_PIN
|
||||
xc_gpio_write_pin(TEST_PIN_5, GPIO_PIN_SET);
|
||||
#endif
|
||||
timer_stat = RF_SEND_TIMER_INTER;
|
||||
recv_crc_ok += 1;
|
||||
#endif
|
||||
} else { /* CRC错误，停止发射ACK并重新填入ACK数据，转接收模式 */
|
||||
CE_CTL_LOW;
|
||||
/* txlo spi en,1=work,默认0 */
|
||||
XC_BT_RF->ana31_reg_l &= ~(1 << 5);
|
||||
XC_BT_RF->ana31_reg_l &= ~(1 << 4);
|
||||
memset(rf_data_t.buff, 0, recv_len);
|
||||
recv_len = 0;
|
||||
rf_wr_cmd(FLUSH_RX);
|
||||
rf_data_config(ack_buff, rf_ack_len);
|
||||
/* ACK data config */
|
||||
rf_rx_ack_payload_event(ack_buff, rf_ack_len); // 96MHz 32bytes 402us
|
||||
rf_set_rx_mode(XINCX_2_4G_CHANNEL, XINCX_2_4G_PIPE0_LEN);
|
||||
timer_stat = RF_FREE_TIMER_INTER;
|
||||
recv_crc_err += 1;
|
||||
}
|
||||
#if DEBUG_PIN
|
||||
xc_gpio_write_pin(TEST_PIN_6, GPIO_PIN_RESET);
|
||||
#endif
|
||||
|
||||
#if DEBUG_PIN
|
||||
// xc_gpio_write_pin(TEST_PIN_3, GPIO_PIN_RESET);
|
||||
#endif // DEBUG_PIN
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set rf 2.4g rx mode
|
||||
* @param uint16_t channel
|
||||
* @retval void
|
||||
*/
|
||||
__RAM_CODE void rf_set_rx_mode(uint16_t channel, uint16_t fifo_len)
|
||||
{
|
||||
CE_CTL_LOW;
|
||||
#if DEBUG_PIN
|
||||
// xc_gpio_write_pin(TEST_PIN_7, GPIO_PIN_SET);
|
||||
#endif // DEBUG_PIN
|
||||
/* 调制频偏 */
|
||||
XC_RF_2_4G->TXPROC_CFG = ((XC_RF_2_4G->TXPROC_CFG & (~0x1FF)) | RF_FREQ_RECV_DEV);
|
||||
/* Set receive length */
|
||||
set_rf_pipe_rx_payLen(fifo_len, fifo_len, fifo_len, fifo_len, fifo_len, fifo_len);
|
||||
/* Set recv mode */
|
||||
set_rf_mode(RX_MODE);
|
||||
/* Set the receiving frequency */
|
||||
set_rf_channel(channel);
|
||||
/* AFC manual configuration */
|
||||
set_rf_afc();
|
||||
|
||||
rf_wr_cmd(FLUSH_RX);
|
||||
XC_RF_2_4G->STATUS |= MASK_RX_DR;
|
||||
#if DEBUG_PIN
|
||||
// xc_gpio_write_pin(TEST_PIN_7, GPIO_PIN_RESET);
|
||||
#endif
|
||||
CE_CTL_HIGH;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief rf 2.4g enhanced pack data loading fifo
|
||||
* @param uint8_t *buff
|
||||
* @param uint8_t len
|
||||
* @retval void
|
||||
*/
|
||||
__RAM_CODE void rf_recv_sf_ack_payload(uint8_t *buff, uint8_t len)
|
||||
{
|
||||
rf_wr_cmd(FLUSH_TX);
|
||||
XC_RF_2_4G->STATUS = MASK_TX_DS | MASK_MAX_RT;
|
||||
rf_wr_cmd(W_TX_PLOAD);
|
||||
#if (1 == XINCX_2_4G_CRC_BYTE)
|
||||
for (uint8_t i = 0; i < rf_ack_len + RF_RECV_EXTEN_LEN; i++)
|
||||
XC_RF_2_4G->TX_FIFO_DATA = ack_buff[i];
|
||||
#elif (2 == XINCX_2_4G_CRC_BYTE)
|
||||
for (uint8_t i = 0; i < rf_ack_len + RF_RECV_EXTEN_LEN + 1; i++) {
|
||||
XC_RF_2_4G->TX_FIFO_DATA = ack_buff[i];
|
||||
}
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief rf 2.4g enhanced pack data loading fifo
|
||||
* @param uint8_t *buff
|
||||
* @param uint8_t len
|
||||
* @retval void
|
||||
*/
|
||||
__RAM_CODE uint8_t rf_recv_enhanced_data(uint8_t *buff)
|
||||
{
|
||||
|
||||
#if (XINCX_RF_TRANS_RATE == RATE_250K)
|
||||
delay_us(60);
|
||||
#endif
|
||||
rf_wr_cmd(R_RX_PLOAD);
|
||||
delay_us(BIT_TIMER * 3); // 接收第1字节
|
||||
rf_data_t.buff[0] = XC_RF_2_4G->RX_FIFO_DATA;
|
||||
/* 获取动态包长度 */
|
||||
#if (COMPATILBE_MODE == PANCHIP_PACKET)
|
||||
panchip_contorl_whiten = whiten_data(&rf_data_t.buff[0], 1, panchip_addr_whiten);
|
||||
recv_len = rf_data_t.buff[0] >> 1;
|
||||
#else
|
||||
recv_len = rf_data_t.buff[0] >> 2;
|
||||
#endif
|
||||
if (recv_len > RF_RECV_AMX_LEN) {
|
||||
recv_len = RF_RECV_AMX_LEN;
|
||||
XC_RF_2_4G->RX_PW_Px_L =
|
||||
(recv_len + RF_RECV_EXTEN_LEN + EXTEND_LEN) | ((recv_len + RF_RECV_EXTEN_LEN + EXTEND_LEN) << 8);
|
||||
}
|
||||
|
||||
if (!recv_len) {
|
||||
CE_CTL_LOW;
|
||||
rf_wr_cmd(FLUSH_RX);
|
||||
rf_data_config(ack_buff, rf_ack_len);
|
||||
/* ACK data config */
|
||||
rf_rx_ack_payload_event(ack_buff, rf_ack_len); // 96MHz 32bytes 402us
|
||||
CE_CTL_HIGH;
|
||||
return 0;
|
||||
}
|
||||
XC_RF_2_4G->RX_PW_Px_L =
|
||||
(recv_len + RF_RECV_EXTEN_LEN + EXTEND_LEN) | ((recv_len + RF_RECV_EXTEN_LEN + EXTEND_LEN) << 8);
|
||||
/* timer 定时退出接收 */
|
||||
#if (COMPATILBE_MODE == PANCHIP_PACKET)
|
||||
xc_timer_set_value(RF_RX_TIMERx, (recv_len + 1 + RF_RECV_EXTEN_LEN) * BIT_TIMER + ACK_DELAY);
|
||||
xc_timer_start(RF_RX_TIMERx);
|
||||
#else
|
||||
xc_timer_set_value(RF_RX_TIMERx, (recv_len + 2) * BIT_TIMER + ACK_DELAY);
|
||||
xc_timer_start(RF_RX_TIMERx);
|
||||
#endif
|
||||
timer_stat = RF_RECV_TIMER_INTER;
|
||||
|
||||
#if DEBUG_PIN
|
||||
xc_gpio_write_pin(TEST_PIN_2, GPIO_PIN_SET);
|
||||
#endif // DEBUG_PIN
|
||||
return recv_len;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Receive data processing and start replying ACK
|
||||
* @param void
|
||||
* @retval void
|
||||
*/
|
||||
__RAM_CODE void rf_pwm_recv_data(void)
|
||||
{
|
||||
NVIC_DisableIRQ(RF24G_IRQn); //
|
||||
xc_timer_stop(RF_RX_TIMERx);
|
||||
rf_prx_ack_flag = false;
|
||||
#if DEBUG_PIN
|
||||
xc_gpio_write_pin(TEST_PIN_1, GPIO_PIN_SET);
|
||||
#endif // DEBUG_PIN
|
||||
|
||||
rf_recv_enhanced_data(rf_data_t.buff);
|
||||
|
||||
#if DEBUG_PIN
|
||||
xc_gpio_write_pin(TEST_PIN_1, GPIO_PIN_RESET);
|
||||
#endif // DEBUG_PIN
|
||||
}
|
||||
|
||||
#if (XINCX_RF_COMPATIBILITY_MODE == PANCHIP_PACKET)
|
||||
void rf_24g_callback(void *context)
|
||||
{
|
||||
uint16_t rf_stat = XC_RF_2_4G->STATUS;
|
||||
#ifdef XC62XX
|
||||
if (rf_stat & MASK_RX_SYNC) {
|
||||
// XC_RF_2_4G->STATUS |= MASK_RX_SYNC;
|
||||
// printf("-----------------------------1\n");
|
||||
XC_RF_2_4G->STATUS |= MASK_RX_SYNC;
|
||||
rf_pwm_recv_data();
|
||||
}
|
||||
|
||||
if (rf_stat & MASK_PBT_CRC_FAIL) {
|
||||
XC_RF_2_4G->STATUS |= MASK_PBT_CRC_FAIL;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
// /* Reception is interrupted when it completes */
|
||||
// if (rf_stat & MASK_RX_DR) {
|
||||
// rf24g_rx_irq_flag = true;
|
||||
|
||||
// CE_CTL_LOW;
|
||||
// #if (1 == XINCX_RF_ADV_NVIC_MODE)
|
||||
// recv_len = rf_rx_event(recv_adv_buf);
|
||||
// #endif // XINCX_RF_ADV_NVIC_MODE
|
||||
|
||||
// #if (1 == XINCX_RF_NVIC_MODE)
|
||||
// recv_len = rf_rx_event(recv_buf);
|
||||
// #endif // XINCX_RF_NVIC_MODE
|
||||
// XC_RF_2_4G->STATUS |= MASK_RX_DR;
|
||||
// #ifdef XC62XX
|
||||
// XC_RF_2_4G->STATUS |= MASK_RX_SYNC;
|
||||
// #endif
|
||||
// }
|
||||
|
||||
/* The sending is interrupted when it completes */
|
||||
if (rf_stat & MASK_TX_DS) {
|
||||
rf24g_tx_irq_flag = true;
|
||||
tx_stat = TX_DATA_OK;
|
||||
XC_RF_2_4G->STATUS |= MASK_TX_DS;
|
||||
}
|
||||
|
||||
/* The launch timeout is interrupted */
|
||||
if (rf_stat & MASK_MAX_RT) {
|
||||
rf24g_tx_irq_flag = true;
|
||||
tx_stat = TX_RETRANS_MAX;
|
||||
XC_RF_2_4G->STATUS |= MASK_MAX_RT;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
/**
|
||||
* @brief PWM 0 Capture the callback function
|
||||
* @param void *context
|
||||
* @retval uint8_t 0
|
||||
*/
|
||||
__RAM_CODE uint8_t pwm_capture_ch0_callback(void *context)
|
||||
{
|
||||
rf_pwm_recv_data();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PWM 1 Capture the callback function
|
||||
* @param void *context
|
||||
* @retval uint8_t 0
|
||||
*/
|
||||
__RAM_CODE uint8_t pwm_capture_ch1_callback(void *context)
|
||||
{
|
||||
rf_pwm_recv_data();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PWM 2 Capture the callback function
|
||||
* @param void *context
|
||||
* @retval uint8_t 0
|
||||
*/
|
||||
__RAM_CODE uint8_t pwm_capture_ch2_callback(void *context)
|
||||
{
|
||||
rf_pwm_recv_data();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Address whitening and writing
|
||||
* @param void
|
||||
* @retval uint8_t whiten_addr
|
||||
*/
|
||||
uint8_t rf_recv_addr(void)
|
||||
{
|
||||
uint16_t whiten_addr = whiten_data((uint8_t *)addr_buff, RF_ADDR_LEN, PANCHIP_WHITEN_INIT_VAL);
|
||||
/* Set PTX address */
|
||||
set_rf_txaddr((addr_buff[0] << 0) | (addr_buff[1] << 8) | (addr_buff[2] << 16) | (addr_buff[3] << 24),
|
||||
(addr_buff[4]));
|
||||
/* Set PRX address */
|
||||
set_rf_pipe0_rxaddr((addr_buff[0] << 0) | (addr_buff[1] << 8) | (addr_buff[2] << 16) | (addr_buff[3] << 24),
|
||||
(addr_buff[4]));
|
||||
return whiten_addr;
|
||||
}
|
||||
|
||||
void rf_set_agc_map(uint8_t agc_gain_1th, uint8_t agc_setp)
|
||||
{
|
||||
uint8_t agc_map[5] = {0};
|
||||
for (uint8_t i = 0; i < sizeof(agc_map); i++) {
|
||||
agc_map[i] = agc_gain_1th - i * agc_setp;
|
||||
}
|
||||
|
||||
XC_RF_2_4G->PGA_SETTING = agc_map[0] | (agc_map[1] << 8) | (agc_map[2] << 16) | (agc_map[3] << 24);
|
||||
XC_RF_2_4G->TX_ADDR_H &= ~(0xFF << 8);
|
||||
XC_RF_2_4G->TX_ADDR_H |= (agc_map[4] << 8);
|
||||
}
|
||||
@@ -0,0 +1,425 @@
|
||||
/*!
|
||||
* \file main.c
|
||||
*
|
||||
* \brief Target main implementation
|
||||
*
|
||||
* \copyright Revised BSD License, see section \ref LICENSE.
|
||||
*
|
||||
* \code
|
||||
*
|
||||
* _ __ _ ________ _
|
||||
* | |/ /(_)___ / ____/ /_ (_)___
|
||||
* | // / __ \/ / / __ \/ / __ \
|
||||
* / |/ / / / / /___/ / / / / /_/ /
|
||||
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
|
||||
* /_/
|
||||
* (C) 2022-2025 XinChip
|
||||
*
|
||||
* \endcode
|
||||
*
|
||||
* \author ( XinChip ) Alex-J
|
||||
*
|
||||
* \author ( XinChip )
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------------------------------
|
||||
INCLUDE HEADE FILES
|
||||
------------------------------------------------------------------------------------*/
|
||||
#include "main.h"
|
||||
#include "xc6xxx_rf_2_4g.h"
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Macros
|
||||
-------------------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Global Variables
|
||||
-------------------------------------------------------------------------------------*/
|
||||
volatile bool rf24g_rx_irq_flag = false;
|
||||
volatile bool rf24g_tx_irq_flag = false;
|
||||
volatile bool rf24g_rx_to_irq_flag = false;
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Func Prototype
|
||||
-------------------------------------------------------------------------------------*/
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Functions
|
||||
-------------------------------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
****************************************************************************************
|
||||
* @brief Clock Initialization
|
||||
*
|
||||
* @param[in]
|
||||
* @param[in]
|
||||
****************************************************************************************
|
||||
*/
|
||||
void clock_init(void)
|
||||
{
|
||||
CLOCK_InitCfg_t clock_cfg;
|
||||
|
||||
clock_cfg.hfclk_src = CLOCK_HFCLK_SRC_XTAL;
|
||||
clock_cfg.hfclk_in = CLOCK_HFCLK_IN_32M;
|
||||
#if (RC_32K)
|
||||
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_RC;
|
||||
#endif //(RC_32K)
|
||||
|
||||
#if (XTAL_32K)
|
||||
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL;
|
||||
#endif // (XTAL_32K)
|
||||
|
||||
#if (XTAL_32768K)
|
||||
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL;
|
||||
#endif // (XTAL_32768K)
|
||||
#ifdef XC62XX
|
||||
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_RC;
|
||||
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32K;
|
||||
#else
|
||||
if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_XTAL) {
|
||||
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32768;
|
||||
} else if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_RC) {
|
||||
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32K;
|
||||
}
|
||||
#endif
|
||||
xc_clock_init_cfg(&clock_cfg);
|
||||
|
||||
SysTick_Config(xc_clock_hfclk_in_get() / 100);
|
||||
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Rf 2.4g dump log
|
||||
* @param void
|
||||
*
|
||||
* @retval void
|
||||
*/
|
||||
#ifdef DEBUG_LOG
|
||||
void rf_dump_log(void)
|
||||
{
|
||||
LOGI("***************** 2.4G Param ******************\n");
|
||||
LOGI("CFG_TOP: 0x%08x\r\n", XC_RF_2_4G->CFG_TOP);
|
||||
LOGI("EN_AA: 0x%08x\r\n", XC_RF_2_4G->EN_AA);
|
||||
LOGI("EN_RXADDR: 0x%08x\r\n", XC_RF_2_4G->EN_RXADDR);
|
||||
LOGI("SETUP_AW: 0x%08x\r\n", XC_RF_2_4G->SETUP_AW);
|
||||
LOGI("SETUP_RETR: 0x%08x\r\n", XC_RF_2_4G->SETUP_RETR);
|
||||
LOGI("RF_CH: 0x%08x\r\n", XC_RF_2_4G->RF_CH);
|
||||
LOGI("SETUP_RF: 0x%08x\r\n", XC_RF_2_4G->SETUP_RF);
|
||||
LOGI("STATUS: 0x%08x\r\n", XC_RF_2_4G->STATUS);
|
||||
LOGI("OBSERVE_TX: 0x%08x\r\n", XC_RF_2_4G->OBSERVE_TX);
|
||||
LOGI("RSSI: 0x%08x\r\n", XC_RF_2_4G->RSSI);
|
||||
LOGI("RX_ADDR_P0: 0x%02x%08x\r\n", 0xFF & (XC_RF_2_4G->RX_ADDR_P0_H), XC_RF_2_4G->RX_ADDR_P0_L);
|
||||
LOGI("RX_ADDR_P1: 0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RX_ADDR_P1_H), XC_RF_2_4G->RX_ADDR_P1_L);
|
||||
LOGI("RX_ADDR_P2TOP5:0x%08x\r\n", XC_RF_2_4G->RX_ADDR_P2TOP5);
|
||||
LOGI("BER_RESULT: 0x%08x%08x\r\n", XC_RF_2_4G->BER_ERR_CNT, XC_RF_2_4G->BER_RECV_CNT);
|
||||
LOGI("AGC_SETTING: 0x%08x\r\n", XC_RF_2_4G->AGC_SETTING);
|
||||
LOGI("PGA_SETTING: 0x%02x%08x\r\n", ((XC_RF_2_4G->TX_ADDR_H) & 0xFF00) >> 8, XC_RF_2_4G->PGA_SETTING);
|
||||
LOGI("TX_ADDR: 0x%02x%08x\r\n", ((XC_RF_2_4G->TX_ADDR_H) & 0xFF), XC_RF_2_4G->TX_ADDR_L);
|
||||
LOGI("RX_PW_PX: 0x%04x %08x\r\n", 0xFFFF & (XC_RF_2_4G->RX_PW_Px_H), XC_RF_2_4G->RX_PW_Px_L);
|
||||
LOGI("STATUS_FIFO: 0x%08x\r\n", XC_RF_2_4G->STATUS_FIFO);
|
||||
LOGI("RSSIREC: 0x%08x\r\n", XC_RF_2_4G->RSSIREC);
|
||||
LOGI("TXPROC_CFG: 0x%08x\r\n", XC_RF_2_4G->TXPROC_CFG);
|
||||
LOGI("RXPROC_CFG: 0x%02x%08x\r\n", 0xFF & (XC_RF_2_4G->RXPROC_CFG_H), XC_RF_2_4G->RXPROC_CFG_L);
|
||||
LOGI("DYNPD: 0x%08x\r\n", XC_RF_2_4G->DYNPD);
|
||||
LOGI("FEATURE: 0x%08x\r\n", XC_RF_2_4G->FEATURE);
|
||||
LOGI("PGA_SETTING_H: 0x%08x\r\n", XC_RF_2_4G->TX_ADDR_H);
|
||||
#ifdef XC62XX
|
||||
LOGI("HW_CONFIG: 0x%08x\r\n", XC_RF_2_4G->HW_CONFIG);
|
||||
LOGI("PBT_CONFIG: 0x%08x\r\n", XC_RF_2_4G->PBT_CONFIG);
|
||||
LOGI("PBT_TIMER: 0x%08x\r\n", XC_RF_2_4G->PBT_TIMER);
|
||||
LOGI("PBT_SYNC_TIME: 0x%08x\r\n", XC_RF_2_4G->PBT_SYNC_TIME);
|
||||
LOGI("PBT_TX_HEAD: 0x%08x\r\n", XC_RF_2_4G->PBT_TX_HEAD);
|
||||
LOGI("PBT_RX_HEAD: 0x%08x\r\n", XC_RF_2_4G->PBT_RX_HEAD);
|
||||
LOGI("PBT_AUTO_TRX_TIME: 0x%08x\r\n", XC_RF_2_4G->PBT_AUTO_TRX_TIME);
|
||||
#endif
|
||||
LOGI("TX_POWER 0x%08x\r\n", (XC_BT_RF->ana21_reg_l >> 6) & 0x3f);
|
||||
LOGI("ana11_reg_l: 0x%08x\r\n", XC_BT_RF->ana11_reg_l);
|
||||
LOGI("***********************************************\n");
|
||||
LOGI("\r\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief RF 2.4g buff info
|
||||
* @param uint8_t * - buff
|
||||
* uint8_t len
|
||||
* @retval void
|
||||
*/
|
||||
void rf_buff_info(uint8_t *buff, uint8_t len)
|
||||
{
|
||||
for (uint8_t i = 0; i < len; i++)
|
||||
LOGI("%02x ", buff[i]);
|
||||
LOGI("\r\n");
|
||||
}
|
||||
|
||||
void app_uart_init(void)
|
||||
{
|
||||
GPIO_InitCfg_t gpio_cfg = {0};
|
||||
|
||||
gpio_cfg.Mux = GPIO_Mux0;
|
||||
gpio_cfg.Pull = GPIO_PULLUP;
|
||||
gpio_cfg.Int = NOT_INT;
|
||||
gpio_cfg.FunSel = UART0_TX;
|
||||
|
||||
gpio_cfg.Pin = GPIO_18;
|
||||
gpio_cfg.Dir = GPIO_DIR_OUTPUT;
|
||||
xc_gpio_init(&gpio_cfg);
|
||||
|
||||
gpio_cfg.FunSel = UART0_RX;
|
||||
gpio_cfg.Pin = GPIO_19;
|
||||
gpio_cfg.Dir = GPIO_DIR_INPUT;
|
||||
xc_gpio_init(&gpio_cfg);
|
||||
|
||||
UART_InitCfg_t uart_cfg = {0};
|
||||
|
||||
uart_cfg.Parity = UART_PARITY_DISABLE;
|
||||
uart_cfg.StopBits = UART_STOP_1_BITS;
|
||||
uart_cfg.WordLength = UART_DATA_8_BITS;
|
||||
uart_cfg.BaudRate = UART_BAUDRATE_115200;
|
||||
uart_cfg.HardwareFlowControl = UART_HWFC_DISABLE;
|
||||
|
||||
xc_uart_init(UART0_IDX, &uart_cfg);
|
||||
}
|
||||
|
||||
|
||||
/* switch mode and set channel */
|
||||
void rf_switch_mode(uint8_t mode, uint16_t channel)
|
||||
{
|
||||
CE_CTL_LOW;
|
||||
|
||||
switch (mode) {
|
||||
case TX_MODE:
|
||||
case RX_MODE:
|
||||
break;
|
||||
|
||||
default:
|
||||
LOGI("The mode is set incorrectly\n");
|
||||
while(1);
|
||||
}
|
||||
|
||||
set_rf_mode(mode);
|
||||
rf_set_channel(channel);
|
||||
|
||||
#ifdef XC62XX
|
||||
XC_RF_2_4G->STATUS = ((XC_RF_2_4G->CFG_TOP >> 30) & 0x3 << 7) | ((XC_RF_2_4G->CFG_TOP >> 4) & 0x7 << 4);
|
||||
#else
|
||||
XC_RF_2_4G->STATUS = MASK_ALL_INTER;
|
||||
#endif
|
||||
|
||||
|
||||
rf_wr_cmd(FLUSH_RX);
|
||||
rf_wr_cmd(FLUSH_TX);
|
||||
|
||||
if (mode) {
|
||||
CE_CTL_HIGH;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* RF接收完成回调 */
|
||||
void rf_24g_rx_dr_cb(void)
|
||||
{
|
||||
/* set flag */
|
||||
rf24g_rx_irq_flag = true;
|
||||
}
|
||||
|
||||
|
||||
/* RF发送完成回调 */
|
||||
void rf_24g_tx_ds_cb(void)
|
||||
{
|
||||
rf24g_tx_irq_flag = true;
|
||||
}
|
||||
|
||||
|
||||
/* RF接收超时回调 */
|
||||
void rf_24g_max_rt_cb(void)
|
||||
{
|
||||
rf24g_rx_to_irq_flag = true;
|
||||
}
|
||||
|
||||
/* RF 发送数据（自动应答） */
|
||||
__RAM_CODE eRF_Tx_Status rf_tx_autoack(uint8_t *buff, uint16_t len)
|
||||
{
|
||||
eRF_Tx_Status ret = TX_DATA_INVALID;
|
||||
|
||||
/* len can't be 0 */
|
||||
if (len == 0)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* rf_off_and_on */
|
||||
rf_off_and_on();
|
||||
|
||||
rf24g_tx_irq_flag = false;
|
||||
rf24g_rx_to_irq_flag = false;
|
||||
|
||||
/* send data */
|
||||
rf_tx_packet(buff, len);
|
||||
|
||||
/* wait for ack */
|
||||
while(1)
|
||||
{
|
||||
/* recv ack */
|
||||
if(rf24g_tx_irq_flag)
|
||||
{
|
||||
ret = TX_DATA_OK;
|
||||
break;
|
||||
}
|
||||
/* time out */
|
||||
else if(rf24g_rx_to_irq_flag)
|
||||
{
|
||||
ret = TX_RETRANS_MAX;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
__RAM_CODE void rf24g_AckPayload_tx_demo(void)
|
||||
{
|
||||
uint8_t ack_status = TX_DATA_INVALID;
|
||||
uint8_t ack_buff[BUFF_LEN] = {0};
|
||||
uint8_t tx_buff[BUFF_LEN] = {0};
|
||||
uint8_t ack_len = 0;
|
||||
uint32_t ack_cnt = 0;
|
||||
uint32_t tx_cnt = 0;
|
||||
|
||||
/* Set testing frequency points */
|
||||
rf_switch_mode( TX_MODE, XINCX_2_4G_CHANNEL);
|
||||
|
||||
/* fill data */
|
||||
for (uint8_t i = 0; i < BUFF_LEN; i++)
|
||||
{
|
||||
tx_buff[i] = i;
|
||||
}
|
||||
|
||||
LOGI( "AutoAck Tx Demo start!\r\n");
|
||||
|
||||
/* main loop */
|
||||
while(true)
|
||||
{
|
||||
/* data transmission */
|
||||
tx_cnt ++;
|
||||
LOGI( "\r\ntx_cnt = %d\r\n",tx_cnt);
|
||||
ack_status = rf_tx_autoack(tx_buff, BUFF_LEN);
|
||||
|
||||
/* recv ack */
|
||||
if(ack_status == TX_DATA_OK)
|
||||
{
|
||||
ack_cnt += 1;
|
||||
|
||||
/* read ack payload */
|
||||
ack_len = rf_read_ack_packet(ack_buff);
|
||||
|
||||
LOGI( "ack_cnt:%d,len=%d\r\n", ack_cnt, ack_len);
|
||||
if(ack_len)
|
||||
{
|
||||
/* print ack data */
|
||||
rf_buff_info( ack_buff, ack_len);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
LOGI( "No ack,ack_cnt=%d\r\n",ack_cnt);
|
||||
}
|
||||
|
||||
delay_ms(10);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
__RAM_CODE void rf24g_AckPayload_rx_demo(void)
|
||||
{
|
||||
uint8_t ack_buff[BUFF_LEN] = {0};
|
||||
uint8_t rx_buff[BUFF_LEN] = {0};
|
||||
uint8_t rx_len;
|
||||
uint32_t rx_cnt = 0;
|
||||
|
||||
/* fill data */
|
||||
for (uint8_t i = 0; i < BUFF_LEN; i++)
|
||||
{
|
||||
ack_buff[i] = BUFF_LEN - i;
|
||||
}
|
||||
|
||||
/* Fill ack pyaload of next packet */
|
||||
rf_fill_ack_packet(ack_buff, BUFF_LEN);
|
||||
|
||||
/* Set the communication mode */
|
||||
rf_switch_mode( RX_MODE, XINCX_2_4G_CHANNEL);
|
||||
|
||||
LOGI( "AutoAck Rx Demo start!\r\n");
|
||||
|
||||
while(true)
|
||||
{
|
||||
if (rf24g_rx_irq_flag)
|
||||
{
|
||||
rf24g_rx_irq_flag = false;
|
||||
|
||||
/* Entering standby mode */
|
||||
CE_CTL_LOW;
|
||||
|
||||
/* Read rf data */
|
||||
rx_len = rf_rx_packet(rx_buff);
|
||||
|
||||
/* Receive Count */
|
||||
rx_cnt += 1;
|
||||
LOGI("recv:%d\r\n", rx_cnt);
|
||||
|
||||
/* Print the received data. */
|
||||
//rf_buff_info(rx_buff, rx_len);
|
||||
|
||||
delay_us(200);
|
||||
|
||||
/* rf_off_and_on */
|
||||
rf_off_and_on();
|
||||
|
||||
/* Fill ack pyaload of next packet */
|
||||
rf_fill_ack_packet(ack_buff, BUFF_LEN);
|
||||
|
||||
/* Start recv */
|
||||
CE_CTL_HIGH;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int main(void)
|
||||
{
|
||||
/* Clock initialization */
|
||||
clock_init();
|
||||
|
||||
/* Serial port initialization */
|
||||
app_uart_init();
|
||||
|
||||
/* rf 2.4g initialization configuration */
|
||||
rf24g_init();
|
||||
|
||||
#if (XINCX_RF_TRANS_RATE == DR_250K)
|
||||
rf_ack_payload_config();
|
||||
#elif (XINCX_RF_TRANS_RATE == DR_2M)
|
||||
/* Set 2M mode register configuration */
|
||||
/* Don't move this function interface */
|
||||
rf_2M_config();
|
||||
#endif
|
||||
|
||||
#if (XINCX_RF_NVIC_MODE)
|
||||
/* Enable RF2.4G interrupts */
|
||||
NVIC_EnableIRQ(RF24G_IRQn);
|
||||
/* Configure the RF2.4G interrupt priority */
|
||||
NVIC_SetPriority(RF24G_IRQn, 0);
|
||||
#endif // XINCX_RF_NVIC_MODE
|
||||
|
||||
xc_system_param_check_rf24g();
|
||||
|
||||
|
||||
#if XINCX_RF_MODE == TX_MODE
|
||||
rf24g_AckPayload_tx_demo();
|
||||
#elif XINCX_RF_MODE == RX_MODE
|
||||
rf24g_AckPayload_rx_demo();
|
||||
#endif
|
||||
|
||||
while(true);
|
||||
}
|
||||
Reference in New Issue
Block a user