xc_drv_fmc_spi_dma.c

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/*-----------------------------------------------------------------------------------
                                       INCLUDE HEADE FILES
 ------------------------------------------------------------------------------------*/
#include "xc_drv_fmc_spi_dma.h"
 
/*------------------------------------------------------------------------------------
                                         Local Variables
 -------------------------------------------------------------------------------------*/
 
static volatile bool wr_tfr_flag;
static volatile bool rd_tfr_flag;
static volatile bool err_flag;
 
/*------------------------------------------------------------------------------------
                                         Func Prototype
 -------------------------------------------------------------------------------------*/
__RAM_CODE uint8_t xc_fmc_spi_dma_flash_read_status(void);
 
/*------------------------------------------------------------------------------------
                                            Functions
 -------------------------------------------------------------------------------------*/
static __RAM_CODE void *ram_memcpy_byte(void *dst, const void *src, int size)
{
    if (dst == NULL || src == NULL || size <= 0)
        return NULL;
 
    char *pdst = (char *)dst;
    char *psrc = (char *)src;
 
    if (pdst > psrc && pdst < psrc + size) {
        pdst = pdst + size - 1;
        psrc = psrc + size - 1;
        while (size--)
            *pdst-- = *psrc--;
    } else {
        while (size--)
            *pdst++ = *psrc++;
    }
 
    return dst;
}
 
__RAM_CODE void xc_fmc_status_wait_idle(void)
{
    uint32_t reg = 0;
    do {
        __READ_REG32(BLE_COMN_AGC_REG_OUT0, reg);
    } while (!(reg & FMC_IDLE_STATUS));
}
 
__RAM_CODE void fmc_dma_write_callback(uint8_t eCode)
{
    wr_tfr_flag = true;
}
 
__RAM_CODE void fmc_dma_read_callback(uint8_t eCode)
{
    rd_tfr_flag = true;
}
 
__RAM_CODE void fmc_dma_write_err(uint8_t eCode)
{
    // -------
    // This function is called by the IRQ handler.
    // We use this function to deal with interrupts that the DMA
    // driver is unable to cater for (these are application
    // specific). All of the interrupts handled by this function
    // are cleared by the DMA driver, so there's no need to clear here.
    // -------
 
    // Check the source of the interrupt
 
    if (eCode == DMA_IRQ_ERR) {
 
        // Just inform the application that this interrupt has occured.
        err_flag = true;
    }
}
 
__RAM_CODE void fmc_dma_read_err(uint8_t eCode)
{
    // -------
    // This function is called by the IRQ handler.
    // We use this function to deal with interrupts that the DMA
    // driver is unable to cater for (these are application
    // specific). All of the interrupts handled by this function
    // are cleared by the DMA driver, so there's no need to clear here.
    // -------
 
    // Check the source of the interrupt
 
    if (eCode == DMA_IRQ_ERR) {
 
        // Just inform the application that this interrupt has occured.
        err_flag = true;
    }
}
 
__RAM_CODE void xc_fmc_dma_mem2prf_finish(void)
{
    while (wr_tfr_flag == false) {
#if (DMAC_NVIC_ENABLE == 0)
        dma_irq_handler(&DMA_Instance);
#endif
        if (err_flag == true) {
            // Wasn't expecting this !!
            DEBUG("\nERROR: Recieved an err interrupt\n");
            err_flag = false;
        }
    }
    wr_tfr_flag = false;
}
 
__RAM_CODE void xc_fmc_dma_prf2mem_finish(void)
{
    while (rd_tfr_flag == false) {
#if (DMAC_NVIC_ENABLE == 0)
        dma_irq_handler(&DMA_Instance);
#endif
        if (err_flag == true) {
            // Wasn't expecting this !!
            DEBUG("\nERROR: Recieved an err interrupt\n");
            err_flag = false;
        }
    }
    rd_tfr_flag = false;
}
 
__RAM_CODE uint8_t xc_fmc_spi_dma_read_config(eDMA_Ch_Num ch_num, uint16_t blockSize, uint8_t *rx_buff)
{
    DMA_Chx_Cfg_t ch_cfg;
    uint8_t errorCode       = DMA_OK;
    uint32_t fmc_prf_addr   = XC_REG_FMC_BASE_ADDR + FMC_DATA_OFFSET;
 
    ch_cfg.sar              = (uint32_t)fmc_prf_addr;
    ch_cfg.dar              = (uint32_t)rx_buff;
 
    ch_cfg.ctl_src_msize    = DMA_MSIZE_1;
    ch_cfg.ctl_dst_msize    = DMA_MSIZE_1;
 
    ch_cfg.ctl_sinc         = DMA_ADDR_NOCHANGE;
    ch_cfg.ctl_dinc         = DMA_ADDR_INCREMENT;
 
    ch_cfg.ctl_src_tr_width = DMA_TRANS_WIDTH_8;
    ch_cfg.ctl_dst_tr_width = DMA_TRANS_WIDTH_8;
 
    ch_cfg.ctl_tt_fc        = DMA_PRF2MEM_DMA;
 
    ch_cfg.ctl_block_ts     = blockSize;
 
    ch_cfg.cfg_hs_sel_src   = DMA_HS_HARDWARE;
    ch_cfg.cfg_hs_sel_dst   = DMA_HS_HARDWARE;
 
    ch_cfg.cfg_fifo_mode    = DMA_FIFO_MODE_SINGLE;
 
    ch_cfg.cfg_src_per      = SSI0_DMA_RX_HS_IF10;
 
    ch_cfg.cfg_ch_prior     = DMA_PRIORITY_1;
    // Now we can intialise the channel configuration structure for
    // DMA channel 0 by loading the structure members with the
    // contents of the DMAC's channel 0 registers.
    errorCode               = xc_dma_set_channel_config(ch_num, &ch_cfg);
    if (errorCode != 0) {
        DEBUG("\nERROR: Failed to initialise configuration\n");
    }
 
    xc_dma_set_listener(ch_num, fmc_dma_read_err);
 
    return errorCode;
}
 
__RAM_CODE uint8_t xc_fmc_spi_dma_write_config(eDMA_Ch_Num ch_num, uint16_t blockSize, uint8_t *tx_buff)
{
    DMA_Chx_Cfg_t ch_cfg;
    uint8_t errorCode       = DMA_OK;
    uint32_t fmc_prf_addr   = XC_REG_FMC_BASE_ADDR + FMC_DATA_OFFSET;
    
    ch_cfg.sar              = (uint32_t)tx_buff;
    ch_cfg.dar              = (uint32_t)fmc_prf_addr;
 
    ch_cfg.ctl_src_msize    = DMA_MSIZE_1;
    ch_cfg.ctl_dst_msize    = DMA_MSIZE_1;
 
    ch_cfg.ctl_sinc         = DMA_ADDR_INCREMENT;
    ch_cfg.ctl_dinc         = DMA_ADDR_NOCHANGE;
 
    ch_cfg.ctl_src_tr_width = DMA_TRANS_WIDTH_8;
    ch_cfg.ctl_dst_tr_width = DMA_TRANS_WIDTH_8;
 
    ch_cfg.ctl_tt_fc        = DMA_MEM2PRF_DMA;
 
    ch_cfg.ctl_block_ts     = blockSize;
 
    ch_cfg.cfg_hs_sel_src   = DMA_HS_HARDWARE;
    ch_cfg.cfg_hs_sel_dst   = DMA_HS_HARDWARE;
 
    ch_cfg.cfg_fifo_mode    = DMA_FIFO_MODE_SINGLE;
 
    ch_cfg.cfg_dst_per      = SSI0_DMA_TX_HS_IF2;
 
    ch_cfg.cfg_ch_prior     = DMA_PRIORITY_0;
    // Now we can intialise the channel configuration structure for
    // DMA channel 0 by loading the structure members with the
    // contents of the DMAC's channel 0 registers.
    errorCode               = xc_dma_set_channel_config(ch_num, &ch_cfg);
    if (errorCode != 0) {
        DEBUG("\nERROR: Failed to initialise configuration\n");
    }
 
    xc_dma_set_listener(ch_num, fmc_dma_write_err);
 
    return errorCode;
}
 
__RAM_CODE void xc_fmc_spi_dma_write_and_read(eDMA_Ch_Num w_chnum, uint16_t w_size, uint8_t *w_buff,
                                              eDMA_Ch_Num r_chnum, uint16_t r_size, uint8_t *r_buff)
{
    uint8_t errorCode;
 
    xc_dma_init( );
 
    errorCode = xc_fmc_spi_dma_read_config(r_chnum, r_size, r_buff);
    if (errorCode != 0) {
        DEBUG("\nERROR: Failed SPI_DMAC_Recv_Cfg\n");
    }
    errorCode = xc_fmc_spi_dma_write_config(w_chnum, w_size + 1, w_buff); 
    if (errorCode != 0) {
        DEBUG("\nERROR: Failed SPI_DMAC_Send_Cfg\n");
    }
 
    xc_dma_enable( );
 
    errorCode = xc_dma_start_transfer(r_chnum,fmc_dma_read_callback);
    if (errorCode != 0) {
        DEBUG("\nERROR: Failed DMAC_StartTransfer read\n");
    }
 
    errorCode = xc_dma_start_transfer(w_chnum, fmc_dma_write_callback);
    if (errorCode != 0) {
        DEBUG("\nERROR: Failed DMAC_StartTransfer write\n");
    }
 
    xc_fmc_dma_mem2prf_finish( );
    xc_fmc_dma_prf2mem_finish( );
 
    xc_dma_disable( );
}
 
void xc_fmc_spi_dma_read_and_write(eDMA_Ch_Num w_chnum, uint16_t w_size, uint8_t *w_buff,
                                   eDMA_Ch_Num r_chnum, uint16_t r_size, uint8_t *r_buff)
{
    uint8_t errorCode;
    
    xc_dma_init( );
    
    errorCode = xc_fmc_spi_dma_read_config(r_chnum, r_size, r_buff);
    if(errorCode != 0) {
        DEBUG("\nERROR: Failed SPI_DMAC_Recv_Cfg\n");
    }
    errorCode = xc_fmc_spi_dma_write_config(w_chnum, w_size+1, w_buff);  
    if(errorCode != 0) {
        DEBUG("\nERROR: Failed SPI_DMAC_Send_Cfg\n");
    }
 
    xc_dma_enable( );
 
    errorCode = xc_dma_start_transfer(r_chnum, fmc_dma_read_callback);
    if(errorCode != 0) {
        DEBUG("\nERROR: Failed DMAC_StartTransfer read\n");
    }
 
    errorCode = xc_dma_start_transfer(w_chnum, fmc_dma_write_callback);
    if(errorCode != 0) {
        DEBUG("\nERROR: Failed DMAC_StartTransfer write\n");
    }
 
    xc_fmc_dma_prf2mem_finish( );
    xc_fmc_dma_mem2prf_finish( );
 
    xc_dma_disable( );
}
__RAM_CODE void xc_fmc_spi_dma_write(eDMA_Ch_Num w_chnum, uint16_t w_size, uint8_t *w_buff)
{
    uint8_t errorCode;
 
    xc_dma_init( );
 
    errorCode = xc_fmc_spi_dma_write_config(w_chnum, w_size, w_buff);
    if (errorCode != 0) {
        DEBUG("\nERROR: Failed SPI_DMAC_Send_Cfg\n");
    }
 
    xc_dma_enable( );
 
    errorCode = xc_dma_start_transfer(w_chnum, fmc_dma_write_callback);
    if (errorCode != 0) {
        DEBUG("\nERROR: Failed DMAC_StartTransfer write\n");
    }
 
    xc_fmc_dma_mem2prf_finish( );
 
    xc_dma_disable( );
}
 
__RAM_CODE void xc_fmc_spi_init(void)
{
    cpr_bt_clk_ctl__bt_clk_en__setf(ENABLE);
 
    cpr_bt_modem_clk_ctl__bt_modem_clk_en__setf(ENABLE);
 
    cpr_ctlapbclken_grctl__bt_pclk_en__setf(ENABLE);
    cpr_ssi0_mclk_ctl__ssi_mclk_en__setf(DISABLE);
    cpr_rstctl_subrst_sw__ssi0_rstn__setf(ENABLE);
    cpr_rstctl_subrst_sw__ssi0_rstn__setf(DISABLE);
 
    xc_fmc_status_wait_idle( );
 
#if (USE_XIP != 1)
    xc_gpio_mux_ctl(35, GPIO_Mux2); // clk
    xc_gpio_mux_ctl(36, GPIO_Mux2); // cs
    xc_gpio_mux_ctl(37, GPIO_Mux2); // d0
    xc_gpio_mux_ctl(38, GPIO_Mux2); // d1
    xc_gpio_mux_ctl(33, GPIO_Mux1); // d2
    xc_gpio_mux_ctl(34, GPIO_Mux1); // d3
                   
    cpr_fmc_ctl_set(0x0503);
    delay_us(200);
    cpr_fmc_ctl_set(0x3503);
    delay_us(50);
#endif
 
    fmc_en__ssic_en__setf(FMC_SSI_EN_SEN_DISABLE);
    fmc_dmac_pack(FMC_SSI_DMAC_RDMAE_DISABLE, FMC_SSI_DMAC_TDMAE_DISABLE);
    fmc_dmatdl_set(1);
    fmc_dmardl_set(1);
    fmc_ctrl0__dfs__setf(0x1f);
 
    fmc_ctrl0__sste__setf(DISABLE);
 
    fmc_se_set(ENABLE);
    fmc_ie_set(DISABLE);
    fmc_baud_set(2);
    fmc_txftl_set(0);
    fmc_rxftl_set(0);
 
    fmc_en__ssic_en__setf(FMC_SSI_EN_SEN_ENABLE);
}
 
__RAM_CODE void xc_fmc_spi_dma_init(uint8_t dfs, uint8_t tdl, uint8_t rdl)
{
    fmc_en__ssic_en__setf(FMC_SSI_EN_SEN_DISABLE);
    fmc_ctrl0__dfs__setf(dfs);
    fmc_dmatdl_set(tdl);
    fmc_dmardl_set(rdl);
    fmc_dmac_pack(FMC_SSI_DMAC_RDMAE_ENABLE, FMC_SSI_DMAC_TDMAE_ENABLE);
    fmc_en__ssic_en__setf(FMC_SSI_EN_SEN_ENABLE);
}
 
__RAM_CODE void xc_fmc_spi_dma_deinit(void)
{
    fmc_dmac_pack(FMC_SSI_DMAC_RDMAE_DISABLE, FMC_SSI_DMAC_TDMAE_DISABLE);
    fmc_en__ssic_en__setf(FMC_SSI_EN_SEN_DISABLE);
 
    fmc_ctrl0__dfs__setf(0x1f);
    fmc_en__ssic_en__setf(FMC_SSI_EN_SEN_ENABLE);
}
 
__RAM_CODE void xc_fmc_spi_dma_flash_power_down(void)
{
    xc_fmc_status_wait_idle();
 
    uint8_t cmd[1];
 
    cmd[0] = CMD_PWRDWN;
 
    xc_fmc_spi_dma_init(0x07, 1, 1);
 
    xc_fmc_spi_dma_write(DMA_CHANNEL0, sizeof(cmd), cmd);
 
    xc_fmc_spi_dma_deinit( );
}
 
__RAM_CODE void xc_fmc_spi_dma_flash_wake_up(void)
{
    xc_fmc_status_wait_idle();
    uint8_t cmd[1];
 
    cmd[0] = CMD_RELEASE_PWRDWN;
 
    xc_fmc_spi_dma_init(0x07, 1, 1);
 
    xc_fmc_spi_dma_write(DMA_CHANNEL0, sizeof(cmd), cmd);
 
    xc_fmc_spi_dma_deinit();
}
 
__RAM_CODE void xc_fmc_spi_dma_flash_wait_busy(void)
{
    while (xc_fmc_spi_dma_flash_read_status() & 0x01)
        ;
}
 
__RAM_CODE void xc_fmc_spi_dma_flash_write_enable(void)
{
    xc_fmc_status_wait_idle();
 
    uint8_t cmd[1];
 
    cmd[0] = CMD_WRITE_ENABLE;
 
    xc_fmc_spi_dma_init(0x07, 1, 1);
 
    xc_fmc_spi_dma_write(DMA_CHANNEL0, sizeof(cmd), cmd);
 
    xc_fmc_spi_dma_deinit();
}
 
__RAM_CODE void xc_fmc_spi_dma_flash_write_disable(void)
{
    xc_fmc_status_wait_idle();
 
    uint8_t cmd[1];
 
    cmd[0] = CMD_WRITE_DISABLE;
 
    xc_fmc_spi_dma_init(0x07, 1, 1);
 
    xc_fmc_spi_dma_write(DMA_CHANNEL0, sizeof(cmd), cmd);
 
    xc_fmc_spi_dma_deinit();
}
 
__RAM_CODE void xc_fmc_spi_dma_flash_erase_sector(uint32_t Dst_Addr)
{
    uint8_t cmd[4] = {0};
 
    xc_fmc_status_wait_idle();
    xc_fmc_spi_dma_flash_wait_busy();
    xc_fmc_spi_dma_flash_write_enable();
    xc_fmc_spi_dma_flash_wait_busy();
 
    cmd[0] = CMD_SECTOR_ERASE;
    cmd[1] = Dst_Addr >> 16;
    cmd[2] = Dst_Addr >> 8;
    cmd[3] = Dst_Addr;
 
    xc_fmc_spi_dma_init(0x07, 1, 1);
 
    xc_fmc_spi_dma_write(DMA_CHANNEL0, sizeof(cmd), cmd);
 
    xc_fmc_spi_dma_deinit();
 
    xc_fmc_spi_dma_flash_wait_busy();
}
 
__RAM_CODE void xc_fmc_spi_dma_flash_erase_page(uint32_t Dst_Addr)
{
    uint8_t cmd[4] = {0};
 
    xc_fmc_spi_dma_flash_write_enable();
    xc_fmc_spi_dma_flash_wait_busy();
    xc_fmc_status_wait_idle();
 
    cmd[0] = CMD_PAGE_ERASE;
    cmd[1] = Dst_Addr >> 16;
    cmd[2] = Dst_Addr >> 8;
    cmd[3] = Dst_Addr;
 
    xc_fmc_spi_dma_init(0x07, 1, 1);
 
    xc_fmc_spi_dma_write(DMA_CHANNEL0, sizeof(cmd), cmd);
 
    xc_fmc_spi_dma_deinit();
 
    xc_fmc_spi_dma_flash_wait_busy();
}
 
__RAM_CODE void xc_fmc_spi_dma_flash_write_page(uint32_t WriteAddr, uint8_t *data, uint16_t size)
{
    uint8_t cmd[FLASH_PAGE_SIZE + 4] = {0};
 
    if (size > FLASH_PAGE_SIZE)
        return;
 
    xc_fmc_spi_dma_flash_write_enable();
 
    xc_fmc_spi_dma_flash_wait_busy();
 
    xc_fmc_status_wait_idle();
 
    cmd[0] = CMD_PAGE_PROGRAM;
    cmd[1] = WriteAddr >> 16;
    cmd[2] = WriteAddr >> 8;
    cmd[3] = WriteAddr;
 
    ram_memcpy_byte(&cmd[4], data, FLASH_PAGE_SIZE);
 
    xc_fmc_spi_dma_init(0x07, 1, 1);
 
    xc_fmc_spi_dma_write(DMA_CHANNEL0, size + 4, cmd);
 
    xc_fmc_spi_dma_deinit();
 
    xc_fmc_spi_dma_flash_wait_busy();
}
 
__RAM_CODE void xc_fmc_spi_dma_flash_read_page(uint32_t ReadAddr, uint8_t *data, uint16_t size)
{
    uint8_t cmd[FLASH_PAGE_SIZE + 4] = {0};
    uint8_t mid[FLASH_PAGE_SIZE + 4] = {0};
 
    if (size > FLASH_PAGE_SIZE)
        return;
 
    xc_fmc_status_wait_idle();
 
    cmd[0] = CMD_READ_DATA;
    cmd[1] = ReadAddr >> 16;
    cmd[2] = ReadAddr >> 8;
    cmd[3] = ReadAddr;
 
    xc_fmc_spi_dma_init(0x07, 1, 1);
 
    xc_fmc_spi_dma_write_and_read(DMA_CHANNEL1, (size + 4), cmd,
                                  DMA_CHANNEL0, (size + 4), mid);
 
    xc_fmc_spi_dma_deinit();
 
    ram_memcpy_byte(data, mid + 4, FLASH_PAGE_SIZE);
 
}
 
__RAM_CODE eXC_RESULT xc_fmc_spi_dma_flash_read(uint32_t readAddr, uint8_t *buff, uint16_t len)
{
    eXC_RESULT ret       = XR_OK;
    uint16_t ReqPageCnt  = 0; 
    uint16_t CurPageNum  = 0; 
    uint16_t CurStartPsr = 0; 
    uint16_t NextPageNum = 0; 
    uint16_t NextStopPsr = 0; 
    uint8_t temp_buff[FLASH_PAGE_SIZE] = {0};
 
    if (len <= FLASH_PAGE_SIZE) {
        CurPageNum  = CUR_PAGE_NUM(readAddr);
        CurStartPsr = CUR_START_PSR(readAddr);
        if ((len + CurStartPsr) > FLASH_PAGE_SIZE)
            ReqPageCnt = 2;
        else
            ReqPageCnt = 1;
 
        if (ReqPageCnt == 1)
        {
            xc_fmc_spi_dma_flash_read_page(CurPageNum * FLASH_PAGE_SIZE, temp_buff,
                                           FLASH_PAGE_SIZE);
 
            ram_memcpy_byte(buff, &temp_buff[CurStartPsr], len);
        } else if (ReqPageCnt == 2) {
            NextPageNum = CurPageNum + 1;
            NextStopPsr = len + CurStartPsr - FLASH_PAGE_SIZE;
 
            xc_fmc_spi_dma_flash_read_page(CurPageNum * FLASH_PAGE_SIZE, temp_buff,
                                           FLASH_PAGE_SIZE);
 
            ram_memcpy_byte(buff, &temp_buff[CurStartPsr], len - NextStopPsr);
 
            uint16_t HaveCopyNum = len - NextStopPsr;
            xc_fmc_spi_dma_flash_read_page(NextPageNum * FLASH_PAGE_SIZE,
                                           temp_buff, FLASH_PAGE_SIZE);
 
            ram_memcpy_byte(buff + HaveCopyNum, temp_buff, NextStopPsr);
        }
    } else {
        CurPageNum        = CUR_PAGE_NUM(readAddr);
        CurStartPsr       = CUR_START_PSR(readAddr);
        NextPageNum       = CurPageNum + 1;
 
        uint16_t buff_idx = 0;
        uint16_t pre_len  = NextPageNum * FLASH_PAGE_SIZE - readAddr;
        uint32_t pre_addr = CurPageNum * FLASH_PAGE_SIZE;
        xc_fmc_spi_dma_flash_read_page(pre_addr, temp_buff, FLASH_PAGE_SIZE);
        
        ram_memcpy_byte(buff, &temp_buff[CurStartPsr], pre_len);
        buff_idx += pre_len;
 
        pre_addr  = NextPageNum * FLASH_PAGE_SIZE;
        while (buff_idx < len) {
            if ((len - buff_idx) >= FLASH_PAGE_SIZE) {
                xc_fmc_spi_dma_flash_read_page(pre_addr, temp_buff,
                                               FLASH_PAGE_SIZE);
 
                ram_memcpy_byte(&buff[buff_idx], temp_buff, FLASH_PAGE_SIZE);
                buff_idx += FLASH_PAGE_SIZE;
                pre_addr += FLASH_PAGE_SIZE;
            } else {
                xc_fmc_spi_dma_flash_read_page(pre_addr, temp_buff,
                                               FLASH_PAGE_SIZE);
 
                ram_memcpy_byte(&buff[buff_idx], temp_buff, len - buff_idx);
                buff_idx += (len - buff_idx);
                pre_addr += (len - buff_idx);
            }
        }
    }
 
    return ret;
}
 
__RAM_CODE eXC_RESULT xc_fmc_spi_dma_flash_write(uint32_t writeAddr, uint8_t *buff, uint16_t size)
{
    eXC_RESULT ret       = XR_OK;
 
    uint32_t cur_addr = writeAddr;
    uint32_t end_addr = writeAddr + size;
    uint16_t wt_len   = 0;
    // The current page number occupied by this data storage
    uint16_t CurPageNum = 0; 
    uint16_t CurSectorNum = 0; 
    // The position occupied by this address on the current page
    uint32_t CurStartPsr = 0; 
    
 
    uint32_t mid = 0;
    xc_fmc_spi_dma_flash_rdid((uint8_t*)&mid);  
    
 
    if(mid != GD_FlASH_RDID){
        uint8_t temp_buff[FLASH_PAGE_SIZE];
        while (cur_addr != end_addr) {
            /* code */
            CurPageNum  = CUR_PAGE_NUM(cur_addr);
            CurStartPsr = CUR_START_PSR(cur_addr);
 
            xc_fmc_spi_dma_flash_read_page(CurPageNum * FLASH_PAGE_SIZE, temp_buff,
                                FLASH_PAGE_SIZE);
            xc_fmc_spi_dma_flash_erase_page(CurPageNum * FLASH_PAGE_SIZE);
            
 
            if (CurStartPsr) {
                ram_memcpy_byte(&temp_buff[CurStartPsr], buff + wt_len,
                                 (FLASH_PAGE_SIZE  - CurStartPsr) > size - wt_len // ��ǰ����ʣ��Ŀռ��Ƿ�����д����
                                     ? size - wt_len
                                     : (FLASH_PAGE_SIZE  - CurStartPsr));
                wt_len += wt_len + ((FLASH_PAGE_SIZE  - CurStartPsr) > size - wt_len
                                        ? size - wt_len
                                        : (FLASH_PAGE_SIZE  - CurStartPsr));
                cur_addr += wt_len;
            } else {
                ram_memcpy_byte(temp_buff, buff + wt_len,
                                 size - wt_len > FLASH_PAGE_SIZE  ? FLASH_PAGE_SIZE 
                                                                 : size - wt_len);
                cur_addr += (size - wt_len > FLASH_PAGE_SIZE  ? FLASH_PAGE_SIZE 
                                                             : size - wt_len);
                wt_len   += (size - wt_len > FLASH_PAGE_SIZE  ? FLASH_PAGE_SIZE 
                                                             : size - wt_len);
            }
            
            xc_fmc_spi_dma_flash_write_page(CurPageNum * FLASH_PAGE_SIZE, temp_buff,
                                     FLASH_PAGE_SIZE);
        }
          
    }else if(mid == GD_FlASH_RDID){    
        uint8_t temp_buff[FLASH_SECTOR_SIZE] = {0};
        while (cur_addr != end_addr) {
            /* code */
            CurSectorNum  = CUR_SECTOR_NUM(cur_addr);
            CurStartPsr = CUR_START_PSR(cur_addr);
            
            for(int i=0;i<FLASH_SECTOR_SIZE/FLASH_PAGE_SIZE;i++){
                xc_fmc_spi_dma_flash_read_page(CurSectorNum * FLASH_SECTOR_SIZE+ i* FLASH_PAGE_SIZE, temp_buff+i*FLASH_PAGE_SIZE,
                                    FLASH_PAGE_SIZE);
            }
            
            xc_fmc_spi_dma_flash_erase_sector(CurSectorNum * FLASH_SECTOR_SIZE);
            
            if (CurStartPsr) {
                ram_memcpy_byte(&temp_buff[CurStartPsr], buff + wt_len,
                                 (FLASH_SECTOR_SIZE - CurStartPsr) > size - wt_len
                                     ? size - wt_len
                                     : (FLASH_SECTOR_SIZE - CurStartPsr));
                wt_len += wt_len + ((FLASH_SECTOR_SIZE - CurStartPsr) > size - wt_len
                                        ? size - wt_len
                                        : (FLASH_SECTOR_SIZE - CurStartPsr));
                cur_addr += wt_len;
            } else {
                ram_memcpy_byte(temp_buff, buff + wt_len,
                                 size - wt_len > FLASH_SECTOR_SIZE ? FLASH_SECTOR_SIZE
                                                                 : size - wt_len);
                cur_addr += (size - wt_len > FLASH_SECTOR_SIZE ? FLASH_SECTOR_SIZE
                                                             : size - wt_len);
                wt_len   += (size - wt_len > FLASH_SECTOR_SIZE ? FLASH_SECTOR_SIZE
                                                             : size - wt_len);
            }
            
            for(int i=0;i<FLASH_SECTOR_SIZE/FLASH_PAGE_SIZE;i++){
                xc_fmc_spi_dma_flash_write_page(CurSectorNum * FLASH_SECTOR_SIZE+ i* FLASH_PAGE_SIZE, temp_buff+i*FLASH_PAGE_SIZE,
                                         FLASH_PAGE_SIZE);
            }
        }        
    }
 
    return ret;
}
 
__RAM_CODE void xc_fmc_spi_dma_flash_rdid(uint8_t *rdid)
{
    xc_fmc_status_wait_idle();
 
    uint8_t cmd[4] = {0};
    uint8_t id[4]  = {0};
 
    cmd[0]         = CMD_RDID;
    cmd[1]         = 0xff;
    cmd[2]         = 0xff;
    cmd[3]         = 0xff;
 
    xc_fmc_spi_dma_init(0x07, 1, 1);
 
    xc_fmc_spi_dma_write_and_read(DMA_CHANNEL1, sizeof(cmd), cmd,
                                  DMA_CHANNEL0, sizeof(id), id);
 
    xc_fmc_spi_dma_deinit();
 
    ram_memcpy_byte(rdid, &id[1], 3);
}
 
__RAM_CODE void xc_fmc_spi_dma_flash_ruid(uint8_t *ruid)
{
    xc_fmc_status_wait_idle();
 
    uint8_t cmd[21] = {0};
    uint8_t id[21]  = {0};
 
    cmd[0]          = CMD_RUID;
    cmd[1]          = 0xff;
    cmd[2]          = 0xff;
    cmd[3]          = 0xff;
    cmd[4]          = 0xff;
 
    xc_fmc_spi_dma_init(0x07, 1, 1);
 
    xc_fmc_spi_dma_write_and_read(DMA_CHANNEL1, sizeof(cmd), cmd,
                                  DMA_CHANNEL0, sizeof(id), id);
 
    xc_fmc_spi_dma_deinit();
 
    ram_memcpy_byte(ruid, &id[5], 16);
}
 
__RAM_CODE uint8_t xc_fmc_spi_dma_flash_read_status(void)
{
    xc_fmc_status_wait_idle();
 
    uint8_t cmd[2] = {0};
    uint8_t sta[2] = {0xff, 0xff};
 
    cmd[0]         = CMD_READ_STATUS;
    cmd[1]         = 0xff;
 
    xc_fmc_spi_dma_init(0x07, 1, 1);
 
    xc_fmc_spi_dma_write_and_read(DMA_CHANNEL1, sizeof(cmd), cmd,
                                  DMA_CHANNEL0, sizeof(sta), sta);
 
    xc_fmc_spi_dma_deinit();
 
    return sta[1];
}
 
__RAM_CODE void xc_fmc_spi_dma_write_and_read_data(
                                    uint8_t *w_data, uint16_t w_size,
                                    uint8_t *r_data, uint16_t r_size)
{
    xc_fmc_spi_dma_init(0x07, 1, 1);
 
    xc_fmc_spi_dma_write_and_read(
                              DMA_CHANNEL1, w_size, w_data,
                              DMA_CHANNEL0, r_size, r_data);  
 
    xc_fmc_spi_dma_deinit();
}
 
void xc_fmc_spi_dma_read_and_write_data( 
                                    uint8_t *w_data, uint16_t w_size,
                                    uint8_t *r_data, uint16_t r_size)
{
    xc_fmc_spi_dma_init(0x07, 1, 1);
 
    xc_fmc_spi_dma_read_and_write(
                              DMA_CHANNEL1, w_size, w_data,
                              DMA_CHANNEL0, r_size, r_data); 
 
    xc_fmc_spi_dma_deinit();
}