45 if (TIMER0_IDX == reg_idx) {
46 cpr_ctlapbclken_grctl__timer_pclk_en__setf(ENABLE);
47 cpr_timer0_clk_ctl__timer_clksel__setf(
49 cpr_timer0_clk_ctl__timer_clk0_div__setf(
51 cpr_timer0_clk_ctl__timer_clk1_div__setf(
53 }
else if (TIMER1_IDX == reg_idx) {
54 cpr_ctlapbclken_grctl__timer_pclk_en__setf(ENABLE);
55 cpr_timer1_clk_ctl__timer_clksel__setf(
57 cpr_timer1_clk_ctl__timer_clk0_div__setf(
59 cpr_timer1_clk_ctl__timer_clk1_div__setf(
61 }
else if (TIMER2_IDX == reg_idx) {
62 cpr_ctlapbclken_grctl__timer_pclk_en__setf(ENABLE);
63 cpr_timer2_clk_ctl__timer_clksel__setf(
65 cpr_timer2_clk_ctl__timer_clk0_div__setf(
67 cpr_timer2_clk_ctl__timer_clk1_div__setf(
69 }
else if (TIMER3_IDX == reg_idx) {
70 cpr_ctlapbclken_grctl__timer_pclk_en__setf(ENABLE);
71 cpr_timer3_clk_ctl__timer_clksel__setf(
73 cpr_timer3_clk_ctl__timer_clk0_div__setf(
75 cpr_timer3_clk_ctl__timer_clk1_div__setf(
78 cpr_lp_ctl__timer_sysclk_sel__setf(ENABLE);
80 timer_tcr__tes__setf(reg_idx, TIMER_TCR_TES_DISABLE);
81 timer_tcr__tms__setf(reg_idx, (uint8_t)init_cfg->
timer_mode);
89 if (TIMER0_IDX == reg_idx) {
90 src_clk = cpr_timer0_clk_ctl__timer_clksel__getf();
93 ticks = TIMER_CLKSRC_32M_DIV_CAL(
94 us, cpr_timer0_clk_ctl__timer_clk0_div__getf());
96 ticks = TIMER_CLKSRC_32K_DIV_CAL(
97 us, cpr_timer0_clk_ctl__timer_clk1_div__getf());
99 ticks = TIMER_CLKSRC_32K_CAL(us);
101 }
else if (TIMER1_IDX == reg_idx) {
102 src_clk = cpr_timer1_clk_ctl__timer_clksel__getf();
105 ticks = TIMER_CLKSRC_32M_DIV_CAL(
106 us, cpr_timer1_clk_ctl__timer_clk0_div__getf());
108 ticks = TIMER_CLKSRC_32K_DIV_CAL(
109 us, cpr_timer1_clk_ctl__timer_clk1_div__getf());
111 ticks = TIMER_CLKSRC_32K_CAL(us);
113 }
else if (TIMER2_IDX == reg_idx) {
114 src_clk = cpr_timer2_clk_ctl__timer_clksel__getf();
117 ticks = TIMER_CLKSRC_32M_DIV_CAL(
118 us, cpr_timer2_clk_ctl__timer_clk0_div__getf());
120 ticks = TIMER_CLKSRC_32K_DIV_CAL(
121 us, cpr_timer2_clk_ctl__timer_clk1_div__getf());
123 ticks = TIMER_CLKSRC_32K_CAL(us);
125 }
else if (TIMER3_IDX == reg_idx) {
126 src_clk = cpr_timer3_clk_ctl__timer_clksel__getf();
129 ticks = TIMER_CLKSRC_32M_DIV_CAL(
130 us, cpr_timer3_clk_ctl__timer_clk0_div__getf());
132 ticks = TIMER_CLKSRC_32K_DIV_CAL(
133 us, cpr_timer3_clk_ctl__timer_clk1_div__getf());
135 ticks = TIMER_CLKSRC_32K_CAL(us);
139 if (ticks < TIMER_MIN_TLC_VAL)
140 ticks = TIMER_MIN_TLC_VAL;
149 timer_tcr__tes__setf(reg_idx, TIMER_TCR_TES_DISABLE);
151 timer_tlc_set(reg_idx, ticks);
156 NVIC_EnableIRQ((IRQn_Type)(TIMER0_IRQn + reg_idx));
157 timer_tcr__tim__setf(reg_idx, TIMER_TCR_TIM_DISABLE);
158 timer_tcr__tes__setf(reg_idx, TIMER_TCR_TES_ENABLE);
163 timer_tcr__tes__setf(reg_idx, TIMER_TCR_TES_DISABLE);
168 (void)timer_tic_get(TIMER0_IDX);
175 (void)timer_tic_get(TIMER1_IDX);
182 (void)timer_tic_get(TIMER2_IDX);
189 (void)timer_tic_get(TIMER3_IDX);
Timer_ModeTypeDef timer_mode
TIMER_SrcClkTypeDef timer_src_clk
Timer_DivClkTypeDef timer_div_clk
void(* timer_handler_callback)(void *context)
void xc_timer_init(uint8_t reg_idx, Timer_InitCfg_t *init_cfg)
void xc_timer_start(uint8_t reg_idx)
void TIMER0_Handler(void)
void TIMER2_Handler(void)
__WEAK void timer0_callback(void *context)
void TIMER1_Handler(void)
void TIMER3_Handler(void)
void xc_timer_set_value(uint8_t reg_idx, uint32_t us)
__WEAK void timer3_callback(void *context)
__WEAK void timer1_callback(void *context)
void xc_timer_stop(uint8_t reg_idx)
static uint32_t xc_timer_us_to_ticks(uint8_t reg_idx, uint32_t us)
timer_handler_callback timer_n_callback[4]
__WEAK void timer2_callback(void *context)
The header of xc_drv_aotimer.c