xushaoxiang
175 lines
6.2 KiB
C
175 lines
6.2 KiB
C
/*!
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* \file xc_drv_aotimer.h
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*
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* \brief The header of xc_drv_aotimer.c
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*
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* \copyright Revised BSD License, see section \ref LICENSE.
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*
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* \code
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*
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* _ __ _ ________ _
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* | |/ /(_)___ / ____/ /_ (_)___
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* | // / __ \/ / / __ \/ / __ \
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* / |/ / / / / /___/ / / / / /_/ /
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* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
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* /_/
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* (C) 2022-2025 XinChip
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*
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* \endcode
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*
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* \author ( XinChip ) Alex-J
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*
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* \author ( XinChip )
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*/
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#ifndef _XC_DRV_SPI_H_
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#define _XC_DRV_SPI_H_
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/*-----------------------------------------------------------------------------------
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INCLUDE HEADE FILES
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------------------------------------------------------------------------------------*/
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#include <stdbool.h>
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#include <stdio.h>
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#include "xc6xxx.h"
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/*------------------------------------------------------------------------------------
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Macros
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-------------------------------------------------------------------------------------*/
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#define SPI_WAIT_TIMEOUT 65535
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// temporary macros -- alex revised
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#define SSI_CTRL0_FRF_MOTOROLA (0x1UL)
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#define SSI_CTRL0_FRF_TI (0x0UL)
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/* SPI_Mode SPI Mode */
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#define SPI_MODE_SLAVE (0x00000000U)
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#define SPI_MODE_MASTER (0x00000001U)
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/* SPI_data_size */
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#define SSI_CTRL0_DFS_LEN_16BIT ((uint16_t)0x0fUL)
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#define SSI_CTRL0_DFS_LEN_8BIT ((uint16_t)0x07UL)
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/* SPI_data_direction */
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#define SSI_CTRL0_TMOD_WR (0x0UL)
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#define SSI_CTRL0_TMOD_W (0x1UL)
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#define SSI_CTRL0_TMOD_R (0x2UL)
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/* SPI_BaudRate_Prescaler */
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#define SSI_BAUD_DIV_2 (0x02UL)
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#define SSI_BAUD_DIV_4 (0x04UL)
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#define SSI_BAUD_DIV_6 (0x06UL)
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#define SSI_BAUD_DIV_8 (0x08UL)
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#define SSI_BAUD_DIV_10 (0x0aUL)
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#define SSI_BAUD_DIV_12 (0x0cUL)
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/* SPI_Clock_Polarity */
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#define SSI_CTRL0_SCPOL_HIGH (0x1UL)
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#define SSI_CTRL0_SCPOL_LOW (0x0UL)
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/* SPI_Clock_Phase */
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#define SSI_CTRL0_SCPHA_LEAD (0x0UL)
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#define SSI_CTRL0_SCPHA_TRAIL (0x1UL)
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/* SPI_MSB_transmission */
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#define SPI_FirstBit_MSB ((uint16_t)0x0000)
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#define SSI_TXFTL_FIFO_0 (0x00UL)
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#define SSI_TXFTL_FIFO_1 (0x01UL)
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#define SSI_TXFTL_FIFO_2 (0x02UL)
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#define SSI_TXFTL_FIFO_3 (0x03UL)
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#define SSI_TXFTL_FIFO_4 (0x04UL)
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#define SSI_TXFTL_FIFO_5 (0x05UL)
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#define SSI_TXFTL_FIFO_6 (0x06UL)
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#define SSI_TXFTL_FIFO_7 (0x07UL)
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#define SSI_RXFTL_FIFO_0 (0x00UL)
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#define SSI_RXFTL_FIFO_1 (0x01UL)
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#define SSI_RXFTL_FIFO_2 (0x02UL)
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#define SSI_RXFTL_FIFO_3 (0x03UL)
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#define SSI_RXFTL_FIFO_4 (0x04UL)
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#define SSI_RXFTL_FIFO_5 (0x05UL)
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#define SSI_RXFTL_FIFO_6 (0x06UL)
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#define SSI_RXFTL_FIFO_7 (0x07UL)
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#define SSI_IE_TXEIE_ENABLE (0x1UL << SSI_TXEIE_POS)
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#define SSI_IE_TXEIE_DISABLE (0x0UL << SSI_TXEIE_POS)
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#define SSI_IE_TXOIE_ENABLE (0x1UL << SSI_TXOIE_POS)
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#define SSI_IE_TXOIE_DISABLE (0x0UL << SSI_TXOIE_POS)
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#define SSI_IE_RXUIE_ENABLE (0x1UL << SSI_RXUIE_POS)
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#define SSI_IE_RXUIE_DISABLE (0x0UL << SSI_RXUIE_POS)
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#define SSI_IE_RXOIE_ENABLE (0x1UL << SSI_RXOIE_POS)
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#define SSI_IE_RXOIE_DISABLE (0x0UL << SSI_RXOIE_POS)
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#define SSI_IE_RXFIE_ENABLE (0x1UL << SSI_RXFIE_POS)
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#define SSI_IE_RXFIE_DISABLE (0x0UL << SSI_RXFIE_POS)
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#define SSI_IS_TXEIS_SET (0x1UL << SSI_TXEIS_POS)
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#define SSI_IS_TXEIS_RESET (0x0UL << SSI_TXEIS_POS)
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#define SSI_IS_TXOIS_SET (0x1UL << SSI_TXOIS_POS)
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#define SSI_IS_TXOIS_RESET (0x0UL << SSI_TXOIS_POS)
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#define SSI_IS_RXUIS_SET (0x1UL << SSI_RXUIS_POS)
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#define SSI_IS_RXUIS_RESET (0x0UL << SSI_RXUIS_POS)
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#define SSI_IS_RXOIS_SET (0x1UL << SSI_RXOIS_POS)
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#define SSI_IS_RXOIS_RESET (0x0UL << SSI_RXOIS_POS)
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#define SSI_IS_RXFIS_SET (0x1UL << SSI_RXFIS_POS)
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#define SSI_IS_RXFIS_RESET (0x0UL << SSI_RXFIS_POS)
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/*------------------------------------------------------------------------------------
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TypeDef
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-------------------------------------------------------------------------------------*/
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typedef struct
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{
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uint16_t Mode;
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uint32_t Direction;
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uint32_t DataSize;
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uint32_t CLKPolarity;
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uint32_t CLKPhase;
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uint32_t NSS;
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uint32_t BaudRatePrescaler;
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uint32_t FirstBit;
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} SPI_InitCfg_t;
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/*------------------------------------------------------------------------------------
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Global Variables
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-------------------------------------------------------------------------------------*/
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typedef void (*timer_handler_callback)(void *context);
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/*------------------------------------------------------------------------------------
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Exported Functions
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-------------------------------------------------------------------------------------*/
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void xc_spi_init(uint8_t reg_idx, SPI_InitCfg_t *init_cfg);
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void xc_spi_rxftl_fifo_set(uint8_t reg_idx, uint8_t val);
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void xc_spi_txftl_fifo_set(uint8_t reg_idx, uint8_t val);
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void xc_spi_enable_it(uint8_t reg_idx, uint8_t val);
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void xc_spi_disable_it(uint8_t reg_idx, uint8_t val);
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void xc_spi_flash_power_down(uint8_t reg_idx);
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void xc_spi_flash_wake_up(uint8_t reg_idx);
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uint8_t xc_spi_flash_wait_busy(uint8_t reg_idx);
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eXC_RESULT xc_spi_flash_erase_sector(uint8_t reg_idx, uint32_t Dst_Addr);
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void xc_spi_flash_erase_page(uint8_t reg_idx, uint32_t Dst_Addr);
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void xc_spi_flash_write_page(uint8_t reg_idx, uint32_t WriteAddr,
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uint8_t *pBuffer);
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void xc_spi_flash_read_page(uint8_t reg_idx, uint32_t ReadAddr, uint8_t *pBuffer);
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eXC_RESULT xc_spi_flash_write(uint8_t reg_idx, uint32_t writeAddr, uint8_t *buff,
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uint16_t size);
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eXC_RESULT xc_spi_flash_read(uint8_t reg_idx, uint32_t readAddr, uint8_t *buff,
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uint16_t size);
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void xc_spi_flash_read_128bit_uid(uint8_t reg_idx, uint8_t *buff);
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eXC_RESULT xc_spi_flash_rdid(uint8_t reg_idx, uint8_t *buff);
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void xc_spi_write_and_read_data(uint8_t reg_idx, uint8_t *w_data, uint16_t w_size,
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uint8_t *r_data, uint16_t r_size);
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#endif // _XC_DRV_AOTIMER_H_
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