xushaoxiang
220 lines
6.8 KiB
C
220 lines
6.8 KiB
C
/**
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****************************************************************************************
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*
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* @file arch_main.c
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*
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* @brief Main loop of the application.
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*
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* Copyright (C) RivieraWaves 2009-2015
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*
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*
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****************************************************************************************
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*/
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/*
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* INCLUDES
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****************************************************************************************
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*/
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#include "rwip_config.h" // RW SW configuration
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#include "arch.h" // architectural platform definitions
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#include "boot.h" // boot definition
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#include "rwip.h" // RW SW initialization
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#include "xc_drv_pwr.h"
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#include <stdbool.h> // boolean definition
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#include <stddef.h> // standard definitions
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#include <stdint.h> // standard integer definition
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#include <stdlib.h> // standard lib functions
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#if (BLE_TEST_MODE_SUPPORT)
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#include "uart.h" // UART initialization
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#endif // (BLE_TEST_MODE_SUPPORT)
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#if (BLE_EMB_PRESENT || BT_EMB_PRESENT)
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#include "rf.h" // RF initialization
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#endif // BLE_EMB_PRESENT || BT_EMB_PRESENT
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#if (BLE_APP_PRESENT)
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// #include "app.h" // application functions
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#endif // BLE_APP_PRESENT
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#if PLF_DMA
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#include "dma.h" // DMA initialization
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#endif // PLF_DMA
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#if (PLF_NVDS)
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#include "nvds.h" // NVDS definitions
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#endif // PLF_NVDS
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#include "reg_assert_mgr.h"
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#if (PLF_PROFILING || PLF_MEM_PROTECTION)
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#include "reg_sw_profiling.h"
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#endif // (PLF_PROFILING || PLF_MEM_PROTECTION)
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#include "platform.h"
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#include "xc6xxx.h"
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// CPU early wake-up time (unit:us)
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#define SLEEP_TIME_EARLY (3000)
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#define HS_TO_US(frame) (((frame) * SLOT_SIZE) >> 1)
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/**
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* @brief clock_init
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* @details
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* @param void
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* @retval void
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*/
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void clock_init(void)
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{
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CLOCK_InitCfg_t clock_cfg;
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clock_cfg.hfclk_src = CLOCK_HFCLK_SRC_XTAL;
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clock_cfg.hfclk_in = CLOCK_HFCLK_IN_32M;
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#if (RC_32K)
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clock_cb.lfclk_src = CLOCK_LFCLK_SRC_RC;
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#endif //(RC_32K)
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#if (XTAL_32K)
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clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL;
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#endif // (XTAL_32K)
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#if (XTAL_32768K)
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clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL;
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#endif // (XTAL_32768K)
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if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_XTAL) {
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clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32768;
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} else if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_RC) {
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clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32K;
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}
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xc_clock_init_cfg(&clock_cfg);
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SysTick_Config(xc_clock_hfclk_in_get() / 100);
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SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
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}
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#if (SLEEP_ENABLE)
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void wakeup_timer_init(void)
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{
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TIMER_BaseInitTypeDef Timer_Init;
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Timer_Init.src_clk = TIMER_CLK_SRC_32K;
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Timer_Init.mode = TIMER_MODE_SINGLE_COUNT;
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Timer_Init.div_clk = TIMER_DIV_CLK_32000Hz;
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// Timer0 Config & Start
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TIMER_Base_Init(XC_TIMER0, &Timer_Init);
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PWR_InitTypeDef PWR_InitStruct = {0};
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PWR_InitStruct.PWR_WakeITSrc = GPIO_IRQn_WAKE | TIMER0_IRQn_WAKE;
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PWR_InitStruct.PWR_SleepMode = LIGHT_SLEEP_MODE;
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PWR_SleepInit(&PWR_InitStruct);
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PWR_GPIO_SleepConfig(PWR_InitStruct.PWR_SleepMode);
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PWR_GPIO_LightSleepWakeConfig(GPIO_2, RIS_EDGE_INT);
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PWR_GPIO_LightSleepWakeConfig(GPIO_3, RIS_EDGE_INT);
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}
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void sleep_wkup()
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{
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PWR_InitTypeDef PWR_InitStruct = {0};
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#if (USE_XIP != 1)
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SPI_InitCfg_t spi_cfg = {0};
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spi_cfg.Mode = SPI_MODE_MASTER;
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spi_cfg.DataSize = SSI_CTRL0_DFS_LEN_8BIT;
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spi_cfg.Direction = SSI_CTRL0_TMOD_WR;
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spi_cfg.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
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spi_cfg.CLKPolarity = SSI_CTRL0_SCPOL_LOW;
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spi_cfg.CLKPhase = SPI_CPHA_LEAD;
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spi_cfg.FirstBit = SPI_FirstBit_MSB;
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xc_spi_init(XC_SPI0, &spi_cfg);
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SPI_Flash_PowerDown(XC_SPI0);
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#endif //(USE_XIP!=1)
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// PWR_InitStruct.PWR_WakeITSrc = GPIO_IRQn_WAKE | TIMER0_IRQn_WAKE ;
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// PWR_InitStruct.PWR_SleepMode = LIGHT_SLEEP_MODE;
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// PWR_SleepInit(&PWR_InitStruct);
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// PWR_GPIO_SleepConfig(PWR_InitStruct.PWR_SleepMode);
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sleep_init();
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PWR_BLE_SleepEnter();
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}
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void Turn_Off_PeripheralClk()
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{
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XC_CPR->SSI0_MCLK_CTL = (((0UL << CPR_SSI_MCLK_CTL_SSI_MCLK_DIV_Pos) |
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CPR_SSI_MCLK_CTL_SSI_MCLK_DIV_WE) |
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((CPR_SSI_MCLK_CTL_SSI_MCLK_EN_DISABLE) |
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CPR_SSI_MCLK_CTL_SSI_MCLK_EN_WE));
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XC_CPR->CTLAPBCLKEN_GRCTL = ((CPR_CTLAPBCLKEN_GRCTL_SSI0_PCLK_EN_DISABLE) |
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(CPR_CTLAPBCLKEN_GRCTL_SSI0_PCLK_EN_Msk
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<< CPR_CTLAPBCLKEN_GRCTL_MASK_OFFSET))
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<< 0;
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XC_CPR->CTLAPBCLKEN_GRCTL = ((CPR_CTLAPBCLKEN_GRCTL_UART0_PCLK_EN_DISABLE) |
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(CPR_CTLAPBCLKEN_GRCTL_UART0_PCLK_EN_Msk
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<< CPR_CTLAPBCLKEN_GRCTL_MASK_OFFSET));
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XC_CPR->UART0_CLK_GRCTL = (((8UL << CPR_UART_CLK_GRCTL_UART0_CLK_GR_Pos) |
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CPR_UART_CLK_GRCTL_UART0_CLK_GR_WE) |
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((CPR_UART_CLK_GRCTL_UART0_CLK_GR_UPD_DISABLE) |
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(CPR_UART_CLK_GRCTL_UART1_CLK_GR_UPD_WE)));
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XC_CPR->CTLAPBCLKEN_GRCTL = ((CPR_CTLAPBCLKEN_GRCTL_UART0_PCLK_EN_DISABLE) |
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(CPR_CTLAPBCLKEN_GRCTL_UART0_PCLK_EN_Msk
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<< CPR_CTLAPBCLKEN_GRCTL_MASK_OFFSET))
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<< 1;
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//
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// XC_CPR->UART1_CLK_GRCTL = (((8UL <<
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// CPR_UART_CLK_GRCTL_UART1_CLK_GR_Pos) |
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// CPR_UART_CLK_GRCTL_UART1_CLK_GR_WE) |
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// ((CPR_UART_CLK_GRCTL_UART1_CLK_GR_UPD_DISABLE)
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// |
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// (CPR_UART_CLK_GRCTL_UART1_CLK_GR_UPD_WE)));
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// XC_CPR->AHBCLKEN_GRCTL =0x1e001e;
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}
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void sleep_schedule()
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{
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// Checks for sleep have to be done with interrupt disabled
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GLOBAL_INT_DISABLE();
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// Check if the processor clock can be gated
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uint32_t duration = 0;
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uint32_t duration_timer = 0;
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// switch(rwip_sleep(&duration, 2, \
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// 0x7D00, RWIP_MINIMUM_SLEEP_TIME)){
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switch (rwip_sleep(&duration, 1, 0x7D00, 20)) {
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case RWIP_DEEP_SLEEP: {
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duration_timer = (HS_TO_US(duration) - SLEEP_TIME_EARLY);
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TIMER_SetUs(XC_TIMER0, duration_timer);
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TIMER_Start_IT(XC_TIMER0);
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sleep_wkup();
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__TIMER_Disable(XC_TIMER0);
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}
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// no break
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case RWIP_CPU_SLEEP: {
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// Wait for interrupt
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// Turn_Off_PeripheralClk();
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// __PWR_SleepSrcMask_Set(0x1e000e);
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// __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
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// __WFI();
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// __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
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// __PWR_SleepSrcMask_Set(0x1e001e);
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} break;
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case RWIP_ACTIVE:
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default: {
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// nothing to do.
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} break;
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}
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// Checks for sleep have to be done with interrupt disabled
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GLOBAL_INT_RESTORE();
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}
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#endif // (SLEEP_ENABLE)
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