xushaoxiang
298 lines
6.6 KiB
C
298 lines
6.6 KiB
C
#include "sleep.h"
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static void system_sleep_init()
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{
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uint32_t wake_it_src;
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#if (USE_XIP == 1)
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#if (USE_ROM_FLASH)
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FMC_SPI_Init_Oprt();
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#else // (USE_ROM_FLASH)
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xc_fmc_spi_init_oprt();
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#endif // (USE_ROM_FLASH)
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#endif
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#if (USE_XIP != 1)
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SPI_InitCfg_t spi_cfg = {0};
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spi_cfg.Mode = SPI_MODE_MASTER;
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spi_cfg.DataSize = SSI_CTRL0_DFS_LEN_8BIT;
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spi_cfg.Direction = SSI_CTRL0_TMOD_WR;
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spi_cfg.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
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spi_cfg.CLKPolarity = SSI_CTRL0_SCPOL_LOW;
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spi_cfg.CLKPhase = SPI_CPHA_LEAD;
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spi_cfg.FirstBit = SPI_FirstBit_MSB;
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xc_spi_init(XC_SPI0, &spi_cfg);
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SPI_Flash_PowerDown(XC_SPI0);
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#endif
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xc_pwr_gpio_sleep_config();
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wake_it_src = RTC_IRQn_WAKE | TIMER0_IRQn_WAKE | TIMER_AO0_IRQn_WAKE | GPIO_IRQn_WAKE;
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xc_pwr_wake_it_set(wake_it_src);
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}
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static void system_lightsleep_cfg()
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{
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#if (USE_XIP != 1)
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cprao_aon_puctrl1_set(0x4); /* puctrl1= 0x4 , SSI0RX must pulldown*/
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#endif
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cprao_aon_sys_time_set((RST_READY_TIME << 12) | (OSC32_STABLE_TIME));
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xc_pwr_pd_lightsleep_set();
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xc_pwr_sleepsrc_mask_set(0x1e001e);
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xc_pwr_osc_off();
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}
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__RAM_CODE void xc_mcu_sleep(void)
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{
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xc_adc_powerdown();
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xc_pwr_usb_off();
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xc_pwr_rc16m_off();
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// xc_pwr_rom_off();
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xc_pwr_modem_off();
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xc_pwr_opa_tempsensor_off();
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xc_pwr_opa_volr_off();
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xc_pwr_revddldo_off();
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cprao_aon_reg4__bb_coreldo_normal_sw_mux__setf(0);
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// xc_pwr_bor_off();
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xc_pwr_dcdc_close();
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xc_pwr_rfdigital_off();
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xc_pwr_rc32k_calib_off();
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rtc_rccal_en_set(0x00);
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xc_pwr_pd_lightsleep_set();
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#if (USE_XIP == 1)
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#if (USE_ROM_FLASH)
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FMC_SPI_Flash_PowerDown();
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#else // (USE_ROM_FLASH)
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xc_fmc_spi_flash_power_down();
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#endif // (USE_ROM_FLASH)
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xc_pwr_rom_off();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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cpr_fmc_ctl_set(0x3000 | (1 << 9)); // close FMC
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for (int i = 0; i < 10; i++) {
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__NOP();
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__NOP();
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__NOP();
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}
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#endif
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__disable_irq();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__WFI();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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cpr_fmc_ctl_set(0x3503);
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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xc_pwr_rom_on();
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for (int i = 0; i < 10; i++) {
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__NOP();
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__NOP();
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__NOP();
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}
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#if (USE_ROM_FLASH)
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FMC_SPI_Flash_WakeUp();
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#else // (USE_ROM_FLASH)
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xc_fmc_spi_flash_wake_up();
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#endif // (USE_ROM_FLASH)
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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xc_pwr_ao_timer_pclk32m_Set();
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#ifdef USED_DCDC
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xc_pwr_dcdc_open();
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#endif
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xc_pwr_modem_on();
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xc_pwr_rfdigital_on();
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xc_adc_wakeup();
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__enable_irq();
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}
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void sleep_init(void)
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{
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xc_rc32k_calib_by_soft();
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system_sleep_init();
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system_lightsleep_cfg();
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xc_fmc_spi_init_oprt();
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xc_fmc_spi_flash_wake_up();
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cpr_slp_cnt_limit_set(1);
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NVIC_EnableIRQ(TIMER0_IRQn);
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}
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__RAM_CODE void enter_sleep(void)
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{
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#if (defined(XC62XX_RFANA2_BIT13_SET) && (CONFIG_HFCLK_IS_OSC32M_PLL_32M == 1))
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extern void rf_ana2_bit13_disable(void);
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rf_ana2_bit13_disable();
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#endif // XC62XX_RFANA2_BIT13_SET && CONFIG_HFCLK_IS_OSC32M_PLL_32M==0
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xc_mcu_sleep();
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#if (defined(XC62XX_RFANA2_BIT13_SET) && (CONFIG_HFCLK_IS_OSC32M_PLL_32M == 1))
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extern void rf_ana2_bit13_enable(void);
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rf_ana2_bit13_enable();
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#endif // XC62XX_RFANA2_BIT13_SET && CONFIG_HFCLK_IS_OSC32M_PLL_32M==0
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}
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void shipmode_deepsleep_cfg()
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{
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#if (USE_XIP!=1)
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cprao_aon_puctrl1_set(0xf);
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#endif
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cprao_aon_sys_time_set((RST_READY_TIME<<12) | (OSC32_STABLE_TIME));
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xc_pwr_pd_deepsleep_set();
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delay_us(100);
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xc_pwr_sleepsrc_mask_set(0x1e001e);
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xc_pwr_osc_off();
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}
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void shipmode_gpio_sleep_config(void)
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{
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#if (USE_XIP == 1)
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/* puctrl1= 0xf ,clk,cs,d0,d1 must pulldown */
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// cprao_aon_puctrl1_set(0xf);
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cprao_aon_puctrl1_set(0x5555F);
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#else
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// if (sleep_mode == LIGHT_SLEEP_MODE) {
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// XC_CPR_AO->PU_CTRLx[0] = 0x4;
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// } else if (sleep_mode == DEEP_SLEEP_MODE) {
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// XC_CPR_AO->PU_CTRLx[0] = 0xf;
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// }
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#endif
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NVIC_DisableIRQ(GPIO_IRQn);
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GPIO_InitCfg_t gpio_cfg = {0};
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gpio_cfg.Mux = GPIO_Mux0;
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gpio_cfg.Dir = GPIO_DIR_INPUT;
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gpio_cfg.FunSel = GPIO_Dx;
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gpio_cfg.Int = NOT_INT;
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gpio_cfg.Pull = GPIO_PULLDOWN;
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// The gpio scripts used cannot be configured. gpio36-39 cannot be
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// configured.
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for (int i = 0; i < GPIO_36; i++) {
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gpio_cfg.Pin = i;
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#if defined(USE_64M_CRYSTAL)
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if (i == GPIO_18 || i == GPIO_19 || i == GPIO_2) // Default for uart0
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#else
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if (i == GPIO_18 || i == GPIO_19 || i == GPIO_11)
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#endif // defined(USE_64M_CRYSTAL)
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{
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} else if (i == GPIO_33 || i == GPIO_34) {
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gpio_cfg.Pull = GPIO_PULLDOWN;
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xc_gpio_init(&gpio_cfg);
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}
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else if (i == GPIO_35) {
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gpio_cfg.Pull = GPIO_PULLDOWN;
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xc_gpio_init(&gpio_cfg);
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} else if (i == GPIO_20 || i == GPIO_21) {
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#if !defined(NO_SUPPORT_LFCLK_XTAL_32768)
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// Pins required when using an external 32k crystal
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if (xc_clock_lfclk_src_get() != CLOCK_LFCLK_SRC_XTAL) {
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xc_gpio_init(&gpio_cfg);
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}
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#endif
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} else {
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xc_gpio_init(&gpio_cfg);
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}
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}
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}
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void shipmode_sleep_init()
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{
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uint32_t wake_it_src;
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#if (USE_XIP == 1)
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#if (USE_ROM_FLASH)
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FMC_SPI_Init_Oprt();
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#else // (USE_ROM_FLASH)
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xc_fmc_spi_init_oprt();
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#endif // (USE_ROM_FLASH)
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#endif
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#if (USE_XIP != 1)
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SPI_InitCfg_t spi_cfg = {0};
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spi_cfg.Mode = SPI_MODE_MASTER;
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spi_cfg.DataSize = SSI_CTRL0_DFS_LEN_8BIT;
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spi_cfg.Direction = SSI_CTRL0_TMOD_WR;
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spi_cfg.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
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spi_cfg.CLKPolarity = SSI_CTRL0_SCPOL_LOW;
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spi_cfg.CLKPhase = SPI_CPHA_LEAD;
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spi_cfg.FirstBit = SPI_FirstBit_MSB;
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xc_spi_init(XC_SPI0, &spi_cfg);
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SPI_Flash_PowerDown(XC_SPI0);
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#endif
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//shipmode_gpio_sleep_config();
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wake_it_src = GPIO_IRQn_WAKE | RTC_IRQn_WAKE | MPU_IRQn_WAKE;
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xc_pwr_wake_it_set(wake_it_src);
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}
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