106 uint8_t errorCode = DMA_OK;
107 uint32_t uart_prf_addr = 0;
109 if(uart_idx == UART2_IDX) {
110 errorCode = DMA_EPERM;
114 if(uart_idx == UART0_IDX) {
115 uart_prf_addr = XC_REG_UART_BASE_ADDR;
116 }
else if(uart_idx == UART1_IDX) {
117 uart_prf_addr = XC_REG_UART_BASE_ADDR + uart_offset[uart_idx];
120 ch_cfg.
sar = (uint32_t)tx_buff;
121 ch_cfg.
dar = (uint32_t)uart_prf_addr;
141 if(uart_idx == UART0_IDX)
143 else if(uart_idx == UART1_IDX)
152 DEBUG(
"\nERROR: Failed to initialise configuration\n");
174 DEBUG(
"\nERROR: Failed XC_UART_DMA_TX_CONFIG\n");
192 if(uart_idx == UART0_IDX) {
195 }
else if(uart_idx == UART1_IDX) {
201 DEBUG(
"\nERROR: Failed Uart DMA_StartTransfer Tx\n");
eDMA_Burst_Trans_Len ctl_dst_msize
eDMA_Fifo_Mode cfg_fifo_mode
eDMA_Trans_Width ctl_src_tr_width
eDMA_SW_HW_HS_Select cfg_hs_sel_src
eDMA_SW_HW_HS_Select cfg_hs_sel_dst
eDMA_Burst_Trans_Len ctl_src_msize
eDMA_Trans_Flow ctl_tt_fc
eDMA_Trans_Width ctl_dst_tr_width
eDMA_HS_Interface cfg_dst_per
eDMA_Addr_Increment ctl_dinc
eDMA_Addr_Increment ctl_sinc
__RAM_CODE uint8_t xc_dma_disable(void)
xc_dma_disable
__RAM_CODE uint8_t xc_dma_set_channel_config(eDMA_Ch_Num ch_num, DMA_Chx_Cfg_t *ch)
xc_dma_set_channel_config
__RAM_CODE bool xc_dma_set_listener(eDMA_Ch_Num ch_num, DMA_Callback userFunction)
xc_dma_set_listener
__RAM_CODE uint8_t xc_dma_init(void)
xc_dma_init
__RAM_CODE void xc_dma_enable(void)
xc_dma_enable
__RAM_CODE uint8_t xc_dma_start_transfer(eDMA_Ch_Num ch_num, DMA_Callback cb_func)
xc_dma_start_transfer
enum dmac_channel_number eDMA_Ch_Num
void xc_uart_dma_send(uint8_t uart_idx)
volatile bool uart0_tx_tfr_flag
uint8_t xc_uart_dma_tx_config(uint8_t uart_idx, eDMA_Ch_Num ch_num, uint16_t blockSize, uint8_t *tx_buff)
void xc_uart_dma_tx_init(uint8_t uart_idx, uint16_t tx_size, uint8_t *tx_buff)
void uart1_tx_callback(uint8_t eCode)
volatile bool uart1_tx_tfr_flag
void uartx_dma_tx_err(uint8_t eCode)
void uart0_tx_callback(uint8_t eCode)
static volatile bool err_flag
The header of xc_drv_uart_dma.c