82#define UART_IER_ERDA_ENABLE (0x1UL)
83#define UART_IER_ERDA_DISABLE (0x0UL)
85#define UART_IER_ETHEI_ENABLE (0x1UL)
86#define UART_IER_ETHEI_DISABLE (0x0UL)
88#define UART_IER_ETSI_ENABLE (0x1UL)
89#define UART_IER_ETSI_DISABLE (0x0UL)
91#define UART_IER_EMSI_ENABLE (0x1UL)
92#define UART_IER_EMSI_DISABLE (0x0UL)
94#define UART_IER_ETSI_ENABLE (0x1UL)
95#define UART_IER_ETSI_DISABLE (0x0UL)
97#define UART_IER_ETHSI_ENABLE (0x1UL)
98#define UART_IER_ETHSI_DISABLE (0x0UL)
100#define UART_IER_ERDAI_ENABLE (0x1UL)
101#define UART_IER_ERDAI_DISABLE (0x0UL)
103#define UART_IER_PTIME_ENABLE (0x1UL)
104#define UART_IER_PTIME_DISABLE (0x0UL)
106#define UART_IIR_IID_EMSI (0x0UL)
107#define UART_IIR_IID_NO_IT (0x1UL)
108#define UART_IIR_IID_ETHEI (0x02UL)
109#define UART_IIR_IID_ERDAI (0x04UL)
110#define UART_IIR_IID_ETSI (0x06UL)
111#define UART_IIR_IID_BUSY (0x07UL)
112#define UART_IIR_IID_TO (0xCUL)
114#define UART_IIR_FS_ENABLE (0x3UL)
115#define UART_IIR_FS_DISABLE (0x0UL)
117#define UART_FCR_FIFO_ENABLE_ENABLE (0x1UL)
118#define UART_FCR_FIFO_ENABLE_DISABLE (0x0UL)
120#define UART_FCR_RCVR_FIFO_RESET_CLEAR (0x1UL)
121#define UART_FCR_RCVR_FIFO_RESET_NOT_CLEAR (0x0UL)
123#define UART_FCR_XMIT_FIFO_RESET_CLEAR (0x1UL)
124#define UART_FCR_XMIT_FIFO_RESET_NOT_CLEAR (0x0UL)
126#define UART_FCR_TX_EMPTY_TRIGGER_FIFO_EMPTY (0x0UL)
127#define UART_FCR_TX_EMPTY_TRIGGER_FIFO_2_BYTE (0x1UL)
128#define UART_FCR_TX_EMPTY_TRIGGER_FIFO_4_3 (0x2UL)
129#define UART_FCR_TX_EMPTY_TRIGGER_FIFO_2_1 (0x3UL)
131#define UART_FCR_RCVR_TRIGGER_FIFO_1_BYTE (0x0UL)
132#define UART_FCR_RCVR_TRIGGER_FIFO_4_1 (0x1UL)
133#define UART_FCR_RCVR_TRIGGER_FIFO_2_1 (0x2UL)
134#define UART_FCR_RCVR_TRIGGER_FIFO_LESS_2_BYTE (0x3UL)
136#define UART_TCR_CLS_Pos (0UL)
137#define UART_TCR_CLS_Msk (0x3UL)
138#define UART_TCR_CLS_5BITS (0x0UL)
139#define UART_TCR_CLS_6BITS (0x1UL)
140#define UART_TCR_CLS_7BITS (0x2UL)
141#define UART_TCR_CLS_8BITS (0x3UL)
143#define UART_TCR_STOP_Pos (2UL)
144#define UART_TCR_STOP_Msk (0x1UL)
145#define UART_TCR_STOP_1BITS (0x0UL)
146#define UART_TCR_STOP_1_5BITS (0x1UL)
148#define UART_TCR_STOP_2BITS (0x1UL)
150#define UART_TCR_PEN_DISABLE (0x0UL)
151#define UART_TCR_PENS_ENABLE (0x1UL)
153#define UART_TCR_EPS_ODD (0x0UL)
154#define UART_TCR_EPS_EVEN (0x1UL)
156#define UART_TCR_BREAK_STOP (0x1UL)
157#define UART_TCR_BREAK_RECOVER (0x0UL)
159#define UART_TCR_DLAB_DLLH_ENABLE (0x1UL)
160#define UART_TCR_DLAB_DLLH_DISABLE (0x0UL)
162#define UART_MCR_RTS_Msk (0x1UL)
163#define UART_MCR_RTS_OUT_HIGH (0x1UL)
164#define UART_MCR_RTS_OUT_LOW (0x0UL)
166#define UART_MCR_AFCE_ENABLE (0x1UL)
167#define UART_MCR_AFCE_DISABLE (0x0UL)
169#define UART_TSR_DR_VALID (0x1UL)
170#define UART_TSR_DR_INVALID (0x0UL)
172#define UART_TSR_OE_VALID (0x1UL)
173#define UART_TSR_OE_INVALID (0x0UL)
175#define UART_TSR_PE_Pos (2UL)
176#define UART_TSR_PE_Msk (0x1UL)
177#define UART_TSR_PE_VALID (0x1UL)
178#define UART_TSR_PE_INVALID (0x0UL)
180#define UART_TSR_FE_VALID (0x1UL)
181#define UART_TSR_FE_INVALID (0x0UL)
183#define UART_TSR_BI_VALID (0x1UL)
184#define UART_TSR_BI_INVALID (0x0UL)
186#define UART_TSR_THRE_VALID (0x1UL)
187#define UART_TSR_THRE_INVALID (0x0UL)
189#define UART_TSR_RX_FIFO_ERROR_VALID (0x1UL)
190#define UART_TSR_RX_FIFO_ERROR_INVALID (0x0UL)
192#define UART_MSR_DCTS_CHANGE (0x1UL)
193#define UART_MSR_DCTS_NO_CHANGE (0x0UL)
195#define UART_MSR_CTS_OUT_LOW (0x1UL)
196#define UART_MSR_CTS_OUT_HIGH (0x0UL)
198#define UART_USR_BUSY_BUSY (0x1UL)
199#define UART_USR_BUSY_IDLE (0x0UL)
202#define UART_BUFF_LEN 64U
204#define UART_DATA_5_BITS UART_TCR_CLS_5BITS
205#define UART_DATA_6_BITS UART_TCR_CLS_6BITS
206#define UART_DATA_7_BITS UART_TCR_CLS_7BITS
207#define UART_DATA_8_BITS UART_TCR_CLS_8BITS
209#define UART_STOP_1_BITS UART_TCR_STOP_1BITS
210#define UART_STOP_1_5_BITS UART_TCR_STOP_1_5BITS
211#define UART_STOP_2_BITS UART_TCR_STOP_2BITS
213#define UART_HWFC_DISABLE UART_MCR_AFCE_DISABLE
214#define UART_HWFC_ENABLE UART_MCR_AFCE_ENABLE
216#define UART_PARITY_ENABLE UART_TCR_PENS_ENABLE
217#define UART_PARITY_DISABLE UART_TCR_PEN_DISABLE
219#define UART_PARITY_EVEN (UART_TCR_EPS_EVEN | UART_PARITY_ENABLE)
220#define UART_PARITY_ODD (UART_TCR_EPS_ODD | UART_PARITY_ENABLE)
222#define UART_BAUDRATE_2400 (0x0120271CUL)
223#define UART_BAUDRATE_4800 (0x0240271CUL)
224#define UART_BAUDRATE_9600 (0x0480271CUL)
225#define UART_BAUDRATE_12800 (0x04802719UL)
226#define UART_BAUDRATE_14400 (0x04802718UL)
227#define UART_BAUDRATE_19200 (0x04802716UL)
228#define UART_BAUDRATE_23040 (0x04802715UL)
229#define UART_BAUDRATE_38400 (0x04802713UL)
230#define UART_BAUDRATE_57600 (0x04802712UL)
231#define UART_BAUDRATE_115200 (0x04802711UL)
232#define UART_BAUDRATE_128000 (0x030007D3UL)
233#define UART_BAUDRATE_230400 (0x09002711UL)
234#define UART_BAUDRATE_256000 (0x060007D3UL)
235#define UART_BAUDRATE_460800 (0x12002711UL)
236#define UART_BAUDRATE_921600 (0x24002711UL)
237#define UART_BAUDRATE_1M (0x00100011UL)
243extern uint8_t
__attribute__((aligned(4))) uart_txdmabuff[UART_BUFF_LEN];
244extern uint8_t
__attribute__((aligned(4))) uart_rxdmabuff[UART_BUFF_LEN];
uart_handler_callback uart_receive_cb
UART Init Structure Definition
uint16_t HardwareFlowControl
void xc_uart_register_receive_cb(uart_handler_callback uart_cb)
void(* uart_handler_callback)(uint8_t *buff, uint16_t len)
uint8_t __attribute__((aligned(4))) uart_txdmabuff[UART_BUFF_LEN]
void xc_uart_enable_rx_it(uint8_t reg_idx)
uint16_t xc_uart_receive_data(uint8_t reg_idx, uint8_t *data)
void xc_uart_send_byte(uint8_t reg_idx, uint8_t byte)
void xc_uart_send_data(uint8_t reg_idx, uint8_t *data, uint16_t len)
UART_IT_TypeDef
UART interrupt ID enumeration
@ UART_IT_Receive_Line_Status
@ UART_IT_Character_Timeout
@ UART_IT_Received_Data_Available
void xc_uart_init(uint8_t reg_idx, UART_InitCfg_t *uart_cfg)
void xc_uart_disable_rx_it(uint8_t reg_idx)