xc_drv_spi_dma.c

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/*-----------------------------------------------------------------------------------
                                   INCLUDE HEADE FILES
 ------------------------------------------------------------------------------------*/
#include "xc_drv_spi_dma.h"
 
/*------------------------------------------------------------------------------------
                                     Local Variables
 -------------------------------------------------------------------------------------*/
 
// Declare global variables
//static volatile bool tfr_flag;
static volatile bool wr_tfr_flag;
static volatile bool rd_tfr_flag;
static volatile bool err_flag;
// static volatile bool srcTran_flag;
// static volatile bool dstTran_flag;
 
// Intermediate buffer
uint8_t mid[FLASH_PAGE_SIZE+4]; 
 
/*------------------------------------------------------------------------------------
                                     Global Variables
 -------------------------------------------------------------------------------------*/
 
/*------------------------------------------------------------------------------------
                                     Func Prototype
 -------------------------------------------------------------------------------------*/
uint8_t xc_spi_dma_flash_read_status(uint8_t spi_idx);
 
/*------------------------------------------------------------------------------------
                                        Functions
 -------------------------------------------------------------------------------------*/
void spi_dma_write_callback(uint8_t eCode)
{
//    DEBUG("T\n");
    wr_tfr_flag = true;
}
 
void spi_dma_read_callback(uint8_t eCode)
{
//    DEBUG("R\n");
    rd_tfr_flag = true;
}
 
void spi_dma_write_err(uint8_t eCode)
{
    // -------
    // This function is called by the IRQ handler.
    // We use this function to deal with interrupts that the DMA
    // driver is unable to cater for (these are application
    // specific). All of the interrupts handled by this function
    // are cleared by the DMA driver, so there's no need to clear here.
    // -------
 
    // Check the source of the interrupt
 
    if(eCode == DMA_IRQ_ERR) {
 
        // Just inform the application that this interrupt has occured.
        err_flag = true;
    }
}
 
void spi_dma_read_err(uint8_t eCode)
{
    // -------
    // This function is called by the IRQ handler.
    // We use this function to deal with interrupts that the DMA
    // driver is unable to cater for (these are application
    // specific). All of the interrupts handled by this function
    // are cleared by the DMA driver, so there's no need to clear here.
    // -------
 
    // Check the source of the interrupt
 
    if(eCode == DMA_IRQ_ERR) {
 
        // Just inform the application that this interrupt has occured.
        err_flag = true;
    }
}
 
void xc_dma_mem2prf_finish(void)
{
    while(wr_tfr_flag == false) { 
        if(err_flag == true) {
            // Wasn't expecting this !!
            DEBUG("\nERROR: Recieved an err interrupt\n");
        }
    }
}
 
void xc_dma_prf2mem_finish(void)
{
    while(rd_tfr_flag == false) { 
        if(err_flag == true) {
            // Wasn't expecting this !!
            DEBUG("\nERROR: Recieved an err interrupt\n");
        }
    }
}
 
uint32_t xc_spi_prf_data_addr(uint8_t spi_idx, uint8_t *eCode)
{
    uint32_t spi_prf_addr = XC_REG_SPI_BASE_ADDR;
 
    if(spi_idx == SPI2_IDX) {
        spi_prf_addr += (SPI2_BASE_OFFSET + SSIx_DATA_OFFSET);
    } else if(spi_idx < SPI2_IDX) {
        if(spi_idx == SPI1_IDX)
            spi_prf_addr += (SPI1_BASE_OFFSET + SSIx_DATA_OFFSET);
        else
            spi_prf_addr += SSIx_DATA_OFFSET;
    } else {
        *eCode = DMA_EPERM;
    }
 
    return spi_prf_addr;
}
 
uint8_t xc_spi_dma_write_config(uint8_t spi_idx, eDMA_Ch_Num ch_num, uint16_t blockSize, uint8_t *tx_buff)
{
    DMA_Chx_Cfg_t ch_cfg;
    uint8_t errorCode = DMA_OK;
    uint8_t data_size = spi_ctrl0__ssi_dfs__getf(spi_idx);
 
    uint32_t spi_prf_addr = xc_spi_prf_data_addr(spi_idx, &errorCode);
    if(errorCode != DMA_OK)
    {
        return errorCode;
    }
 
    ch_cfg.sar              = (uint32_t)tx_buff;
    ch_cfg.dar              = (uint32_t)spi_prf_addr;
    
    ch_cfg.ctl_src_msize    = DMA_MSIZE_1;//DMAC_MSIZE_4;//DMAC_MSIZE_1;
    ch_cfg.ctl_dst_msize    = DMA_MSIZE_1;//DMAC_MSIZE_4;//DMAC_MSIZE_1;
 
    ch_cfg.ctl_sinc         = DMA_ADDR_INCREMENT;
    ch_cfg.ctl_dinc         = DMA_ADDR_NOCHANGE;
 
    if(data_size == 0x07) {
        ch_cfg.ctl_src_tr_width = DMA_TRANS_WIDTH_8;
        ch_cfg.ctl_dst_tr_width = DMA_TRANS_WIDTH_8;
    } else if(data_size == 0x0f) {
        ch_cfg.ctl_src_tr_width = DMA_TRANS_WIDTH_16;
        ch_cfg.ctl_dst_tr_width = DMA_TRANS_WIDTH_16;
    }
 
    ch_cfg.ctl_tt_fc        = DMA_MEM2PRF_DMA;
 
    ch_cfg.ctl_block_ts     = blockSize;
 
    ch_cfg.cfg_hs_sel_src   = DMA_HS_HARDWARE;
    ch_cfg.cfg_hs_sel_dst   = DMA_HS_HARDWARE;
    
    ch_cfg.cfg_fifo_mode    = DMA_FIFO_MODE_SINGLE;
    
    if(spi_idx == 0)
        ch_cfg.cfg_dst_per      = SSI0_DMA_TX_HS_IF2;
    else if(spi_idx == 1)
        ch_cfg.cfg_dst_per      = SSI1_DMA_TX_HS_IF3;
    else if(spi_idx == 2)
        ch_cfg.cfg_dst_per      = SSI2_DMA_TX_HS_IF4;
    
//    ch_cfg.cfg_ch_prior     = DMA_PRIORITY_0;
    // Now we can intialise the channel configuration structure for
    // DMA channel 0 by loading the structure members with the
    // contents of the DMAC's channel 0 registers.
    errorCode = xc_dma_set_channel_config(ch_num, &ch_cfg);
    if(errorCode != 0) {
        DEBUG("\nERROR: Failed to initialise configuration\n");
    }
 
    xc_dma_set_listener(ch_num, spi_dma_write_err);
 
    return errorCode;
}
 
uint8_t xc_spi_dma_read_config(uint8_t spi_idx, eDMA_Ch_Num ch_num, uint16_t blockSize, uint8_t *rx_buff)
{
    DMA_Chx_Cfg_t ch_cfg;
    uint8_t errorCode = DMA_OK;
    uint8_t data_size = spi_ctrl0__ssi_dfs__getf(spi_idx);
    
    uint32_t spi_prf_addr = xc_spi_prf_data_addr(spi_idx, &errorCode);
    if(errorCode != DMA_OK)
    {
        return errorCode;
    }
 
    ch_cfg.sar              = (uint32_t)spi_prf_addr;
    ch_cfg.dar              = (uint32_t)rx_buff;
    
    ch_cfg.ctl_src_msize    = DMA_MSIZE_1;
    ch_cfg.ctl_dst_msize    = DMA_MSIZE_1;
 
    ch_cfg.ctl_sinc         = DMA_ADDR_NOCHANGE;
    ch_cfg.ctl_dinc         = DMA_ADDR_INCREMENT;
 
    if(data_size == 0x07) {
        ch_cfg.ctl_src_tr_width = DMA_TRANS_WIDTH_8;
        ch_cfg.ctl_dst_tr_width = DMA_TRANS_WIDTH_8;
    } else if(data_size == 0x0f) {
        ch_cfg.ctl_src_tr_width = DMA_TRANS_WIDTH_16;
        ch_cfg.ctl_dst_tr_width = DMA_TRANS_WIDTH_16;
    }
 
    ch_cfg.ctl_tt_fc        = DMA_PRF2MEM_DMA;
 
    ch_cfg.ctl_block_ts     = blockSize;
 
    ch_cfg.cfg_hs_sel_src   = DMA_HS_HARDWARE;
    ch_cfg.cfg_hs_sel_dst   = DMA_HS_HARDWARE;
 
    ch_cfg.cfg_fifo_mode    = DMA_FIFO_MODE_SINGLE;
 
    if(spi_idx == 0)
        ch_cfg.cfg_src_per      = SSI0_DMA_RX_HS_IF10;
    else if(spi_idx == 1)
        ch_cfg.cfg_src_per      = SSI1_DMA_RX_HS_IF11;
    else if(spi_idx == 2)
        ch_cfg.cfg_src_per      = SSI2_DMA_RX_HS_IF14;
 
//    ch_cfg.cfg_ch_prior     = DMAC_PRIORITY_1;
    // Now we can intialise the channel configuration structure for
    // DMA channel 0 by loading the structure members with the
    // contents of the DMAC's channel 0 registers.
    errorCode = xc_dma_set_channel_config(ch_num, &ch_cfg);
    if(errorCode != 0) {
        DEBUG("\nERROR: Failed to initialise configuration\n");
    }
 
    xc_dma_set_listener(ch_num, spi_dma_read_err);
 
    return errorCode;
}
 
void xc_spi_dma_write_and_read(uint8_t spi_idx,
                               eDMA_Ch_Num w_chnum, uint16_t w_size, uint8_t *w_buff,
                               eDMA_Ch_Num r_chnum, uint16_t r_size, uint8_t *r_buff)
{
    uint8_t errorCode;
    
    xc_dma_init( );
    
    errorCode = xc_spi_dma_read_config(spi_idx, r_chnum, r_size, r_buff);
    if(errorCode != 0) {
        DEBUG("\nERROR: Failed SPI_DMAC_Recv_Cfg\n");
    }
    errorCode = xc_spi_dma_write_config(spi_idx, w_chnum, w_size+1, w_buff);  //w_size+1
    if(errorCode != 0) {
        DEBUG("\nERROR: Failed SPI_DMAC_Send_Cfg\n");
    }
 
    xc_dma_enable( );
 
    errorCode = xc_dma_start_transfer(r_chnum, spi_dma_read_callback);
    if(errorCode != 0) {
        DEBUG("\nERROR: Failed DMAC_StartTransfer read\n");
    }
 
    errorCode = xc_dma_start_transfer(w_chnum, spi_dma_write_callback);
    if(errorCode != 0) {
        DEBUG("\nERROR: Failed DMAC_StartTransfer write\n");
    }
 
    xc_dma_mem2prf_finish( );
    xc_dma_prf2mem_finish( );
 
    xc_dma_disable( );
    
    wr_tfr_flag  = false;
    rd_tfr_flag  = false;
    err_flag     = false;
}
 
void xc_spi_dma_read_and_write(uint8_t spi_idx,
                               eDMA_Ch_Num w_chnum, uint16_t w_size, uint8_t *w_buff,
                               eDMA_Ch_Num r_chnum, uint16_t r_size, uint8_t *r_buff)
{
    uint8_t errorCode;
    
    xc_dma_init( );
    
    errorCode = xc_spi_dma_read_config(spi_idx, r_chnum, r_size, r_buff);
    if(errorCode != 0) {
        DEBUG("\nERROR: Failed SPI_DMAC_Recv_Cfg\n");
    }
    errorCode = xc_spi_dma_write_config(spi_idx, w_chnum, w_size+1, w_buff);  //w_size+1
    if(errorCode != 0) {
        DEBUG("\nERROR: Failed SPI_DMAC_Send_Cfg\n");
    }
 
    xc_dma_enable( );
 
    errorCode = xc_dma_start_transfer(r_chnum, spi_dma_read_callback);
    if(errorCode != 0) {
        DEBUG("\nERROR: Failed DMAC_StartTransfer read\n");
    }
 
    errorCode = xc_dma_start_transfer(w_chnum, spi_dma_write_callback);
    if(errorCode != 0) {
        DEBUG("\nERROR: Failed DMAC_StartTransfer write\n");
    }
 
    xc_dma_prf2mem_finish( );
    xc_dma_mem2prf_finish( );
 
    xc_dma_disable( );
    
    wr_tfr_flag  = false;
    rd_tfr_flag  = false;
    err_flag     = false;
}
 
void xc_spi_dma_write(uint8_t spi_idx, eDMA_Ch_Num w_chnum, uint16_t w_size, uint8_t *w_buff)
{
    uint8_t errorCode;
    
    xc_dma_init( );
    
    errorCode = xc_spi_dma_write_config(spi_idx, w_chnum, w_size, w_buff);  //w_size+1
    if(errorCode != 0) {
        DEBUG("\nERROR: Failed SPI_DMAC_Send_Cfg\n");
    }
 
    xc_dma_enable( );
 
    errorCode = xc_dma_start_transfer(w_chnum, spi_dma_write_callback);
    if(errorCode != 0) {
        DEBUG("\nERROR: Failed DMAC_StartTransfer write\n");
    }
 
    xc_dma_mem2prf_finish( );
//    xc_dma_prf2mem_finish( );
 
    xc_dma_disable( );
    
    wr_tfr_flag  = false;
//    rd_tfr_flag  = false;
    err_flag     = false;
}
 
void xc_spi_dma_read(uint8_t spi_idx, eDMA_Ch_Num r_chnum, uint16_t r_size, uint8_t *r_buff)
{
    uint8_t errorCode;
    
    xc_dma_init( );
    
    errorCode = xc_spi_dma_read_config(spi_idx, r_chnum, r_size, r_buff);
    if(errorCode != 0) {
        DEBUG("\nERROR: Failed SPI_DMAC_Send_Cfg\n");
    }
 
    xc_dma_enable( );
 
    errorCode = xc_dma_start_transfer(r_chnum, spi_dma_read_callback);
    if(errorCode != 0) {
        DEBUG("\nERROR: Failed DMAC_StartTransfer read\n");
    }
 
//    xc_dma_mem2prf_finish( );
    xc_dma_prf2mem_finish( );
    
    xc_dma_disable( );
    
//    wr_tfr_flag  = false;
    rd_tfr_flag  = false;
    err_flag     = false;
}
 
void xc_spi_dma_init(uint8_t spi_idx, uint8_t dfs, uint8_t tdl, uint8_t rdl)
{
    spi_en__ssi_sen__setf(spi_idx, DISABLE);
    spi_dmas_pack(spi_idx, ENABLE, ENABLE);
    spi_ctrl0__ssi_dfs__setf(spi_idx, dfs);
    spi_dmatdl_set(spi_idx, tdl);
    spi_dmardl_set(spi_idx, rdl);
    spi_en__ssi_sen__setf(spi_idx, ENABLE);
}
 
void xc_spi_dma_deinit(uint8_t spi_idx)
{
    spi_dmas_pack(spi_idx, DISABLE, DISABLE);
    spi_en__ssi_sen__setf(spi_idx, DISABLE);;
}
 
void xc_spi_dma_write_data(uint8_t spi_idx, uint8_t *data, uint16_t size)
{   
    xc_spi_dma_init(spi_idx, 0x07, 1, 1);
 
    xc_spi_dma_write(spi_idx, DMA_CHANNEL0, size, data);   //DMA_CHANNEL0
 
    xc_spi_dma_deinit(spi_idx);
}
 
void xc_spi_dma_read_data(uint8_t spi_idx, uint8_t *data, uint16_t size)
{
    xc_spi_dma_init(spi_idx, 0x07, 1, 1);
 
    xc_spi_dma_read(spi_idx, DMA_CHANNEL0, size, data);   //DMA_CHANNEL0
 
    xc_spi_dma_deinit(spi_idx);
}
 
void xc_spi_dma_write_and_read_data(uint8_t spi_idx, 
                                    uint8_t *w_data, uint16_t w_size,
                                    uint8_t *r_data, uint16_t r_size)
{
    xc_spi_dma_init(spi_idx, 0x07, 1, 1);
 
    xc_spi_dma_write_and_read(spi_idx,
                              DMA_CHANNEL1, w_size, w_data,
                              DMA_CHANNEL0, r_size, r_data);  //DMA_CHANNEL0
 
    xc_spi_dma_deinit(spi_idx);
}
 
void xc_spi_dma_read_and_write_data(uint8_t spi_idx, 
                                    uint8_t *w_data, uint16_t w_size,
                                    uint8_t *r_data, uint16_t r_size)
{
    xc_spi_dma_init(spi_idx, 0x07, 1, 1);
 
    xc_spi_dma_read_and_write(spi_idx, 
                              DMA_CHANNEL1, w_size, w_data,
                              DMA_CHANNEL0, r_size, r_data);  //DMA_CHANNEL0
 
    xc_spi_dma_deinit(spi_idx);
}
 
 
void xc_spi_dma_flash_power_down(uint8_t spi_idx)
{
    uint8_t cmd[1];
 
    xc_spi_dma_flash_wait_busy(spi_idx);
 
    cmd[0] = CMD_PWRDWN;
 
    xc_spi_dma_init(spi_idx, 0x07, 1, 1);
 
    xc_spi_dma_write(spi_idx, DMA_CHANNEL0, sizeof(cmd), cmd);
 
    xc_spi_dma_deinit(spi_idx);
}
 
void xc_spi_dma_flash_wakeup(uint8_t spi_idx)
{
    uint8_t cmd[1];
 
    xc_spi_dma_flash_wait_busy(spi_idx);
 
    cmd[0] = CMD_RELEASE_PWRDWN;
 
    xc_spi_dma_init(spi_idx, 0x07, 1, 1);
 
    xc_spi_dma_write(spi_idx, DMA_CHANNEL0, sizeof(cmd), cmd);
 
    xc_spi_dma_deinit(spi_idx);
}
 
 
void xc_spi_dma_flash_wait_busy(uint8_t spi_idx)
{
    while( ( xc_spi_dma_flash_read_status(spi_idx) & 0x01 ) );
}
 
void xc_spi_dma_flash_write_enable(uint8_t spi_idx)
{
    uint8_t cmd[1];
    
    xc_spi_dma_flash_wait_busy(spi_idx);
 
    cmd[0] = CMD_WRITE_ENABLE;
 
    xc_spi_dma_init(spi_idx, 0x07, 1, 1);
 
    xc_spi_dma_write(spi_idx, DMA_CHANNEL0, sizeof(cmd), cmd);
 
    xc_spi_dma_deinit(spi_idx);
}
 
void xc_spi_dma_flash_write_disable(uint8_t spi_idx)
{
    uint8_t cmd[1];
 
    xc_spi_dma_flash_wait_busy(spi_idx);
    
    cmd[0] = CMD_WRITE_DISABLE;
 
    xc_spi_dma_init(spi_idx, 0x07, 1, 1);
 
    xc_spi_dma_write(spi_idx, DMA_CHANNEL0, sizeof(cmd), cmd);
 
    xc_spi_dma_deinit(spi_idx);
}
 
void xc_spi_dma_flash_erase_sector(uint8_t spi_idx, uint32_t Dst_Addr)
{
    uint8_t cmd[4] = { 0 };
 
    xc_spi_dma_flash_wait_busy(spi_idx);
    xc_spi_dma_flash_write_enable(spi_idx);
    xc_spi_dma_flash_wait_busy(spi_idx);
 
    cmd[0] = CMD_SECTOR_ERASE;
    cmd[1] = Dst_Addr>>16;
    cmd[2] = Dst_Addr>>8;
    cmd[3] = Dst_Addr;
    
    xc_spi_dma_init(spi_idx, 0x07, 1, 1);
 
    xc_spi_dma_write(spi_idx, DMA_CHANNEL0, sizeof(cmd), cmd);
 
    xc_spi_dma_deinit(spi_idx);
}
 
void xc_spi_dma_flash_erase_page(uint8_t spi_idx, uint32_t Dst_Addr)
{
    uint8_t cmd[4] = { 0 };
    uint32_t mid = 0;
    xc_spi_dma_flash_rdid(spi_idx, (uint8_t*)&mid);
    if(mid != GD_FlASH_RDID){
        xc_spi_dma_flash_wait_busy(spi_idx);
        xc_spi_dma_flash_write_enable(spi_idx);
        xc_spi_dma_flash_wait_busy(spi_idx);
 
        cmd[0] = CMD_PAGE_ERASE;
        cmd[1] = Dst_Addr>>16;
        cmd[2] = Dst_Addr>>8;
        cmd[3] = Dst_Addr;
        
        xc_spi_dma_init(spi_idx, 0x07, 1, 1);
 
        xc_spi_dma_write(spi_idx, DMA_CHANNEL0, sizeof(cmd), cmd);
 
        xc_spi_dma_deinit(spi_idx);        
    }
}
 
 
uint8_t xc_spi_dma_flash_read_status(uint8_t spi_idx)
{
    uint8_t cmd[2] = { 0 };
    uint8_t sta[2] = { 0xff, 0xff };
    
    // memset(sta, 0xff, sizeof(sta));
 
    cmd[0] = CMD_READ_STATUS;
    cmd[1] = 0xff;
    
    xc_spi_dma_init(spi_idx, 0x07, 1, 1);
    
    xc_spi_dma_write_and_read(spi_idx,
                              DMA_CHANNEL1, sizeof(cmd), cmd,
                              DMA_CHANNEL0, sizeof(sta), sta);
 
    xc_spi_dma_deinit(spi_idx);
 
    return sta[1];
}
 
void xc_spi_dma_flash_write_page(uint8_t spi_idx, uint32_t WriteAddr, uint8_t *data, uint16_t size)
{
    uint8_t dts = 0x07;
    uint8_t cmd[FLASH_PAGE_SIZE+4] = { 0 };
 
    if(size > FLASH_PAGE_SIZE)
        return;    
 
    xc_spi_dma_flash_wait_busy(spi_idx);
    xc_spi_dma_flash_write_enable(spi_idx);
    xc_spi_dma_flash_wait_busy(spi_idx);
    
    cmd[0] = CMD_PAGE_PROGRAM;
    cmd[1] = WriteAddr  >> 16;
    cmd[2] = WriteAddr  >> 8;
    cmd[3] = WriteAddr;
 
    dts = 0x07;
    memcpy(&cmd[4], data, FLASH_PAGE_SIZE);
    
    xc_spi_dma_init(spi_idx, dts, 1, 1);
 
    xc_spi_dma_write(spi_idx, DMA_CHANNEL1, FLASH_PAGE_SIZE+4, cmd);
 
    xc_spi_dma_deinit(spi_idx);
}
 
void xc_spi_dma_flash_read_page(uint8_t spi_idx, uint32_t ReadAddr, uint8_t *data, uint16_t size)
{
    uint16_t buad_idx = spi_baud__ssi_sckdv__getf(spi_idx);
    uint8_t dts = 0x07;
    uint8_t cmd[FLASH_PAGE_SIZE+4] = { 0 };
 
    if(size > FLASH_PAGE_SIZE)
        return;
    
    xc_spi_dma_flash_wait_busy(spi_idx);
        
    memset(mid, 0xff, sizeof(mid));
 
    if(buad_idx != SSI_BAUD_DIV_2) {
        cmd[0] = CMD_READ_DATA;
        cmd[1] = ReadAddr  >> 16;
        cmd[2] = ReadAddr  >> 8;
        cmd[3] = ReadAddr;
 
        dts = 0x07;
    } else {
        cmd[0] = ReadAddr  >> 16;
        cmd[1] = CMD_READ_DATA;
        cmd[2] = ReadAddr;
        cmd[3] = ReadAddr  >> 8;
 
        dts = 0x0f;
    }
    
    xc_spi_dma_init(spi_idx, dts, 1, 1);
    
    xc_spi_dma_write_and_read(spi_idx,
                              DMA_CHANNEL0, (FLASH_PAGE_SIZE+4), cmd,
                              DMA_CHANNEL1, (FLASH_PAGE_SIZE+4), mid);
 
    xc_spi_dma_deinit(spi_idx);
 
    if(buad_idx != SSI_BAUD_DIV_2) {
        memcpy(data, mid+4, FLASH_PAGE_SIZE);
    } else {
        for(uint16_t n=0; n<(FLASH_PAGE_SIZE/2); n++)
        {
            data[2*n] = mid[2*n+5];
            data[2*n+1] = mid[2*n+4];
        }
    }      
}
 
eXC_RESULT xc_spi_dma_flash_read(uint8_t spi_idx, uint32_t readAddr, uint8_t *buff, uint16_t len)
{
    eXC_RESULT ret = XR_OK;
    uint16_t ReqPageCnt = 0;        //本次读取数据要占用的页号
    uint16_t CurPageNum = 0;        //本次数据读取所占用的当前页号
    uint16_t CurStartPsr = 0;         //本次地址在 当前页所占的位置
    uint16_t NextPageNum = 0;       //本次数据读取可能 占用到的下一个页号
    uint16_t NextStopPsr = 0;         //本次数据读取可能 占用的下一个页的结束地址
    uint8_t temp_buff[FLASH_PAGE_SIZE] = { 0 };
 
    if(len <= FLASH_PAGE_SIZE)
    {
        CurPageNum = CUR_PAGE_NUM(readAddr);
        CurStartPsr = CUR_START_PSR(readAddr);
        if((len + CurStartPsr) > FLASH_PAGE_SIZE)
            ReqPageCnt = 2;
        else
            ReqPageCnt = 1;
 
        if(ReqPageCnt == 1 )                    //说明这里只读取一个页
        {
            xc_spi_dma_flash_read_page(spi_idx, CurPageNum*FLASH_PAGE_SIZE, temp_buff, FLASH_PAGE_SIZE);
            memcpy(buff, &temp_buff[CurStartPsr], len);
        }
        else if(ReqPageCnt == 2)
        {
            NextPageNum = CurPageNum + 1;
            NextStopPsr = len + CurStartPsr - FLASH_PAGE_SIZE;
            //读取的第一个页
            xc_spi_dma_flash_read_page(spi_idx, CurPageNum*FLASH_PAGE_SIZE, temp_buff, FLASH_PAGE_SIZE);
            memcpy(buff, &temp_buff[CurStartPsr], len-NextStopPsr);
            //读取的第二个页
            uint16_t HaveCopyNum = len - NextStopPsr;
            xc_spi_dma_flash_read_page(spi_idx, NextPageNum*FLASH_PAGE_SIZE, temp_buff, FLASH_PAGE_SIZE);
            memcpy(buff+HaveCopyNum, temp_buff, NextStopPsr);
        }
    }
    else
    {
        CurPageNum = CUR_PAGE_NUM(readAddr);
        CurStartPsr = CUR_START_PSR(readAddr);
        NextPageNum = CurPageNum + 1;
 
        uint16_t buff_idx = 0;
        uint16_t pre_len = NextPageNum*FLASH_PAGE_SIZE - readAddr;
        uint32_t pre_addr = CurPageNum*FLASH_PAGE_SIZE;
        xc_spi_dma_flash_read_page(spi_idx, pre_addr, temp_buff, FLASH_PAGE_SIZE);
        memcpy(buff, &temp_buff[CurStartPsr], pre_len);
        buff_idx += pre_len;
 
        pre_addr = NextPageNum*FLASH_PAGE_SIZE;
        while(buff_idx < len)
        {
            if((len - buff_idx) >= FLASH_PAGE_SIZE)
            {
                xc_spi_dma_flash_read_page(spi_idx, pre_addr, temp_buff, FLASH_PAGE_SIZE);
                memcpy(&buff[buff_idx], temp_buff, FLASH_PAGE_SIZE);
                buff_idx += FLASH_PAGE_SIZE;
                pre_addr += FLASH_PAGE_SIZE;
            }
            else
            {
                xc_spi_dma_flash_read_page(spi_idx, pre_addr, temp_buff, FLASH_PAGE_SIZE);
                memcpy(&buff[buff_idx], temp_buff, len - buff_idx);
                buff_idx += (len - buff_idx);
                pre_addr += (len - buff_idx);
            }
        }
    }
    
    return ret;
}
 
eXC_RESULT xc_spi_dma_flash_write(uint8_t reg_idx, uint32_t writeAddr, uint8_t *buff,
                           uint16_t size)
{
    uint32_t cur_addr = writeAddr;
    uint32_t end_addr = writeAddr + size;
    uint16_t wt_len   = 0;
    // The current page number occupied by this data storage
    uint16_t CurPageNum = 0; 
    uint16_t CurSectorNum = 0; 
    // The position occupied by this address on the current page
    uint32_t CurStartPsr = 0; 
      
    uint32_t mid = 0;
    xc_spi_dma_flash_rdid(reg_idx ,(uint8_t*)&mid);
    
    if(mid != GD_FlASH_RDID){
        uint8_t temp_buff[FLASH_PAGE_SIZE];
        while (cur_addr != end_addr) {
            /* code */
            CurPageNum  = CUR_PAGE_NUM(cur_addr);
            CurStartPsr = CUR_START_PSR(cur_addr);
 
            xc_spi_dma_flash_read_page(reg_idx, CurPageNum * FLASH_PAGE_SIZE, temp_buff, FLASH_PAGE_SIZE);
 
            xc_spi_dma_flash_erase_page(reg_idx, CurPageNum * FLASH_PAGE_SIZE);
 
            if (CurStartPsr) {
                memcpy(&temp_buff[CurStartPsr], buff + wt_len,
                                 (FLASH_PAGE_SIZE  - CurStartPsr) > size - wt_len // 当前扇区剩余的空间是否满足写长度
                                     ? size - wt_len
                                     : (FLASH_PAGE_SIZE  - CurStartPsr));
                wt_len += wt_len + ((FLASH_PAGE_SIZE  - CurStartPsr) > size - wt_len
                                        ? size - wt_len
                                        : (FLASH_PAGE_SIZE  - CurStartPsr));
                cur_addr += wt_len;
            } else {
                memcpy(temp_buff, buff + wt_len,
                                 size - wt_len > FLASH_PAGE_SIZE  ? FLASH_PAGE_SIZE 
                                                                 : size - wt_len);
                cur_addr += (size - wt_len > FLASH_PAGE_SIZE  ? FLASH_PAGE_SIZE 
                                                             : size - wt_len);
                wt_len   += (size - wt_len > FLASH_PAGE_SIZE  ? FLASH_PAGE_SIZE 
                                                             : size - wt_len);
            }
            
            xc_spi_dma_flash_write_page(reg_idx, CurPageNum * FLASH_PAGE_SIZE, temp_buff, FLASH_PAGE_SIZE);
        }
          
    }else if(mid == GD_FlASH_RDID){
        uint8_t temp_buff[FLASH_SECTOR_SIZE];
        while (cur_addr != end_addr) {
            /* code */
            CurSectorNum  = CUR_SECTOR_NUM(cur_addr);
            CurStartPsr = CUR_START_PSR(cur_addr);
            for(int i=0;i<FLASH_SECTOR_SIZE/FLASH_PAGE_SIZE;i++){
                xc_spi_dma_flash_read_page(reg_idx, CurSectorNum * FLASH_SECTOR_SIZE + i* FLASH_PAGE_SIZE, temp_buff+i*FLASH_PAGE_SIZE, FLASH_PAGE_SIZE);
            }
            
            xc_spi_dma_flash_erase_sector(reg_idx ,CurSectorNum * FLASH_SECTOR_SIZE);
 
            if (CurStartPsr) {
                memcpy(&temp_buff[CurStartPsr], buff + wt_len,
                                 (FLASH_SECTOR_SIZE - CurStartPsr) > size - wt_len // 当前扇区剩余的空间是否满足写长度
                                     ? size - wt_len
                                     : (FLASH_SECTOR_SIZE - CurStartPsr));
                wt_len += wt_len + ((FLASH_SECTOR_SIZE - CurStartPsr) > size - wt_len
                                        ? size - wt_len
                                        : (FLASH_SECTOR_SIZE - CurStartPsr));
                cur_addr += wt_len;
            } else {
                memcpy(temp_buff, buff + wt_len,
                                 size - wt_len > FLASH_SECTOR_SIZE ? FLASH_SECTOR_SIZE
                                                                 : size - wt_len);
                cur_addr += (size - wt_len > FLASH_SECTOR_SIZE ? FLASH_SECTOR_SIZE
                                                             : size - wt_len);
                wt_len   += (size - wt_len > FLASH_SECTOR_SIZE ? FLASH_SECTOR_SIZE
                                                             : size - wt_len);
            }
            
            for(int i=0;i<FLASH_SECTOR_SIZE/FLASH_PAGE_SIZE;i++){
                xc_spi_dma_flash_write_page(reg_idx,  CurSectorNum * FLASH_SECTOR_SIZE + i* FLASH_PAGE_SIZE, temp_buff+i*FLASH_PAGE_SIZE, FLASH_PAGE_SIZE); 
            }
        }       
    }
    
    return XR_OK;      
}
 
void xc_spi_dma_flash_rdid(uint8_t spi_idx, uint8_t *rdid)
{
    uint8_t cmd[4] = { 0 };
    uint8_t id[4] = { 0 };
    
    xc_spi_dma_flash_wait_busy(spi_idx);
    
    cmd[0] = CMD_RDID;
    cmd[1] = 0xff;
    cmd[2] = 0xff;
    cmd[3] = 0xff;
    
    xc_spi_dma_init(spi_idx, 0x07, 1, 1);
    
    xc_spi_dma_write_and_read(spi_idx, 
                              DMA_CHANNEL1, sizeof(cmd), cmd,
                              DMA_CHANNEL0, sizeof(id), id);
 
    xc_spi_dma_deinit(spi_idx);
 
    memcpy(rdid, &id[1], 3);
}
 
void xc_spi_dma_flash_ruid(uint8_t spi_idx, uint8_t *ruid)
{
    uint16_t buad_idx = spi_baud__ssi_sckdv__getf(spi_idx);
    uint8_t dts = 0x07;
    uint8_t cmd[22] = { 0 };
    uint8_t id[22] = { 0 };
    
    xc_spi_dma_flash_wait_busy(spi_idx);
 
    if(buad_idx != SSI_BAUD_DIV_2) {
        cmd[0] = CMD_RUID;
        cmd[1] = 0x00;
        cmd[2] = 0x00;
        cmd[3] = 0x00;
        cmd[4] = 0x00;
        
        dts = 0x07;
    } else {
        cmd[0] = 0x00;
        cmd[1] = CMD_RUID;
        cmd[2] = 0x00;
        cmd[3] = 0x00;
        cmd[4] = 0x00;
        cmd[5] = 0x00;
 
        dts = 0x0f;
    }
    
    xc_spi_dma_init(spi_idx, dts, 1, 1);
    
    xc_spi_dma_write_and_read(spi_idx,
                              DMA_CHANNEL1, sizeof(cmd), cmd,
                              DMA_CHANNEL0, sizeof(id), id);
 
    xc_spi_dma_deinit(spi_idx);
 
    if(buad_idx != SSI_BAUD_DIV_2) {
        memcpy(ruid, &id[5], 16);
    } else {
        ruid[0] = id[4];
        ruid[15] = id[21];
        for(uint8_t i=0; i<7; i++)
        {
            ruid[2*i+1] = id[2*i+7];
            ruid[2*i+2] = id[2*i+6];
        }
    }
}