xc_drv_fmc_spi.h

浏览该文件的文档.

 
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __XC_DRV_FMC_SPI_H_
#define __XC_DRV_FMC_SPI_H_
 
/*-----------------------------------------------------------------------------------
                                       INCLUDE HEADE FILES
 ------------------------------------------------------------------------------------*/
 
#include "xc6xxx.h"
 
/*------------------------------------------------------------------------------------
                                       Macros
 -------------------------------------------------------------------------------------*/
#define __RAM_CODE                     __attribute__((section("ram_code")))
 
#define __WRITE_REG32(REG, VAL)        ((*REG) = (VAL))
#define __READ_REG32(REG, VAL)         ((VAL) = (*REG))
#define __SET_BIT(REG, BIT)            ((REG) |= (BIT))
#define __CLEAR_BIT(REG, BIT)          ((REG) &= ~(BIT))
 
#define FMC_SSI_CTRL0_DFS_LEN_4BIT     (0x03UL)
#define FMC_SSI_CTRL0_DFS_LEN_5BIT     (0x04UL)
#define FMC_SSI_CTRL0_DFS_LEN_6BIT     (0x05UL)
#define FMC_SSI_CTRL0_DFS_LEN_7BIT     (0x06UL)
#define FMC_SSI_CTRL0_DFS_LEN_8BIT     (0x07UL)
#define FMC_SSI_CTRL0_DFS_LEN_9BIT     (0x08UL)
#define FMC_SSI_CTRL0_DFS_LEN_10BIT    (0x09UL)
#define FMC_SSI_CTRL0_DFS_LEN_11BIT    (0x0aUL)
#define FMC_SSI_CTRL0_DFS_LEN_12BIT    (0x0bUL)
#define FMC_SSI_CTRL0_DFS_LEN_13BIT    (0x0cUL)
#define FMC_SSI_CTRL0_DFS_LEN_14BIT    (0x0dUL)
#define FMC_SSI_CTRL0_DFS_LEN_15BIT    (0x0eUL)
#define FMC_SSI_CTRL0_DFS_LEN_16BIT    (0x0fUL)
 
#define FMC_SSI_CTRL0_DFS_LEN_17BIT    (0x10UL)
#define FMC_SSI_CTRL0_DFS_LEN_18BIT    (0x11UL)
#define FMC_SSI_CTRL0_DFS_LEN_19BIT    (0x12UL)
#define FMC_SSI_CTRL0_DFS_LEN_20BIT    (0x13UL)
#define FMC_SSI_CTRL0_DFS_LEN_21BIT    (0x14UL)
#define FMC_SSI_CTRL0_DFS_LEN_22BIT    (0x15UL)
#define FMC_SSI_CTRL0_DFS_LEN_23BIT    (0x16UL)
#define FMC_SSI_CTRL0_DFS_LEN_24BIT    (0x17UL)
#define FMC_SSI_CTRL0_DFS_LEN_25BIT    (0x18UL)
#define FMC_SSI_CTRL0_DFS_LEN_26BIT    (0x19UL)
#define FMC_SSI_CTRL0_DFS_LEN_27BIT    (0x1AUL)
#define FMC_SSI_CTRL0_DFS_LEN_28BIT    (0x1BUL)
#define FMC_SSI_CTRL0_DFS_LEN_29BIT    (0x1CUL)
#define FMC_SSI_CTRL0_DFS_LEN_30BIT    (0x1DUL)
#define FMC_SSI_CTRL0_DFS_LEN_31BIT    (0x1EUL)
#define FMC_SSI_CTRL0_DFS_LEN_32BIT    (0x1FUL)
 
#define FMC_SSI_CTRL0_FRF_MOTOROLA     (0x0UL)
#define FMC_SSI_CTRL0_FRF_TI           (0x1UL)
 
#define FMC_SSI_CTRL0_SCPHA_LEAD       (0x0UL)
#define FMC_SSI_CTRL0_SCPHA_TRAIL      (0x1UL)
 
#define FMC_SSI_CTRL0_SCPOL_HIGH       (0x1UL)
#define FMC_SSI_CTRL0_SCPOL_LOW        (0x0UL)
 
#define FMC_SSI_CTRL0_TMOD_WR          (0x0UL)
#define FMC_SSI_CTRL0_TMOD_W           (0x1UL)
#define FMC_SSI_CTRL0_TMOD_R           (0x2UL)
 
#define FMC_SSI_CTRL0_SLV_OE_ENABLE    (0x0UL)
#define FMC_SSI_CTRL0_SLV_OE_DISABLE   (0x1UL)
 
#define FMC_SSI_CTRL0_SRL_NORMAL       (0x0UL)
#define FMC_SSI_CTRL0_SRL_LOOKBACK     (0x1UL)
 
#define FMC_SSI_CTRL0_SSTE_ENABLE      (0x1UL)
#define FMC_SSI_CTRL0_SSTE_DISABLE     (0x0UL)
 
#define FMC_SSI_CTRL0_CFS_SIZE_Bit_01  (0x0UL)
#define FMC_SSI_CTRL0_CFS_SIZE_Bit_02  (0x1UL)
#define FMC_SSI_CTRL0_CFS_SIZE_Bit_03  (0x2UL)
#define FMC_SSI_CTRL0_CFS_SIZE_Bit_04  (0x3UL)
#define FMC_SSI_CTRL0_CFS_SIZE_Bit_05  (0x4UL)
#define FMC_SSI_CTRL0_CFS_SIZE_Bit_06  (0x5UL)
#define FMC_SSI_CTRL0_CFS_SIZE_Bit_07  (0x6UL)
#define FMC_SSI_CTRL0_CFS_SIZE_Bit_08  (0x7UL)
#define FMC_SSI_CTRL0_CFS_SIZE_Bit_09  (0x8UL)
 
#define FMC_SSI_CTRL0_SPI_FRF_STANDARD (0x0UL)
 
#define FMC_SSI_CTRL0_SPI_FRF_DUAL     (0x1UL)
#define FMC_SSI_CTRL0_SPI_FRF_QUAD     (0x2UL)
#define FMC_SSI_CTRL0_SPI_FRF_OCTAL    (0x3UL)
 
#define FMC_SSI_EN_SEN_ENABLE          (0x1UL)
#define FMC_SSI_EN_SEN_DISABLE         (0x0UL)
 
#define FMC_SSI_SE_SS0_SELECT_YES      (0x1UL)
#define FMC_SSI_SE_SS0_SELECT_NO       (0x0UL)
 
#define FMC_SSI_BAUD_DIV_2             (0x02UL)
#define FMC_SSI_BAUD_DIV_4             (0x04UL)
#define FMC_SSI_BAUD_DIV_6             (0x06UL)
#define FMC_SSI_BAUD_DIV_8             (0x08UL)
#define FMC_SSI_BAUD_DIV_10            (0x10UL)
#define FMC_SSI_BAUD_DIV_12            (0x12UL)
 
#define FMC_SSI_TXFTL_FIFO_0           (0x00UL)
#define FMC_SSI_TXFTL_FIFO_1           (0x01UL)
#define FMC_SSI_TXFTL_FIFO_2           (0x02UL)
#define FMC_SSI_TXFTL_FIFO_3           (0x03UL)
#define FMC_SSI_TXFTL_FIFO_4           (0x04UL)
#define FMC_SSI_TXFTL_FIFO_5           (0x05UL)
#define FMC_SSI_TXFTL_FIFO_6           (0x06UL)
#define FMC_SSI_TXFTL_FIFO_7           (0x07UL)
 
#define FMC_SSI_RXFTL_FIFO_0           (0x00UL)
#define FMC_SSI_RXFTL_FIFO_1           (0x01UL)
#define FMC_SSI_RXFTL_FIFO_2           (0x02UL)
#define FMC_SSI_RXFTL_FIFO_3           (0x03UL)
#define FMC_SSI_RXFTL_FIFO_4           (0x04UL)
#define FMC_SSI_RXFTL_FIFO_5           (0x05UL)
#define FMC_SSI_RXFTL_FIFO_6           (0x06UL)
#define FMC_SSI_RXFTL_FIFO_7           (0x07UL)
 
#define FMC_SSI_STS_BUSY_SET           (0x1UL << BUSY_POS)
#define FMC_SSI_STS_BUSY_RESET         (0x0UL << BUSY_POS)
 
#define FMC_SSI_STS_TFNF_SET           (0x1UL << TFNF_POS)
#define FMC_SSI_STS_TFNF_RESET         (0x0UL << TFNF_POS)
 
#define FMC_SSI_STS_TFE_SET            (0x1UL << TFE_POS)
#define FMC_SSI_STS_TFE_RESET          (0x0UL << TFE_POS)
 
#define FMC_SSI_STS_RFNE_SET           (0x1UL << RFNE_POS)
#define FMC_SSI_STS_RFNE_RESET         (0x0UL << RFNE_POS)
 
#define FMC_SSI_STS_RFF_SET            (0x1UL << RFF_POS)
#define FMC_SSI_STS_RFF_RESET          (0x0UL << RFF_POS)
 
#define FMC_SSI_STS_TXE_SET            (0x1UL << TXE_POS)
#define FMC_SSI_STS_TXE_RESET          (0x0UL << TXE_POS)
 
#define FMC_SSI_IE_TXEIE_ENABLE        (0x1UL << TXEIE_POS)
#define FMC_SSI_IE_TXEIE_DISABLE       (0x0UL << TXEIE_POS)
 
#define FMC_SSI_IE_TXOIE_ENABLE        (0x1UL << TXOIE_POS)
#define FMC_SSI_IE_TXOIE_DISABLE       (0x0UL << TXOIE_POS)
 
#define FMC_SSI_IE_RXUIE_ENABLE        (0x1UL << RXUIE_POS)
#define FMC_SSI_IE_RXUIE_DISABLE       (0x0UL << RXUIE_POS)
 
#define FMC_SSI_IE_RXOIE_ENABLE        (0x1UL << RXOIE_POS)
#define FMC_SSI_IE_RXOIE_DISABLE       (0x0UL << RXOIE_POS)
 
#define FMC_SSI_IE_RXFIE_ENABLE        (0x1UL << RXFIE_POS)
#define FMC_SSI_IE_RXFIE_DISABLE       (0x0UL << RXFIE_POS)
 
#define FMC_SSI_IS_TXEIS_SET           (0x1UL << TXEIS_POS)
#define FMC_SSI_IS_TXEIS_RESET         (0x0UL << TXEIS_POS)
 
#define FMC_SSI_IS_TXOIS_SET           (0x1UL << TXOIS_POS)
#define FMC_SSI_IS_TXOIS_RESET         (0x0UL << TXOIS_POS)
 
#define FMC_SSI_IS_RXUIS_SET           (0x1UL << RXUIS_POS)
#define FMC_SSI_IS_RXUIS_RESET         (0x0UL << RXUIS_POS)
 
#define FMC_SSI_IS_RXOIS_SET           (0x1UL << RXOIS_POS)
#define FMC_SSI_IS_RXOIS_RESET         (0x0UL << RXOIS_POS)
 
#define FMC_SSI_SSI_IS_RXFIS_SET       (0x1UL << RXFIS_POS)
#define FMC_SSI_SSI_IS_RXFIS_RESET     (0x0UL << RXFIS_POS)
 
#define FMC_SSI_RIS_TXEIR_SET          (0x1UL << TXEIR_POS)
#define FMC_SSI_RIS_TXEIR_RESET        (0x0UL << TXEIR_POS)
 
#define FMC_SSI_RIS_TXOIR_SET          (0x1UL << TXOIR_POS)
#define FMC_SSI_RIS_TXOIR_RESET        (0x0UL << TXOIR_POS)
 
#define FMC_SSI_RIS_RXUIR_SET          (0x1UL << RXUIR_POS)
#define FMC_SSI_RIS_RXUIR_RESET        (0x0UL << RXUIR_POS)
 
#define FMC_SSI_RIS_RXOIR_SET          (0x1UL << RXOIR_POS)
#define FMC_SSI_RIS_RXOIR_RESET        (0x0UL << RXOIR_POS)
 
#define FMC_SSI_RIS_RXFIR_SET          (0x1UL << RXFIR_POS)
#define FMC_SSI_RIS_RXFIR_RESET        (0x0UL << RXFIR_POS)
 
#define PUYA_FLASH_STATUS_WIP_SET      (0x01UL)
#define PUYA_FLASH_STATUS_WIP_RESET    (0x00UL)
 
#define CMD_READ_DATA                  (uint8_t)0x03
#define CMD_READ_STATUS                (uint8_t)0x05
#define CMD_CHIP_ERASE                 (uint8_t)0xc7
#define CMD_WRITE_ENABLE               (uint8_t)0x06
#define CMD_WRITE_DISABLE              (uint8_t)0x04
#define CMD_PAGE_PROGRAM               (uint8_t)0x02
#define CMD_BLOCK_ERASE                (uint8_t)0xD8
#define CMD_SECTOR_ERASE               (uint8_t)0x20
#define CMD_PAGE_ERASE                 (uint8_t)0x81
#define CMD_RELEASE_PWRDWN             (uint8_t)0xAB
#define CMD_PWRDWN                     (uint8_t)0xB9
#define CMD_RUID                       (uint8_t)0x4B
#define CMD_RDID                       (uint8_t)0x9F
#define CMD_QREMS                      (uint8_t)0x94
#define CMD_WRITE_STATUS_REG           (uint8_t)0x01
 
#define FLASH_PAGE_SIZE                256
#define FLASH_SECTOR_SIZE              4096
 
#define CUR_PAGE_NUM(addr)             (addr / FLASH_PAGE_SIZE)
#define CUR_START_PSR(addr)            (addr % FLASH_PAGE_SIZE)
#define CUR_SECTOR_NUM(addr)           (addr / FLASH_SECTOR_SIZE)
#define CUR_SECTOR_PSR(addr)           (addr % FLASH_SECTOR_SIZE)
 
#define BLE_COMMON_BASE                0x53022000UL
#define BLE_COMN_AGC_REG_OUT0          ((volatile uint32_t *)(BLE_COMMON_BASE + 0x28))
#define FMC_IDLE_STATUS                ((uint32_t)0x01 << 31)
 
 
#define CMD_ERASE_SECURITY_REG        (uint8_t)0x44
#define CMD_READ_SECURITY_REG         (uint8_t)0x48
#define CMD_PROGRAM_SECURITY_REG      (uint8_t)0x42
 
#define OTP_PROGRAM_PAGE_0                (uint8_t)0x0
#define OTP_PROGRAM_PAGE_1                (uint8_t)0x10   
#define OTP_PROGRAM_PAGE_2                (uint8_t)0x20
#define OTP_PROGRAM_PAGE_3                (uint8_t)0x30 
 
#define FLASH_2M_FLAG         0x15
#define FLASH_1M_FLAG         0x14
#define FLASH_512K_FLAG       0x13
#define FLASH_256K_FLAG       0x12
#define FLASH_128K_FLAG       0x11
 
#define FLASH_2M_SIZE         1024*2048
#define FLASH_1M_SIZE         1024*1024
#define FLASH_512K_SIZE       1024*512
#define FLASH_256K_SIZE       1024*256
#define FLASH_128K_SIZE       1024*128
 
#define YOUCUN_FLASH   0x60B3
#define PURAN_128K_FLASH    0x4485
#define GD25WD40_512K_FLASH    0x64C8
 
#define     FLASH_PAGE_SIZE         256 
#define     FLASH_SECTOR_SIZE       4096
 
typedef struct board_c
{
      uint32_t adc2v4_cail;
      uint32_t adc2v4_reverse_verif;  
    uint32_t flash_id;
      uint32_t flash_id_reverse_verif;
    uint32_t ft_rest;
      uint32_t ft_rest_reverse_verif;
    uint32_t chip_cnt;  
      uint32_t chip_cnt_reverse_verif;  
      uint32_t rc_cail;  
      uint32_t rc_cail_reverse_verif;  
}board_card_t;
 
/*------------------------------------------------------------------------------------
                                        Inline Functions
 -------------------------------------------------------------------------------------*/
 
/*------------------------------------------------------------------------------------
                                        Exported Functions
 -------------------------------------------------------------------------------------*/
void xc_fmc_spi_init_oprt(void);
void xc_fmc_spi_flash_power_down(void);
void xc_fmc_spi_flash_wake_up(void);
void xc_fmc_spi_flash_wait_busy(void);
void xc_fmc_spi_flash_write_enable(void);
void xc_fmc_spi_flash_erase_sector(uint32_t addr);
void xc_fmc_spi_flash_erase_page(uint32_t addr);
void xc_fmc_spi_flash_write_page(uint32_t addr, uint8_t *buff,
                                            uint16_t size);
void xc_fmc_spi_flash_read_page(uint32_t addr, uint8_t *buff,
                                           uint16_t size);
void xc_fmc_spi_otp_read_page(uint32_t addr, uint8_t *data,
                                        uint16_t size);
uint8_t xc_fmc_spi_flash_write(uint32_t addr, uint8_t *buff,
                                          uint16_t len);
uint8_t xc_fmc_spi_flash_read(uint32_t addr, uint8_t *buff,
                                         uint16_t len);
void xc_fmc_spi_flash_ruid(uint8_t *ruid);
void xc_fmc_spi_flash_rdid(uint8_t *rdid);
bool flash_size_and_type_get(uint32_t *flash_size, uint16_t *flash_type);
bool xc_adc_2v4_calibrate_read(uint16_t * adc_calibrate);
bool xc_unique_identification_read(uint8_t *unique_id);
 
#endif /* __XC6xxx_FMC_SPI_H_ */