54 cpr_ctlapbclken_grctl__i2c_pclk_en__setf(ENABLE);
56 cpr_rstctl_subrst_sw__i2c_rstn__setf(RSTCTL_ENABLE);
57 cpr_rstctl_subrst_sw__i2c_rstn__setf(RSTCTL_DISABLE);
59 cpr_i2c_clk_ctl__i2c_clk_en__setf(ENABLE);
60 cpr_i2c_clk_ctl__i2c_clk_div__setf(init_cfg->
DivClk);
64 i2c_enable__enable__setf(I2C_ENABLE_EN_DISABLE);
66 i2c_rx_tl__rx_tl__setf(I2C_RX_TL_FIFO_1);
67 i2c_tx_tl__tx_tl__setf(I2C_TX_TL_FIFO_0);
69 i2c_intr_en_set(I2C_INTR_EN_RX_UNDER_DISABLE | I2C_INTR_EN_RX_OVER_DISABLE | I2C_INTR_EN_RX_FULL_DISABLE |
70 I2C_INTR_EN_TX_OVER_DISABLE | I2C_INTR_EN_TX_EMPTY_DISABLE | I2C_INTR_EN_RD_REQ_DISABLE |
71 I2C_INTR_EN_TX_ABRT_DISABLE | I2C_INTR_EN_RX_DONE_DISABLE | I2C_INTR_EN_ACTIVITY_DISABLE |
72 I2C_INTR_EN_STOP_DET_DISABLE | I2C_INTR_EN_START_DET_DISABLE | I2C_INTR_EN_GEN_CALL_DISABLE);
74 i2c_tar__i2c_10bitaddr_master__setf(I2C_TAR_I2C_7BITADDR_MODE);
76 if (init_cfg->
I2C_Mode == I2C_MODE_MASTER) {
79 i2c_con__master_mode__setf(I2C_CON_MASTER_MODE_ENABLE);
80 i2c_con__slave_disable__setf(I2C_CON_SLAVE_DISABLE_DISABLE);
82 }
else if (init_cfg->
I2C_Mode == I2C_MODE_SLAVE) {
84 i2c_con__master_mode__setf(I2C_CON_MASTER_MODE_DISABLE);
85 i2c_con__slave_disable__setf(I2C_CON_SLAVE_DISABLE_ENABLE);
87 i2c_con__addr_10bit_slave__setf(I2C_CON_7BITADDR_SLAVE_MODE);
89 i2c_con__restart_en__setf(I2C_CON_RESTART_EN_DISABLE);
95 i2c_con__speed__setf(I2C_CON_SPEED_STANDARD_MODE);
98 i2c_ss_scl_hcnt__ss_scl_hcnt__setf(I2C_MLCK32M_FREQUENCY_HCNT_100K);
99 i2c_ss_scl_lcnt__ss_scl_lcnt__setf(I2C_MLCK32M_FREQUENCY_LCNT_100K);
101 i2c_ss_scl_hcnt__ss_scl_hcnt__setf(I2C_MLCK48M_FREQUENCY_HCNT_100K);
102 i2c_ss_scl_lcnt__ss_scl_lcnt__setf(I2C_MLCK48M_FREQUENCY_LCNT_100K);
104 i2c_ss_scl_hcnt__ss_scl_hcnt__setf(I2C_MLCK64M_FREQUENCY_HCNT_100K);
105 i2c_ss_scl_lcnt__ss_scl_lcnt__setf(I2C_MLCK64M_FREQUENCY_LCNT_100K);
108 i2c_con__speed__setf(I2C_CON_SPEED_FAST_MODE);
111 i2c_fs_scl_hcnt__fs_scl_hcnt__setf(I2C_MLCK32M_FREQUENCY_HCNT_400K);
112 i2c_fs_scl_lcnt__fs_scl_lcnt__setf(I2C_MLCK32M_FREQUENCY_LCNT_400K);
114 i2c_fs_scl_hcnt__fs_scl_hcnt__setf(I2C_MLCK48M_FREQUENCY_HCNT_400K);
115 i2c_fs_scl_lcnt__fs_scl_lcnt__setf(I2C_MLCK48M_FREQUENCY_LCNT_400K);
118 i2c_fs_scl_hcnt__fs_scl_hcnt__setf(I2C_MLCK64M_FREQUENCY_HCNT_400K);
119 i2c_fs_scl_lcnt__fs_scl_lcnt__setf(I2C_MLCK64M_FREQUENCY_LCNT_400K);
122 i2c_con__speed__setf(I2C_CON_SPEED_FAST_MODE);
125 i2c_fs_scl_hcnt__fs_scl_hcnt__setf(I2C_MLCK32M_FREQUENCY_HCNT_1M);
126 i2c_fs_scl_lcnt__fs_scl_lcnt__setf(I2C_MCLK32M_FREQUENCY_LCNT_1M);
128 i2c_fs_scl_hcnt__fs_scl_hcnt__setf(I2C_MLCK48M_FREQUENCY_HCNT_1M);
129 i2c_fs_scl_lcnt__fs_scl_lcnt__setf(I2C_MCLK48M_FREQUENCY_LCNT_1M);
131 i2c_fs_scl_hcnt__fs_scl_hcnt__setf(I2C_MLCK64M_FREQUENCY_HCNT_1M);
132 i2c_fs_scl_lcnt__fs_scl_lcnt__setf(I2C_MCLK64M_FREQUENCY_LCNT_1M);
138 i2c_enable__enable__setf(I2C_ENABLE_EN_ENABLE);
160 i2c_enable__enable__setf(I2C_ENABLE_EN_DISABLE);
161 i2c_tar__i2c_tar__setf(addr);
162 i2c_enable__enable__setf(I2C_ENABLE_EN_ENABLE);
165uint32_t
xc_i2c_write_block(uint8_t dev_addr, uint8_t *src,
size_t len, uint16_t reset, uint16_t stop)
169 uint32_t abort_reason = 0;
171 uint16_t timeout = 0xFFFF;
173 for (
int i = 0; i < len; i++) {
175 i2c_data_cmd_set(I2C_DATA_CMD_CMD_WRITE | stop | reset | *src++);
179 }
while (timeout-- && !(i2c_raw_intr_stat_get() & I2C_RAW_INTR_STAT_TX_EMPTY_SET));
185 abort_reason = i2c_tx_abrt_source_get();
187 i2c_clr_tx_abrt_get();
195uint32_t
xc_i2c_read_block(uint8_t dev_addr, uint8_t *dst,
size_t len, uint16_t reset, uint16_t stop)
199 uint32_t abort_reason;
200 uint16_t timeout = 0xFFFF;
202 for (
int i = 0; i < len; i++) {
203 while (!(I2C_FIFO_LEN - i2c_txflr_get()))
206 i2c_data_cmd_set(I2C_DATA_CMD_CMD_READ | stop | reset);
210 }
while (timeout-- && !i2c_rxflr_get());
213 DEBUG(
"xc_i2c_read_block timeout\n");
217 abort_reason = i2c_tx_abrt_source_get();
219 DEBUG(
"xc_i2c_read_block tx_abrt\n");
220 i2c_clr_tx_abrt_get();
224 *dst++ = i2c_data_cmd_get();
235 stat = i2c_intr_stat_get();
236 val = i2c_clr_intr_get();
238 if (stat & I2C_INTR_STAT_RX_DONE_SET) {
240 if (stat & I2C_INTR_STAT_RX_FULL_SET) {
241 val = i2c_data_cmd__dat__getf();
247 if (stat & I2C_INTR_STAT_RD_REQ_SET) {
253 if (stat & I2C_INTR_STAT_TX_EMPTY_SET) {
255 if (stat & I2C_INTR_STAT_STOP_DET_SET) {
261 FlagStatus bitstatus = RESET;
263 if ((i2c_status_get() & i2c_flag) != (uint32_t)RESET) {
i2c_write_callback i2c_write_cb
i2c_read_callback i2c_read_cb
CLOCK_HFCLK_In_Typedef xc_clock_hfclk_in_get(void)
xc_clock_hfclk_in_get
void xc_i2c_fifo_txtl_set(uint32_t val)
void xc_i2c_register_write_cb(i2c_write_callback i2c_cb)
FlagStatus i2c_flag_status_get(uint32_t i2c_flag)
uint32_t xc_i2c_read_block(uint8_t dev_addr, uint8_t *dst, size_t len, uint16_t reset, uint16_t stop)
void xc_i2c_init(I2C_InitCfg_t *init_cfg)
void xc_i2c_fifo_rxtl_set(uint32_t val)
void xc_i2c_enable_it(uint32_t val)
void xc_i2c_register_read_cb(i2c_read_callback i2c_cb)
I2C_Block_t i2c_ctl_block
void xc_i2c_ctl_block_reset(void)
uint32_t xc_i2c_write_block(uint8_t dev_addr, uint8_t *src, size_t len, uint16_t reset, uint16_t stop)
void xc_i2c_slave_addr_set(uint8_t addr)
The header of xc_drv_i2c.c
void(* i2c_read_callback)(uint8_t *buff, uint16_t len)
void(* i2c_write_callback)(void)