45 if (dst == NULL || src == NULL || size <= 0)
48 char *pdst = (
char *)dst;
49 char *psrc = (
char *)src;
51 if (pdst > psrc && pdst < psrc + size) {
52 pdst = pdst + size - 1;
53 psrc = psrc + size - 1;
78 __READ_REG32(BLE_COMN_AGC_REG_OUT0, reg);
79 }
while (!(reg & FMC_IDLE_STATUS));
98 uint8_t remain = size % 4;
99 uint16_t cnt = size / 4;
100 uint32_t mid_data[64 + 1] = {0};
103 for (n = 0; n < cnt; n++) {
104 mid_data[n] = ((txdata[n * 4] << 24) | (txdata[n * 4 + 1] << 16) |
105 (txdata[n * 4 + 2] << 8) | txdata[n * 4 + 3]);
110 for (n = 0; n < remain; n++) {
111 mid_data[cnt] |= (txdata[cnt * 4 + n] << (24 - 8 * n));
118 for (n = 0; n < cnt; n++)
119 fmc_data__fmc_dr__setf(mid_data[n]);
121 fmc_data__fmc_dr__setf(mid_data[0]);
124 while (!(fmc_sts_get() & FMC_SSI_STS_TFE_SET) ||
125 (fmc_sts_get() & FMC_SSI_STS_BUSY_SET))
145 uint8_t remain = size % 4;
146 uint16_t cnt = size / 4;
147 uint32_t mid_data = 0;
150 for (n = 0; n < cnt; n++) {
151 mid_data = fmc_data__fmc_dr__getf();
153 rxdata[n * 4] = mid_data >> 24;
154 rxdata[n * 4 + 1] = mid_data >> 16;
155 rxdata[n * 4 + 2] = mid_data >> 8;
156 rxdata[n * 4 + 3] = mid_data;
161 mid_data = fmc_data__fmc_dr__getf();
163 for (n = 0; n < remain; n++) {
164 rxdata[cnt * 4 + n] = mid_data >> 24;
165 rxdata[cnt * 4 + 1 + n] = mid_data >> 16;
166 rxdata[cnt * 4 + 2 + n] = mid_data >> 8;
167 rxdata[cnt * 4 + 3 + n] = mid_data;
171 while (fmc_sts_get() & FMC_SSI_STS_RFNE_SET) {
172 mid_data = fmc_data__fmc_dr__getf();
188 fmc_en__ssic_en__setf(FMC_SSI_EN_SEN_DISABLE);
189 if (dfs != FMC_SSI_CTRL0_DFS_LEN_32BIT) {
190 fmc_ctrl0__dfs__setf(dfs);
193 fmc_en__ssic_en__setf(FMC_SSI_EN_SEN_ENABLE);
208 fmc_en__ssic_en__setf(FMC_SSI_EN_SEN_DISABLE);
209 fmc_ctrl0__dfs__setf(FMC_SSI_CTRL0_DFS_LEN_32BIT);
210 fmc_en__ssic_en__setf(FMC_SSI_EN_SEN_ENABLE);
225 cpr_bt_clk_ctl__bt_clk_en__setf(ENABLE);
227 cpr_bt_modem_clk_ctl__bt_modem_clk_en__setf(ENABLE);
229 cpr_ctlapbclken_grctl__bt_pclk_en__setf(ENABLE);
230 cpr_ssi0_mclk_ctl__ssi_mclk_en__setf(DISABLE);
231 cpr_rstctl_subrst_sw__ssi0_rstn__setf(RSTCTL_ENABLE);
232 cpr_rstctl_subrst_sw__ssi0_rstn__setf(RSTCTL_DISABLE);
236 fmc_en__ssic_en__setf(FMC_SSI_EN_SEN_DISABLE);
238 fmc_ctrl0__sste__setf(FMC_SSI_CTRL0_SSTE_DISABLE);
240 fmc_ctrl0__dfs__setf(FMC_SSI_CTRL0_DFS_LEN_32BIT);
242 fmc_ctrl0__slv_oe__setf(FMC_SSI_CTRL0_SLV_OE_ENABLE);
244 fmc_se__ss0__setf(FMC_SSI_EN_SEN_ENABLE);
246 fmc_ie_set(FMC_SSI_IE_TXEIE_DISABLE | FMC_SSI_IE_TXOIE_DISABLE |
247 FMC_SSI_IE_RXUIE_DISABLE | FMC_SSI_IE_RXOIE_DISABLE |
248 FMC_SSI_IE_RXFIE_DISABLE);
250 fmc_baud__sckdv__setf(FMC_SSI_BAUD_DIV_2);
251 fmc_txftl__tft__setf(FMC_SSI_TXFTL_FIFO_0);
252 fmc_rxftl__rft__setf(FMC_SSI_RXFTL_FIFO_0);
253 fmc_en__ssic_en__setf(FMC_SSI_EN_SEN_ENABLE);
305 cmd[3] = CMD_RELEASE_PWRDWN;
329 uint8_t cmd[2] = {0};
330 uint8_t sta[4] = {0xff, 0xff, 0xff, 0xff};
332 cmd[0] = CMD_READ_STATUS;
377 uint8_t cmd[4] = {0};
382 cmd[3] = CMD_WRITE_ENABLE;
409 uint8_t cmd[4] = {0};
411 cmd[0] = CMD_SECTOR_ERASE;
440 if(
mid != GD_FlASH_RDID){
447 uint8_t cmd[4] = {0};
449 cmd[0] = CMD_PAGE_ERASE;
478 if (size > FLASH_PAGE_SIZE)
481 uint8_t cmd[16 + 4] = {0};
483 for (uint8_t i = 0; i < 16; i++) {
488 cmd[0] = CMD_PAGE_PROGRAM;
523 uint8_t temp_buff[FLASH_PAGE_SIZE] = {0};
524 if (size > FLASH_PAGE_SIZE)
529 uint8_t cmd[16 + 5] = {0};
530 uint8_t
mid[16 + 5] = {0};
533 uint8_t address_h = 0;
534 uint8_t address_l = 0;
535 uint32_t addr_offset=0;
537 for (uint8_t i = 0; i < 3; i++) {
539 address_h = ((addr_offset) & 0x100) >> 8;
540 address_l = addr_offset & 0xff;
542 cmd[0] = CMD_READ_SECURITY_REG;
544 cmd[2] = addr & 0xFE | address_h;
580 if (size > FLASH_PAGE_SIZE)
585 uint8_t cmd[16 + 4] = {0};
586 uint8_t
mid[16 + 4] = {0};
589 for (uint8_t i = 0; i < 16; i++) {
590 cmd[0] = CMD_READ_DATA;
610 uint32_t cur_addr = addr;
611 uint32_t end_addr = addr + size;
614 uint16_t CurPageNum = 0;
615 uint16_t CurSectorNum = 0;
617 uint32_t CurStartPsr = 0;
623 if(
mid != GD_FlASH_RDID){
624 uint8_t temp_buff[FLASH_PAGE_SIZE];
625 while (cur_addr != end_addr) {
627 CurPageNum = CUR_PAGE_NUM(cur_addr);
628 CurStartPsr = CUR_START_PSR(cur_addr);
636 memcpy(&temp_buff[CurStartPsr], buff + wt_len,
637 (FLASH_PAGE_SIZE - CurStartPsr) > size - wt_len
639 : (FLASH_PAGE_SIZE - CurStartPsr));
640 wt_len += wt_len + ((FLASH_PAGE_SIZE - CurStartPsr) > size - wt_len
642 : (FLASH_PAGE_SIZE - CurStartPsr));
645 memcpy(temp_buff, buff + wt_len,
646 size - wt_len > FLASH_PAGE_SIZE ? FLASH_PAGE_SIZE
648 cur_addr += (size - wt_len > FLASH_PAGE_SIZE ? FLASH_PAGE_SIZE
650 wt_len += (size - wt_len > FLASH_PAGE_SIZE ? FLASH_PAGE_SIZE
658 }
else if(
mid == GD_FlASH_RDID){
659 uint8_t temp_buff[FLASH_SECTOR_SIZE] = {0};
660 while (cur_addr != end_addr) {
662 CurSectorNum = CUR_SECTOR_NUM(cur_addr);
663 CurStartPsr = CUR_START_PSR(cur_addr);
665 for(
int i=0;i<FLASH_SECTOR_SIZE/FLASH_PAGE_SIZE;i++){
674 (FLASH_SECTOR_SIZE - CurStartPsr) > size - wt_len
676 : (FLASH_SECTOR_SIZE - CurStartPsr));
677 wt_len += wt_len + ((FLASH_SECTOR_SIZE - CurStartPsr) > size - wt_len
679 : (FLASH_SECTOR_SIZE - CurStartPsr));
683 size - wt_len > FLASH_SECTOR_SIZE ? FLASH_SECTOR_SIZE
685 cur_addr += (size - wt_len > FLASH_SECTOR_SIZE ? FLASH_SECTOR_SIZE
687 wt_len += (size - wt_len > FLASH_SECTOR_SIZE ? FLASH_SECTOR_SIZE
691 for(
int i=0;i<FLASH_SECTOR_SIZE/FLASH_PAGE_SIZE;i++){
717 uint32_t cur_addr = addr;
718 uint32_t end_addr = addr + size;
720 uint16_t CurPageNum = 0;
721 uint32_t CurStartPsr = 0;
722 uint8_t temp_buff[FLASH_PAGE_SIZE] = {0};
724 while (cur_addr != end_addr) {
725 CurPageNum = CUR_PAGE_NUM(cur_addr);
726 CurStartPsr = CUR_START_PSR(cur_addr);
731 (FLASH_PAGE_SIZE - CurStartPsr) > size - rd_len
733 : (FLASH_PAGE_SIZE - CurStartPsr));
734 rd_len += rd_len + ((FLASH_PAGE_SIZE - CurStartPsr) > size - rd_len
736 : (FLASH_PAGE_SIZE - CurStartPsr));
740 size - rd_len > FLASH_PAGE_SIZE ? FLASH_PAGE_SIZE
742 cur_addr += (size - rd_len > FLASH_PAGE_SIZE ? FLASH_PAGE_SIZE
744 rd_len += (size - rd_len > FLASH_PAGE_SIZE ? FLASH_PAGE_SIZE
770 uint8_t cmd[21] = {0};
771 uint8_t
id[21] = {0};
805 uint8_t cmd[4] = {0};
838 uint8_t flash_flag =0;
843 flash_flag = (
mid >> 16) & 0xff;
844 *flash_type = (
mid & 0xffff);
847 case FLASH_128K_FLAG:
848 *flash_size = FLASH_128K_SIZE;
850 case FLASH_256K_FLAG:
851 *flash_size = FLASH_256K_SIZE;
853 case FLASH_512K_FLAG:
854 *flash_size = FLASH_512K_SIZE;
857 *flash_size = FLASH_1M_SIZE;
860 *flash_size = FLASH_2M_SIZE;
880 return ((val >> 8) & 0x0000FF00) |
899 if(value == ~value_reverse_verif)
924 GLOBAL_INT_DISABLE( );
933 if(flash_type == GD25WD40_512K_FLASH)
942 GLOBAL_INT_RESTORE( );
951 GLOBAL_INT_DISABLE( );
952 if(flash_type == GD25WD40_512K_FLASH)
960 GLOBAL_INT_RESTORE( );
988 GLOBAL_INT_DISABLE( );
997 if(flash_type == GD25WD40_512K_FLASH)
1005 GLOBAL_INT_RESTORE( );
1019 GLOBAL_INT_DISABLE( );
1020 if(flash_type == GD25WD40_512K_FLASH)
1028 GLOBAL_INT_RESTORE( );
uint32_t chip_cnt_reverse_verif
uint32_t adc2v4_reverse_verif
uint32_t ft_rest_reverse_verif
uint32_t flash_id_reverse_verif
static volatile uint32_t mid
bool xc_adc_2v4_calibrate_read(uint16_t *adc_calibrate)
xc_adc_2v4_calibrate_read
static __RAM_CODE void xc_fmc_status_wait_idle(void)
xc_fmc_status_wait_idle
__RAM_CODE void xc_fmc_spi_otp_read_page(uint32_t addr, uint8_t *data, uint16_t size)
xc_fmc_spi_flash_read_page
__RAM_CODE void xc_fmc_spi_flash_erase_page(uint32_t addr)
xc_fmc_spi_flash_erase_page
__RAM_CODE void xc_fmc_spi_flash_erase_sector(uint32_t addr)
xc_fmc_spi_flash_erase_sector
bool flash_size_and_type_get(uint32_t *flash_size, uint16_t *flash_type)
flash_size_and_type_get
__RAM_CODE uint8_t xc_fmc_spi_flash_write(uint32_t addr, uint8_t *buff, uint16_t size)
static __RAM_CODE void xc_fmc_spi_flash_write_enable(void)
xc_fmc_spi_flash_write_enable
__RAM_CODE void xc_fmc_spi_flash_rdid(uint8_t *rdid)
xc_fmc_spi_flash_rdid
static __RAM_CODE void xc_fmc_spi_flash_wait_busy(void)
xc_fmc_spi_flash_wait_busy
__RAM_CODE void xc_fmc_spi_init_oprt(void)
xc_fmc_spi_init_oprt
static __RAM_CODE void xc_fmc_spi_read_nbyte(uint8_t *rxdata, uint16_t size)
xc_fmc_spi_read_nbyte
bool xc_unique_identification_read(uint8_t *unique_id)
xc_unique_identification_read
__RAM_CODE void xc_fmc_spi_flash_power_down(void)
xc_fmc_spi_flash_power_down
static __RAM_CODE void xc_fmc_spi_write_nbyte(uint8_t *txdata, uint16_t size)
xc_fmc_spi_write_nbyte
static __RAM_CODE void * ram_memcpy_bytes(void *dst, const void *src, int size)
xc_ram_memcpy_bytes
__RAM_CODE void xc_fmc_spi_flash_read_page(uint32_t addr, uint8_t *data, uint16_t size)
xc_fmc_spi_flash_read_page
__RAM_CODE void xc_fmc_spi_flash_write_page(uint32_t addr, uint8_t *data, uint16_t size)
xc_fmc_spi_flash_write_page
__RAM_CODE void xc_fmc_spi_flash_ruid(uint8_t *ruid)
xc_fmc_spi_flash_ruid
__RAM_CODE void xc_fmc_spi_flash_wake_up(void)
xc_fmc_spi_flash_power_down
static __RAM_CODE uint8_t xc_fmc_spi_flash_status(void)
xc_fmc_spi_flash_status
uint16_t extract32_16(uint32_t val)
extract32_16
static __RAM_CODE void xc_fmc_spi_enable(uint8_t dfs)
xc_fmc_spi_enable
bool reverse_verif_is_true(uint32_t value, uint32_t value_reverse_verif)
reverse_verif_is_true
static __RAM_CODE void xc_fmc_spi_disable(void)
xc_fmc_spi_enable
__RAM_CODE uint8_t xc_fmc_spi_flash_read(uint32_t addr, uint8_t *buff, uint16_t size)
xc_fmc_spi_flash_write
The header of xc_drv_fmc_spi.c