xc_drv_i2c.h

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#ifndef _XC_DRV_I2C_H_
#define _XC_DRV_I2C_H_
 
/*-----------------------------------------------------------------------------------
                                       INCLUDE HEADE FILES
 ------------------------------------------------------------------------------------*/
#include <stdbool.h>
#include <stdio.h>
 
#include "xc6xxx.h"
 
#define I2C_FIFO_LEN          16
 
/* I2C Init structure definition  */
typedef struct
{
 
    uint32_t I2C_ClockSpeed;
 
    uint16_t I2C_Mode;
 
    uint16_t I2C_SlaveAddr;
 
    uint8_t DivClk;
} I2C_InitCfg_t;
 
enum
{
    I2C_FREQUENCY_100K = 0,
    I2C_FREQUENCY_400K = 1,
    I2C_FREQUENCY_1M   = 2,
};
 
typedef void (*i2c_write_callback)(void);
typedef void (*i2c_read_callback)(uint8_t* buff, uint16_t len);
 
typedef struct{
    i2c_read_callback i2c_read_cb;
    i2c_write_callback i2c_write_cb;
} I2C_Block_t;
/*------------------------------------------------------------------------------------
                                             Macros
 -------------------------------------------------------------------------------------*/
 
#define I2C_CON_MASTER_MODE_ENABLE        (0x1UL)
#define I2C_CON_MASTER_MODE_DISABLE       (0x0UL)
 
#define I2C_CON_SPEED_STANDARD_MODE       (0x1UL)
#define I2C_CON_SPEED_FAST_MODE           (0x2UL)
 
#define I2C_CON_10BITADDR_SLAVE_MODE      (0x1UL)
#define I2C_CON_7BITADDR_SLAVE_MODE       (0x0UL)
 
#define I2C_CON_10BITADDR_MASTER_MODE     (0x1UL)
#define I2C_CON_7BITADDR_MASTER_MODE      (0x0UL)
 
#define I2C_CON_RESTART_EN_ENABLE         (0x1UL)
#define I2C_CON_RESTART_EN_DISABLE        (0x0UL)
 
#define I2C_CON_SLAVE_DISABLE_ENABLE      (0x0UL)
#define I2C_CON_SLAVE_DISABLE_DISABLE     (0x1UL)
 
#define I2C_TAR_GC_OR_START_GC            (0x0UL)
#define I2C_TAR_GC_OR_START_Start         (0x1UL)
 
#define I2C_TAR_SPECIA_EXECUTE            (0x1UL)
#define I2C_TAR_SPECIA_IGNORE             (0x0UL)
 
#define I2C_TAR_I2C_10BITADDR_MODE        (0x1UL)
#define I2C_TAR_I2C_7BITADDR_MODE         (0x0UL)
 
#define I2C_DATA_CMD_CMD_READ             (0x1UL << CMD_POS)
#define I2C_DATA_CMD_CMD_WRITE            (0x0UL << CMD_POS)
 
#define I2C_DATA_CMD_STOP_SET             (0x1UL << I2C_STOP_POS)
#define I2C_DATA_CMD_STOP_RESET           (0x0UL << I2C_STOP_POS)
 
#define I2C_DATA_CMD_RESTART_SET          (0x1UL << RESTART_POS)
#define I2C_DATA_CMD_RESTART_RESET        (0x0UL << RESTART_POS)
 
#define I2C_DATA_CMD_DAT_SET              (0x1UL << DAT_LSB)
#define I2C_DATA_CMD_DAT_RESET            (0x0UL << DAT_LSB)
 
#define I2C_MLCK32M_FREQUENCY_HCNT_100K   (0x8EUL)
#define I2C_MLCK32M_FREQUENCY_LCNT_100K   (0x9EUL)
#define I2C_MLCK32M_FREQUENCY_HCNT_400K   (0x18UL)
#define I2C_MLCK32M_FREQUENCY_LCNT_400K   (0x25UL)
#define I2C_MLCK32M_FREQUENCY_HCNT_1M     (0x07UL)
#define I2C_MCLK32M_FREQUENCY_LCNT_1M     (0x0AUL)
 
#define I2C_MLCK48M_FREQUENCY_HCNT_100K   (0xDBUL)
#define I2C_MLCK48M_FREQUENCY_LCNT_100K   (0xEBUL)
#define I2C_MLCK48M_FREQUENCY_HCNT_400K   (0x28UL)
#define I2C_MLCK48M_FREQUENCY_LCNT_400K   (0x38UL)
#define I2C_MLCK48M_FREQUENCY_HCNT_1M     (0x0DUL)
#define I2C_MCLK48M_FREQUENCY_LCNT_1M     (0x0FUL)
 
#define I2C_MLCK64M_FREQUENCY_HCNT_100K   (0x128UL)
#define I2C_MLCK64M_FREQUENCY_LCNT_100K   (0x138UL)
#define I2C_MLCK64M_FREQUENCY_HCNT_400K   (0x39UL)
#define I2C_MLCK64M_FREQUENCY_LCNT_400K   (0x49UL)
#define I2C_MLCK64M_FREQUENCY_HCNT_1M     (0x10UL)
#define I2C_MCLK64M_FREQUENCY_LCNT_1M     (0x14UL)
 
#define I2C_INTR_STAT_RX_UNDER_RESET      (0x0UL << R_RX_UNDER_POS)
#define I2C_INTR_STAT_RX_UNDER_SET        (0x1UL << R_RX_UNDER_POS)
 
#define I2C_INTR_STAT_RX_OVER_RESET       (0x0UL << R_RX_OVER_POS)
#define I2C_INTR_STAT_RX_OVER_SET         (0x1UL << R_RX_OVER_POS)
 
#define I2C_INTR_STAT_RX_FULL_RESET       (0x0UL << R_RX_FULL_POS)
#define I2C_INTR_STAT_RX_FULL_SET         (0x1UL << R_RX_FULL_POS)
 
#define I2C_INTR_STAT_TX_OVER_RESET       (0x0UL << R_TX_OVER_POS)
#define I2C_INTR_STAT_TX_OVER_SET         (0x1UL << R_TX_OVER_POS)
 
#define I2C_INTR_STAT_TX_EMPTY_RESET      (0x0UL << R_TX_EMPTY_POS)
#define I2C_INTR_STAT_TX_EMPTY_SET        (0x1UL << R_TX_EMPTY_POS)
 
#define I2C_INTR_STAT_RD_REQ_RESET        (0x0UL << R_RD_REQ_POS)
#define I2C_INTR_STAT_RD_REQ_SET          (0x1UL << R_RD_REQ_POS)
 
#define I2C_INTR_STAT_TX_ABRT_RESET       (0x0UL << R_TX_ABRT_POS)
#define I2C_INTR_STAT_TX_ABRT_SET         (0x1UL << R_TX_ABRT_POS)
 
#define I2C_INTR_STAT_RX_DONE_RESET       (0x0UL << R_RX_DONE_POS)
#define I2C_INTR_STAT_RX_DONE_SET         (0x1UL << R_RX_DONE_POS)
 
#define I2C_INTR_STAT_ACTIVITY_RESET      (0x0UL << R_ACTIVITY_POS)
#define I2C_INTR_STAT_ACTIVITY_SET        (0x1UL << R_ACTIVITY_POS)
 
#define I2C_INTR_STAT_STOP_DET_RESET      (0x0UL << R_STOP_DET_POS)
#define I2C_INTR_STAT_STOP_DET_SET        (0x1UL << R_STOP_DET_POS)
 
#define I2C_INTR_STAT_START_DET_RESET     (0x1UL << R_START_DET_POS)
#define I2C_INTR_STAT_START_DET_SET       (0x1UL << R_START_DET_POS)
 
#define I2C_INTR_STAT_GEN_CALL_RESET      (0x0UL << R_GEN_CALL_POS)
#define I2C_INTR_STAT_GEN_CALL_SET        (0x1UL << R_GEN_CALL_POS)
 
#define I2C_INTR_EN_RX_UNDER_DISABLE      (0x0UL << EN_RX_UNDER_POS)
#define I2C_INTR_EN_RX_UNDER_ENABLE       (0x1UL << EN_RX_UNDER_POS)
 
#define I2C_INTR_EN_RX_OVER_DISABLE       (0x0UL << EN_RX_OVER_POS)
#define I2C_INTR_EN_RX_OVER_ENABLE        (0x1UL << EN_RX_OVER_POS)
 
#define I2C_INTR_EN_RX_FULL_DISABLE       (0x0UL << EN_RX_FULL_POS)
#define I2C_INTR_EN_RX_FULL_ENABLE        (0x1UL << EN_RX_FULL_POS)
 
#define I2C_INTR_EN_TX_OVER_DISABLE       (0x0UL << EN_TX_OVER_POS)
#define I2C_INTR_EN_TX_OVER_ENABLE        (0x1UL << EN_TX_OVER_POS)
 
#define I2C_INTR_EN_TX_EMPTY_DISABLE      (0x0UL << EN_TX_EMPTY_POS)
#define I2C_INTR_EN_TX_EMPTY_ENABLE       (0x1UL << EN_TX_EMPTY_POS)
 
#define I2C_INTR_EN_RD_REQ_DISABLE        (0x0UL << EN_RD_REQ_POS)
#define I2C_INTR_EN_RD_REQ_ENABLE         (0x1UL << EN_RD_REQ_POS)
 
#define I2C_INTR_EN_TX_ABRT_DISABLE       (0x0UL << EN_TX_ABRT_POS)
#define I2C_INTR_EN_TX_ABRT_ENABLE        (0x1UL << EN_TX_ABRT_POS)
 
#define I2C_INTR_EN_RX_DONE_DISABLE       (0x0UL << EN_RX_DONE_POS)
#define I2C_INTR_EN_RX_DONE_ENABLE        (0x1UL << EN_RX_DONE_POS)
 
#define I2C_INTR_EN_ACTIVITY_DISABLE      (0x0UL << EN_ACTIVITY_POS)
#define I2C_INTR_EN_ACTIVITY_ENABLE       (0x1UL << EN_ACTIVITY_POS)
 
#define I2C_INTR_EN_STOP_DET_DISABLE      (0x0UL << EN_STOP_DET_POS)
#define I2C_INTR_EN_STOP_DET_ENABLE       (0x1UL << EN_STOP_DET_POS)
 
#define I2C_INTR_EN_START_DET_DISABLE     (0x0UL << EN_START_DET_POS)
#define I2C_INTR_EN_START_DET_ENABLE      (0x1UL << EN_START_DET_POS)
 
#define I2C_INTR_EN_GEN_CALL_DISABLE      (0x0UL << EN_GEN_CALL_POS)
#define I2C_INTR_EN_GEN_CALL_ENABLE       (0x1UL << EN_GEN_CALL_POS)
 
#define I2C_RAW_INTR_STAT_RX_UNDER_RESET  (0x0UL << RX_UNDER_POS)
#define I2C_RAW_INTR_STAT_RX_UNDERL_SET   (0x1UL << RX_UNDER_POS)
 
#define I2C_RAW_INTR_STAT_RX_OVER_RESET   (0x0UL << RX_OVER_POS)
#define I2C_RAW_INTR_STAT_RX_OVER_SET     (0x1UL << RX_OVER_POS)
 
#define I2C_RAW_INTR_STAT_RX_FULL_RESET   (0x0UL << RX_FULL_POS)
#define I2C_RAW_INTR_STAT_RX_FULL_SET     (0x1UL << RX_FULL_POS)
 
#define I2C_RAW_INTR_STAT_TX_OVER_RESET   (0x0UL << TX_OVER_POS)
#define I2C_RAW_INTR_STAT_TX_OVER_SET     (0x1UL << TX_OVER_POS)
 
#define I2C_RAW_INTR_STAT_TX_EMPTY_RESET  (0x0UL << TX_EMPTY_POS)
#define I2C_RAW_INTR_STAT_TX_EMPTY_SET    (0x1UL << TX_EMPTY_POS)
 
#define I2C_RAW_INTR_STAT_RD_REQ_RESET    (0x0UL << RD_REQ_POS)
#define I2C_RAW_INTR_STAT_RD_REQ_SET      (0x1UL << RD_REQ_POS)
 
#define I2C_RAW_INTR_STAT_TX_ABRT_RESET   (0x0UL << TX_ABRT_POS)
#define I2C_RAW_INTR_STAT_TX_ABRT_SET     (0x1UL << TX_ABRT_POS)
 
#define I2C_RAW_INTR_STAT_RX_DONE_RESET   (0x0UL << RX_DONE_POS)
#define I2C_RAW_INTR_STAT_RX_DONE_SET     (0x1UL << RX_DONE_POS)
 
#define I2C_RAW_INTR_STAT_ACTIVITY_RESET  (0x0UL << ACTIVITY_POS)
#define I2C_RAW_INTR_STAT_ACTIVITY_SET    (0x1UL << ACTIVITY_POS)
 
#define I2C_RAW_INTR_STAT_STOP_DET_RESET  (0x0UL << STOP_DET_POS)
#define I2C_RAW_INTR_STAT_STOP_DET_SET    (0x1UL << STOP_DET_POS)
 
#define I2C_RAW_INTR_STAT_START_DET_RESET (0x0UL << START_DET_POS)
#define I2C_RAW_INTR_STAT_START_DET_SET   (0x1UL << START_DET_POS)
 
#define I2C_RAW_INTR_STAT_GEN_CALL_RESET  (0x0UL << GEN_CALL_POS)
#define I2C_RAW_INTR_STAT_GEN_CALL_SET    (0x1UL << GEN_CALL_POS)
 
#define I2C_RX_TL_FIFO_1                  (0x0UL)
#define I2C_RX_TL_FIFO_2                  (0x1UL)
#define I2C_RX_TL_FIFO_3                  (0x2UL)
#define I2C_RX_TL_FIFO_4                  (0x3UL)
#define I2C_RX_TL_FIFO_5                  (0x4UL)
#define I2C_RX_TL_FIFO_6                  (0x5UL)
#define I2C_RX_TL_FIFO_7                  (0x6UL)
#define I2C_RX_TL_FIFO_8                  (0x7UL)
#define I2C_RX_TL_FIFO_9                  (0x8UL)
#define I2C_RX_TL_FIFO_10                 (0x9UL)
#define I2C_RX_TL_FIFO_11                 (0xAUL)
#define I2C_RX_TL_FIFO_12                 (0xBUL)
#define I2C_RX_TL_FIFO_13                 (0xCUL)
#define I2C_RX_TL_FIFO_14                 (0xDUL)
#define I2C_RX_TL_FIFO_15                 (0xEUL)
#define I2C_RX_TL_FIFO_16                 (0xFUL)
 
#define I2C_TX_TL_FIFO_0                  (0x0UL)
#define I2C_TX_TL_FIFO_1                  (0x1UL)
#define I2C_TX_TL_FIFO_2                  (0x2UL)
#define I2C_TX_TL_FIFO_3                  (0x3UL)
#define I2C_TX_TL_FIFO_4                  (0x4UL)
#define I2C_TX_TL_FIFO_5                  (0x5UL)
#define I2C_TX_TL_FIFO_6                  (0x6UL)
#define I2C_TX_TL_FIFO_7                  (0x7UL)
#define I2C_TX_TL_FIFO_8                  (0x8UL)
#define I2C_TX_TL_FIFO_9                  (0x9UL)
#define I2C_TX_TL_FIFO_10                 (0xAUL)
#define I2C_TX_TL_FIFO_11                 (0xBUL)
#define I2C_TX_TL_FIFO_12                 (0xCUL)
#define I2C_TX_TL_FIFO_13                 (0xDUL)
#define I2C_TX_TL_FIFO_14                 (0xEUL)
#define I2C_TX_TL_FIFO_15                 (0xFUL)
 
#define I2C_ENABLE_EN_DISABLE             (0x0UL)
#define I2C_ENABLE_EN_ENABLE              (0x1UL)
 
#define I2C_STATUS_ACTIVITY_RESET         (0x0UL << I2C_ACTIVITY_POS)
#define I2C_STATUS_ACTIVITY_SET           (0x1UL << I2C_ACTIVITY_POS)
 
#define I2C_STATUS_TFNF_RESET             (0x0UL << TFNF_POS)
#define I2C_STATUS_TFNF_SET               (0x1UL << TFNF_POS)
 
#define I2C_STATUS_TFE_RESET              (0x0UL << TFE_POS)
#define I2C_STATUS_TFE_SET                (0x1UL << TFE_POS)
 
#define I2C_STATUS_RFNE_RESET             (0x0UL << RFNE_POS)
#define I2C_STATUS_RFNE_SET               (0x1UL << RFNE_POS)
 
#define I2C_STATUS_RFF_RESET              (0x0UL << RFF_POS)
#define I2C_STATUS_RFF_SET                (0x1UL << RFF_POS)
 
#define I2C_STATUS_MST_ACTIVITY_RESET     (0x0UL << 5)
#define I2C_STATUS_MST_ACTIVITY_SET       (0x1UL << 5)
 
 
 
#define I2C_MODE_MASTER                   I2C_CON_MASTER_MODE_ENABLE
#define I2C_MODE_SLAVE                    I2C_CON_SLAVE_DISABLE_ENABLE
 
#define I2C_CLOCK_SPEED_100K              I2C_FREQUENCY_100K
#define I2C_CLOCK_SPEED_400K              I2C_FREQUENCY_400K
#define I2C_CLOCK_SPEED_1M                I2C_FREQUENCY_1M
 
void xc_i2c_init(I2C_InitCfg_t *i2c_cfg);
void xc_i2c_enable_it(uint32_t val);
void xc_i2c_fifo_rxtl_set(uint32_t val);
void xc_i2c_fifo_txtl_set(uint32_t val);
 
FlagStatus i2c_flag_status_get(uint32_t i2c_flag);
void xc_i2c_register_read_cb(i2c_read_callback i2c_cb);
void xc_i2c_register_write_cb(i2c_write_callback i2c_cb);
 
uint32_t xc_i2c_write_block(uint8_t dev_addr, uint8_t *src, size_t len, uint16_t reset, uint16_t stop);
uint32_t xc_i2c_read_block(uint8_t dev_addr, uint8_t *dst, size_t len, uint16_t reset, uint16_t stop);
#endif