BLE5.2 1.0
开发文档说明
xc_drv_fmc_spi.c
浏览该文件的文档.
1
25/*-----------------------------------------------------------------------------------
26 INCLUDE HEADE FILES
27 ------------------------------------------------------------------------------------*/
28#include "xc_drv_fmc_spi.h"
29
30/*------------------------------------------------------------------------------------
31 Functions
32 -------------------------------------------------------------------------------------*/
43__RAM_CODE static void *ram_memcpy_bytes(void *dst, const void *src, int size)
44{
45 if (dst == NULL || src == NULL || size <= 0)
46 return NULL;
47
48 char *pdst = (char *)dst;
49 char *psrc = (char *)src;
50
51 if (pdst > psrc && pdst < psrc + size) {
52 pdst = pdst + size - 1;
53 psrc = psrc + size - 1;
54 while (size--)
55 *pdst-- = *psrc--;
56 } else {
57 while (size--)
58 *pdst++ = *psrc++;
59 }
60
61 return dst;
62}
63
74__RAM_CODE static void xc_fmc_status_wait_idle(void)
75{
76 uint32_t reg = 0;
77 do {
78 __READ_REG32(BLE_COMN_AGC_REG_OUT0, reg);
79 } while (!(reg & FMC_IDLE_STATUS));
80}
81
92__RAM_CODE static void xc_fmc_spi_write_nbyte(uint8_t *txdata, uint16_t size)
93{
94 if (size == 0)
95 return;
96
97 uint16_t n;
98 uint8_t remain = size % 4;
99 uint16_t cnt = size / 4;
100 uint32_t mid_data[64 + 1] = {0};
101
102 if (cnt != 0) {
103 for (n = 0; n < cnt; n++) {
104 mid_data[n] = ((txdata[n * 4] << 24) | (txdata[n * 4 + 1] << 16) |
105 (txdata[n * 4 + 2] << 8) | txdata[n * 4 + 3]);
106 }
107 }
108
109 if (remain != 0) {
110 for (n = 0; n < remain; n++) {
111 mid_data[cnt] |= (txdata[cnt * 4 + n] << (24 - 8 * n));
112 }
113 }
114
115 if (cnt != 0) {
116 if (remain != 0)
117 cnt = cnt + 1;
118 for (n = 0; n < cnt; n++)
119 fmc_data__fmc_dr__setf(mid_data[n]);
120 } else {
121 fmc_data__fmc_dr__setf(mid_data[0]);
122 }
123
124 while (!(fmc_sts_get() & FMC_SSI_STS_TFE_SET) ||
125 (fmc_sts_get() & FMC_SSI_STS_BUSY_SET))
126 ;
127}
128
139__RAM_CODE static void xc_fmc_spi_read_nbyte(uint8_t *rxdata, uint16_t size)
140{
141 if (size == 0)
142 return;
143
144 uint16_t n;
145 uint8_t remain = size % 4;
146 uint16_t cnt = size / 4;
147 uint32_t mid_data = 0;
148
149 if (cnt != 0) {
150 for (n = 0; n < cnt; n++) {
151 mid_data = fmc_data__fmc_dr__getf();
152
153 rxdata[n * 4] = mid_data >> 24;
154 rxdata[n * 4 + 1] = mid_data >> 16;
155 rxdata[n * 4 + 2] = mid_data >> 8;
156 rxdata[n * 4 + 3] = mid_data;
157 }
158 }
159
160 if (remain != 0) {
161 mid_data = fmc_data__fmc_dr__getf();
162
163 for (n = 0; n < remain; n++) {
164 rxdata[cnt * 4 + n] = mid_data >> 24;
165 rxdata[cnt * 4 + 1 + n] = mid_data >> 16;
166 rxdata[cnt * 4 + 2 + n] = mid_data >> 8;
167 rxdata[cnt * 4 + 3 + n] = mid_data;
168 }
169 }
170
171 while (fmc_sts_get() & FMC_SSI_STS_RFNE_SET) {
172 mid_data = fmc_data__fmc_dr__getf();
173 }
174}
175
186__RAM_CODE static void xc_fmc_spi_enable(uint8_t dfs)
187{
188 fmc_en__ssic_en__setf(FMC_SSI_EN_SEN_DISABLE);
189 if (dfs != FMC_SSI_CTRL0_DFS_LEN_32BIT) {
190 fmc_ctrl0__dfs__setf(dfs);
191 }
192
193 fmc_en__ssic_en__setf(FMC_SSI_EN_SEN_ENABLE);
194}
195
206__RAM_CODE static void xc_fmc_spi_disable(void)
207{
208 fmc_en__ssic_en__setf(FMC_SSI_EN_SEN_DISABLE);
209 fmc_ctrl0__dfs__setf(FMC_SSI_CTRL0_DFS_LEN_32BIT);
210 fmc_en__ssic_en__setf(FMC_SSI_EN_SEN_ENABLE);
211}
212
223__RAM_CODE void xc_fmc_spi_init_oprt(void)
224{
225 cpr_bt_clk_ctl__bt_clk_en__setf(ENABLE);
226
227 cpr_bt_modem_clk_ctl__bt_modem_clk_en__setf(ENABLE);
228
229 cpr_ctlapbclken_grctl__bt_pclk_en__setf(ENABLE);
230 cpr_ssi0_mclk_ctl__ssi_mclk_en__setf(DISABLE);
231 cpr_rstctl_subrst_sw__ssi0_rstn__setf(RSTCTL_ENABLE);
232 cpr_rstctl_subrst_sw__ssi0_rstn__setf(RSTCTL_DISABLE);
233
235
236 fmc_en__ssic_en__setf(FMC_SSI_EN_SEN_DISABLE);
237
238 fmc_ctrl0__sste__setf(FMC_SSI_CTRL0_SSTE_DISABLE);
239
240 fmc_ctrl0__dfs__setf(FMC_SSI_CTRL0_DFS_LEN_32BIT);
241
242 fmc_ctrl0__slv_oe__setf(FMC_SSI_CTRL0_SLV_OE_ENABLE);
243
244 fmc_se__ss0__setf(FMC_SSI_EN_SEN_ENABLE);
245
246 fmc_ie_set(FMC_SSI_IE_TXEIE_DISABLE | FMC_SSI_IE_TXOIE_DISABLE |
247 FMC_SSI_IE_RXUIE_DISABLE | FMC_SSI_IE_RXOIE_DISABLE |
248 FMC_SSI_IE_RXFIE_DISABLE);
249
250 fmc_baud__sckdv__setf(FMC_SSI_BAUD_DIV_2);
251 fmc_txftl__tft__setf(FMC_SSI_TXFTL_FIFO_0);
252 fmc_rxftl__rft__setf(FMC_SSI_RXFTL_FIFO_0);
253 fmc_en__ssic_en__setf(FMC_SSI_EN_SEN_ENABLE);
254}
255
268__RAM_CODE void xc_fmc_spi_flash_power_down(void)
269{
271
272 uint8_t cmd[4];
273
274 cmd[0] = 0;
275 cmd[1] = 0;
276 cmd[2] = 0;
277 cmd[3] = CMD_PWRDWN;
278
279 xc_fmc_spi_enable(FMC_SSI_CTRL0_DFS_LEN_8BIT);
280 xc_fmc_spi_write_nbyte(cmd, sizeof(cmd));
282}
283
296__RAM_CODE void xc_fmc_spi_flash_wake_up(void)
297{
299
300 uint8_t cmd[4];
301
302 cmd[0] = 0;
303 cmd[1] = 0;
304 cmd[2] = 0;
305 cmd[3] = CMD_RELEASE_PWRDWN;
306
307 xc_fmc_spi_enable(FMC_SSI_CTRL0_DFS_LEN_8BIT);
308 xc_fmc_spi_write_nbyte(cmd, sizeof(cmd));
309
311}
312
325__RAM_CODE static uint8_t xc_fmc_spi_flash_status(void)
326{
328
329 uint8_t cmd[2] = {0};
330 uint8_t sta[4] = {0xff, 0xff, 0xff, 0xff};
331
332 cmd[0] = CMD_READ_STATUS;
333 cmd[1] = 0xff;
334
335 xc_fmc_spi_enable(FMC_SSI_CTRL0_DFS_LEN_32BIT);
336 xc_fmc_spi_write_nbyte(cmd, sizeof(cmd));
337 xc_fmc_spi_read_nbyte(sta, sizeof(sta));
339
340 return sta[1];
341}
342
355__RAM_CODE static void xc_fmc_spi_flash_wait_busy(void)
356{
357 while ((xc_fmc_spi_flash_status() & PUYA_FLASH_STATUS_WIP_SET))
358 ;
359}
360
373__RAM_CODE static void xc_fmc_spi_flash_write_enable(void)
374{
376
377 uint8_t cmd[4] = {0};
378
379 cmd[0] = 0;
380 cmd[1] = 0;
381 cmd[2] = 0;
382 cmd[3] = CMD_WRITE_ENABLE;
383
384 xc_fmc_spi_enable(FMC_SSI_CTRL0_DFS_LEN_8BIT);
385 xc_fmc_spi_write_nbyte(cmd, sizeof(cmd));
387}
388
401__RAM_CODE void xc_fmc_spi_flash_erase_sector(uint32_t addr)
402{
404
408
409 uint8_t cmd[4] = {0};
410
411 cmd[0] = CMD_SECTOR_ERASE;
412 cmd[1] = addr >> 16;
413 cmd[2] = addr >> 8;
414 cmd[3] = addr;
415
416 xc_fmc_spi_enable(FMC_SSI_CTRL0_DFS_LEN_32BIT);
417 xc_fmc_spi_write_nbyte(cmd, sizeof(cmd));
419
421}
422
435__RAM_CODE void xc_fmc_spi_flash_erase_page(uint32_t addr)
436{
437 uint32_t mid = 0;
438 xc_fmc_spi_flash_rdid((uint8_t*)&mid);
439
440 if(mid != GD_FlASH_RDID){
442
446
447 uint8_t cmd[4] = {0};
448
449 cmd[0] = CMD_PAGE_ERASE;
450 cmd[1] = addr >> 16;
451 cmd[2] = addr >> 8;
452 cmd[3] = addr;
453
454 xc_fmc_spi_enable(FMC_SSI_CTRL0_DFS_LEN_32BIT);
455 xc_fmc_spi_write_nbyte(cmd, sizeof(cmd));
457
459 }
460}
461
475__RAM_CODE void xc_fmc_spi_flash_write_page(uint32_t addr, uint8_t *data,
476 uint16_t size)
477{
478 if (size > FLASH_PAGE_SIZE)
479 return;
480
481 uint8_t cmd[16 + 4] = {0};
482
483 for (uint8_t i = 0; i < 16; i++) {
487
488 cmd[0] = CMD_PAGE_PROGRAM;
489 cmd[1] = addr >> 16;
490 cmd[2] = addr >> 8;
491 cmd[3] = addr;
492
493 ram_memcpy_bytes(&cmd[4], data + i * 16, 16);
494
496
497 xc_fmc_spi_enable(FMC_SSI_CTRL0_DFS_LEN_32BIT);
498 xc_fmc_spi_write_nbyte(cmd, sizeof(cmd));
499
500 addr += 16;
501 }
502
505}
506
507
520__RAM_CODE void xc_fmc_spi_otp_read_page(uint32_t addr, uint8_t *data,
521 uint16_t size)
522{
523 uint8_t temp_buff[FLASH_PAGE_SIZE] = {0};
524 if (size > FLASH_PAGE_SIZE)
525 return;
526
528
529 uint8_t cmd[16 + 5] = {0};
530 uint8_t mid[16 + 5] = {0};
531 uint16_t rx_idx = 0;
532
533 uint8_t address_h = 0;
534 uint8_t address_l = 0;
535 uint32_t addr_offset=0;
536
537 for (uint8_t i = 0; i < 3; i++) {
538
539 address_h = ((addr_offset) & 0x100) >> 8;
540 address_l = addr_offset & 0xff;
541
542 cmd[0] = CMD_READ_SECURITY_REG;
543 cmd[1] = 0X00;
544 cmd[2] = addr & 0xFE | address_h;
545 cmd[3] = address_l;
546 cmd[4] = 0xff;
547
548 xc_fmc_spi_enable(FMC_SSI_CTRL0_DFS_LEN_32BIT);
549 xc_fmc_spi_write_nbyte(cmd, sizeof(cmd));
550 xc_fmc_spi_read_nbyte(mid, sizeof(cmd));
551
552 ram_memcpy_bytes(&temp_buff[rx_idx], mid + 5, 16);
553 addr_offset += 16;
554 rx_idx += 16;
555 }
557
558 ram_memcpy_bytes(data,temp_buff,size);
559}
560
561
562
563
564
577__RAM_CODE void xc_fmc_spi_flash_read_page(uint32_t addr, uint8_t *data,
578 uint16_t size)
579{
580 if (size > FLASH_PAGE_SIZE)
581 return;
582
584
585 uint8_t cmd[16 + 4] = {0};
586 uint8_t mid[16 + 4] = {0};
587 uint16_t rx_idx = 0;
588
589 for (uint8_t i = 0; i < 16; i++) {
590 cmd[0] = CMD_READ_DATA;
591 cmd[1] = addr >> 16;
592 cmd[2] = addr >> 8;
593 cmd[3] = addr;
594
595 xc_fmc_spi_enable(FMC_SSI_CTRL0_DFS_LEN_32BIT);
596 xc_fmc_spi_write_nbyte(cmd, sizeof(cmd));
597 xc_fmc_spi_read_nbyte(mid, sizeof(cmd));
598
599 ram_memcpy_bytes(&data[rx_idx], mid + 4, 16);
600 addr += 16;
601 rx_idx += 16;
602 }
603
605}
606
607__RAM_CODE uint8_t xc_fmc_spi_flash_write(uint32_t addr, uint8_t *buff,
608 uint16_t size)
609{
610 uint32_t cur_addr = addr;
611 uint32_t end_addr = addr + size;
612 uint16_t wt_len = 0;
613 // The current page number occupied by this data storage
614 uint16_t CurPageNum = 0;
615 uint16_t CurSectorNum = 0;
616 // The position occupied by this address on the current page
617 uint32_t CurStartPsr = 0;
618
619
620 uint32_t mid = 0;
621 xc_fmc_spi_flash_rdid((uint8_t*)&mid);
622
623 if(mid != GD_FlASH_RDID){
624 uint8_t temp_buff[FLASH_PAGE_SIZE];
625 while (cur_addr != end_addr) {
626 /* code */
627 CurPageNum = CUR_PAGE_NUM(cur_addr);
628 CurStartPsr = CUR_START_PSR(cur_addr);
629
630 xc_fmc_spi_flash_read_page(CurPageNum * FLASH_PAGE_SIZE, temp_buff,
631 FLASH_PAGE_SIZE);
632 xc_fmc_spi_flash_erase_page(CurPageNum * FLASH_PAGE_SIZE);
633
634
635 if (CurStartPsr) {
636 memcpy(&temp_buff[CurStartPsr], buff + wt_len,
637 (FLASH_PAGE_SIZE - CurStartPsr) > size - wt_len // 当前扇区剩余的空间是否满足写长度
638 ? size - wt_len
639 : (FLASH_PAGE_SIZE - CurStartPsr));
640 wt_len += wt_len + ((FLASH_PAGE_SIZE - CurStartPsr) > size - wt_len
641 ? size - wt_len
642 : (FLASH_PAGE_SIZE - CurStartPsr));
643 cur_addr += wt_len;
644 } else {
645 memcpy(temp_buff, buff + wt_len,
646 size - wt_len > FLASH_PAGE_SIZE ? FLASH_PAGE_SIZE
647 : size - wt_len);
648 cur_addr += (size - wt_len > FLASH_PAGE_SIZE ? FLASH_PAGE_SIZE
649 : size - wt_len);
650 wt_len += (size - wt_len > FLASH_PAGE_SIZE ? FLASH_PAGE_SIZE
651 : size - wt_len);
652 }
653
654 xc_fmc_spi_flash_write_page(CurPageNum * FLASH_PAGE_SIZE, temp_buff,
655 FLASH_PAGE_SIZE);
656 }
657
658 }else if(mid == GD_FlASH_RDID){
659 uint8_t temp_buff[FLASH_SECTOR_SIZE] = {0};
660 while (cur_addr != end_addr) {
661 /* code */
662 CurSectorNum = CUR_SECTOR_NUM(cur_addr);
663 CurStartPsr = CUR_START_PSR(cur_addr);
664
665 for(int i=0;i<FLASH_SECTOR_SIZE/FLASH_PAGE_SIZE;i++){
666 xc_fmc_spi_flash_read_page(CurSectorNum * FLASH_SECTOR_SIZE+ i* FLASH_PAGE_SIZE, temp_buff+i*FLASH_PAGE_SIZE,
667 FLASH_PAGE_SIZE);
668 }
669
670 xc_fmc_spi_flash_erase_sector(CurSectorNum * FLASH_SECTOR_SIZE);
671
672 if (CurStartPsr) {
673 ram_memcpy_bytes(&temp_buff[CurStartPsr], buff + wt_len,
674 (FLASH_SECTOR_SIZE - CurStartPsr) > size - wt_len
675 ? size - wt_len
676 : (FLASH_SECTOR_SIZE - CurStartPsr));
677 wt_len += wt_len + ((FLASH_SECTOR_SIZE - CurStartPsr) > size - wt_len
678 ? size - wt_len
679 : (FLASH_SECTOR_SIZE - CurStartPsr));
680 cur_addr += wt_len;
681 } else {
682 ram_memcpy_bytes(temp_buff, buff + wt_len,
683 size - wt_len > FLASH_SECTOR_SIZE ? FLASH_SECTOR_SIZE
684 : size - wt_len);
685 cur_addr += (size - wt_len > FLASH_SECTOR_SIZE ? FLASH_SECTOR_SIZE
686 : size - wt_len);
687 wt_len += (size - wt_len > FLASH_SECTOR_SIZE ? FLASH_SECTOR_SIZE
688 : size - wt_len);
689 }
690
691 for(int i=0;i<FLASH_SECTOR_SIZE/FLASH_PAGE_SIZE;i++){
692 xc_fmc_spi_flash_write_page(CurSectorNum * FLASH_SECTOR_SIZE+ i* FLASH_PAGE_SIZE, temp_buff+i*FLASH_PAGE_SIZE,
693 FLASH_PAGE_SIZE);
694 }
695 }
696 }
697
698
699 return 0;
700}
701
714__RAM_CODE uint8_t xc_fmc_spi_flash_read(uint32_t addr, uint8_t *buff,
715 uint16_t size)
716{
717 uint32_t cur_addr = addr;
718 uint32_t end_addr = addr + size;
719 uint16_t rd_len = 0;
720 uint16_t CurPageNum = 0;
721 uint32_t CurStartPsr = 0;
722 uint8_t temp_buff[FLASH_PAGE_SIZE] = {0};
723
724 while (cur_addr != end_addr) {
725 CurPageNum = CUR_PAGE_NUM(cur_addr);
726 CurStartPsr = CUR_START_PSR(cur_addr);
727 xc_fmc_spi_flash_read_page(CurPageNum * FLASH_PAGE_SIZE, temp_buff,
728 FLASH_PAGE_SIZE);
729 if (CurStartPsr) {
730 ram_memcpy_bytes(buff + rd_len, &temp_buff[CurStartPsr],
731 (FLASH_PAGE_SIZE - CurStartPsr) > size - rd_len
732 ? size - rd_len
733 : (FLASH_PAGE_SIZE - CurStartPsr));
734 rd_len += rd_len + ((FLASH_PAGE_SIZE - CurStartPsr) > size - rd_len
735 ? size - rd_len
736 : (FLASH_PAGE_SIZE - CurStartPsr));
737 cur_addr += rd_len;
738 } else {
739 ram_memcpy_bytes(buff + rd_len, temp_buff,
740 size - rd_len > FLASH_PAGE_SIZE ? FLASH_PAGE_SIZE
741 : size - rd_len);
742 cur_addr += (size - rd_len > FLASH_PAGE_SIZE ? FLASH_PAGE_SIZE
743 : size - rd_len);
744 rd_len += (size - rd_len > FLASH_PAGE_SIZE ? FLASH_PAGE_SIZE
745 : size - rd_len);
746 }
747 }
748
749 return 0;
750}
751
752
765__RAM_CODE void xc_fmc_spi_flash_ruid(uint8_t *ruid)
766{
769
770 uint8_t cmd[21] = {0};
771 uint8_t id[21] = {0};
772
773 cmd[0] = CMD_RUID;
774 cmd[1] = 0x00;
775 cmd[2] = 0x00;
776 cmd[3] = 0x00;
777 cmd[4] = 0x00;
778
779 xc_fmc_spi_enable(FMC_SSI_CTRL0_DFS_LEN_32BIT);
780 xc_fmc_spi_write_nbyte(cmd, sizeof(cmd));
781
782 xc_fmc_spi_read_nbyte(id, sizeof(id));
784
785 ram_memcpy_bytes(ruid, &id[5], 16);
786}
787
800__RAM_CODE void xc_fmc_spi_flash_rdid(uint8_t *rdid)
801{
804
805 uint8_t cmd[4] = {0};
806 uint8_t id[4] = {0};
807
808 cmd[0] = CMD_RDID;
809 cmd[1] = 0x0;
810 cmd[2] = 0x0;
811 cmd[3] = 0x0;
812
813 xc_fmc_spi_enable(FMC_SSI_CTRL0_DFS_LEN_32BIT);
814 xc_fmc_spi_write_nbyte(cmd, sizeof(cmd));
815
816 xc_fmc_spi_read_nbyte(id, sizeof(id));
817
819
820 ram_memcpy_bytes(rdid, &id[1], 3);
821}
822
823
835bool flash_size_and_type_get(uint32_t *flash_size, uint16_t *flash_type)
836{
837 uint32_t mid = 0;
838 uint8_t flash_flag =0;
841 xc_fmc_spi_flash_rdid((uint8_t*)&mid);
842
843 flash_flag = (mid >> 16) & 0xff;
844 *flash_type = (mid & 0xffff);
845 switch(flash_flag)
846 {
847 case FLASH_128K_FLAG:
848 *flash_size = FLASH_128K_SIZE;
849 break;
850 case FLASH_256K_FLAG:
851 *flash_size = FLASH_256K_SIZE;
852 break;
853 case FLASH_512K_FLAG:
854 *flash_size = FLASH_512K_SIZE;
855 break;
856 case FLASH_1M_FLAG:
857 *flash_size = FLASH_1M_SIZE;
858 break;
859 case FLASH_2M_FLAG:
860 *flash_size = FLASH_2M_SIZE;
861 break;
862 default:
863 return false ;
864 }
865 return true;
866}
867
879uint16_t extract32_16(uint32_t val) {
880 return ((val >> 8) & 0x0000FF00) |
881 (val >> 24);
882}
883
897bool reverse_verif_is_true(uint32_t value, uint32_t value_reverse_verif)
898{
899 if(value == ~value_reverse_verif)
900 {
901 return true;
902 }
903 else
904 {
905 return false;
906 }
907}
919bool xc_adc_2v4_calibrate_read(uint16_t * adc_calibrate)
920{
921 uint32_t flash_size;
922 uint16_t flash_type;
923 board_card_t board_card;
924 GLOBAL_INT_DISABLE( );
927
928 if(false == flash_size_and_type_get(&flash_size, &flash_type))
929 {
930 return false;
931 }
932
933 if(flash_type == GD25WD40_512K_FLASH)
934 {
935 xc_fmc_spi_flash_read(flash_size - FLASH_SECTOR_SIZE, (uint8_t *)&board_card, sizeof(board_card));
936 }
937 else
938 {
939 xc_fmc_spi_flash_read(flash_size - FLASH_PAGE_SIZE, (uint8_t *)&board_card, sizeof(board_card));
940 }
941
942 GLOBAL_INT_RESTORE( );
943
944 if(reverse_verif_is_true(board_card.adc2v4_cail, board_card.adc2v4_reverse_verif))
945 {
946 *adc_calibrate = extract32_16(board_card.adc2v4_cail);
947 return true ;
948 }
949 else
950 {
951 GLOBAL_INT_DISABLE( );
952 if(flash_type == GD25WD40_512K_FLASH)
953 {
954 xc_fmc_spi_otp_read_page(OTP_PROGRAM_PAGE_0,(uint8_t *)&board_card, sizeof(board_card));
955 }
956 else
957 {
958 xc_fmc_spi_otp_read_page(OTP_PROGRAM_PAGE_1,(uint8_t *)&board_card, sizeof(board_card));
959 }
960 GLOBAL_INT_RESTORE( );
961
962 if(reverse_verif_is_true(board_card.adc2v4_cail, board_card.adc2v4_reverse_verif))
963 {
964 *adc_calibrate = extract32_16(board_card.adc2v4_cail) ;
965 return true ;
966 }
967 }
968 return false;
969}
970
971
983bool xc_unique_identification_read(uint8_t *unique_id)
984{
985 uint32_t flash_size;
986 uint16_t flash_type;
987 board_card_t board_card;
988 GLOBAL_INT_DISABLE( );
991
992 if(false == flash_size_and_type_get(&flash_size, &flash_type))
993 {
994 return false;
995 }
996
997 if(flash_type == GD25WD40_512K_FLASH)
998 {
999 xc_fmc_spi_flash_read(flash_size - FLASH_SECTOR_SIZE, (uint8_t *)&board_card, sizeof(board_card));
1000 }
1001 else
1002 {
1003 xc_fmc_spi_flash_read(flash_size - FLASH_PAGE_SIZE, (uint8_t *)&board_card, sizeof(board_card));
1004 }
1005 GLOBAL_INT_RESTORE( );
1006
1007 if((reverse_verif_is_true(board_card.flash_id, board_card.flash_id_reverse_verif))\
1008 &&(reverse_verif_is_true(board_card.ft_rest, board_card.ft_rest_reverse_verif))\
1009 &&(reverse_verif_is_true(board_card.chip_cnt, board_card.chip_cnt_reverse_verif)))
1010 {
1011 *(uint16_t *)&unique_id[0] = extract32_16(board_card.flash_id);
1012 *(uint16_t *)&unique_id[2] = extract32_16(board_card.ft_rest);
1013 *(uint16_t *)&unique_id[4] = extract32_16(board_card.chip_cnt);
1014
1015 return true ;
1016 }
1017 else
1018 {
1019 GLOBAL_INT_DISABLE( );
1020 if(flash_type == GD25WD40_512K_FLASH)
1021 {
1022 xc_fmc_spi_otp_read_page(OTP_PROGRAM_PAGE_0,(uint8_t *)&board_card, sizeof(board_card));
1023 }
1024 else
1025 {
1026 xc_fmc_spi_otp_read_page(OTP_PROGRAM_PAGE_1,(uint8_t *)&board_card, sizeof(board_card));
1027 }
1028 GLOBAL_INT_RESTORE( );
1029
1030 if((reverse_verif_is_true(board_card.flash_id, board_card.flash_id_reverse_verif))\
1031 &&(reverse_verif_is_true(board_card.ft_rest, board_card.ft_rest_reverse_verif))\
1032 &&(reverse_verif_is_true(board_card.chip_cnt, board_card.chip_cnt_reverse_verif)))
1033 {
1034 *(uint16_t *)&unique_id[0] = extract32_16(board_card.flash_id);
1035 *(uint16_t *)&unique_id[2] = extract32_16(board_card.ft_rest);
1036 *(uint16_t *)&unique_id[4] = extract32_16(board_card.chip_cnt);
1037
1038 return true ;
1039 }
1040 }
1041 return false;
1042}
uint32_t flash_id
uint32_t chip_cnt_reverse_verif
uint32_t adc2v4_reverse_verif
uint32_t ft_rest_reverse_verif
uint32_t chip_cnt
uint32_t flash_id_reverse_verif
uint32_t adc2v4_cail
uint32_t ft_rest
static volatile uint32_t mid
bool xc_adc_2v4_calibrate_read(uint16_t *adc_calibrate)
xc_adc_2v4_calibrate_read
static __RAM_CODE void xc_fmc_status_wait_idle(void)
xc_fmc_status_wait_idle
__RAM_CODE void xc_fmc_spi_otp_read_page(uint32_t addr, uint8_t *data, uint16_t size)
xc_fmc_spi_flash_read_page
__RAM_CODE void xc_fmc_spi_flash_erase_page(uint32_t addr)
xc_fmc_spi_flash_erase_page
__RAM_CODE void xc_fmc_spi_flash_erase_sector(uint32_t addr)
xc_fmc_spi_flash_erase_sector
bool flash_size_and_type_get(uint32_t *flash_size, uint16_t *flash_type)
flash_size_and_type_get
__RAM_CODE uint8_t xc_fmc_spi_flash_write(uint32_t addr, uint8_t *buff, uint16_t size)
static __RAM_CODE void xc_fmc_spi_flash_write_enable(void)
xc_fmc_spi_flash_write_enable
__RAM_CODE void xc_fmc_spi_flash_rdid(uint8_t *rdid)
xc_fmc_spi_flash_rdid
static __RAM_CODE void xc_fmc_spi_flash_wait_busy(void)
xc_fmc_spi_flash_wait_busy
__RAM_CODE void xc_fmc_spi_init_oprt(void)
xc_fmc_spi_init_oprt
static __RAM_CODE void xc_fmc_spi_read_nbyte(uint8_t *rxdata, uint16_t size)
xc_fmc_spi_read_nbyte
bool xc_unique_identification_read(uint8_t *unique_id)
xc_unique_identification_read
__RAM_CODE void xc_fmc_spi_flash_power_down(void)
xc_fmc_spi_flash_power_down
static __RAM_CODE void xc_fmc_spi_write_nbyte(uint8_t *txdata, uint16_t size)
xc_fmc_spi_write_nbyte
static __RAM_CODE void * ram_memcpy_bytes(void *dst, const void *src, int size)
xc_ram_memcpy_bytes
__RAM_CODE void xc_fmc_spi_flash_read_page(uint32_t addr, uint8_t *data, uint16_t size)
xc_fmc_spi_flash_read_page
__RAM_CODE void xc_fmc_spi_flash_write_page(uint32_t addr, uint8_t *data, uint16_t size)
xc_fmc_spi_flash_write_page
__RAM_CODE void xc_fmc_spi_flash_ruid(uint8_t *ruid)
xc_fmc_spi_flash_ruid
__RAM_CODE void xc_fmc_spi_flash_wake_up(void)
xc_fmc_spi_flash_power_down
static __RAM_CODE uint8_t xc_fmc_spi_flash_status(void)
xc_fmc_spi_flash_status
uint16_t extract32_16(uint32_t val)
extract32_16
static __RAM_CODE void xc_fmc_spi_enable(uint8_t dfs)
xc_fmc_spi_enable
bool reverse_verif_is_true(uint32_t value, uint32_t value_reverse_verif)
reverse_verif_is_true
static __RAM_CODE void xc_fmc_spi_disable(void)
xc_fmc_spi_enable
__RAM_CODE uint8_t xc_fmc_spi_flash_read(uint32_t addr, uint8_t *buff, uint16_t size)
xc_fmc_spi_flash_write
The header of xc_drv_fmc_spi.c