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xc_drv_i2c.c
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1
24/*------------------------------------------------------------------------------------
25 INCLUDE HEADE FILES
26 -------------------------------------------------------------------------------------*/
27#include "xc_drv_i2c.h"
28
29/*------------------------------------------------------------------------------------
30 Macros
31 -------------------------------------------------------------------------------------*/
32
33/*------------------------------------------------------------------------------------
34 Global Variables
35 -------------------------------------------------------------------------------------*/
37/*------------------------------------------------------------------------------------
38 TypeDef
39 -------------------------------------------------------------------------------------*/
40
41/*------------------------------------------------------------------------------------
42 Local Variables
43-------------------------------------------------------------------------------------*/
44
45/*------------------------------------------------------------------------------------
46 Func Prototype
47 -------------------------------------------------------------------------------------*/
48void xc_i2c_ctl_block_reset(void);
49/*------------------------------------------------------------------------------------
50 Functions
51 -------------------------------------------------------------------------------------*/
53{
54 cpr_ctlapbclken_grctl__i2c_pclk_en__setf(ENABLE);
55
56 cpr_rstctl_subrst_sw__i2c_rstn__setf(RSTCTL_ENABLE);
57 cpr_rstctl_subrst_sw__i2c_rstn__setf(RSTCTL_DISABLE);
58
59 cpr_i2c_clk_ctl__i2c_clk_en__setf(ENABLE);
60 cpr_i2c_clk_ctl__i2c_clk_div__setf(init_cfg->DivClk);
61
62 i2c_flag_status_get(I2C_STATUS_ACTIVITY_SET);
63
64 i2c_enable__enable__setf(I2C_ENABLE_EN_DISABLE);
65
66 i2c_rx_tl__rx_tl__setf(I2C_RX_TL_FIFO_1);
67 i2c_tx_tl__tx_tl__setf(I2C_TX_TL_FIFO_0);
68
69 i2c_intr_en_set(I2C_INTR_EN_RX_UNDER_DISABLE | I2C_INTR_EN_RX_OVER_DISABLE | I2C_INTR_EN_RX_FULL_DISABLE |
70 I2C_INTR_EN_TX_OVER_DISABLE | I2C_INTR_EN_TX_EMPTY_DISABLE | I2C_INTR_EN_RD_REQ_DISABLE |
71 I2C_INTR_EN_TX_ABRT_DISABLE | I2C_INTR_EN_RX_DONE_DISABLE | I2C_INTR_EN_ACTIVITY_DISABLE |
72 I2C_INTR_EN_STOP_DET_DISABLE | I2C_INTR_EN_START_DET_DISABLE | I2C_INTR_EN_GEN_CALL_DISABLE);
73
74 i2c_tar__i2c_10bitaddr_master__setf(I2C_TAR_I2C_7BITADDR_MODE);
75
76 if (init_cfg->I2C_Mode == I2C_MODE_MASTER) {
77
78 i2c_tar__i2c_tar__setf(init_cfg->I2C_SlaveAddr);
79 i2c_con__master_mode__setf(I2C_CON_MASTER_MODE_ENABLE);
80 i2c_con__slave_disable__setf(I2C_CON_SLAVE_DISABLE_DISABLE);
81
82 } else if (init_cfg->I2C_Mode == I2C_MODE_SLAVE) {
83 i2c_sar__setf(init_cfg->I2C_SlaveAddr);
84 i2c_con__master_mode__setf(I2C_CON_MASTER_MODE_DISABLE);
85 i2c_con__slave_disable__setf(I2C_CON_SLAVE_DISABLE_ENABLE);
86
87 i2c_con__addr_10bit_slave__setf(I2C_CON_7BITADDR_SLAVE_MODE);
88
89 i2c_con__restart_en__setf(I2C_CON_RESTART_EN_DISABLE);
90 }
91
93
94 if (init_cfg->I2C_ClockSpeed == I2C_FREQUENCY_100K) {
95 i2c_con__speed__setf(I2C_CON_SPEED_STANDARD_MODE);
96
98 i2c_ss_scl_hcnt__ss_scl_hcnt__setf(I2C_MLCK32M_FREQUENCY_HCNT_100K);
99 i2c_ss_scl_lcnt__ss_scl_lcnt__setf(I2C_MLCK32M_FREQUENCY_LCNT_100K);
101 i2c_ss_scl_hcnt__ss_scl_hcnt__setf(I2C_MLCK48M_FREQUENCY_HCNT_100K);
102 i2c_ss_scl_lcnt__ss_scl_lcnt__setf(I2C_MLCK48M_FREQUENCY_LCNT_100K);
104 i2c_ss_scl_hcnt__ss_scl_hcnt__setf(I2C_MLCK64M_FREQUENCY_HCNT_100K);
105 i2c_ss_scl_lcnt__ss_scl_lcnt__setf(I2C_MLCK64M_FREQUENCY_LCNT_100K);
106 }
107 } else if (init_cfg->I2C_ClockSpeed == I2C_FREQUENCY_400K) {
108 i2c_con__speed__setf(I2C_CON_SPEED_FAST_MODE);
109
111 i2c_fs_scl_hcnt__fs_scl_hcnt__setf(I2C_MLCK32M_FREQUENCY_HCNT_400K);
112 i2c_fs_scl_lcnt__fs_scl_lcnt__setf(I2C_MLCK32M_FREQUENCY_LCNT_400K);
114 i2c_fs_scl_hcnt__fs_scl_hcnt__setf(I2C_MLCK48M_FREQUENCY_HCNT_400K);
115 i2c_fs_scl_lcnt__fs_scl_lcnt__setf(I2C_MLCK48M_FREQUENCY_LCNT_400K);
116
118 i2c_fs_scl_hcnt__fs_scl_hcnt__setf(I2C_MLCK64M_FREQUENCY_HCNT_400K);
119 i2c_fs_scl_lcnt__fs_scl_lcnt__setf(I2C_MLCK64M_FREQUENCY_LCNT_400K);
120 }
121 } else {
122 i2c_con__speed__setf(I2C_CON_SPEED_FAST_MODE);
123
125 i2c_fs_scl_hcnt__fs_scl_hcnt__setf(I2C_MLCK32M_FREQUENCY_HCNT_1M);
126 i2c_fs_scl_lcnt__fs_scl_lcnt__setf(I2C_MCLK32M_FREQUENCY_LCNT_1M);
128 i2c_fs_scl_hcnt__fs_scl_hcnt__setf(I2C_MLCK48M_FREQUENCY_HCNT_1M);
129 i2c_fs_scl_lcnt__fs_scl_lcnt__setf(I2C_MCLK48M_FREQUENCY_LCNT_1M);
131 i2c_fs_scl_hcnt__fs_scl_hcnt__setf(I2C_MLCK64M_FREQUENCY_HCNT_1M);
132 i2c_fs_scl_lcnt__fs_scl_lcnt__setf(I2C_MCLK64M_FREQUENCY_LCNT_1M);
133 }
134 }
135
136 i2c_flag_status_get(I2C_STATUS_ACTIVITY_SET);
137
138 i2c_enable__enable__setf(I2C_ENABLE_EN_ENABLE);
139}
140
141void xc_i2c_enable_it(uint32_t val) { i2c_intr_en_set(val); }
142
143void xc_i2c_fifo_rxtl_set(uint32_t val) { i2c_rx_tl__rx_tl__setf(val); }
144
145void xc_i2c_fifo_txtl_set(uint32_t val) { i2c_tx_tl__tx_tl__setf(val); }
146
148{
149 memset(&i2c_ctl_block, 0, sizeof(i2c_ctl_block));
152}
153
155
157
158void xc_i2c_slave_addr_set(uint8_t addr)
159{
160 i2c_enable__enable__setf(I2C_ENABLE_EN_DISABLE);
161 i2c_tar__i2c_tar__setf(addr);
162 i2c_enable__enable__setf(I2C_ENABLE_EN_ENABLE);
163}
164
165uint32_t xc_i2c_write_block(uint8_t dev_addr, uint8_t *src, size_t len, uint16_t reset, uint16_t stop)
166{
167 xc_i2c_slave_addr_set(dev_addr);
168
169 uint32_t abort_reason = 0;
170
171 uint16_t timeout = 0xFFFF;
172
173 for (int i = 0; i < len; i++) {
174
175 i2c_data_cmd_set(I2C_DATA_CMD_CMD_WRITE | stop | reset | *src++);
176
177 do {
178
179 } while (timeout-- && !(i2c_raw_intr_stat_get() & I2C_RAW_INTR_STAT_TX_EMPTY_SET));
180
181 if (!timeout) {
182 break;
183 }
184
185 abort_reason = i2c_tx_abrt_source_get();
186 if (abort_reason) {
187 i2c_clr_tx_abrt_get();
188 break;
189 }
190 }
191
192 return abort_reason;
193}
194
195uint32_t xc_i2c_read_block(uint8_t dev_addr, uint8_t *dst, size_t len, uint16_t reset, uint16_t stop)
196{
197 xc_i2c_slave_addr_set(dev_addr);
198
199 uint32_t abort_reason;
200 uint16_t timeout = 0xFFFF;
201
202 for (int i = 0; i < len; i++) {
203 while (!(I2C_FIFO_LEN - i2c_txflr_get()))
204 ;
205
206 i2c_data_cmd_set(I2C_DATA_CMD_CMD_READ | stop | reset);
207
208 do {
209
210 } while (timeout-- && !i2c_rxflr_get());
211
212 if (!timeout) {
213 DEBUG("xc_i2c_read_block timeout\n");
214 break;
215 }
216
217 abort_reason = i2c_tx_abrt_source_get();
218 if (abort_reason) {
219 DEBUG("xc_i2c_read_block tx_abrt\n");
220 i2c_clr_tx_abrt_get();
221 break;
222 }
223
224 *dst++ = i2c_data_cmd_get();
225 }
226
227 return abort_reason;
228}
229
231{
232 uint8_t val;
233 uint32_t stat;
234
235 stat = i2c_intr_stat_get();
236 val = i2c_clr_intr_get();
237
238 if (stat & I2C_INTR_STAT_RX_DONE_SET) {
239 }
240 if (stat & I2C_INTR_STAT_RX_FULL_SET) {
241 val = i2c_data_cmd__dat__getf();
242
243 if (i2c_ctl_block.i2c_read_cb != NULL) {
244 i2c_ctl_block.i2c_read_cb(&val, 1);
245 }
246 }
247 if (stat & I2C_INTR_STAT_RD_REQ_SET) {
248
249 if (i2c_ctl_block.i2c_write_cb != NULL) {
251 }
252 }
253 if (stat & I2C_INTR_STAT_TX_EMPTY_SET) {
254 }
255 if (stat & I2C_INTR_STAT_STOP_DET_SET) {
256 }
257}
258
259FlagStatus i2c_flag_status_get(uint32_t i2c_flag)
260{
261 FlagStatus bitstatus = RESET;
262
263 if ((i2c_status_get() & i2c_flag) != (uint32_t)RESET) {
264 bitstatus = SET;
265 } else {
266 bitstatus = RESET;
267 }
268
269 return bitstatus;
270}
271
i2c_write_callback i2c_write_cb
Definition xc_drv_i2c.h:63
i2c_read_callback i2c_read_cb
Definition xc_drv_i2c.h:62
uint16_t I2C_Mode
Definition xc_drv_i2c.h:44
uint16_t I2C_SlaveAddr
Definition xc_drv_i2c.h:46
uint8_t DivClk
Definition xc_drv_i2c.h:48
uint32_t I2C_ClockSpeed
Definition xc_drv_i2c.h:42
CLOCK_HFCLK_In_Typedef xc_clock_hfclk_in_get(void)
xc_clock_hfclk_in_get
@ CLOCK_HFCLK_IN_48M
@ CLOCK_HFCLK_IN_32M
@ CLOCK_HFCLK_IN_64M
void i2c_user_handler()
Definition xc_drv_i2c.c:230
void xc_i2c_fifo_txtl_set(uint32_t val)
Definition xc_drv_i2c.c:145
void xc_i2c_register_write_cb(i2c_write_callback i2c_cb)
Definition xc_drv_i2c.c:156
FlagStatus i2c_flag_status_get(uint32_t i2c_flag)
Definition xc_drv_i2c.c:259
uint32_t xc_i2c_read_block(uint8_t dev_addr, uint8_t *dst, size_t len, uint16_t reset, uint16_t stop)
Definition xc_drv_i2c.c:195
void xc_i2c_init(I2C_InitCfg_t *init_cfg)
Definition xc_drv_i2c.c:52
void xc_i2c_fifo_rxtl_set(uint32_t val)
Definition xc_drv_i2c.c:143
void xc_i2c_enable_it(uint32_t val)
Definition xc_drv_i2c.c:141
void xc_i2c_register_read_cb(i2c_read_callback i2c_cb)
Definition xc_drv_i2c.c:154
I2C_Block_t i2c_ctl_block
Definition xc_drv_i2c.c:36
void I2C_Handler()
Definition xc_drv_i2c.c:272
void xc_i2c_ctl_block_reset(void)
Definition xc_drv_i2c.c:147
uint32_t xc_i2c_write_block(uint8_t dev_addr, uint8_t *src, size_t len, uint16_t reset, uint16_t stop)
Definition xc_drv_i2c.c:165
void xc_i2c_slave_addr_set(uint8_t addr)
Definition xc_drv_i2c.c:158
The header of xc_drv_i2c.c
void(* i2c_read_callback)(uint8_t *buff, uint16_t len)
Definition xc_drv_i2c.h:59
@ I2C_FREQUENCY_400K
Definition xc_drv_i2c.h:54
@ I2C_FREQUENCY_100K
Definition xc_drv_i2c.h:53
void(* i2c_write_callback)(void)
Definition xc_drv_i2c.h:58