33#define RC_ADJ_VAL_MIN 0x0
34#define RC_ADJ_VAL_MID 0x1fff
35#define RC_ADJ_VAL_MAX 0x3fff
37#define RANGE_LPO_RTM 0x400
39#define _32K_STAND_HZ 32000
43#define CALIB_TIME_MS 10
44#define CALIB_DELAY_CHECK (CALIB_TIME_MS + 20)
46#define CALIB_STEP_CYCLE_32K (CALIB_TIME_MS * 32)
51static volatile uint32_t
mid = RC_ADJ_VAL_MID;
77 cpr_ctl_pclk_grctl__ctl_pclk_gr_upd__setf(0x1UL);
78 cpr_ctl_pclk_grctl__ctl_pclk_gr__setf(4U);
83 cpr_ctl_pclk_grctl__ctl_pclk_gr__setf(2U);
84 cpr_ctl_pclk_grctl__ctl_pclk_gr_upd__setf(0x1UL);
88 cpr_ctl_pclk_grctl__ctl_pclk_gr_upd__setf(0x1UL);
89 cpr_ctl_pclk_grctl__ctl_pclk_gr__setf(8U);
92 cpr_ctlapbclken_grctl__rtc_pclk_en__setf(0x1UL);
94 cprao_aon_clken_grctl__rtc_clk_en__setf(0x1UL);
96 rtc_rccal_lfcfg_set(0x100031);
102 rtc_rccal_hfcfg_set(25000);
103 rtc_rccal_lim1_set(3);
104 rtc_rccal_lim2_set(13);
108 rtc_rccal_hfcfg_set(37500);
109 rtc_rccal_lim1_set(4);
110 rtc_rccal_lim2_set(19);
113 rtc_rccal_adj_step_set(0x1404);
114 rtc_rccal_adj_val_set(0x1fff);
116 rtc_rccal_adj_cfg_set(0x1fff4000 | rc_adj_val);
117 rtc_rccal_intsta_set(0x03);
118 rtc_rccal_inten_set(0x01);
119 for (uint16_t dly = 0; dly < 1000; dly++)
121 rtc_rccal_en_set(0x01);
133 uint32_t hfcnt_load = rtc_rccal_hfcfg_get();
134 uint32_t lfdiv = rtc_rccal_lfcfg_get();
136 uint8_t hfcnt_dir = (hfcnt_val >> 31);
137 uint16_t f_lfclk = 0;
139 if (hfcnt_dir == 0) {
147 f_lfclk = 24000000 * (lfdiv + 1) / (hfcnt_load - hfcnt_val);
154 (hfcnt_load + hfcnt_val - 0x80000000);
158 24000000 * (lfdiv + 1) / (hfcnt_load + hfcnt_val - 0x80000000);
179 if (freq < rc32_offset_min)
181 else if (freq >= rc32_offset_max)
198 uint16_t f_lfclk = 0;
199 uint8_t rccal_int_sta;
207 rccal_int_sta = rtc_rccal_intsta_get();
208 }
while (!(rccal_int_sta & 0x01));
210 rtc_rccal_inten_set(0x00);
211 rtc_rccal_intsta_set(rccal_int_sta);
217 rtc_rccal_en_set(0x00);
221 if (
mid > RC_ADJ_VAL_MAX) {
222 mid = RC_ADJ_VAL_MIN;
227 mid = RC_ADJ_VAL_MAX;
231 rtc_rccal_adj_cfg_set(0x1fff4000 |
mid);
232 rtc_rccal_inten_set(0x01);
234 rtc_rccal_en_set(0x01);
236 DEBUG(
"f_lfclk: %d\n", f_lfclk);
241 rtc_rccal_en_set(0x00);
242 rtc_rccal_adj_cfg_set(0x00001fff);
243 rtc_rccal_adj_cfg__freq_adj_offset__setf(
mid);
244 rtc_rccal_adj_cfg__freq_adj_hw_clr__setf(0x01);
245 rtc_rccal_intsta_set(0x03);
247 for (uint16_t dly = 0; dly < 1000; dly++)
250 rtc_rccal_en_set(0x01);
264 uint32_t f_lfclk = 0;
265 uint32_t t32k_cnt = 0;
270 rtc_rccal_inten_set(0x00);
271 rtc_rccal_intsta_set(0x03);
274 rtc_ao_timer_ctl_set(0);
275 rtc_ao_timer_ctl__rtc_ao_timer_value__setf(CALIB_STEP_CYCLE_32K);
276 rtc_ao_timer_ctl__rtc_freq_timer_en__setf(1);
280 ao_intr = rtc_all_intr_ao_get();
281 }
while ((ao_intr & 0x20) == 0);
283 t32k_cnt = rtc_freq_32k_timer_val_get();
285 rtc_ao_timer_ctl__rtc_ao_timer_clr__setf(0x1UL);
286 rtc_ao_timer_ctl_set(0);
291 f_lfclk = (uint32_t)((((
float)((16.0) * CALIB_STEP_CYCLE_32K)) /
296 f_lfclk = (uint32_t)((((
float)((24.0) * CALIB_STEP_CYCLE_32K)) /
301 if (f_lfclk > _32K_STAND_HZ) {
302 mid =
mid - ((uint32_t)(((
float)(f_lfclk - _32K_STAND_HZ)) /
304 }
else if (f_lfclk < _32K_STAND_HZ) {
305 mid =
mid + ((uint32_t)(((
float)(_32K_STAND_HZ - f_lfclk)) /
308 DEBUG(
"f_lfclk: %d\n", f_lfclk);
310 rtc_rccal_en_set(0x00);
311 rtc_rccal_adj_cfg_set(0x1fff4000 |
mid);
313 rtc_rccal_en_set(0x01);
315 if (f_lfclk == _32K_STAND_HZ)
void xc_rc32k_calib_by_hw(void)
RC32k_Calib_by_hw
static volatile uint32_t mid
eLFREQ_Sta xc_rc32k_freq_scope(uint16_t freq)
xc_rc32k_freq_scope
void xc_rc32k_calib_init(uint16_t rc_adj_val)
xc_rc32k_calib_init
uint16_t xc_flfclk_calcu(uint32_t hfcnt_val)
xc_flfclk_calcu
void xc_rc32k_calib_by_soft(void)
rc32k_calib_by_soft
The header of xc_drv_calib.c
CLOCK_HFCLK_In_Typedef xc_clock_hfclk_in_get(void)
xc_clock_hfclk_in_get