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xc_drv_uart_dma.c
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25/*-----------------------------------------------------------------------------------
26 INCLUDE HEADE FILES
27 ------------------------------------------------------------------------------------*/
28#include "xc_drv_uart_dma.h"
29
30/*------------------------------------------------------------------------------------
31 Local Variables
32 -------------------------------------------------------------------------------------*/
33volatile bool uart0_tx_tfr_flag = true;
34volatile bool uart1_tx_tfr_flag = true;
35static volatile bool err_flag = false;
36
37/*------------------------------------------------------------------------------------
38 Functions
39-------------------------------------------------------------------------------------*/
48void uart0_tx_callback(uint8_t eCode)
49{
51 uart0_tx_tfr_flag = true;
52}
53
62void uart1_tx_callback(uint8_t eCode)
63{
65 uart1_tx_tfr_flag = true;
66}
67
76void uartx_dma_tx_err(uint8_t eCode)
77{
78 // -------
79 // This function is called by the IRQ handler.
80 // We use this function to deal with interrupts that the DMA
81 // driver is unable to cater for (these are application
82 // specific). All of the interrupts handled by this function
83 // are cleared by the DMA driver, so there's no need to clear here.
84 // -------
85
86 // Check the source of the interrupt
87
88 if(eCode == DMA_IRQ_ERR) {
89
90 // Just inform the application that this interrupt has occured.
91 err_flag = true;
92 }
93}
94
103uint8_t xc_uart_dma_tx_config(uint8_t uart_idx, eDMA_Ch_Num ch_num, uint16_t blockSize, uint8_t *tx_buff)
104{
105 DMA_Chx_Cfg_t ch_cfg;
106 uint8_t errorCode = DMA_OK;
107 uint32_t uart_prf_addr = 0;
108
109 if(uart_idx == UART2_IDX) {
110 errorCode = DMA_EPERM;
111 return errorCode;
112 }
113
114 if(uart_idx == UART0_IDX) {
115 uart_prf_addr = XC_REG_UART_BASE_ADDR;
116 } else if(uart_idx == UART1_IDX) {
117 uart_prf_addr = XC_REG_UART_BASE_ADDR + uart_offset[uart_idx];
118 }
119
120 ch_cfg.sar = (uint32_t)tx_buff;
121 ch_cfg.dar = (uint32_t)uart_prf_addr;
122
123 ch_cfg.ctl_src_msize = DMA_MSIZE_1;//DMAC_MSIZE_4;//DMAC_MSIZE_1;
124 ch_cfg.ctl_dst_msize = DMA_MSIZE_1;//DMAC_MSIZE_4;//DMAC_MSIZE_1;
125
128
131
132 ch_cfg.ctl_tt_fc = DMA_MEM2PRF_DMA;
133
134 ch_cfg.ctl_block_ts = blockSize;
135
138
140
141 if(uart_idx == UART0_IDX)
143 else if(uart_idx == UART1_IDX)
145
146// ch_cfg.cfg_ch_prior = DMAC_PRIORITY_0;
147 // Now we can intialise the channel configuration structure for
148 // DMA channel 0 by loading the structure members with the
149 // contents of the DMAC's channel 0 registers.
150 errorCode = xc_dma_set_channel_config(ch_num, &ch_cfg);
151 if(errorCode != 0) {
152 DEBUG("\nERROR: Failed to initialise configuration\n");
153 }
154
156
157 return errorCode;
158}
159
168void xc_uart_dma_tx_init(uint8_t uart_idx, uint16_t tx_size, uint8_t *tx_buff)
169{
170 xc_dma_init( );
171
172 uint8_t errorCode = xc_uart_dma_tx_config(uart_idx, DMA_CHANNEL1, tx_size, tx_buff);
173 if(errorCode != 0) {
174 DEBUG("\nERROR: Failed XC_UART_DMA_TX_CONFIG\n");
175 }
176}
177
186void xc_uart_dma_send(uint8_t uart_idx)
187{
188 uint8_t errorCode;
189
190 xc_dma_enable( );
191
192 if(uart_idx == UART0_IDX) {
193 uart0_tx_tfr_flag = false;
195 } else if(uart_idx == UART1_IDX) {
196 uart1_tx_tfr_flag = false;
198 }
199
200 if(errorCode != 0) {
201 DEBUG("\nERROR: Failed Uart DMA_StartTransfer Tx\n");
202 }
203}
eDMA_Burst_Trans_Len ctl_dst_msize
Definition xc_drv_dma.h:218
eDMA_Fifo_Mode cfg_fifo_mode
Definition xc_drv_dma.h:227
eDMA_Trans_Width ctl_src_tr_width
Definition xc_drv_dma.h:221
eDMA_SW_HW_HS_Select cfg_hs_sel_src
Definition xc_drv_dma.h:228
eDMA_SW_HW_HS_Select cfg_hs_sel_dst
Definition xc_drv_dma.h:229
eDMA_Burst_Trans_Len ctl_src_msize
Definition xc_drv_dma.h:217
eDMA_Trans_Flow ctl_tt_fc
Definition xc_drv_dma.h:226
eDMA_Trans_Width ctl_dst_tr_width
Definition xc_drv_dma.h:222
eDMA_HS_Interface cfg_dst_per
Definition xc_drv_dma.h:223
eDMA_Addr_Increment ctl_dinc
Definition xc_drv_dma.h:220
eDMA_Addr_Increment ctl_sinc
Definition xc_drv_dma.h:219
__RAM_CODE uint8_t xc_dma_disable(void)
xc_dma_disable
Definition xc_drv_dma.c:235
__RAM_CODE uint8_t xc_dma_set_channel_config(eDMA_Ch_Num ch_num, DMA_Chx_Cfg_t *ch)
xc_dma_set_channel_config
Definition xc_drv_dma.c:630
__RAM_CODE bool xc_dma_set_listener(eDMA_Ch_Num ch_num, DMA_Callback userFunction)
xc_dma_set_listener
Definition xc_drv_dma.c:673
__RAM_CODE uint8_t xc_dma_init(void)
xc_dma_init
Definition xc_drv_dma.c:588
__RAM_CODE void xc_dma_enable(void)
xc_dma_enable
Definition xc_drv_dma.c:222
__RAM_CODE uint8_t xc_dma_start_transfer(eDMA_Ch_Num ch_num, DMA_Callback cb_func)
xc_dma_start_transfer
Definition xc_drv_dma.c:705
@ DMA_FIFO_MODE_SINGLE
Definition xc_drv_dma.h:197
@ DMA_MEM2PRF_DMA
Definition xc_drv_dma.h:186
@ DMA_MSIZE_1
Definition xc_drv_dma.h:130
@ DMA_IRQ_ERR
Definition xc_drv_dma.h:124
@ UART0_DMA_TX_HS_IF0
Definition xc_drv_dma.h:165
@ UART1_DMA_TX_HS_IF1
Definition xc_drv_dma.h:166
enum dmac_channel_number eDMA_Ch_Num
@ DMA_HS_HARDWARE
Definition xc_drv_dma.h:159
@ DMA_ADDR_INCREMENT
Definition xc_drv_dma.h:142
@ DMA_ADDR_NOCHANGE
Definition xc_drv_dma.h:144
@ DMA_CHANNEL1
Definition xc_drv_dma.h:72
@ DMA_TRANS_WIDTH_8
Definition xc_drv_dma.h:149
void xc_uart_dma_send(uint8_t uart_idx)
volatile bool uart0_tx_tfr_flag
uint8_t xc_uart_dma_tx_config(uint8_t uart_idx, eDMA_Ch_Num ch_num, uint16_t blockSize, uint8_t *tx_buff)
void xc_uart_dma_tx_init(uint8_t uart_idx, uint16_t tx_size, uint8_t *tx_buff)
void uart1_tx_callback(uint8_t eCode)
volatile bool uart1_tx_tfr_flag
void uartx_dma_tx_err(uint8_t eCode)
void uart0_tx_callback(uint8_t eCode)
static volatile bool err_flag
The header of xc_drv_uart_dma.c