xc_drv_pwr.h

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/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __XC_DRV_PWR_H_
#define __XC_DRV_PWR_H_
 
/*-----------------------------------------------------------------------------------
                                       INCLUDE HEADE FILES
 ------------------------------------------------------------------------------------*/
#include "xc6xxx.h"
 
/*------------------------------------------------------------------------------------
                                             Macros
 -------------------------------------------------------------------------------------*/
#define RST_READY_TIME            0x07
#define OSC32_STABLE_TIME         80
#define WAIT_BLE_EXIT_LOWpwr_TIME 20 // 15
#define PRE_WAKEUP_TIME                                                        \
    (RST_READY_TIME + OSC32_STABLE_TIME + WAIT_BLE_EXIT_LOWpwr_TIME)
#define DEEP_SLEEP_MODE                 0
#define LIGHT_SLEEP_MODE                1
 
#define DEEP_SLEEP_GPIO_WAKE_HIGH_LEVEL 0
#define DEEP_SLEEP_GPIO_WAKE_LOW_LEVEL  1
 
#define BLE_IRQn_WAKE                   (1 << BLE_IRQn)
#define GPIO_IRQn_WAKE                  (1 << GPIO_IRQn)
#define RTC_IRQn_WAKE                   (1 << RTC_IRQn)
#define TIMER0_IRQn_WAKE                (1 << TIMER0_IRQn)
#define TIMER1_IRQn_WAKE                (1 << TIMER1_IRQn)
#define TIMER2_IRQn_WAKE                (1 << TIMER2_IRQn)
#define TIMER3_IRQn_WAKE                (1 << TIMER3_IRQn)
#define TIMER_AO0_IRQn_WAKE             (1 << TIMER_AO0_IRQn)
#define TIMER_AO1_IRQn_WAKE             (1 << TIMER_AO1_IRQn)
 
#define pwr_GPIO_LightSleepConfig       pwr_GPIO_SleepConfig
#define pwr_GPIO_DeepSleepConfig        pwr_GPIO_SleepConfig
 
/*------------------------------------------------------------------------------------
                                            TypeDef
 -------------------------------------------------------------------------------------*/
/* pwr Init structure definition  */
typedef struct
{
    uint32_t pwr_wake_it_src;
 
    uint32_t pwr_sleep_mode;
 
} PWR_InitCfg_t;
 
/*------------------------------------------------------------------------------------
                                        Inline Functions
 -------------------------------------------------------------------------------------*/
static __inline void xc_pwr_wake_it_set(uint32_t Val)
{
    cprao_slpctl_int_mask_set(0xFFFFFFFF & (~Val));
}
 
static __inline void xc_pwr_usb_off(void) { cpr_rf_reg5_set(0x1C); }
 
static __inline void xc_pwr_rc16m_off(void)
{
    cpr_rf_reg0__rc_16m_disalbe__setf(ENABLE);
}
 
static __inline void xc_pwr_aotimer_src_set32k(void)
{
    cprao_aon_reg1__timer_ao_sleep_clksw__setf(ENABLE);
}
 
static __inline void xc_pwr_aotimer_src_set32m(void)
{
    cprao_aon_reg1__timer_ao_sleep_clksw__setf(DISABLE);
}
 
static __inline void xc_pwr_pd_lightsleep_set(void)
{
    cprao_aon_slp_pd_mask_set(0x101);
}
 
static __inline void xc_pwr_pd_deepsleep_set(void)
{
    cprao_aon_slp_pd_mask_set(0x0);
}
 
static __inline void xc_pwr_osc_off(void)
{
    cprao_aon_slp_ctl_set(0x0);
}
 
static __inline void xc_pwr_modem_off(void)
{
    cprao_aon_vdd_iso_en__vddmdm_en__setf(ENABLE);
    cprao_aon_vdd_switch_en__vddmdm_en__setf(DISABLE);
}
 
static __inline void xc_pwr_modem_on(void)
{
    cprao_aon_vdd_iso_en__vddmdm_en__setf(DISABLE);
    cprao_aon_vdd_switch_en__vddmdm_en__setf(ENABLE);
}
 
__RAM_CODE static __inline void xc_pwr_rom_off(void)
{
    cprao_aon_vdd_iso_en__vddrom_en__setf(ENABLE);
    cprao_aon_vdd_switch_en__vddrom_en__setf(DISABLE);
}
 
__RAM_CODE static __inline void xc_pwr_rom_on(void)
{
    cprao_aon_vdd_iso_en__vddrom_en__setf(DISABLE);
    cprao_aon_vdd_switch_en__vddrom_en__setf(ENABLE);
}
 
static __inline void xc_pwr_rfdigital_off(void)
{
    uint32_t val;
 
    val  = cprao_aon_coreldo_en_get();
 
    val &= 0xFFFFFFFE;
 
    cprao_aon_coreldo_en_set(val);
}
 
static __inline void xc_pwr_rfdigital_on(void)
{
    uint32_t val;
 
    val  = cprao_aon_coreldo_en_get();
 
    val |= 1 << 0;
 
    cprao_aon_coreldo_en_set(val);
}
 
static __inline void xc_pwr_sleepsrc_mask_set(uint32_t val)
{
    cpr_slp_src_mask_set(val);
}
 
static __inline void xc_pwr_opa_volr_off(void)
{
    // OPA volr off
    uint32_t val;
    val  = cpr_opa_ctrl_reg__volr__getf();
    val |= 1 << 2;
    cpr_opa_ctrl_reg__opa_ctrl__setf(val);
}
 
static __inline void xc_pwr_revddldo_off()
{
    cprao_aon_reg4__bb_lpoldo_ibc__setf(4);
}
 
static __inline void xc_pwr_opa_tempsensor_off(void)
{
    cpr_opa_ctrl_reg__en_temp_sensor__setf(DISABLE);
}
 
static __inline void xc_pwr_bor_on(void)
{
    cprao_aon_bor_ctr_reg0__en_bor__setf(DISABLE);
}
 
static __inline void xc_pwr_bor_off(void)
{
    cprao_aon_bor_ctr_reg0__en_bor__setf(DISABLE);
}
 
static __inline void xc_pwr_rc32k_calib_off() {}
 
/*------------------------------------------------------------------------------------
                                        Exported Functions
 -------------------------------------------------------------------------------------*/
void xc_pwr_sleep_init(PWR_InitCfg_t *pwr_cfg);
void xc_pwr_ao_timer_pclk32m_Set(void);
void xc_pwr_ao_timer_pclk32k_set(void);
void xc_pwr_gpio_sleep_config(void);
 
void pwr_cpu_sleep_init(void);
__RAM_CODE void xc_pwr_cpu_sleep_enter(void);
__RAM_CODE void xc_pwr_ble_sleep_enter(void);
// void xc_sleep_init(void);
// void xc_gpio_sleep_config(void);
__RAM_CODE void xc_deep_sleep(void);
__RAM_CODE void xc_sleep(void);
 
void xc_pwr_gpio_lightsleep_wake_config(uint8_t pin, uint8_t edge_it);
void xc_pwr_pwrkey_init(void);
void xc_pwr_pwrkey_deepsleep_wake_config(uint8_t pin, uint8_t level);
void pwr_gpio_sleep_wake_config(uint8_t sleep_mode, uint8_t pin, uint8_t it);
 
void xc_pwr_dcdc_init(uint8_t vol_level);
void xc_pwr_dcdc_close(void);
void xc_pwr_dcdc_open(void);
 
void xc_pwr_vol_set(void);
 
#ifdef __cplusplus
}
#endif
 
#endif /* __XC6xxx_HAL_pwr_H_ */