moyuhai
222 lines
4.9 KiB
C
222 lines
4.9 KiB
C
#ifndef __CA51F2_SFR_H__
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#define __CA51F2_SFR_H__
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sfr P0 = 0x80;
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sfr SP = 0x81;
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sfr DP0L = 0x82;
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sfr DP0H = 0x83;
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sfr DP1L = 0x84;
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sfr DP1H = 0x85;
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sfr PWCON = 0x86;
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sfr PCON = 0x87;
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sfr TCON = 0x88;
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sfr TMOD = 0x89;
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sfr TL0 = 0x8a;
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sfr TL1 = 0x8b;
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sfr TH0 = 0x8c;
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sfr TH1 = 0x8d;
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sfr IDLST = 0x8e;
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sfr STPST = 0x8f;
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sfr PWMEN = 0x90;
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sfr PWM2DUTH = 0x91;
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sfr PWM3DUTL = 0x92;
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sfr PWM3DUTH = 0x93;
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sfr PWM4DUTL = 0x94;
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sfr PWM4DUTH = 0x95;
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sfr PWM5DUTL = 0x96;
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sfr PWM5DUTH = 0x97;
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sfr S0CON = 0x98;
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sfr S0BUF = 0x99;
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sfr PWM5DIVH = 0x9a;
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sfr PWM0DUTL = 0x9b;
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sfr PWM0DUTH = 0x9c;
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sfr PWM1DUTL = 0x9d;
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sfr PWM1DUTH = 0x9e;
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sfr PWM2DUTL = 0x9f;
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sfr WDCON = 0xa0;
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sfr WDFLG = 0xa1;
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sfr WDVTHL = 0xa2;
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sfr WDVTHH = 0xa3;
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sfr PWM3DIVH = 0xa4;
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sfr PWM4DIVL = 0xa5;
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sfr PWM4DIVH = 0xa6;
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sfr PWM5DIVL = 0xa7;
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sfr IE = 0xa8;
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sfr PWM0DIVL = 0xa9;
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sfr PWM0DIVH = 0xaa;
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sfr PWM1DIVL = 0xab;
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sfr PWM1DIVH = 0xac;
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sfr PWM2DIVL = 0xad;
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sfr PWM2DIVH = 0xae;
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sfr PWM3DIVL = 0xaf;
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sfr P3 = 0xb0;
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sfr PWM0CKD = 0xb1;
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sfr PWM1CKD = 0xb2;
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sfr PWM2CKD = 0xb3;
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sfr PWM3CKD = 0xb4;
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sfr PWM4CKD = 0xb5;
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sfr PWM5CKD = 0xb6;
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sfr PWMIF = 0xb7;
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sfr IP = 0xb8;
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sfr PWM0CON = 0xb9;
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sfr PWM1CON = 0xba;
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sfr PWM2CON = 0xbb;
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sfr PWM3CON = 0xbc;
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sfr PWM4CON = 0xbd;
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sfr PWM5CON = 0xbe;
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sfr LEFLG = 0xbf;
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sfr I2CCON = 0xc0;
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sfr I2CADR = 0xc1;
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sfr I2CADM = 0xc2;
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sfr I2CCR = 0xc3;
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sfr I2CDAT = 0xc4;
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sfr I2CSTA = 0xc5;
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sfr I2CFLG = 0xc6;
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sfr LEDAT1 = 0xc7;
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sfr T2CON = 0xc8;
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sfr T2MOD = 0xc9;
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sfr T2CL = 0xca;
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sfr T2CH = 0xcb;
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sfr TL2 = 0xcc;
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sfr TH2 = 0xcd;
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sfr LEDWTML = 0xce;
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sfr LEDWTMH = 0xcf;
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sfr PSW = 0xd0;
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sfr EP0CON = 0xd1;
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sfr EP1CON = 0xd2;
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sfr EP2CON = 0xd3;
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sfr EPIF = 0xd4;
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sfr TMCON = 0xd5;
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sfr TMSNU = 0xd6;
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sfr LEDAT0 = 0xd7;
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sfr UDCKS = 0xd8;
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sfr TK3MSH = 0xd9;
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sfr TK4MSL = 0xda;
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sfr TK4MSH = 0xdb;
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sfr TK5MSL = 0xdc;
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sfr TK5MSH = 0xdd;
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sfr AK0CON = 0xde;
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sfr AK1CON = 0xdf;
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sfr ACC = 0xe0;
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sfr TK0MSL = 0xe1;
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sfr TK0MSH = 0xe2;
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sfr TK1MSL = 0xe3;
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sfr TK1MSH = 0xe4;
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sfr TK2MSL = 0xe5;
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sfr TK2MSH = 0xe6;
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sfr TK3MSL = 0xe7;
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sfr LVDCON = 0xe8;
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sfr ATK2CH = 0xe9;
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sfr ATK3CL = 0xea;
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sfr ATK3CH = 0xeb;
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sfr ATK4CL = 0xec;
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sfr ATK4CH = 0xed;
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sfr ATK5CL = 0xee;
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sfr ATK5CH = 0xef;
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sfr B = 0xf0;
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sfr TK4CHS = 0xf1;
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sfr TK5CHS = 0xf2;
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sfr ATK0CL = 0xf3;
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sfr ATK0CH = 0xf4;
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sfr ATK1CL = 0xf5;
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sfr ATK1CH = 0xf6;
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sfr ATK2CL = 0xf7;
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sfr TKCON = 0xf8;
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sfr TKCFG = 0xf9;
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sfr TKMTS = 0xfa;
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sfr TKIF = 0xfb;
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sfr TK0CHS = 0xfc;
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sfr TK1CHS = 0xfd;
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sfr TK2CHS = 0xfe;
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sfr TK3CHS = 0xff;
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/* BIT Register */
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/* PSW */
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sbit CY = 0xD7;
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sbit AC = 0xD6;
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sbit F0 = 0xD5;
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sbit RS1 = 0xD4;
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sbit RS0 = 0xD3;
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sbit OV = 0xD2;
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sbit DPS = 0xD1;
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sbit P = 0xD0;
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/* TCON */
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sbit TF1 = 0x8F;
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sbit TR1 = 0x8E;
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sbit TF0 = 0x8D;
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sbit TR0 = 0x8C;
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sbit IE1 = 0x8B;
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sbit IT1 = 0x8A;
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sbit IE0 = 0x89;
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sbit IT0 = 0x88;
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/* S0CON */
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sbit SM0 = 0x9F;
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sbit SM1 = 0x9E;
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sbit SM2 = 0x9D;
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sbit REN = 0x9C;
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sbit TB8 = 0x9B;
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sbit RB8 = 0x9A;
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sbit TI0 = 0x99;
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sbit RI0 = 0x98;
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/* IE */
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sbit EA = 0xAF;
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sbit INT4EN = 0xAE;
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sbit INT3EN = 0xAD;
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sbit ES0 = 0xAC;
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sbit ET1 = 0xAB;
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sbit EX1 = 0xAA;
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sbit ET0 = 0xA9;
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sbit EX0 = 0xA8;
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/* IP */
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sbit PS1 = 0xBE;
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sbit PT2 = 0xBD;
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sbit PS0 = 0xBC;
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sbit PT1 = 0xBB;
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sbit PX1 = 0xBA;
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sbit PT0 = 0xB9;
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sbit PX0 = 0xB8;
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/* T2CON */
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sbit TF2 = 0xCF;
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sbit TR2 = 0xCE;
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sbit T2R1 = 0xCD;
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sbit T2R0 = 0xCC;
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sbit T2IE = 0xCB;
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sbit UCKS = 0xCA;
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sbit T2P1 = 0xC9;
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sbit T2P0 = 0xC8;
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/* P0 */
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sbit P00 = P0^0;
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sbit P01 = P0^1;
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sbit P02 = P0^2;
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sbit P03 = P0^3;
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sbit P04 = P0^4;
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sbit P05 = P0^5;
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sbit P06 = P0^6;
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sbit P07 = P0^7;
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/* P3 */
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sbit P30 = P3^0;
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sbit P31 = P3^1;
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sbit P32 = P3^2;
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sbit P33 = P3^3;
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sbit P34 = P3^4;
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sbit P35 = P3^5;
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#endif
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